Communication system, communication method, electronic apparatus, storage medium, and program product

Abstract

The invention discloses a communication system, a communication method, an electronic device, a storage medium and a program product, and relates to the technical field of communication, a storage element is arranged between a slave device and a master device, the storage element can be used for caching a data frame from the slave device, and the essence is that an intermediate buffer mechanism is constructed, and the data frame is cached. The data frame of the slave device can be written into the storage element corresponding to the slave device in advance, so that the master device can read the data frame at any time according to communication requirements. By adopting the technical scheme provided by the invention, the master device can read the required data frame as required without waiting for the real-time response of the slave device, so that the problem of relatively low communication efficiency caused by the reasons such as complex data processing, fault or communication congestion of the slave device can be avoided, and the effect of improving the communication efficiency of the communication system is achieved. The method is especially suitable for application scenes with high real-time requirements.

Description

Technical Field

[0001] This application relates to the field of communication technologies, and in particular, to a communication system, a communication method, an electronic device, a storage medium, and a program product. Background Art

[0002] In application scenarios such as industrial control networks, smart home systems, and sensor networks, it is often necessary to set a master device to communicate with multiple slave devices simultaneously to achieve efficient data collection, control instruction issuance, and system collaborative work.

[0003] In the related art, the master device is directly connected to multiple slave devices, and the master device communicates with each slave device in a polling manner. With this communication method, the master device needs to access each slave device in a fixed order. If a certain slave device responds slowly due to complex data processing, a fault, or communication congestion, etc., it will cause a significant increase in the polling waiting time of the subsequent devices, thereby resulting in low communication efficiency. This communication method is difficult to meet application scenarios with high real-time requirements. Summary of the Invention

[0004] This application provides a communication system, a communication method, an electronic device, a storage medium, and a program product to at least solve the problem of low communication efficiency in the related art.

[0005] This application provides a communication system, the communication system includes multiple slave devices, multiple storage elements, and a master device; the multiple slave devices and the multiple storage elements are in one-to-one correspondence; the slave device includes a first serial port, the storage element includes a second serial port and a third serial port; the master device includes a fourth serial port; For any one of the slave devices, the first serial port of the slave device is connected to the second serial port of the storage element corresponding to the slave device; For any one of the storage elements, the third serial port of the storage element is connected to the fourth serial port of the master device.

[0006] This application also provides a communication method, the communication method is applied to the communication system provided in any one of the above of this application, and the communication method includes: The storage element receives and caches the data frame from the slave device; In response to an access instruction to the slave device, the storage element outputs the cached data frame from the slave device to the master device.

[0007] This application also provides an electronic device, including: a memory for storing a computer program; a processor for implementing the steps of any one of the above communication methods when executing the computer program.

[0008] The present application also provides a computer-readable storage medium storing a computer program, wherein the computer program, when executed by a processor, implements the steps of any one of the above communication methods.

[0009] The present application also provides a computer program product including a computer program, which, when executed by a processor, implements the steps of any one of the above communication methods.

[0010] With the present application, since a storage element is provided between the slave device and the master device, the storage element can be used to cache data frames from the slave device. In essence, an intermediate buffering mechanism is constructed so that the data frames of the slave device can be written into the corresponding storage element of the slave device in advance for the master device to read at any time according to communication requirements. By adopting the technical solution provided by the present application, the master device can read the required data frames on demand without waiting for the real-time response of the slave device. Therefore, it can avoid the problem of low communication efficiency caused by complex data processing, faults or communication blockages of the slave device, and achieves the beneficial effect of improving the communication efficiency of the communication system. It is particularly applicable to application scenarios with high real-time requirements. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] To more clearly illustrate the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0012] Figure 1 It is a block diagram of a communication system provided by an embodiment of the present application; Figure 2 It is a block diagram of another communication system provided by an embodiment of the present application; Figure 3 It is a flowchart of a communication method provided by an embodiment of the present application; Figure 4 It is a working principle diagram of a storage element provided by an embodiment of the present application; Figure 5 It is a working principle diagram of another storage element provided by an embodiment of the present application; Figure 6 It is a working principle diagram of another storage element provided by an embodiment of the present application; Figure 7 It is a schematic diagram of a data frame format provided by an embodiment of the present application; Figure 8 It is a schematic diagram of a principle for obtaining a data group provided by an embodiment of the present application; Figure 9A structural block diagram of a server provided by an embodiment of the present application. Detailed implementation manners

[0013] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

[0014] It should be noted that in the description of the present application, the terms "include", "comprise" or any other variant thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements but also includes other elements not explicitly listed, or further includes elements inherent to such process, method, article or device. The terms "first", "second", etc. in the present application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0015] In order to enable those skilled in the art of the present technology to better understand the solution of the present application, the present application will be further described in detail below in conjunction with the accompanying drawings and specific implementation manners.

[0016] An embodiment of the present application provides a communication system, which includes a plurality of slave devices, a plurality of storage elements, and a master device; the plurality of slave devices and the plurality of storage elements are in one-to-one correspondence; each slave device includes a first serial port, and each storage element includes a second serial port and a third serial port; the master device includes a fourth serial port; for any slave device, the first serial port of the slave device is connected to the second serial port of the storage element corresponding to the slave device; for any storage element, the third serial port of the storage element is connected to the fourth serial port of the master device.

[0017] Figure 1 A structural block diagram of a communication system provided by an embodiment of the present application. Exemplarily, refer to Figure 1 , this communication system includes 4 slave devices (respectively slave device 1 to slave device 4), 4 storage elements (respectively storage element 1 to storage element 4), and 1 master device.

[0018] Exemplarily, continue to refer to Figure 1 , taking the master device accessing slave device 1 as an example, before receiving an access instruction for slave device 1, the data frame from slave device 1 is pre-buffered to storage element 1 in advance. When an access instruction for slave device 1 is received, storage element 1 sends the data frame from slave device 1 cached therein to the master device.

[0019] The technical solution provided by this application can cache the data frames from the slave device by setting a storage element between the slave device and the master device. In essence, it constructs an intermediate buffering mechanism that enables the data frames of the slave device to be written into the corresponding storage element of the slave device in advance for the master device to read at any time according to communication requirements. By adopting the technical solution provided by this application, the master device can read the required data frames on demand without waiting for the real-time response of the slave device. Therefore, it can avoid the problem of low communication efficiency caused by complex data processing, failures, or communication blockages of the slave device, and improve the communication efficiency of the communication system. It is particularly applicable to application scenarios with high real-time requirements.

[0020] Furthermore, it can also be set that the communication system further includes a first logic control element, a second logic control element, and a master control element; the first logic control element includes a plurality of first signal transmission channels, and both ends of any one of the first signal transmission channels are respectively connected to the first serial port of the slave device and the second serial port of the storage element with a corresponding relationship; the second logic control element includes a plurality of second signal transmission channels, one end of any one of the second signal transmission channels is connected to the third serial port of the storage element, and the other end is connected to the fourth serial port of the master device; different second signal transmission channels are connected to different storage elements; the master control element is connected to the first logic control element and the second logic control element.

[0021] Exemplarily, referring to Figure 2 , in this communication system, there are a total of 4 slave devices (respectively slave device 1 to slave device 4) and 4 storage elements (respectively storage element 1 to storage element 4). The first logic control element includes 4 first signal transmission channels, namely: the first signal transmission channel between slave device 1 and storage element 1, the first signal transmission channel between slave device 2 and storage element 2, the first signal transmission channel between slave device 3 and storage element 3, and the first signal transmission channel between slave device 4 and storage element 4. The first logic control element can adjust the on-off state of each first signal transmission channel under the control of the first state adjustment signal, so that some or all of the first signal transmission channels are in the conducting state. The slave device and the storage element connected by the first signal transmission channel in the conducting state can realize data interaction.

[0022] The second logic control element includes 4 second signal transmission channels, namely: the second signal transmission channel between storage element 1 and the master device, the second signal transmission channel between storage element 2 and the master device, the second signal transmission channel between storage element 3 and the master device, and the second signal transmission channel between storage element 4 and the master device. The second logic control element can adjust the on-off state of each second signal transmission channel in turn under the control of the second state adjustment signal, so that the master device can interact with each storage element in turn to realize data interaction.

[0023] By adding a first logic control element, a second logic control element, and a master control element to the communication system, it is possible to achieve data interaction between the master device and some or all of the slave devices by adjusting the on / off states of the first signal transmission channel and the second signal transmission channel according to communication needs. The adjustment process does not require manual adjustment of the connection relationship between the slave device and the master device.

[0024] Furthermore, it can be further set that the communication system further includes a first processor; the first processor is connected to the master control element.

[0025] Furthermore, it can be further set that the master control element is connected to at least one storage element.

[0026] Figure 3 This is a flowchart of a communication method provided by an embodiment of the present application. Refer to Figure 3 The communication method includes: S110. The storage element receives and caches the data frame from the slave device.

[0027] S120. In response to an access instruction to the slave device, the storage element outputs the cached data frame from the slave device to the master device.

[0028] Exemplarily, continue to refer to Figure 1 Taking the master device accessing the slave device 1 as an example, before the access instruction 22 to the slave device 1 is received, the data frame from the slave device 1 is cached in the storage element 1 in advance. When the access instruction to the slave device 1 is received, the storage element 1 sends the data frame from the slave device 1 cached inside it to the master device.

[0029] The technical solution provided by the present application sets a storage element between the slave device and the master device and uses this storage element to cache the data frame from the slave device. In essence, it constructs an intermediate buffering mechanism so that the data frame of the slave device can be written into the corresponding storage element of the slave device in advance for the master device to read at any time according to communication needs. By adopting the technical solution provided by the present application, the master device can read the required data frame on demand without waiting for the real-time response of the slave device. Therefore, it can avoid the problem of low communication efficiency caused by complex data processing, faults, or communication blockage of the slave device, and can improve the communication efficiency of the communication system. It is especially suitable for application scenarios with high real-time requirements.

[0030] Based on the above technical solution, optionally, the method may further include: the storage element receives and caches the data frame from the master device; the data frame from the master device has a corresponding slave device; the storage element outputs the data frame from the master device to the corresponding slave device.

[0031] Exemplarily, assume that the master device needs to send data frame 2 to slave device 1. Continuing to refer to Figure 1 , storage element 1 receives and caches data frame 2 from the master device, and subsequently storage element 1 outputs data frame 2 from the master device to slave device 1.

[0032] With the above setting method, the master device can complete the sending operation of the data frame without waiting for the real-time response of the slave device. After writing the data frame from the master device into the storage element, it is regarded as the transmission completed, thereby releasing the communication resources of the master device and improving its concurrent processing ability.

[0033] Based on the above technical solutions, optionally, the communication system further includes a first logic control element, a second logic control element, and a master control element; the first logic control element includes a plurality of first signal transmission channels, and both ends of any one of the first signal transmission channels are respectively connected to a slave device and a storage element with a corresponding relationship; the second logic control element includes a plurality of second signal transmission channels, one end of any one of the second signal transmission channels is connected to the storage element, and the other end is connected to the master device; the storage elements connected by different second signal transmission channels are different; the master control element is connected to the first logic control element and the second logic control element. The method further includes: the master control element sends a first state adjustment signal to the first logic control element and a second state adjustment signal to the second logic control element; the first logic control element adjusts the on-off state of the first signal transmission channels based on the first state adjustment signal, so that the slave device and the storage element connected by the first signal transmission channels in the on state can realize data interaction; the second logic control element adjusts the on-off state of the second signal transmission channels based on the second state adjustment signal, so that the master device and the storage element can realize data interaction.

[0034] Exemplarily, referring to Figure 2 , in this communication system, there are a total of 4 slave devices (respectively slave device 1 to slave device 4) and 4 storage elements (respectively storage element 1 to storage element 4). The first logic control element includes 4 first signal transmission channels, which are respectively: the first signal transmission channel between slave device 1 and storage element 1, the first signal transmission channel between slave device 2 and storage element 2, the first signal transmission channel between slave device 3 and storage element 3, and the first signal transmission channel between slave device 4 and storage element 4. The first logic control element can adjust the on-off state of each first signal transmission channel under the control of the first state adjustment signal, so that some or all of the first signal transmission channels are in the on state. The slave device and the storage element connected by the first signal transmission channels in the on state can realize data interaction.

[0035] The second logic control element includes four second signal transmission channels, namely: the second signal transmission channel between the storage element 1 and the master device, the second signal transmission channel between the storage element 2 and the master device, the second signal transmission channel between the storage element 3 and the master device, and the second signal transmission channel between the storage element 4 and the master device. The second logic control element can alternately adjust the on / off states of the respective second signal transmission channels under the control of the second state adjustment signal, so that the master device can alternately perform data interaction with each storage element.

[0036] By adding a first logic control element, a second logic control element, and a master control element to the communication system, it is possible to, according to communication needs, realize data interaction between the master device and some or all of the slave devices among multiple slave devices by adjusting the on / off states of the first signal transmission channel and the on / off states of the second signal transmission channel. The adjustment process does not require manual adjustment of the connection relationship between the slave device and the master device.

[0037] On the basis of the above technical solutions, optionally, the storage element includes a plurality of first storage units and a plurality of second storage units; the plurality of first storage units are arranged in a first order to form a first storage sequence; the plurality of second storage units are arranged in a second order to form a second storage sequence; the storage element caches the data frames from the slave device and outputs the data frames from the slave device to the master device, including: the first storage sequence caches the data frames from the slave device in a first-in-first-out manner and outputs the data frames to the master device; the storage element caches the data frames from the master device and outputs the data frames from the master device to the slave device, including: the second storage sequence caches the data frames from the master device in a first-in-first-out manner and outputs the data frames to the slave device.

[0038] Exemplarily, see Figure 4 , in this storage element, there are three first storage units (respectively the first storage unit 1 to 3) and three second storage units (respectively the second storage unit 1 to 3). The three first storage units are arranged in a first order to form a first storage sequence. In the first storage sequence, the first storage unit 1 is the first storage unit in this first storage sequence, so the first storage unit 1 is the first storage unit at the head of the sequence. The first storage unit 3 is the last storage unit in this first storage sequence, so the first storage unit 3 is the first storage unit at the end of the sequence. When storing a data frame in the first storage sequence, the data frame is stored in the first storage unit at the end of the sequence (i.e., the first storage unit 3). When reading a data frame from the first storage sequence, the data frame in the first storage unit at the head of the sequence (i.e., the first storage unit 1) is read.

[0039] Similarly, three second storage units are arranged in a second order to form a second storage sequence. In the second storage sequence, the second storage unit 1 is the first storage unit in this second storage sequence. Therefore, the second storage unit 1 is the second storage unit located at the beginning of the sequence. The second storage unit 3 is the last storage unit in this second storage sequence. Therefore, the second storage unit 3 is the second storage unit located at the end of the sequence. When storing a data frame in the second storage sequence, the data frame is stored in the second storage unit located at the end of the sequence (i.e., the second storage unit 3). When reading a data frame from the second storage sequence, the data frame in the second storage unit located at the beginning of the sequence (i.e., the second storage unit 1) is read.

[0040] Further, the first storage sequence caches data frames from the slave device, including: when the data frame is not included in the first storage unit located at the end of the sequence, the storage element receives the data frame from the slave device and stores the received data frame in the first storage unit located at the end of the sequence; the second storage sequence caches data frames from the master device, including: when the data frame is not included in the second storage unit located at the end of the sequence, the storage element receives the data frame from the master device and stores the received data frame in the second storage unit located at the end of the sequence.

[0041] Exemplarily, continue to refer to Figure 2 , the storage element 1 is connected to the slave device 1 through the first signal transmission channel and is connected to the master device through the second signal transmission channel. Refer to Figure 4 , in the storage element 1, the first storage unit 3 is the first storage unit located at the end of the sequence. When the storage element 1 detects that the first storage unit 3 does not include a data frame, the storage element 1 receives the data frame 13 from the slave device 1 and stores the received data frame 13 in the first storage unit located at the end of the sequence. The result after storing the data frame 13 is as Figure 5 shown.

[0042] Similarly, continue to refer to Figure 4 , the second storage unit 3 is the second storage unit located at the end of the sequence. When the storage element 1 detects that the second storage unit 3 does not include a data frame, the storage element 1 receives the data frame 23 from the master device and stores the received data frame 23 in the second storage unit located at the end of the sequence. The result after storing the data frame 13 is as Figure 5 shown.

[0043] By setting to obtain and cache the data frame from the slave device when the data frame is not included in the first storage unit located at the end of the sequence, and to obtain and cache the data frame from the master device when the data frame is not included in the second storage unit located at the end of the sequence, this method can effectively avoid the adverse situation of data loss caused by data frame overflow or data frame being overwritten in the first storage unit.

[0044] Further, the first storage sequence outputs the cached data frames to the master device, including: outputting the data frame in the first storage unit at the sequence head to the master device; the storage element sequentially moves the data frames stored in the remaining first storage units in the first storage sequence except the first storage unit at the sequence head to the previous first storage unit thereof; and clearing the data frame in the first storage unit at the sequence tail. The second storage sequence outputs the cached data frames to the slave device, including: outputting the data frame in the second storage unit at the sequence head to the slave device, the storage element sequentially moves the data frames stored in the remaining second storage units in the second storage sequence except the second storage unit at the sequence head to the previous second storage unit thereof, and clearing the data frame in the second storage unit at the sequence tail.

[0045] Exemplarily, continue to refer to Figure 5 , the first storage unit 1 is the first storage unit at the sequence head. After the master device reads the data frame 11 in the first storage unit 1, the data frame 12 in the first storage unit 2 is moved to the first storage unit 1, so that in the first storage unit 1, the data frame 12 overwrites the data frame 11. The data frame 13 in the first storage unit 3 is moved to the first storage unit 2, so that in the second storage unit 2, the data frame 13 overwrites the data frame 12. The data frame 13 in the second storage unit 3 is cleared, so that the first storage unit 3 does not include a data frame after clearing. Finally, the first storage sequence is obtained as Figure 6 shown. In this way, the first storage sequence can cache the data frames from the slave device in a first-in-first-out manner and output the data frames to the master device.

[0046] Similarly, continue to refer to Figure 5 , the second storage unit 1 is the second storage unit at the sequence head. After the master device reads the data frame 21 in the second storage unit 1, the data frame 22 in the second storage unit 2 is moved to the second storage unit 1, so that in the second storage unit 1, the data frame 22 overwrites the data frame 21. The data frame 23 in the second storage unit 3 is moved to the second storage unit 2, so that in the second storage unit 2, the data frame 23 overwrites the data frame 22. The data frame 23 in the second storage unit 3, so that the second storage unit 3 does not include a data frame after clearing. Finally, the second storage sequence is obtained as Figure 6 shown. In this way, the second storage sequence can cache the data frames from the master device in a first-in-first-out manner and output the data frames to the slave device.

[0047] Based on the above technical solutions, optionally, the method may further include: when each first storage unit in the first storage sequence includes a data frame, the storage element sends a first full-load signal to the first logic control element; after receiving the first full-load signal, the first logic control element sends a first pause signal to the slave device; after receiving the first pause signal, the slave device pauses sending data to the storage element. The purpose of this setting is that when each first storage unit in the first storage sequence stores a data frame, the slave device is restricted from sending data frames to the first storage sequence by means of the first full-load signal, thereby effectively avoiding data loss caused by the inability to write new data frames or data loss caused by new data frames overwriting data frames not read by the master device.

[0048] Similarly, when each second storage unit in the second storage sequence includes a data frame, the storage element sends a second full-load signal to the second logic control element; after receiving the second full-load signal, the second logic control element sends a second pause signal to the master device, and after receiving the second pause signal, the master device pauses sending data to the storage element. The purpose of this setting is that when each second storage unit in the second storage sequence stores a data frame, the master device is restricted from sending data frames to the second storage sequence by means of the second full-load signal, thereby effectively avoiding data loss caused by the inability to write new data frames or data loss caused by new data frames overwriting data frames not read by the slave device.

[0049] Furthermore, it can also be set that when the first storage unit at the end of the sequence does not include a data frame, the storage element receives a data frame from the slave device, including: when the first storage unit at the end of the sequence does not include a data frame, the storage element sends a first no-load signal to the first logic control element; after receiving the first no-load signal, the first logic control element sends a first resume signal to the slave device; after receiving the first resume signal, the slave device sends a data frame to the storage element; the storage element receives the data frame from the slave device. The essence of this setting is to control the slave device to resume sending data frames to the storage element by means of the first no-load signal when the slave device pauses sending data frames to the storage element. This setting method can make full use of the data storage space of the storage element, reduce resource idling caused by the storage space not being fully occupied, and can further improve communication efficiency.

[0050] Similarly, when the second storage unit at the end of the sequence does not include a data frame, the storage element receives a data frame from the master device, including: when the second storage unit at the end of the sequence does not include a data frame, the storage element sends a second idle signal to the second logic control element; after receiving the second idle signal, the second logic control element sends a second recovery signal to the master device; after receiving the second recovery signal, the master device sends a data frame to the storage element; the storage element receives the data frame from the master device. The essence of this setting is to control the master device to resume sending data frames to the storage element by means of the second idle signal in the case where the master device pauses sending data frames to the storage element. This setting method can make full use of the data storage space of the storage element, reduce the resource idleness caused by the unfilled storage space, and can further improve the communication efficiency.

[0051] Based on the above technical solutions, optionally, the slave device and the storage element perform data interaction at a first baud rate; the storage element and the master device perform data interaction at a second baud rate; when the number of the first signal transmission channels in the conducting state is N, the second baud rate is greater than or equal to N times the first baud rate. Exemplarily, if the number of the first signal transmission channels in the conducting state is 4, assuming that the data transmission rate between the slave device and the storage element is the first baud rate F, and the data transmission rate between the storage element and the master device is the second baud rate, the second baud rate is greater than or equal to 4F. In practice, since the data traffic sent from the slave device to the master device is much larger than the instruction traffic sent from the master device to the slave device, the essence of this setting is to limit the rate at which the master device reads the buffered data frames in the storage element to be N times or more the rate at which the storage element writes the buffered data frames from the slave device. This can enable the storage element to normally transfer data frames and avoid data frame accumulation caused by the storage element being unable to forward data frames in time, resulting in data transmission delay.

[0052] This application does not limit the specific format of the data frame. In practical applications, it can be set that the data frame includes a start bit, data bits, a check bit, and an end bit. The start bit, data bits, check bit, and end bit are arranged in a fourth preset order. Exemplarily, see Figure 7 that in this data frame, the fourth preset order is the start bit, data bits, check bit, and end bit.

[0053] Based on the above technical solutions, optionally, the method may further include: the master device processes the data frames received through the second signal transmission channels to obtain a plurality of data groups; wherein, any one of the data groups includes a plurality of data frames, and different data frames come from different second signal transmission channels. Analyze the data groups in sequence.

[0054] Exemplarily, see Figure 8, the slave device 1 sequentially sent data frames 1-1, 1-2, etc. to the master device. The slave device 2 sequentially sent data frames 2-1, 2-2, etc. to the master device. The slave device 3 sequentially sent data frames 3-1, 3-2, etc. to the master device. The slave device 4 sequentially sent data frames 4-1, 4-2, etc. to the master device. The sequence of data frames received by the master device was data frame 1-1, data frame 2-1, data frame 3-1, data frame 4-1, data frame 1-2, data frame 2-2, data frame 3-2, data frame 4-2. Processing this sequence of data frames can obtain two data groups. Among them, data frame 1-1, data frame 2-1, data frame 3-1, and data frame 4-1 constitute a data group. Data frame 1-2, data frame 2-2, data frame 3-2, and data frame 4-2 constitute a data group. Different data frames in any one data group come from different second signal transmission channels, and the number of data frames from any one second signal transmission channel is one. In practice, the data frames sent by the slave device may be related in time or logic. Parsing in units of data groups rather than in units of data frames can help the master device determine the global state of the system.

[0055] Further, the method may further include: during the process of data interaction between the slave device connected to the first signal transmission channel in the conducting state and the storage element, when receiving a data frame fails through a certain conducting first signal transmission channel, a padding signal is stored in the storage element corresponding to the first signal transmission channel. The role of the padding signal is to write a padding signal with a preset format or identifier into the corresponding storage element in the case where receiving a data frame fails due to communication anomalies, slave device failures, data frame loss, etc. through the first signal transmission channel, preventing data parsing errors or system anomalies caused by empty frames. In addition, when the master device reads the padding signal, it can identify that the data frame corresponding to the padding signal has not been received normally, thereby triggering operations such as fault alarms, improving the maintainability of the system.

[0056] Based on the above technical solution, optionally, the communication system further includes a first processor, the first processor is connected to the master control element, and the master control element sends a first state adjustment signal to the first logic control element and a second state adjustment signal to the second logic control element, including: the first processor sends a first control signal to the master control element; the master control element responds to the first control signal and sends a first state adjustment signal to the first logic control element and a second state adjustment signal to the second logic control element.

[0057] Exemplarily, refer to Figure 2, a first processor is associated with a control program through which a user can control the first processor to send a first control signal to a master control element. The first control signal can be, for example, information indicating which slave device or devices the master device needs to establish a communication link with. Based on the first control signal, the master control element sends a first state adjustment signal to a first logic control element. The first state adjustment signal can be, for example, a signal reflecting the target state of each first signal transmission channel. The target state of the first signal transmission channel is the state to which the first signal transmission channel is desired to be adjusted, which can specifically be a conducting state or a non-conducting state. Based on the first control signal, the master control element sends a second state adjustment signal to a second logic control element. The second state adjustment signal can be, for example, a signal reflecting the target state of each second signal transmission channel. The target state of the second signal transmission channel is the state to which the second signal transmission channel is desired to be adjusted, which can specifically be a conducting state or a non-conducting state. Subsequently, the first logic control element adjusts the states of the internal first signal transmission channels to the target state based on the first state adjustment signal, and the second logic control element adjusts the states of the internal second signal transmission channels to the target state based on the second state adjustment signal.

[0058] Further, in this communication system, the master control element is connected to at least one storage element; the master control element sending the first state adjustment signal to the first logic control element and the second state adjustment signal to the second logic control element includes: the master device sending a second control signal to the second logic control element; the second logic control element forwarding the second control signal to the storage element; the storage element forwarding the second control signal to the master control element; and the master control element sending the first state adjustment signal to the first logic control element and the second state adjustment signal to the second logic control element in response to the second control signal.

[0059] Exemplarily, continuing to refer to Figure 2 , the user can directly operate the master device to send a second control signal to the second logic control element. The second control signal can be, for example, information indicating which slave device or devices the master device needs to establish a communication link with. The second control signal is then transmitted to the master control element via the storage element. Based on the second control signal, the master control element sends a first state adjustment signal to the first logic control element.

[0060] This application provides two control signal transmission paths for the master control element: the first is that the first processor directly sends a first control signal to the master control element; the second is that the master device sends a second control signal, and the second control signal is transmitted to the master control element via the second logic control element and the storage element. The above two control signal transmission paths can meet the differentiated usage requirements of users.

[0061] In practice, the technical method provided by this application can be applied to a server. Figure 9A schematic diagram for applying the technical method provided by this application to a server. Refer to Figure 9 , the server includes a BMC (Baseboard Management Controller), a CPLD (Complex Programmable Logic Device), a CPU (Central Processing Unit), and a UART CON (Universal Asynchronous Receiver-Transmitter Connector).

[0062] Among them, the BMC is an embedded controller independent of the main CPU, used for remote management of devices such as servers, monitoring hardware status (such as temperature, voltage), and fault alarm. The CPLD is an integrated circuit that can implement logic circuit functions through programming and is commonly used for logic control, interface expansion, etc. in digital circuit design. The CPU is the core computing unit of the server, responsible for executing instructions and processing data, and is the "brain" of the system.

[0063] In the server, the CPLD includes UART Control Logic, UART Switch Logic0, UART Switch Logic1, FIFO0, FIFO1, FIFO2, and FIFO3. UART Control Logic is the overall control element, UART Switch Logic0 is the first logic control element, and UART Switch Logic1 is the second logic control element. FIFO0, FIFO1, FIFO2, and FIFO3 respectively represent four storage elements. UART Switch Logic is connected to four slave devices through the UART3~UART6 buses. Here, the slave device can be, for example, an OCP (Open Compute Project) network card or a smart network card, etc. The UART CON is used to connect to the master device. Here, the master device can be, for example, an external device (i.e., a device connected to the server but not belonging to the server, such as a computer connected to the server to understand the running status of the server).

[0064] Specifically, UART Switch Logic0 is connected to the serial port design inside the server and is responsible for selecting the UART channel to the FIFO. UART Switch Logic1 is connected to the external UART CONN of the server and is responsible for selecting the FIFO to the UART_PLD signal and informing the user whether data can be normally received currently through RTS_PLD.

[0065] Each FIFO has two storage sequences (the storage sequences can specifically be register units) inside. The first storage sequence is used to cache data frames from the slave devices connected to the UART bus, and the second storage sequence is used to store data frames from the master devices connected to UARTCONN. Each FIFO communicates and exchanges data with UART Switch Logic0 through VUART0~3 virtual signals, and informs UART Switch Logic0 whether the first storage sequence in the current FIFO is in a full-load state through VRTS0~3 virtual signals. The FIFO communicates and exchanges data with UART Switch Logic1 through VUART4~7 virtual signals, and informs UART Switch Logic0 whether the second storage sequence in the current FIFO is in a full-load state through VRTS4~7 virtual signals; UART Control Logic is respectively connected to UART Switch Logic0 and UART Switch Logic1, and is used to control the specific UART gating logic. In addition, UART Control Logic also monitors the serial communication data in FIFO0 to identify the serial port switching instructions issued by the user through the serial port.

[0066] UART Control Logic configures UART Switch Logic0~1 to gate different UART slave devices to the corresponding FIFOs according to user requirements. For example, if the user hopes that the external device communicates with UART3~UART6 simultaneously, then UARTSwitch Logic0~1 will gate UART3 to FIFO0, UART4 to FIFO1, UART5 to FIFO2, and UART6 to FIFO3. During communication, UART3~UART6 store data frames into the corresponding FIFOs at baud rate F1, while the external device exchanges data frames with FIFO0~3 at baud rate F2 through the UART_PLD signal. Among them, F2≥4·F1.

[0067] The following takes UART3 and FIFO0 as an example to illustrate the data reading and writing process: See Figure 9 and Figure 4When a slave device connected to URAT3 sends data frame 13, data frame 13 is transmitted via the UART3 bus, through UART Switch Logic0, and to FIFO0. FIFO0 stores data frame 13 in first storage unit 3, located at the end of FIFO0's first storage sequence. When all first storage units in FIFO0's first storage sequence contain data frames, FIFO0 notifies UART Switch Logic0 via the VTRS0 signal (i.e., the first full signal). UART Switch Logic0 then transmits a first pause signal (specifically, a software flow control signal) to notify the corresponding slave device to pause data frame transmission.

[0068] See also Figure 9 and Figure 5 , UART Switch Logic1 will read the data frame 11 in the first storage unit 1 in the first storage sequence of each FIFO in turn, and send the data frame 11 to the external device through UART_PLD in sequence. After UART Switch Logic1 reads the data frame 11, FIFO0 will control the data frame 12 and data frame 13 to perform shift processing. Figure 6 After the shift process, the first storage unit at the end of the first storage sequence contains no data frame. FIFO0 notifies UART Switch Logic0 via the VTRS0 signal (i.e., the first no-load signal). UART Switch Logic0 then sends a first resume signal (specifically, a software flow control signal) to notify the corresponding slave device to resume data transmission.

[0069] Continue to see Figure 9 and Figure 5 When the master device sends data frame 23, UART Switch Logic1 stores data frame 23 in FIFO0 via VUART4. When all second storage units in the second storage sequence of FIFO0 are filled with data frames, FIFO0 notifies UART Switch Logic1 via the VTRS4 signal (i.e., the second full signal). UART Switch Logic1 then sends a second pause signal (specifically, a software flow control signal) to notify the external device to pause data frame transmission. UART Switch Logic0 reads data frame 21 from FIFO0 via VUART0 and forwards it to UART3. After reading data frame 21, FIFO0 controls the shifting of data frames 22 and 23. See [Refer to the following text]. Figure 6, after the shift process, there is no data frame in the second storage unit 3. FIFO0 will inform UART SwitchLogic1 through the VTRS4 signal (i.e., the second no-load signal), and UART Switch Logic1 will send a second recovery signal (which can be a software flow control signal or an RTS_PLD entity signal specifically) to inform the external device to continue data frame transmission.

[0070] Continue to refer to Figure 9 , in this server, the CPU is connected to the BMC through the eSPI bus. The BMC parses the system serial port data in the eSPI bus and transmits the system serial port data to the CPLD through the SYS_UART line; at the same time, the BMC transmits its own serial port data to the CPLD through the BMC_UART line, so that the external device connected to the UART CON can obtain the system serial port data and the BMC's own serial port data through the CPLD.

[0071] Through the description of the above embodiments, those skilled in the art can clearly understand that the method according to the above embodiments can be implemented by means of software plus a necessary general hardware platform. Of course, it can also be implemented by hardware, but in many cases, the former is a better implementation method.

[0072] The embodiment of the present application also provides an electronic device, including a memory and a processor. A computer program is stored in the memory, and the processor is configured to run the computer program to execute the steps in any one of the above communication method embodiments.

[0073] The embodiment of the present application also provides a computer-readable storage medium, in which a computer program is stored. The computer program is configured to execute the steps in any one of the above XX method embodiments when running.

[0074] In an exemplary embodiment, the above computer-readable storage medium may include, but is not limited to: USB flash drive, read-only memory (abbreviated as ROM), random access memory (abbreviated as RAM), mobile hard disk, magnetic disk or optical disc and other various media that can store computer programs.

[0075] The embodiment of the present application also provides a computer program product. The above computer program product includes a computer program, and when the computer program is executed by a processor, it implements the steps in any one of the above communication method embodiments.

[0076] Embodiments of the present application further provide another computer program product, including a non-volatile computer-readable storage medium storing a computer program, where the computer program, when executed by a processor, implements the steps in any of the above communication method embodiments.

[0077] Those skilled in the art can further realize that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be implemented by electronic hardware, computer software, or a combination of the two. To clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described according to functions in the above description. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Skilled professionals can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present application.

[0078] The above has introduced in detail a communication system, a communication method, an electronic device, a storage medium, and a program product provided by the present application. Specific examples are used herein to elaborate on the principle and implementation manner of the present application. The description of the above embodiments is only used to help understand the method and its core idea of the present application. It should be noted that for those of ordinary skill in the art in the technical field, without departing from the principle of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the protection scope of the claims of the present application.

Claims

1. A communication system, characterized in that, The communication system includes a plurality of slave devices, a plurality of storage elements, and a master device; the plurality of slave devices and the plurality of storage elements are in one-to-one correspondence; the slave device includes a first serial port, and the storage element includes a second serial port and a third serial port; the master device includes a fourth serial port; For any one of the slave devices, the first serial port of the slave device is connected to the second serial port of the storage element corresponding to the slave device; For any one of the storage elements, the third serial port of the storage element is connected to the fourth serial port of the master device.

2. The communication system according to claim 1, wherein The communication system further includes a first logic control element, a second logic control element, and a master control element; The first logic control element includes a plurality of first signal transmission channels, and both ends of any one of the first signal transmission channels are respectively connected to the first serial port of the slave device and the second serial port of the storage element having a corresponding relationship; The second logic control element includes a plurality of second signal transmission channels, one end of any one of the second signal transmission channels is connected to the third serial port of the storage element, and the other end is connected to the fourth serial port of the master device; The storage elements connected by different second signal transmission channels are different; The master control element is connected to the first logic control element and the second logic control element.

3. The communication system according to claim 2, wherein The communication system further includes a first processor; the first processor is connected to the master control element.

4. The communication system according to claim 2, characterized in that, The master control element is connected to at least one of the storage elements.

5. A communication method, characterized in that, The communication method is applied to the communication system according to any one of claims 1-4, and the communication method includes: The storage element receives and caches a data frame from the slave device; In response to an access instruction to the slave device, the storage element outputs the cached data frame from the slave device to the master device.

6. The method according to claim 5, wherein The method further includes: The storage element receives and caches a data frame from the master device; the data frame from the master device has a corresponding slave device; The storage element outputs the data frame from the master device to the corresponding slave device.

7. The method according to claim 6, wherein The communication system further includes a first logic control element, a second logic control element, and a master control element; the first logic control element includes a plurality of first signal transmission channels, and both ends of any one of the first signal transmission channels are respectively connected to the slave device and the storage element having a corresponding relationship; The second logic control element includes a plurality of second signal transmission channels, one end of any one of the second signal transmission channels is connected to the storage element, and the other end is connected to the master device; The storage elements connected by different second signal transmission channels are different; The master control element is connected to the first logic control element and the second logic control element, and the method further includes: The master control element sends a first state adjustment signal to the first logic control element and a second state adjustment signal to the second logic control element; The first logic control element adjusts the on / off state of the first signal transmission channel based on the first state adjustment signal, so that data interaction is achieved between the slave device and the storage element connected to the first signal transmission channel in the on state; The second logic control element adjusts the on / off state of the second signal transmission channel based on the second state adjustment signal, so that data interaction is achieved between the master device and the storage element.

8. The method according to claim 7, wherein The storage element includes a plurality of first storage units and a plurality of second storage units; the plurality of first storage units are arranged in a first order to form a first storage sequence; the plurality of second storage units are arranged in a second order to form a second storage sequence; The storage element caches data frames from the slave device and outputs the data frames from the slave device to the master device, including: the first storage sequence caches data frames from the slave device in a first-in-first-out manner and outputs the data frames to the master device; The storage element caches data frames from the master device and outputs the data frames from the master device to the slave device, including: the second storage sequence caches data frames from the master device in a first-in-first-out manner and outputs the data frames to the slave device.

9. The method according to claim 8, wherein The first storage sequence caches data frames from the slave device, including: when the data frame is not included in the first storage unit at the end of the sequence, the storage element receives the data frame from the slave device and stores the received data frame in the first storage unit at the end of the sequence; The second storage sequence caches data frames from the master device, including: when the data frame is not included in the second storage unit at the end of the sequence, the storage element receives the data frame from the master device and stores the received data frame in the second storage unit at the end of the sequence.

10. The method according to claim 9, wherein The first storage sequence outputs the cached data frames to the master device, including: outputting the data frame in the first storage unit at the head of the sequence to the master device, and the storage element sequentially moves the data frames stored in the remaining first storage units in the first storage sequence except the first storage unit at the head of the sequence to the previous first storage unit, and clears the data frame in the first storage unit at the end of the sequence; The second storage sequence outputs the cached data frames to the slave device, including: outputting the data frame in the second storage unit at the head of the sequence to the slave device, and the storage element sequentially moves the data frames stored in the remaining second storage units in the second storage sequence except the second storage unit at the head of the sequence to the previous second storage unit, and clears the data frame in the second storage unit at the end of the sequence.

11. The method according to claim 10, characterized in that, The method further includes: When each of the first storage units in the first storage sequence includes a data frame, the storage element sends a first full-load signal to the first logic control element; after receiving the first full-load signal, the first logic control element sends a first pause signal to the slave device; after receiving the first pause signal, the slave device pauses sending data to the storage element. When each of the second storage units in the second storage sequence includes a data frame, the storage element sends a second full-load signal to the second logic control element; after receiving the second full-load signal, the second logic control element sends a second pause signal to the master device, and after receiving the second pause signal, the master device pauses sending data to the storage element.

12. The method according to claim 11, wherein When the first storage unit at the end of the sequence does not include a data frame, the storage element receiving a data frame from the slave device includes: when the first storage unit at the end of the sequence does not include a data frame, the storage element sends a first no-load signal to the first logic control element; after receiving the first no-load signal, the first logic control element sends a first resume signal to the slave device; after receiving the first resume signal, the slave device sends a data frame to the storage element; the storage element receives the data frame from the slave device. When the second storage unit at the end of the sequence does not include a data frame, the storage element receiving a data frame from the master device includes: when the second storage unit at the end of the sequence does not include a data frame, the storage element sends a second no-load signal to the second logic control element; after receiving the second no-load signal, the second logic control element sends a second resume signal to the master device; after receiving the second resume signal, the master device sends a data frame to the storage element; the storage element receives the data frame from the master device.

13. The method according to claim 7, wherein The communication system further includes a first processor, the first processor is connected to the master control element, and the master control element sends a first status adjustment signal to the first logic control element and a second status adjustment signal to the second logic control element, including: The first processor sends a first control signal to the master control element; In response to the first control signal, the master control element sends a first status adjustment signal to the first logic control element and a second status adjustment signal to the second logic control element.

14. The method according to claim 7, characterized in that, The master control element is connected to at least one of the storage elements; the master control element sending a first status adjustment signal to the first logic control element and a second status adjustment signal to the second logic control element includes: The master device sends a second control signal to the second logic control element; The second logic control element forwards the second control signal to the storage element; The storage element forwards the second control signal to the master control element; The master control element responds to the second control signal, and sends a first state adjustment signal to the first logic control element and a second state adjustment signal to the second logic control element.

15. An electronic device, characterized in that, Comprising: a memory for storing a computer program; a processor for implementing the steps of the communication method according to any one of claims 5 to 14 when executing the computer program.

16. A computer-readable storage medium, characterized in that, A computer program is stored in the computer-readable storage medium, wherein the computer program implements the steps of the communication method according to any one of claims 5 to 14 when being executed by a processor.

17. A computer program product, comprising a computer program, characterized in that, The computer program implements the steps of the communication method according to any one of claims 5 to 14 when being executed by a processor.

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