Method and system for mapping signal STM-1 to OTN based on GMP

Abstract

The invention discloses a method and a system for mapping a signal STM-1 to an OTN (Optical Transport Network) based on GMP (Good Manufacturing Practice). The invention discloses a GMP (Good Manufacturing Practice)-based signal STM-1-OTN (Optical Transport Network) mapping method. The method comprises the following steps of: multiplexing 2 * 7 paths of STM-1 frame data into two paths of STM1MUX signals; mapping the two paths of STM1MUX signals into two paths of ODU0 frames through GMP (Good Manufacturing Practice); mapping the two paths of ODU0 frames into one path of OPU1 frames through AMP; and packaging the OPU1 frame into an ODU1 frame, and finally generating an OTU1 frame. The mapping system from the signal STM-1 to the OTN based on the GMP comprises a management CPU, a sending end FPGA1, a receiving end FPGA2, a first OTN optical module and a second OTN optical module. By adopting the method, the bandwidth is greatly saved, and the resource waste is reduced.

Description

Technical Field

[0001] The present invention relates to the field of communications, and in particular, to a method and system for mapping STM-1 signals to OTN based on GMP. Background Art

[0002] With the upgrading of technologies, in the transmission network, OTN (Optical Transport Network) has gradually replaced SDH (Synchronous Digital Hierarchy) as the mainstream transmission network technology. However, in the currently deployed transmission network, there are still a large number of SDH devices in use. Therefore, a technology for transmitting SDH signals through the OTN network is required to achieve the compatibility between the SDH network and the OTN network. STM-N is a rate system in synchronous transmission SDH and is a globally common interface standard. The specific rates are as follows: STM-1: 155M, STM-4: 622M, STM-16: 2488M, STM-64: 10G. Currently, the mainstream solution is to map one STM-1 or STM-4 in the SDH signal to ODU0 through GMP (Generic Mapping Procedure), map one STM-16 to ODU1 through AMP, and map one STM-64 to ODU2 through AMP. Among them, ODU0 and ODU1 are terms in optical communications, representing different optical channel data units respectively.

[0003] However, the nominal rate of the low-speed SDH signal STM-1 is 155.52 Mbit / s, while the nominal rate of ODU0 is 1.244 Gbit / s. When currently using GMP mapping to map the low-speed SDH signal STM-1 into the ODU0 frame, the existing solution is to map 1 STM-1 into 1 ODU0 frame. Due to the large rate difference between STM-1 and ODU0, a large amount of fixed stuffing FS (Fixed Stuff) needs to be inserted into the ODU0 payload area during mapping. These fixed stuffing do not transmit data and will cause a large amount of bandwidth waste. Therefore, how to avoid this waste of broadband resources is an urgent problem to be solved. Summary of the Invention

[0004] In view of the above problems, the present invention proposes a method and system for mapping STM-1 signals to OTN based on GMP.

[0005] To achieve the object of the present invention, a method for mapping STM-1 signals to OTN based on GMP is provided, including the following steps: s1: The transmitting - end FPGA1 receives 2×7 STM - 1 frame data of the corresponding enabled interface based on the pre - enabled STM - 1 interface number; meanwhile, the transmitting - end FPGA1 generates empty STM - 1 frame data to replace the non - enabled STM - 1 interfaces. The transmitting - end FPGA1 also generates empty STM - 1 frame data to replace the non - enabled STM - 1 interfaces in the 2×7 STM - 1 frame data. The empty STM - 1 data frame only contains the frame - header overhead, and the rest is all 0, which is convenient for the receiving - end to locate the frame - header of the STM1_MUX signal.

[0006] s2: The transmitting - end FPGA1 synchronizes the 2×7 STM - 1 frame data to the system clock, then performs framing, frame synchronization, and de - scrambling processing on it in sequence, and numbers the processed 2×7 STM - 1 frame data from 0 to 13 to obtain STM - 1 frame data numbered 0 to 13 respectively. s3: The transmitting - end FPGA1 time - division multiplexes the STM - 1 frame data numbered 0 to 6 into 1 STM1_MUX signal in a byte - interleaved manner, and time - division multiplexes the STM - 1 frame data numbered 7 to 13 into another STM1_MUX signal. s4: Map the 2 STM1_MUX signals to 2 ODU0 frames respectively through the GMP mapping method. s5: The transmitting - end FPGA1 maps the 2 ODU0 frames to an OPU1 frame through AMP mapping. s6: The transmitting - end FPGA1 successively adds ODU1 overhead, OTU1 overhead, and frame - header overhead to the OPU1 frame to form an OTU1 frame, then performs a scrambling operation on the OTU1 frame, and then sends the scrambled OTU1 frame into the OTN network through the OTN optical module. s7: The receiving - end FPGA2 receives the scrambled OTU1 frame from the OTN network, performs a de - scrambling operation on it, and obtains the OTU1 frame; extracts the 2 ODU0 frames from the OTU1 frame through the AMP de - mapping method. s8: The receiving - end FPGA2 extracts and obtains the 2 STM1_MUX signals from the 2 ODU0 frames through the GMP de - mapping method. s9: The receiving - end FPGA2 performs de - multiplexing operations on the 2 STM1_MUX signals respectively, and obtains the 2×7 STM - 1 frame data, completing framing and frame synchronization. s10: The receiving - end FPGA2 confirms and obtains the STM - 1 interface corresponding to the 2×7 - path STM - 1 frame data based on the overhead at the 6th column of the 2nd row of the 2×7 - path STM - 1 frame data. After setting this overhead to 0, it scrambles the 2×7 - path STM - 1 frame data, then synchronizes the scrambled 2×7 - path STM - 1 frame data to the SDH clock, and finally sends it out from the corresponding STM - 1 interface.

[0007] Further, in the step s1, the process of pre - enabling the STM - 1 interface number includes: configuring the interface number of the STM - 1 interface by using the management CPU.

[0008] Further, in the step s2, the numbers from 0 to 13 of the 2×7 - path STM - 1 frame data are stored in the empty overhead bytes at the 6th column of the 2nd row of the 2×7 - path STM - 1 frame data.

[0009] Further, in the step s2, when performing descrambling processing on the 2×7 - path STM - 1 frame data, the SDH scrambling polynomial is .

[0010] Further, in the step s5, the specific process by which the transmitting - end FPGA1 maps the 2 - path ODU0 frames to the OPU1 frame through AMP is as follows: The transmitting - end FPGA1 stores the 2 - path ODU0 frames in the asynchronous FIFO; the transmitting - end FPGA1 takes out the 2 - path ODU0 frames from the asynchronous FIFO and maps them to 2 8×1904 ODTU01s respectively, and adjusts the byte overhead according to the data transmission status at the same time; Insert the adjusted 2 8×1904 ODTU01s into the OPU1 payload in a byte - interleaved manner. For every 2 frames, there are the overheads of 2 ODTU01s. That is, when the 8th bit of MFAS is 0, the OPU overhead corresponds to the overhead of the first ODTU01, and when the 8th bit of MFAS is 1, the OPU overhead corresponds to the overhead of the second ODTU01.

[0011] Further, the specific process of adjusting the byte overhead according to the data transmission status is as follows: The transmitting - end FPGA1 checks the remaining capacity of the asynchronous FIFO. If the remaining capacity of the asynchronous FIFO is less than the preset threshold A, a negative adjustment overhead is inserted into the JC overhead of the 2 8×1904 ODTU01s; if the remaining capacity of the asynchronous FIFO is greater than the preset threshold B, a positive adjustment overhead is inserted into the JC overhead of the 2 8×1904 ODTU01s.

[0012] Further, in the step s6, the scrambling polynomial for scrambling the OTU1 frame is: .

[0013] The present invention also provides a mapping system for mapping signals from STM-1 to OTN based on GMP, including: a management CPU, a transmitting end FPGA1, a receiving end FPGA2, a first OTN optical module, and a second OTN optical module; The transmitting end FPGA1 includes: a first STM-1 interface module, a first STM-1 processing module, an SDH to OTN module, a first CPU interface module, and a first SERDES interface; the first STM-1 processing module includes: a first asynchronous FIFO, a first STM-1 preprocessing module, and an STM-1 multiplexing module; the SDH to OTN module includes: a GMP mapping module, an AMP mapping module, and an OTU1 framing module; The receiving end FPGA2 includes: a second STM-1 interface module, a second STM-1 processing module, an OTN to SDH module, a second CPU interface module, and a second SERRES interface; the second STM-1 processing module includes: a second asynchronous FIFO, a second STM-1 preprocessing module, and an STM-1 demultiplexing module; the OTN to SDH module includes: a GMP demapping module, an AMP demapping module, and an OPU1 extraction module; The management CPU is used for: configuring the enable of the first STM-1 interface module through the LOCAL BUS bus; reading the frame synchronization status of the 2×7 STM-1 frame data of the receiving end FPGA2 collected by the second CPU interface module through the LOCAL BUS bus; The first STM-1 interface module is used for: accepting the 2×7 STM-1 frame data of the corresponding enabled interface according to the enable of the first STM-1 interface module configured by the management CPU; then generating empty STM-1 data frames for the unenabled interfaces in the accepted 2×7 STM-1 frame data; and finally storing the 2×7 STM-1 frame data into the first asynchronous FIFO; The first asynchronous FIFO is used for: synchronizing the 2×7 STM-1 frame data to the system clock; The first STM-1 preprocessing module is used for: performing framing and frame synchronization on the 2×7 STM-1 frame data, and descrambling, and then inserting numbers 0 to 13 at the 6th column of the 2nd row of the 2×7 STM-1 frame data; The STM-1 multiplexing module is used for: time-division multiplexing the 2×7 STM-1 frame data into 2 STM1_MUX signals in an inter-byte interleaving manner; The GMP mapping module is used for: respectively mapping the two STM1_MUX signals to two ODU0 frames through GMP; The AMP mapping module is used for: mapping the two ODU0 frames to an OPU1 frame through AMP; The OTU1 framing module is used for: successively adding ODU1 overhead, OTU1 overhead and frame header overhead to the OPU1 frame to form an OTU1 frame, and then performing scrambling operation on the OTU1 frame; The first SERDES interface is used for: sending the scrambled OTU1 frame into the OTN network through the first OTN optical module; The first CPU interface module is used for: configuring the enabling of the 2×7 STM-1 interfaces of the transmitting end FPGA1; The second SERRES port is used for: receiving the scrambled OTU1 frame from the OTN network; The OPU1 extraction module is used for: first descrambling the scrambled OTU1 frame and extracting the OPU1 frame; The AMP demapping module is used for: demapping the OPU1 frame into two ODU0 frames through AMP; The GMP demapping module is used for: demapping the two ODU0 frames into two STM1_MUX signals through GMP; The STM-1 demultiplexing module is used for: demultiplexing the two STM1_MUX signals into the 2×7 STM-1 frame data; The second STM-1 preprocessing module is used for: performing framing and frame synchronization on the 2×7 STM-1 frame data, and sending the frame synchronization status to the management CPU through the second CPU interface module; parsing the overhead in the 6th column of the 2nd row of the 2×7 STM-1 frame data to obtain the corresponding interface number, then restoring the overhead to 0, scrambling the 2×7 STM-1 frame data, and then storing the scrambled 2×7 STM-1 frame data into the second asynchronous FIFO corresponding to the interface number; The second asynchronous FIFO is used for: synchronizing the scrambled 2×7 STM-1 frame data to the SDH clock; The second STM-1 interface module is used for: sending out the scrambled 2×7 STM-1 frame data in the second asynchronous FIFO.

[0014] Compared with the prior art, the present invention has the following beneficial technical effects: In the present invention, in the process of mapping the SDH signal STM-1 to OTN, two ODU0s are implemented to carry up to 14 STM-1 signals, reducing the fixed stuffing FS inserted in the ODU0 payload area, greatly reducing bandwidth waste, and increasing the data transmission efficiency of the SDH signal in the OTN network. Description of the Drawings

[0015] Figure 1 is a schematic flowchart of a method for mapping the signal STM-1 to OTN based on GMP according to an embodiment; Figure 2 is a schematic block diagram of a system for mapping the signal STM-1 to OTN based on GMP according to an embodiment; Figure 3 is a schematic diagram of an STM-1 interface module according to an embodiment; Figure 4 is a schematic diagram of the STM1_MUX signal multiplexing structure according to an embodiment; Figure 5 is a schematic diagram of the GMP mapping from STM1_MUX to the OPU0 payload according to an embodiment; Figure 6 is a flowchart of the service processing of the transmitting end FPGA1 according to an embodiment; Figure 7 is a flowchart of the service processing of the receiving end FPGA2 according to an embodiment. Detailed Embodiments

[0016] In order to make the objectives, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0017] Referring to "embodiments" herein means that the specific features, structures or characteristics described in connection with the embodiments can be included in at least one embodiment of the present application. The phrase appears in various places in the specification and does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art will explicitly and implicitly understand that the embodiments described herein can be combined with other embodiments.

[0018] Refer to Figure 1 as shown Figure 1 is a schematic flowchart of a method for mapping the signal STM-1 to OTN based on GMP according to an embodiment. The method for mapping the signal STM-1 to OTN based on GMP includes the following steps: S1: The transmitting - end FPGA1 receives 2×7 STM - 1 frame data of the corresponding enabled interface based on the pre - enabled STM - 1 interface number; meanwhile, the transmitting - end FPGA1 generates empty STM - 1 frame data to replace the non - enabled STM - 1 interfaces; as Figure 3 shown, it is a schematic diagram of the STM - 1 interface module of an embodiment.

[0019] S2: The transmitting - end FPGA1 synchronizes the 2×7 STM - 1 frame data to the system clock, then performs framing, frame synchronization, and descrambling processing on it in sequence, and numbers the processed 2×7 STM - 1 frame data from 0 to 13 to obtain STM - 1 frame data numbered 0 to 13 respectively; S3: The transmitting - end FPGA1 time - division multiplexes the STM - 1 frame data numbered 0 to 6 into 1 STM1_MUX signal and the STM - 1 frame data numbered 7 to 13 into another STM1_MUX signal in a byte - interleaved manner; as Figure 4 shown, it is a schematic diagram of the STM1_MUX signal multiplexing structure of an embodiment.

[0020] S4: Map the 2 STM1_MUX signals to 2 ODU0 frames respectively through GMP mapping; as Figure 5 shown, it is a schematic diagram of the GMP mapping from STM1_MUX to OPU0 payload of an embodiment; S5: The transmitting - end FPGA1 maps the 2 ODU0 frames to OPU1 frames through AMP mapping; S6: The transmitting - end FPGA1 successively adds ODU1 overhead, OTU1 overhead, and frame - header overhead to the OPU1 frame to form an OTU1 frame, then performs a scrambling operation on the OTU1 frame, and then sends the scrambled OTU1 frame into the OTN network through the OTN optical module; S7: The receiving - end FPGA2 receives the scrambled OTU1 frame from the OTN network, performs a descrambling operation on it, and obtains the OTU1 frame; obtains the 2 ODU0 frames from the OTU1 frame through AMP demapping; S8: The receiving - end FPGA2 extracts and obtains the 2 STM1_MUX signals from the 2 ODU0 frames through GMP demapping; S9: The receiving - end FPGA2 performs demultiplexing operations on the 2 STM1_MUX signals respectively, and obtains the 2×7 STM - 1 frame data, completing framing and frame synchronization; s10: The receiving end FPGA2 confirms and obtains the STM-1 interface corresponding to the 2×7-channel STM-1 frame data based on the 2nd row and 6th column overhead of the 2×7-channel STM-1 frame data, sets the overhead to 0, scrambles the 2×7-channel STM-1 frame data, synchronizes the scrambled 2×7-channel STM-1 frame data to the SDH clock, and then sends it out from the corresponding STM-1 interface.

[0021] In one embodiment, in step s1, the process of pre-enabling the STM-1 interface number includes: configuring the interface number of the STM-1 interface using a management CPU.

[0022] In one embodiment, in step s2, numbers 0 to 13 of the 2×7-channel STM-1 frame data are stored in an empty overhead byte in row 2 and column 6 of the 2×7-channel STM-1 frame data.

[0023] In one embodiment, in step s2, when descrambling the 2×7-channel STM-1 frame data, the SDH scrambling code polynomial is: .

[0024] In one embodiment, in step s5, the specific process of the transmitting end FPGA1 mapping the two ODU0 frames into the OPU1 frame through the AMP includes the following: The transmitting end FPGA1 stores the two ODU0 frames in an asynchronous FIFO; the transmitting end FPGA1 takes the two ODU0 frames from the asynchronous FIFO and maps them into two 8×1904 ODTU01s respectively, while adjusting the byte overhead according to the data transmission status; The adjusted two 8×1904 ODTU01s are inserted into the OPU1 payload in a byte-interleaved manner. Every two multiframes correspond to the overhead of two ODTU01s. That is, when the eighth bit of the MFAS is 0, the OPU overhead corresponds to the overhead of the first ODTU01. When the eighth bit of the MFAS is 1, the OPU overhead corresponds to the overhead of the second ODTU01.

[0025] In one embodiment, the specific process of adjusting the byte overhead according to the transmission status of the data includes the following: The transmitting end FPGA1 checks the remaining capacity of the asynchronous FIFO. If the remaining capacity of the asynchronous FIFO is less than a preset threshold A, a negative adjustment overhead is inserted into the JC overhead of the two 8×1904 ODTU01s. If the remaining capacity of the asynchronous FIFO is greater than a preset threshold B, a positive adjustment overhead is inserted into the JC overhead of the two 8×1904 ODTU01s.

[0026] In one embodiment, in the step s6, the scrambling polynomial for scrambling the OTU1 frame is: .

[0027] Figure 2 FIG. 6 is a schematic diagram of a module of a GMP-based signal STM-1 to OTN mapping system according to an embodiment. The GMP-based signal STM-1 to OTN mapping system includes: a management CPU, a transmitting end FPGA1, a receiving end FPGA2, a first OTN optical module, and a second OTN optical module; The transmitting end FPGA1 includes: a first STM-1 interface module, a first STM-1 processing module, an SDH to OTN module, a first CPU interface module, and a first SERDES interface; the first STM-1 processing module includes: a first asynchronous FIFO, a first STM-1 preprocessing module, and an STM-1 multiplexing module; the SDH to OTN module includes: a GMP mapping module, an AMP mapping module, and an OTU1 framing module; The receiving end FPGA2 includes: a second STM-1 interface module, a second STM-1 processing module, an OTN to SDH module, a second CPU interface module, and a second SERRES interface; the second STM-1 processing module includes: a second asynchronous FIFO, a second STM-1 preprocessing module, and an STM-1 demultiplexing module; the OTN to SDH module includes: a GMP demapping module, an AMP demapping module, and an OPU1 extraction module; The management CPU is configured to: configure the enable of the first STM-1 interface module through the LOCAL BUS bus; read the frame synchronization status of the 2×7 STM-1 frame data of the receiving end FPGA2 collected by the second CPU interface module through the LOCAL BUS bus; The first STM-1 interface module is configured to: receive the 2×7 STM-1 frame data of the corresponding enabled interface according to the enable of the first STM-1 interface module configured by the management CPU, generate an empty STM-1 data frame for the unenabled interface, and finally store the 2×7 STM-1 frame data and the empty STM-1 data frame into the first asynchronous FIFO; The first asynchronous FIFO is configured to: synchronize the 2×7 STM-1 frame data to the system clock; The first STM-1 preprocessing module is configured to: perform framing and frame synchronization on the 2×7 STM-1 frame data, descramble it, and then insert numbers 0 to 13 at the 6th column of the 2nd row of the 2×7 STM-1 frame data; The STM-1 multiplexing module is used for: time-division multiplexing the 2×7 STM-1 frame data into 2 STM1_MUX signals by byte interleaving; The GMP mapping module is used for: respectively mapping the 2 STM1_MUX signals into 2 ODU0 frames through GMP; The AMP mapping module is used for: mapping the 2 ODU0 frames into an OPU1 frame through AMP; The OTU1 framing module is used for: sequentially adding ODU1 overhead, OTU1 overhead, and frame header overhead to the OPU1 frame to form an OTU1 frame, and then performing scrambling operation on the OTU1 frame; The first SERDES interface is used for: sending the scrambled OTU1 frame into the OTN network through the first OTN optical module; The first CPU interface module is used for: configuring the enabling of the 2×7 STM-1 interfaces of the transmitting end FPGA1; The second SERRES interface is used for: receiving the scrambled OTU1 frame from the OTN network; The OPU1 extraction module is used for: first descrambling the scrambled OTU1 frame and extracting the OPU1 frame; The AMP demapping module is used for: demapping the OPU1 frame into 2 ODU0 frames through AMP; The GMP demapping module is used for: demapping the 2 ODU0 frames into 2 STM1_MUX signals through GMP; The STM-1 demultiplexing module is used for: demultiplexing the 2 STM1_MUX signals into the 2×7 STM-1 frame data; The second STM-1 preprocessing module is used for: performing framing and frame synchronization on the 2×7 STM-1 frame data, and sending the frame synchronization status to the management CPU through the second CPU interface module; parsing the overhead in the 6th column of the 2nd row of the 2×7 STM-1 frame data to obtain the corresponding interface number, then restoring the overhead to 0, scrambling the 2×7 STM-1 frame data, and then storing the scrambled 2×7 STM-1 frame data into the second asynchronous FIFO corresponding to the interface number; The second asynchronous FIFO is used for: synchronizing the scrambled 2×7 STM-1 frame data to the SDH clock; The second STM-1 interface module is used for: sending out the scrambled 2×7 STM-1 frame data in the second asynchronous FIFO.

[0028] In one embodiment, as Figure 6As shown in the figure, first, the management CPU configures the enable signals of the 2×7-channel STM-1 interfaces. The transmitting FPGA1 receives the STM-1 frame signals of the corresponding enabled interfaces according to the STM-1 interface numbers configured by the management CPU. For the unenabled interfaces, FPGA1 generates empty STM-1 frames as substitutes. The 2×7-channel STM-1 signals are cached in the first asynchronous FIFO and synchronized to the system clock; The transmitting FPGA1 performs framing and frame synchronization operations on these 2×7-channel STM-1 signals respectively; The transmitting FPGA1 descrambles the STM-1 signals that have completed frame synchronization, and inserts numbers from 0 to 13 in the overhead at the 6th column of the 2nd row of the STM-1 frame structure for the receiving FPGA2 to distinguish the STM-1 interface numbers; The transmitting FPGA1 time-division multiplexes the STM-1 signals numbered from 0 to 6 and 7 to 13 in an inter-byte interleaved form to form 2 STM1_MUX signals; The transmitting FPGA1 maps the 2 STM1_MUX signals into OPU0 through the GMP method respectively, and adds ODU0 overhead to form an ODU0 frame; The transmitting FPGA1 maps 2 ODU0 frames into 1 OPU1 frame through the AMP method, adds OPU1 overhead, ODU1 overhead, OTU1 overhead and frame header overhead to form an OTU1 frame, and performs scrambling; The transmitting FPGA1 transmits the OTU1 to the first OTN optical module through the first SERDES interface and enters the OTN network.

[0029] In one embodiment, as Figure 7 shown, the receiving FPGA2 receives the OTU1 frame transmitted from the OTN network through the second SERDES interface from the second OTN optical module and descrambles it; The receiving FPGA2 extracts the OPU1 payload from the OTU1 frame and demaps 2 ODU0 frames through the AMP method; The receiving FPGA2 demaps 2 STM1_MUX signals from the 2 ODU0 frames through the GMP method; The receiving FPGA2 demultiplexes 2×7-channel STM-1 frame data from the 2 STM1_MUX signals; The receiving FPGA2 performs framing and frame synchronization on the 2×7-channel STM-1 data respectively, and sends the frame synchronization status to the management CPU; The receiving FPGA2 obtains the corresponding STM-1 frame interface number according to the overhead at the 6th column of the 2nd row of the STM-1 frame, restores the overhead to 0, and scrambles the STM-1 frame; The receiving - end FPGA2 caches the 2×7 - channel STM - 1 frame data into the second asynchronous FIFO, synchronizes the 2×7 - channel STM - 1 frame data to the SDH clock, and sends the data out from the corresponding interface.

[0030] The technical features of the above - mentioned embodiments can be combined arbitrarily. For the sake of concise description, not all possible combinations of the technical features in the above - mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope recorded in this specification.

[0031] It should be noted that the terms "first / second / third" involved in the embodiments of the present application are only used to distinguish similar objects and do not represent a specific order for the objects. Understandably, "first / second / third" can be interchanged in a specific order or sequence when permitted. It should be understood that the objects distinguished by "first / second / third" can be interchanged appropriately so that the embodiments of the present application described here can be implemented in an order other than those illustrated or described here.

[0032] The terms "including" and "having" in the embodiments of the present application and any variations thereof are intended to cover non - exclusive inclusion. For example, a process, method, device, product, or equipment that includes a series of steps or modules is not limited to the listed steps or modules, but optionally further includes steps or modules that are not listed, or optionally further includes other steps or modules inherent to these processes, methods, products, or equipment.

[0033] The above - mentioned embodiments only represent several implementation manners of the present application. Their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of the invention patent. It should be pointed out that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application should be subject to the appended claims.

Claims

1. A method for mapping STM-1 signals to OTN based on GMP, characterized in that, The steps are as follows: S1: The transmitting end FPGA1 receives 2×7 STM-1 frame data of the corresponding enabled interface based on the pre-enabled STM-1 interface number; meanwhile, the transmitting end FPGA1 generates empty STM-1 frame data to replace the non-enabled STM-1 interfaces. S2: The transmitting end FPGA1 synchronizes the 2×7 STM-1 frame data to the system clock, then performs framing, frame synchronization, and descrambling processing on it in sequence, and numbers the processed 2×7 STM-1 frame data from 0 to 13 to obtain STM-1 frame data numbered 0 to 13 respectively. S3: The transmitting end FPGA1 time-division multiplexes the STM-1 frame data numbered 0 to 6 into 1 STM1_MUX signal in a byte-interleaved manner, and time-division multiplexes the STM-1 frame data numbered 7 to 13 into another STM1_MUX signal. S4: Map the 2 STM1_MUX signals to 2 ODU0 frames respectively through the GMP mapping method. S5: The transmitting end FPGA1 maps the 2 ODU0 frames to an OPU1 frame through AMP. S6: The transmitting end FPGA1 adds ODU1 overhead, OTU1 overhead, and frame header overhead to the OPU1 frame in sequence to form an OTU1 frame, then performs a scrambling operation on the OTU1 frame, and then sends the scrambled OTU1 frame into the OTN network through the OTN optical module. S7: The receiving end FPGA2 receives the scrambled OTU1 frame from the OTN network, performs a descrambling operation on it, and obtains the OTU1 frame; extracts and obtains the 2 STM1_MUX signals from the OTU1 frame through the AMP demapping method. S8: The receiving end FPGA2 extracts and obtains the 2 STM1_MUX signals from the 2 ODU0 frames through the GMP demapping method. S9: The receiving end FPGA2 performs demultiplexing operations on the 2 STM1_MUX signals respectively, and obtains the 2×7 STM-1 frame data, and completes framing and frame synchronization. S10: The receiving end FPGA2 confirms and obtains the STM-1 interface corresponding to the 2×7 STM-1 frame data based on the overhead in the second row and sixth column of the 2×7 STM-1 frame data, then sets this overhead to 0, scrambles the 2×7 STM-1 frame data, then synchronizes the scrambled 2×7 STM-1 frame data to the SDH clock, and then sends it out from the corresponding STM-1 interface.

2. The mapping method of STM-1 signal to OTN based on GMP according to claim 1, characterized in that, In step S1, the process of pre-enabling the STM-1 interface number includes: configuring the interface number of the STM-1 interface using the management CPU.

3. The mapping method of STM-1 signal to OTN based on GMP according to claim 2, characterized in that, In step S2, the numbers 0 to 13 of the 2×7 STM-1 frame data are stored in the empty overhead bytes in the second row and sixth column of the 2×7 STM-1 frame data.

4. The method for mapping the signal STM-1 to OTN based on GMP according to claim 3, wherein In the step S2, when performing descrambling processing on the 2×7-channel STM-1 frame data, the SDH scrambling polynomial is .

5. The mapping method of STM-1 signal to OTN based on GMP according to claim 4, characterized in that, In step S5, the specific process of the transmitting end FPGA1 mapping the 2 ODU0 frames to an OPU1 frame through AMP is as follows: The transmitting FPGA1 stores the two ODU0 frames into the asynchronous FIFO; the transmitting FPGA1 extracts the two ODU0 frames from the asynchronous FIFO, maps them into two 8×1904 ODTU01s respectively, and adjusts the byte overhead according to the data transmission status. The two adjusted 8×1904 ODTU01s are inserted into the OPU1 payload in a byte-interleaved manner. For every two superframes, there are the overheads of two ODTU01s. That is, when the 8th bit of MFAS is 0, the OPU overhead corresponds to the overhead of the first ODTU01; when the 8th bit of MFAS is 1, the OPU overhead corresponds to the overhead of the second ODTU01.

6. The method for mapping the signal STM-1 to OTN based on GMP according to claim 5, characterized in that, The specific process of adjusting the byte overhead according to the data transmission status includes the following: The transmitting FPGA1 checks the remaining capacity of the asynchronous FIFO. If the remaining capacity of the asynchronous FIFO is less than the preset threshold A, a negative adjustment overhead is inserted into the JC overhead of the two 8×1904 ODTU01s; if the remaining capacity of the asynchronous FIFO is greater than the preset threshold B, a positive adjustment overhead is inserted into the JC overhead of the two 8×1904 ODTU01s.

7. The method for mapping the signal STM-1 to OTN based on GMP according to claim 6, wherein In the step S6, the scrambling polynomial for scrambling the OTU1 frame is as follows: .

8. A mapping system for STM-1 to OTN signals based on GMP, characterized in that, It includes: A management CPU, a transmitting FPGA1, a receiving FPGA2, a first OTN optical module, and a second OTN optical module; The transmitting FPGA1 includes: a first STM-1 interface module, a first STM-1 processing module, an SDH-to-OTN module, a first CPU interface module, and a first SERDES interface; the first STM-1 processing module includes: a first asynchronous FIFO, a first STM-1 preprocessing module, and an STM-1 multiplexing module; the SDH-to-OTN module includes: a GMP mapping module, an AMP mapping module, and an OTU1 framing module. The receiving FPGA2 includes: a second STM-1 interface module, a second STM-1 processing module, an OTN-to-SDH module, a second CPU interface module, and a second SERRES interface; the second STM-1 processing module includes: a second asynchronous FIFO, a second STM-1 preprocessing module, and an STM-1 demultiplexing module; the OTN-to-SDH module includes: a GMP demapping module, an AMP demapping module, and an OPU1 extraction module. The management CPU is used for: configuring the enable of the first STM-1 interface module through the LOCAL BUS; reading the frame synchronization status of the 2×7 STM-1 frame data of the receiving FPGA2 collected by the second CPU interface module through the LOCAL BUS. The first STM-1 interface module is used for: accepting the 2×7 STM-1 frame data of the corresponding enabled interface according to the enable of the first STM-1 interface module configured by the management CPU; then generating empty STM-1 data frames for the unenabled interfaces in the accepted 2×7 STM-1 frame data; finally, storing the 2×7 STM-1 frame data into the first asynchronous FIFO. The first asynchronous FIFO is used for: synchronizing the 2×7-channel STM-1 frame data to the system clock; The first STM-1 preprocessing module is used for: performing framing and frame synchronization on the 2×7-channel STM-1 frame data, descrambling, and then inserting numbers 0 to 13 at the 6th column of the 2nd row of the 2×7-channel STM-1 frame data; The STM-1 multiplexing module is used for: time-division multiplexing the 2×7-channel STM-1 frame data into 2 STM1_MUX signals in an inter-byte interleaving manner; The GMP mapping module is used for: respectively mapping the 2 STM1_MUX signals into 2 ODU0 frames through GMP; The AMP mapping module is used for: mapping the 2 ODU0 frames into an OPU1 frame through AMP; The OTU1 framing module is used for: successively adding ODU1 overhead, OTU1 overhead, and frame header overhead to the OPU1 frame to form an OTU1 frame, and then performing a scrambling operation on the OTU1 frame; The first SERDES interface is used for: sending the scrambled OTU1 frame into the OTN network through the first OTN optical module; The first CPU interface module is used for: configuring the enabling of the 2×7 STM-1 interfaces of the transmitting FPGA1; The second SERRES port is used for: receiving the scrambled OTU1 frame from the OTN network; The OPU1 extraction module is used for: first descrambling the scrambled OTU1 frame and extracting the OPU1 frame; The AMP demapping module is used for: demapping the OPU1 frame into 2 ODU0 frames through AMP; The GMP demapping module is used for: demapping the 2 ODU0 frames into 2 STM1_MUX signals through GMP; The STM-1 demultiplexing module is used for: demultiplexing the 2 STM1_MUX signals into the 2×7-channel STM-1 frame data; The second STM-1 preprocessing module is used for: performing framing and frame synchronization on the 2×7-channel STM-1 frame data, and sending the frame synchronization status to the management CPU through the second CPU interface module; parsing the overhead at the 6th column of the 2nd row of the 2×7-channel STM-1 frame data to obtain the corresponding interface number, then restoring the overhead to 0, scrambling the 2×7-channel STM-1 frame data, and then storing the scrambled 2×7-channel STM-1 frame data into the second asynchronous FIFO corresponding to the interface number; The second asynchronous FIFO is used for: synchronizing the scrambled 2×7-channel STM-1 frame data to the SDH clock; The second STM-1 interface module is used for: sending out the scrambled 2×7-channel STM-1 frame data in the second asynchronous FIFO.

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