Semiconductor device and manufacturing method thereof

Abstract

The present disclosure relates to the field of semiconductor technology and provides a semiconductor device and a method for manufacturing the same. The method is used to solve the technical problem of how to reduce the difficulty of bit line manufacturing. The manufacturing method includes: providing a substrate, the substrate including multiple active layers and a storage space separating each active layer; the active layer including a first part and a second part; along the direction from the first part to the second part, the size of the second part in the first direction gradually decreases; forming a filling structure surrounding the first part and a first sacrificial layer covering the filling structure in the storage space; the first sacrificial layer protrudes from the surface of the filling structure; the remaining storage space exposes multiple second parts arranged along the second direction; and forming a bit line structure in the remaining storage space. In this way, a self-aligned bit line can be formed, avoiding a high-difficulty, high-aspect-ratio bit line etching process, and reducing the difficulty of bit line manufacturing.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor technology, including but not limited to a semiconductor device and a method for manufacturing the same. Background Art

[0002] Each memory cell in a dynamic random access memory (DRAM) typically consists of a transistor and a capacitor. The transistor's gate is coupled to a word line (also known as a word line structure), one of the transistor's source and drain is coupled to a bit line (also known as a bit line structure), and the other of the transistor's source and drain is coupled to a capacitor (also known as a capacitor structure or capacitor).

[0003] With the continuous advancement of semiconductor technology, DRAM is moving towards a three-dimensional structure with higher integration and smaller size. DRAM with a three-dimensional architecture is commonly referred to as three-dimensional DRAM (3D DRAM). Currently, 3D DRAM still needs further improvement. Summary of the Invention

[0004] According to a first aspect of an embodiment of the present disclosure, a method for manufacturing a semiconductor device is provided, comprising: providing a substrate, the substrate comprising a plurality of active layers arrayed along a first direction and a second direction and an accommodating space separating each of the active layers; wherein each of the active layers comprises a first portion and a second portion arranged along a third direction; along a direction from the first portion to the second portion, a size of the second portion in the first direction gradually decreases; the third direction intersects with the first direction and is perpendicular to the second direction; a filling structure surrounding the first portion and a first sacrificial layer covering an outer surface of the filling structure are formed in the accommodating space; wherein the first sacrificial layer is located along the third direction. The surface of the second part protrudes from the filling structure toward the second part between two adjacent active layers in the first direction; the remaining accommodating space between two adjacent first sacrificial layers exposes a plurality of second parts arranged along the second direction; a bit line structure is formed in the remaining accommodating space; wherein, the bit line structure includes a first bit line part and a second bit line part alternately arranged along the second direction, the first bit line part covers the second part, and the second bit line part connects two adjacent first bit line parts; the sum of the sizes of the first bit line part and the second part covered by the first bit line part in the first direction is greater than the size of the second bit line part in the first direction.

[0005] In some embodiments, the filling structure surrounding the first portion and the first sacrificial layer covering the outer surface of the filling structure are formed in the accommodating space, comprising: sequentially forming an initial first dielectric layer, an initial first insulating layer and an initial first sacrificial layer in the accommodating space; wherein the initial first dielectric layer covers the exposed surface of the accommodating space; the initial first dielectric layer, the initial first insulating layer and the initial first sacrificial layer jointly fill the first gap between two adjacent active layers along the second direction; etching the initial first sacrificial layer and the initial first insulating layer to expose the initial first dielectric layer; wherein, The retained initial first insulating layer covers the initial first dielectric layer on the active layer; the retained initial first sacrificial layer constitutes the first sacrificial layer; a portion of the initial first dielectric layer is removed to expose the second portion and at least a portion of the first portion; wherein the retained initial first dielectric layer constitutes a first dielectric layer, the first dielectric layer extends along the first direction and surrounds the first region of the active layer; a word line structure coupled to the channel region of the exposed first portion is formed; a second dielectric layer is formed surrounding the second region of the exposed first portion; wherein the second dielectric layer is located between the word line structure and the bit line structure.

[0006] In some embodiments, the manufacturing method further includes: removing the initial first insulating layer protruding from the surface of the second dielectric layer to form a first insulating layer; wherein the first insulating layer is located between two adjacent word line structures and between two adjacent second dielectric layers.

[0007] In some embodiments, forming a bit line structure in the remaining accommodating space includes: filling the remaining accommodating space with a conductive material to form an initial bit line structure, wherein the initial bit line structure and the first sacrificial layer are alternately arranged along the first direction; removing the first sacrificial layer to form a first groove between two adjacent initial bit line structures; removing part of the initial bit line structure through the first groove; wherein the retained initial bit line structure constitutes the bit line structure.

[0008] In some embodiments, providing a base includes: providing a substrate, forming an initial stacked structure and an initial isolation side wall alternately arranged along the first direction on the substrate, the initial stacked structure including a second sacrificial layer and a semiconductor layer alternately stacked along the second direction; forming a plurality of second grooves extending through the initial stacked structure and the initial isolation side wall, the plurality of second grooves being arranged along the third direction, and each second groove extending along the first direction; removing a portion of the second sacrificial layer between two adjacent semiconductor layers through the second grooves to expose a portion of the semiconductor layer; thinning the exposed semiconductor layer along the second direction to form an initial active layer having a size smaller than that of the semiconductor layer in the second direction; forming a third sacrificial layer between two adjacent initial active layers; wherein the size of the initial active layer in the third direction is equal to the size of the third sacrificial layer in the third direction.

[0009] In some embodiments, providing the substrate further includes: removing a portion of the initial isolation sidewall through the second groove to expose portions of the two sidewalls of the initial active layer opposite to each other along the first direction; and removing the exposed portion of the initial active layer along the first direction and the third direction to form the active layer.

[0010] In some embodiments, a size of the active layer in the third direction is smaller than a size of the initial active layer in the third direction.

[0011] In some embodiments, the manufacturing method also includes: forming a plurality of third trenches extending through the initial stacked structure and the initial isolation sidewall, the plurality of third trenches and the plurality of second trenches being alternately arranged along the third direction, and each of the third trenches extending along the first direction; removing a portion of the second sacrificial layer through the third trench, and forming a second insulating layer at the position where the second sacrificial layer is removed; removing the semiconductor layer between two adjacent second insulating layers through the third trench to form a second gap between two adjacent second insulating layers; wherein the second gap and the third trench are connected; and forming a capacitor structure in the connected second gap and the third trench.

[0012] According to a second aspect of an embodiment of the present disclosure, a semiconductor device is provided, comprising: a plurality of active layers and a plurality of bit line structures; the plurality of active layers are arranged in an array along a first direction and a second direction; wherein each of the active layers comprises a first portion and a second portion arranged along a third direction; along a direction from the first portion to the second portion, the size of the second portion in the first direction gradually decreases; the third direction intersects with the first direction and is perpendicular to the second direction; the plurality of bit line structures are arranged along the first direction; wherein each of the bit line structures comprises a first bit line portion and a second bit line portion alternately arranged along the second direction; the first bit line portion covers the second portion, and the second bit line portion connects two adjacent first bit line portions; the sum of the sizes of the first bit line portion and the second portion covered by the first bit line portion in the first direction is greater than the size of the second bit line portion in the first direction.

[0013] In some embodiments, the semiconductor device further includes: a first dielectric layer, the first dielectric layer extending along the first direction; wherein the first dielectric layer surrounds a plurality of first regions of the active layers arranged along the first direction; a word line structure, the word line structure extending along the first direction; wherein the word line structure is coupled to a plurality of channel regions of the first portions arranged along the first direction; and a second dielectric layer, the second dielectric layer surrounding a second region of the first portion; wherein the second dielectric layer is located between the word line structure and the bit line structure.

[0014] In some embodiments, the semiconductor device further includes: a capacitor structure, wherein the capacitor structure and the bit line structure are respectively located at opposite ends of the active layer along the third direction; wherein the capacitor structure is connected to the first region.

[0015] In an embodiment of the present disclosure, a substrate with an accommodating space is provided, and each active layer on the substrate includes a first part and a second part arranged along a third direction, and the width of the second part gradually decreases along the direction from the first part to the second part; a filling structure surrounding the first part and a first sacrificial layer covering the outer surface of the filling structure are formed in the accommodating space, the first sacrificial layer is located between two adjacent active layers along the first direction and protrudes from the surface of the filling structure toward the second part, and the remaining accommodating space between the two adjacent first sacrificial layers exposes multiple second parts arranged along the second direction; a bit line structure is formed in the remaining accommodating space, the bit line structure includes a first bit line part and a second bit line part alternately arranged along the second direction, the first bit line part covers the second part, and the second bit line part connects the two adjacent first bit line parts; the sum of the widths of the first bit line part and the second part covered by the first bit line part is greater than the width of the second bit line part. In this way, firstly, the width of the second portion gradually decreases, and a "tip" can be formed at the end of the active layer, providing more spatial flexibility for the subsequent filling of the bit line structure; secondly, the first sacrificial layer protrudes from the filling structure toward the surface of the second portion, and the remaining accommodation space between two adjacent first sacrificial layers exposes multiple second portions arranged along the second direction, which can accurately control the shape and position of the bit line structure, that is, form a self-aligned bit line (self-align BL), thereby avoiding the high difficulty and high aspect ratio bit line etching process; thirdly, the first bit line partially covers the second portion, which can increase the contact area between the bit line structure and the active layer, which is beneficial to reducing the contact resistance between the bit line structure and the active layer and improving the electrical performance; fourthly, it can simplify the manufacturing process and reduce the difficulty of bit line manufacturing, and provide a new solution for achieving high integration and small size 3D DRAM. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 It is a schematic flow chart of a method for manufacturing a semiconductor device provided by an embodiment of the present disclosure;

[0017] Figure 2 is a partial cross-sectional view in the YZ direction after the initial stacked structure is formed according to an embodiment of the present disclosure;

[0018] Figure 3 is a schematic diagram of a three-dimensional structure after thinning the semiconductor layer provided by an embodiment of the present disclosure;

[0019] Figure 4 is a partial cross-sectional view in the YZ direction after the semiconductor layer is thinned according to an embodiment of the present disclosure;

[0020] Figure 5 is a schematic diagram of a three-dimensional structure after forming a third sacrificial layer according to an embodiment of the present disclosure;

[0021] Figure 6is a partial cross-sectional view in the YZ direction after the third sacrificial layer is formed according to an embodiment of the present disclosure;

[0022] Figure 7 This is a schematic diagram of the three-dimensional structure after back-etching the isolation sidewall provided by an embodiment of the present disclosure;

[0023] Figure 8 is a schematic diagram of a three-dimensional structure after trimming the initial active layer provided by an embodiment of the present disclosure;

[0024] Figure 9 It is a partial cross-sectional view in the YZ direction and the YX direction after the initial active layer is trimmed according to an embodiment of the present disclosure;

[0025] Figure 10 is a schematic diagram of the three-dimensional structure of the substrate provided by an embodiment of the present disclosure;

[0026] Figure 11 The embodiment of the present disclosure provides Figure 10 A partial side view of the base in FIG;

[0027] Figure 12 The embodiment of the present disclosure provides Figure 10 A partial top view of the base in FIG;

[0028] Figure 13 is a schematic diagram of a three-dimensional structure after forming an initial first dielectric layer and an initial first insulating layer according to an embodiment of the present disclosure;

[0029] Figure 14 The embodiment of the present disclosure provides Figure 13 A partial side view after forming an initial first dielectric layer;

[0030] Figure 15 The embodiment of the present disclosure provides Figure 13 A local top view after forming the initial first dielectric layer;

[0031] Figure 16 The embodiment of the present disclosure provides Figure 13 A partial side view after forming an initial first insulating layer;

[0032] Figure 17 The embodiment of the present disclosure provides Figure 13 A partial top view after forming an initial first insulating layer;

[0033] Figure 18 is a schematic diagram of a three-dimensional structure after forming an initial first sacrificial layer according to an embodiment of the present disclosure;

[0034] Figure 19 The embodiment of the present disclosure provides Figure 18 A partial side view after forming an initial first sacrificial layer;

[0035] Figure 20 The embodiment of the present disclosure provides Figure 18 A local top view after forming the initial first sacrificial layer;

[0036] Figure 21 is a schematic diagram of a three-dimensional structure after a portion of the initial first dielectric layer is removed according to an embodiment of the present disclosure;

[0037] Figure 22 is a schematic diagram of a three-dimensional structure after a word line structure is formed according to an embodiment of the present disclosure;

[0038] Figure 23 is a schematic diagram of a three-dimensional structure after forming a second dielectric layer according to an embodiment of the present disclosure;

[0039] Figure 24 is a schematic diagram of a three-dimensional structure after a bit line structure is formed according to an embodiment of the present disclosure;

[0040] Figure 25 It is a partial cross-sectional view of the bit line structure provided by an embodiment of the present disclosure in the XZ plane.

[0041] Figure 26 It is a schematic diagram of the three-dimensional structure after the first sacrificial layer is removed provided by an embodiment of the present disclosure.

[0042] Figure 27 is a schematic diagram of a three-dimensional structure after removing part of the initial bit line structure provided by an embodiment of the present disclosure;

[0043] Figure 28 It is a schematic diagram of the three-dimensional structure of the semiconductor device provided by the embodiment of the present disclosure. DETAILED DESCRIPTION

[0044] The following will clearly and completely describe the technical solutions in the embodiments of the present disclosure in conjunction with the embodiments of the present disclosure and the accompanying drawings. Obviously, the embodiments described are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of the present disclosure.

[0045] In the following description, numerous specific details are provided to provide a more thorough understanding of the present disclosure. However, it will be apparent to those skilled in the art that the present disclosure can be practiced without one or more of these details. In other instances, certain technical features known in the art are not described to avoid confusion with the present disclosure; that is, all features of actual embodiments are not described herein, nor are well-known functions and structures described in detail.

[0046] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0047] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to, or coupled to" another element or layer, it may be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on, directly adjacent to, directly connected to, or directly coupled to" another element or layer, there may be no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer, or part discussed below may be represented as a second element, component, region, layer, or part. However, when the second element, component, region, layer, or part is discussed, it does not necessarily mean that the first element, component, region, layer, or part exists in the present disclosure.

[0048] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," etc., may be used herein for convenience of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatially relative terms are intended to include different orientations of the device in use and operation. For example, if the device in the drawings is turned over, then the elements or features described as "under" or "beneath" or "beneath" the other elements will be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "under" can include both the above and below orientations. The device can be oriented otherwise (rotated 90 degrees or in other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0049] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present disclosure. When used herein, the singular forms "a", "an", and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0050] In order to fully understand the present disclosure, detailed steps and detailed structures will be presented in the following description to illustrate the technical solution of the present disclosure. The preferred embodiments of the present disclosure are described in detail below. However, in addition to these detailed descriptions, the present disclosure may also have other implementation methods.

[0051] Before introducing the embodiments of the present disclosure, the various directions that may be involved below are defined. The extension direction of the word line structure is defined as the first direction (i.e., the X direction), the extension direction of the bit line structure is defined as the second direction (i.e., the Z direction), and the extension direction of the active layer is defined as the third direction (i.e., the Y direction). The X and Y directions intersect and are both parallel to the plane of the substrate, and the Z direction is perpendicular to the plane of the substrate, that is, the X and Y directions intersect and are both perpendicular to the Z direction. The following three-dimensional structure schematic diagram will be explained as an example in which any two of the X, Y, and Z directions are perpendicular to each other.

[0052] Figure 1 This is a flow chart of a method for manufacturing a semiconductor device provided by an embodiment of the present disclosure. Figure 1 As shown, the production method comprises at least the following steps:

[0053] Step S110: Providing a substrate, the substrate comprising a plurality of active layers arrayed along a first direction and a second direction and accommodation spaces separating the active layers; wherein each active layer comprises a first portion and a second portion arranged along a third direction; a dimension of the second portion in the first direction gradually decreases along a direction from the first portion to the second portion; the third direction intersects the first direction and is perpendicular to the second direction;

[0054] Step S120: forming a filling structure surrounding the first portion and a first sacrificial layer covering an outer surface of the filling structure within the accommodation space; wherein the first sacrificial layer is located between two adjacent active layers along the first direction and protrudes from the filling structure toward the surface of the second portion; and the remaining accommodation space between the two adjacent first sacrificial layers exposes the plurality of second portions arranged along the second direction;

[0055] Step S130: forming a bit line structure in the remaining accommodation space; wherein the bit line structure includes a first bit line portion and a second bit line portion alternately arranged along the second direction, the first bit line portion covers the second portion, and the second bit line portion connects two adjacent first bit line portions; the sum of the dimensions of the first bit line portion and the second portion covered by the first bit line portion in the first direction is greater than the dimension of the second bit line portion in the first direction.

[0056] Figures 2 to 27 All of them are structural diagrams of semiconductor devices during the manufacturing process. Figure 2 、 Figure 4 、 Figure 6 、 Figure 9and Figure 25 All of them are partial cross-sectional views of semiconductor devices during the manufacturing process; Figure 11 、 Figure 14 、 Figure 16 and Figure 19 All are partial side views of semiconductor devices during the manufacturing process; Figure 12 、 Figure 15 、 Figure 17 and Figure 20 All of the figures are partial top views of semiconductor devices during the manufacturing process; the remaining figures are schematic diagrams of the three-dimensional structure of semiconductor devices during the manufacturing process. Figures 2 to 27 The manufacturing process of semiconductor devices is described in detail.

[0057] In step S110, refer to Figures 10 to 12 As shown, a substrate is provided, which includes a plurality of active layers 214 arranged in an array along the X and Z directions and a receiving space S separating each active layer 214; wherein each active layer 214 includes a first portion 222 and a second portion 224 arranged along the Y direction; along the direction from the first portion 222 to the second portion 224, the size of the second portion 224 in the X direction gradually decreases. For a clearer illustration, Figure 11 Shown Figure 10 A partial side view of the base in Figure 12 Shown Figure 10 Partial top view of the substrate in .

[0058] Figures 2 to 10 The steps of forming the base are shown below. Figures 2 to 10 The process of forming the substrate is described in detail.

[0059] Reference Figures 2 to 4 As shown, the above-mentioned step S110 includes: providing a substrate 202, forming an initial stacked structure 204S and an initial isolation sidewall (not shown in the figure) alternately arranged along the X direction on the substrate 202, the initial stacked structure 204S including a second sacrificial layer 208 and a semiconductor layer 210 alternately stacked along the Z direction; forming a plurality of second trenches 212 extending through the initial stacked structure 204S and the initial isolation sidewall, the plurality of second trenches 212 being arranged along the Y direction, and each second trench 212 extending along the X direction; removing a portion of the second sacrificial layer 208 between two adjacent semiconductor layers 210 through the second trenches 212 to expose a portion of the semiconductor layer 210; and thinning the exposed semiconductor layer 210 along the Z direction to form an initial active layer 214S having a size smaller than that of the semiconductor layer 210 in the Z direction.

[0060] The process of forming the initial stacked structure 204S and the initial isolation sidewall includes: forming a second sacrificial layer 208 and a semiconductor layer 210 alternately stacked along the Z direction on the substrate 202; forming a plurality of isolation trenches extending through the second sacrificial layer 208 and the semiconductor layer 210, wherein the plurality of isolation trenches are arranged along the X direction and each isolation trench extends along the Y direction; and filling the isolation trenches with isolation material to form the initial isolation sidewall.

[0061] The material of the substrate 202 may include a single-element semiconductor material (e.g., silicon (Si) or germanium (Ge)), a III-V compound semiconductor material (e.g., gallium nitride (GaN), gallium arsenide (GaAs), or indium phosphide (InP), etc.), a II-VI compound semiconductor material (e.g., zinc sulfide (ZnS), cadmium sulfide (CdS), or cadmium telluride (CdTe), etc.), an organic semiconductor material, or other semiconductor materials known in the art.

[0062] The formation process of the second sacrificial layer 208 and the semiconductor layer 210 includes, but is not limited to, an epitaxial growth process, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0063] The material of semiconductor layer 210 includes, but is not limited to, single-crystal silicon, and the material of second sacrificial layer 208 includes, but is not limited to, silicon germanium (SiGe). As an example, SiGe can be epitaxially grown on a surface of single-crystal silicon. SiGe can be selectively and directionally grown on the surface of single-crystal silicon, and the process flow is simple and controllable.

[0064] It should be noted that the thickness and quantity of the second sacrificial layer 208 and the semiconductor layer 210 are not limited in this embodiment. In practical applications, they can be reasonably set according to needs. In this embodiment and below, the thickness refers to the size of a structure or film layer in the Z direction, and will not be further described hereafter.

[0065] The isolation trench formation process includes, but is not limited to, a dry etching process. The initial isolation sidewall formation process includes, but is not limited to, CVD, PVD, ALD, or any combination thereof. The initial isolation sidewall material includes, but is not limited to, silicon oxide.

[0066] The formation process of the second trench 212 includes, but is not limited to, a dry etching process. Figure 3 The second trench 212 extending along the X direction is shown. It can be understood that the initial stacked structure 204S and the initial isolation sidewall between two adjacent second trenches 212 are respectively formed as follows: Figure 3The stacked structures 204 and isolation spacers 206 shown, i.e., stacked structures 204 and isolation spacers 206 are formed alternately along the X-direction between two adjacent second trenches 212. The second trenches 212 expose the stacked structures 204 and isolation spacers 206 alternately arranged along the X-direction. It should be noted that in this embodiment, there is no limit on the number of stacked structures 204 and isolation spacers 206 alternately arranged along the X-direction. In practical applications, a reasonable design can be made based on actual needs.

[0067] The process of removing part of the second sacrificial layer 208 may include but is not limited to a wet etching process. For example, the second sacrificial layer 208 exposed by the second trench 212 may be etched laterally (i.e., along the Y direction) using a wet etching process, thereby exposing part of the semiconductor layer 210 and forming an initial first gap between the exposed part of the semiconductor layer 210, and the initial first gap is connected to the second trench 212.

[0068] The process of thinning the semiconductor layer 210 may include but is not limited to a dry etching process. The structure after thinning the semiconductor layer 210 is as follows: Figure 3 and Figure 4 As shown, the thickness of the thinned semiconductor layer 210 is less than the thickness of the unthinned semiconductor layer 210 , that is, the thickness of the initial active layer 214S is less than the thickness of the semiconductor layer 210 .

[0069] Thinning the semiconductor layer 210 can expand the initial first gap to Figure 3 and Figure 4 The height of the first gap S1 shown is greater than the thickness of the second sacrificial layer 208 (or the second insulating layer 216 hereinafter). In this embodiment and below, the height refers to the dimension of a gap or trench in the Z direction, and will not be further described. It should be noted that a portion of the wordline structure 234 will be formed within the first gap S1. By thinning the semiconductor layer 210, the space for forming the wordline structure 234 can be increased, which helps reduce coupling between adjacent wordline structures 234.

[0070] In some embodiments, combined Figure 2 and Figure 3 As shown, the above-mentioned manufacturing method further includes: forming a plurality of third trenches extending through the initial stacked structure 204S and the initial isolation spacer, the plurality of third trenches and the plurality of second trenches 212 being arranged alternately along the Y direction, and each third trench extending along the X direction; removing a portion of the second sacrificial layer 208 through the third trenches, and forming a second insulating layer 216 at the location where the second sacrificial layer 208 was removed. Here, the third trenches and the second insulating layer 216 can be formed first, and then the sacrificial stack can be filled in the third trenches before forming the second trenches 212. Otherwise, the formed second insulating layer 216 will fill the first gap S1. The sacrificial stack can include a silicon oxide layer and a polysilicon layer.

[0071] The process for forming the third trench includes but is not limited to a dry etching process, and the process for removing the second sacrificial layer 208 may include but is not limited to a wet etching process. The insulating material is filled in the removed position of the second sacrificial layer 208 to form a Figure 3 As shown, the second insulating layer 216 and the unthinned semiconductor layer 210 are alternately stacked along the Z direction.

[0072] Figure 3 FIG. 2 shows that the second insulating layer 216 and the sacrificial stack are first formed, and then the second trench 212 and the first gap S1 are formed. The first gap S1 exposes the second insulating layer 216. During the thinning process of the semiconductor layer 210, the exposed second insulating layer 216 may be slightly etched, so that the thickness of the second insulating layer 216 gradually decreases toward the end of the second trench 212.

[0073] In some embodiments, reference Figure 3 、 Figure 5 and Figure 6 As shown, step S110 further includes forming a third sacrificial layer 218 between two adjacent initial active layers 214S; wherein the size of the initial active layer 214S in the Y direction is equal to the size of the third sacrificial layer 218 in the Y direction, that is, the length of the third sacrificial layer 218 is equal to the length of the initial active layer 214S. In this embodiment and below, the length refers to the size of a structure or film layer in the Y direction, and will not be further described.

[0074] The formation process of the third sacrificial layer 218 includes but is not limited to CVD, PVD, ALD or any combination thereof. The material of the third sacrificial layer 218 includes but is not limited to silicon nitride. For example, silicon nitride is filled into the first gap S1 to form a Figure 5 and Figure 6 The third sacrificial layer 218 is shown. In practical applications, silicon nitride may cover the exposed surface of the second trench 212, and the silicon nitride on the surface of the second trench 212 may be removed by etching back.

[0075] In some embodiments, reference Figure 5 、 Figures 7 to 9 As shown, the above step S110 also includes: removing a portion of the initial isolation sidewall through the second trench 212 to expose portions of two opposite sidewalls of the initial active layer 214S along the X direction; and removing the exposed portion of the initial active layer 214S along the X direction and the Y direction to form the active layer 214.

[0076] Reference Figure 5 As shown, the isolation spacer 206 exposed by etching back the second trench 212 can be formed as shown in FIG. Figure 7The fourth trench S2 shown is connected to the second trench 212 and is shorter than the length of the initial active layer 214S. The fourth trench S2 exposes portions of two opposing sidewalls of each initial active layer 214S stacked along the Z direction, along the X direction. That is, the fourth trench S2 does not completely expose the two opposing sidewalls of the initial active layer 214S along the X direction. The formation process of the fourth trench S2 includes, but is not limited to, a dry etching process.

[0077] By using the connected second trench 212 and the fourth trench S2, the exposed initial active layer 214S is trimmed by a wet etching process to form a Figure 10 Here, the initial active layer 214S is trimmed along the Y direction to reduce the length of the initial active layer 214S, so that the length of the active layer 214 is smaller than the length of the initial active layer 214S, that is, the size of the active layer 214 in the Y direction is smaller than the size of the initial active layer 214S in the Y direction, and the following is formed: Figure 8 and Figure 9 trimming the initial active layer 214S along the X direction to reduce the width of the initial active layer 214S, so that the width of the active layer 214 is smaller than the width of the initial active layer 214S, and forming a Figure 9 Here, since the second groove S4 is blocked by the third sacrificial layer 218, Figure 8 The second groove S4 cannot be seen in the three-dimensional image. The width in this embodiment and the following text refers to the size of a structure or film layer in the X direction, which will not be described in detail hereafter.

[0078] In some embodiments, combined Figures 8 to 10 As shown, the above step S110 further includes: etching back a portion of the isolation sidewall 206 to form a fifth trench T5, the fifth trench T5 exposing two opposite sidewalls of the initial active layer 214S along the X direction; removing the third sacrificial layer 218 to form an accommodating space S. Here, after removing the third sacrificial layer 218, a structure as shown in FIG. Figure 10 Active layer 214 is shown. Figure 10 The active layer 214 in FIG. 2 may include a first portion 222 and a second portion 224 arranged along the Y direction.

[0079] The process of etching back the isolation sidewall 206 may include but is not limited to a dry etching process, and the process of removing the third sacrificial layer 218 may include but is not limited to a wet etching process. Etching back a portion of the isolation sidewall 206 may form a fifth trench T5. The fifth trench T5, the exposed first gap S1, the first groove S3 and the second groove S4 are connected to each other and form an accommodating space S. The accommodating space S is connected to the second trench 212. In order to more clearly illustrate the accommodating space S, Figure 10 and Figure 11 The first gap S1 , the first groove S3 , the second groove S4 and the fifth trench T5 to be exposed are marked with white dotted frames respectively.

[0080] In some embodiments, the second insulating layer 216 and the isolation sidewall 206 are made of the same material, for example, silicon oxide. During the etching back of the isolation sidewall 206, a portion of the second insulating layer 216 may be etched, exposing a portion of the semiconductor layer 210. The exposed semiconductor layer 210 and the trimmed initial active layer 214S together form a Figure 10 Active layer 214 is shown. Figure 10 The active layer 214 may include a third portion 226, a first portion 222, and a second portion 224 arranged in sequence along the Y direction. The thickness of the first portion 222 and the second portion 224 are both less than the thickness of the third portion 226. The width of the first portion 222 is less than or equal to the width of the third portion 226, and the width of the second portion 224 gradually decreases along the direction from the first portion 222 to the second portion 224.

[0081] For ease of understanding, the following description will be made by taking an example in which the active layer 214 includes a third portion 226 , a first portion 222 , and a second portion 224 sequentially arranged along the Y direction.

[0082] In other embodiments, the substrate in the above step S110 may also be directly provided to perform step S120.

[0083] In step S120, refer to Figure 23 As shown, a filling structure 238 surrounding the first portion 222 and a first sacrificial layer 232 covering the outer surface of the filling structure 238 are formed in the accommodating space S; wherein the first sacrificial layer 232 is located between two adjacent active layers 214 along the X direction and protrudes from the filling structure 238 toward the surface of the second portion 224; the remaining accommodating space S between two adjacent first sacrificial layers 232 exposes multiple second portions 224 arranged along the Z direction.

[0084] Figures 13 to 23 The steps of forming the filling structure 238 and the first sacrificial layer 232 in the accommodating space S are shown. Figures 13 to 23 The formation process of the filling structure 238 and the first sacrificial layer 232 will be described in detail.

[0085] Reference Figure 13 and Figure 18As shown, the above-mentioned step S120 includes: sequentially forming an initial first dielectric layer 228S, an initial first insulating layer 230S and an initial first sacrificial layer 232S in the accommodating space S; wherein the initial first dielectric layer 228S covers the exposed surface of the accommodating space S; the initial first dielectric layer 228S, the initial first insulating layer 230S and the initial first sacrificial layer 232S together fill the first gap S1 between two adjacent active layers 214 along the Z direction.

[0086] The formation process of the initial first dielectric layer 228S includes but is not limited to CVD, PVD, ALD or any combination thereof. For example, the ALD process is used to deposit the dielectric layer 228S. Figure 13 As shown, the initial first dielectric layer 228S may conformally cover the exposed surface of the accommodating space S. The material of the initial first dielectric layer 228S includes, but is not limited to, silicon nitride.

[0087] To make it clearer, Figure 14 Shown Figure 13 A partial side view after forming the initial first dielectric layer 228S, Figure 15 Shown Figure 13 A partial top view after the initial first dielectric layer 228S is formed. Figure 14 and Figure 15 As shown, an initial first dielectric layer 228S wraps around the exposed surface of each active layer 214 .

[0088] The formation process of the initial first insulating layer 230S includes but is not limited to CVD, PVD, ALD or any combination thereof. For example, the ALD process is used to deposit the first insulating layer 230S. Figure 13 The initial first insulating layer 230S shown may conformally cover the initial first dielectric layer 228S, and each first gap S1 is filled with the initial first dielectric layer 228S and the initial first insulating layer 230S. The material of the initial first insulating layer 230S includes but is not limited to silicon oxide.

[0089] To make it clearer, Figure 16 Shown Figure 13 A partial side view after forming the initial first insulating layer 230S, Figure 17 Shown Figure 13 A partial top view after forming the initial first insulating layer 230S. Figure 16 and Figure 17As shown, the exposed surface of each active layer 214 is sequentially wrapped with an initial first dielectric layer 228S and an initial first insulating layer 230S. Due to trimming of the initial active layer 214S, a first groove S3 and a second groove S4 are formed. After conformally depositing the initial first dielectric layer 228S and the initial first insulating layer 230S, each active layer 214 wrapped with the initial first dielectric layer 228S and the initial first insulating layer 230S has a "quasi-spherical" end.

[0090] The formation process of the initial first sacrificial layer 232S includes but is not limited to CVD, PVD, ALD or any combination thereof. For example, the ALD process is used to deposit the first sacrificial layer 232S. Figure 18 The initial first sacrificial layer 232S shown may conformally cover the initial first insulating layer 230S. The material of the initial first sacrificial layer 232S includes, but is not limited to, amorphous carbon.

[0091] To make it clearer, Figure 19 Shown Figure 18 A partial side view after forming the initial first sacrificial layer 232S, Figure 20 Shown Figure 18 A partial top view after the initial first sacrificial layer 232S is formed. Figure 18 and Figure 19 As shown, the initial first sacrificial layer 232S may substantially fill the remaining accommodating space S (eg, the fifth trench T5 where the initial first dielectric layer 228S and the initial first insulating layer 230S are formed) and cover the exposed surface of the second trench 212 .

[0092] In some embodiments, reference Figure 18 and Figure 21 As shown, the above-mentioned step S120 further includes: etching the initial first sacrificial layer 232S and the initial first insulating layer 230S to expose the initial first dielectric layer 228S; wherein the retained initial first insulating layer 230S covers the initial first dielectric layer 228S on the active layer 214; the retained initial first sacrificial layer 232S constitutes the first sacrificial layer 232; and removing a portion of the initial first dielectric layer 228S to expose the second portion 224 and at least a portion of the first portion 222; wherein the retained initial first dielectric layer 228S constitutes the first dielectric layer 228, and the first dielectric layer 228 extends along the X-direction and surrounds the first region of the active layer 214.

[0093] Combine Figure 18 As shown, a first etching process may be performed on the initial first sacrificial layer 232S until the initial first insulating layer 230S is exposed, and the remaining initial first sacrificial layer 232S is formed as shown in FIG. Figure 21The first sacrificial layer 232 is shown. Here, the initial first insulating layer 230S can serve as an etch stop layer for a first etching process, which includes but is not limited to a dry etching process.

[0094] Still combined Figure 18 As shown, a second etching process may be performed on the exposed initial first insulating layer 230S until the initial first dielectric layer 228S is exposed, and the retained initial first insulating layer 230S covers the initial first dielectric layer 228S on the active layer 214. The retained initial first insulating layer 230S is as shown in FIG. Figure 21 Here, the initial first dielectric layer 228S can serve as an etch stop layer for the second etching process, and the second etching process includes but is not limited to a dry etching process.

[0095] Still combined Figure 18 As shown, the exposed initial first dielectric layer 228S is etched back, and a plurality of word line accommodating spaces arranged along the Z direction are formed at the position where the initial first dielectric layer 228S is removed, and the word line accommodating spaces expose the second portion 224 and at least a portion of the first portion 222. The retained initial first dielectric layer 228S is formed as shown in FIG. Figure 21 Here, the plurality of word line accommodating spaces can be separated from each other by the retained initial first insulating layer 230S, so that the subsequently formed word line structures 234 can be separated from each other by the first insulating layer 230, thus reducing the steps of forming word line isolation structures.

[0096] It should be noted that, when the active layer 214 includes the first portion 222, the second portion 224 and the third portion 226, the initial first dielectric layer 228S can be etched back to expose the second portion 224 and the first portion 222, and the first dielectric layer 228 can surround the third portion 226, as shown in FIG. Figure 21 As shown, the third portion 226 can be doped to form a first region. In the case where the active layer 214 includes the first portion 222 and the second portion 224, the initial first dielectric layer 228S can be etched back to expose the second portion 224 and a portion of the first portion 222. The first dielectric layer 228 can surround the unexposed first portion 222, and the unexposed first portion 222 can be doped to form a first region. Here, the first region can be one of a source and a drain.

[0097] For ease of understanding, the following description will be made by taking the example of the first dielectric layer 228 surrounding the third portion 226 .

[0098] In some embodiments, reference Figure 22 As shown, the above step S120 further includes: forming a word line structure 234 coupled to the channel region of the exposed first portion 222 .

[0099] The word line structure 234 may include a gate dielectric layer and a gate structure, wherein the gate dielectric layer is located between the channel region and the gate structure, and multiple gate structures arranged along the X direction are coupled to each other to form a word line, and the gate structure and the word line may refer to the same structure. Part of the word line located on the sidewall of the channel region can serve as a gate structure in the transistor. In other words, multiple transistors arranged along the X direction can be coupled to the same word line. Depending on the number of sidewalls of the channel region covered by the gate structure, the transistor can be divided into a single-gate transistor, a double-gate transistor, a triple-gate transistor, or a full-surround gate (Gate All Around, GAA) transistor. In practical applications, the type of transistor can be reasonably set according to needs.

[0100] The gate dielectric layer may be formed by processes including, but not limited to, thermal oxidation, CVD, PVD, ALD, or any combination thereof. The gate dielectric layer may be formed from, but not limited to, silicon oxide. For example, exposed silicon may be thermally oxidized to form a silicon oxide gate dielectric layer.

[0101] The gate structure may be formed using a process including, but not limited to, CVD, PVD, ALD, or any combination thereof. The gate structure may be formed using a material including, but not limited to, titanium nitride (TiN), metal tungsten, or a combination thereof.

[0102] It should be noted that coupling in this article refers to the operative connection of multiple conductive structures. Depending on actual needs, it may include but is not limited to the following situations: (1) two conductive structures are directly electrically connected; (2) two conductive structures are indirectly electrically connected, for example, through other conductive structures; (3) although the two conductive structures are not electrically connected, one conductive structure can control the electrical properties of the other conductive structure in response to an electrical signal, for example, a gate dielectric layer is provided between the channel region and the gate structure.

[0103] In some embodiments, reference Figure 23 As shown, step S120 further includes forming a second dielectric layer 236 surrounding the second region of the exposed first portion 222; wherein the second dielectric layer 236 is located between the word line structure 234 and the bit line structure 244. Here, the first portion 222 may be doped to form a channel region and a second region, respectively, and the second region may be the other of a source and a drain.

[0104] The second dielectric layer 236 may be formed by, but is not limited to, CVD, PVD, ALD, or any combination thereof. The second dielectric layer 236 may be formed by, but is not limited to, silicon nitride.

[0105] In some embodiments, the second portion 224 may be doped, and the doped second portion 224 and the second region may together constitute, for example, a drain of a transistor. In other embodiments, the end of the second portion 224 relatively close to the first portion 222 may be doped, and the doped second portion 224 and the second region may together constitute, for example, a drain of a transistor. Here, the other end of the second portion 224 relatively far from the first portion 222 may react with the conductive material filling the bitline accommodating space described below to form a metal silicide. The metal silicide may reduce the contact resistance between the active layer 214 and the bitline structure 244.

[0106] Of course, in other embodiments, the second portion 224 may entirely react with the conductive material filling the bit line accommodating space to generate metal silicide.

[0107] In some embodiments, reference Figure 22 and Figure 23 As shown, the above manufacturing method further includes: removing the initial first insulating layer 230S protruding from the surface of the second dielectric layer 236 to form a first insulating layer 230; wherein the first insulating layer 230 is located between two adjacent word line structures 234 and between two adjacent second dielectric layers 236.

[0108] exist Figure 22 The word line structure 234 is formed as follows Figure 23 After the second dielectric layer 236 is formed, the remaining initial first insulating layer 230S may protrude from the surface of the second dielectric layer 236, and the protruding initial first insulating layer 230S may be etched back to form a substrate as shown in FIG. Figure 23 The first insulating layer 230 shown in FIG. 1 has an exposed surface that is recessed compared to the exposed surface of the second dielectric layer 236. The first insulating layer 230 can be used as a word line isolation structure. Of course, in other embodiments, the first insulating layer 230 can also be Figure 23 The surface of the second dielectric layer 236 is substantially flat.

[0109] It can be understood that the first dielectric layer 228, the first insulating layer 230, the word line structure 234, and the second dielectric layer 236 formed in the accommodating space S constitute a filling structure 238. The first sacrificial layer 232 covers the outer surface of the filling structure 238, and the inner surface of the filling structure 238 contacts the first portion 222. The first sacrificial layer 232 protrudes from the surface of the filling structure 238 toward the second portion 224, thereby leaving a portion of the accommodating space S between two adjacent first sacrificial layers 232. The remaining accommodating space S constitutes a bit line accommodating space. The bit line accommodating space and the first sacrificial layer 232 are alternately arranged along the X direction, and the bit line accommodating space exposes multiple second portions 224 arranged along the Z direction, as shown in FIG. Figure 23 shown.

[0110] In step S130, refer to Figure 24 As shown, a bit line structure 244 is formed in the remaining accommodation space S; wherein the bit line structure 244 includes a first bit line portion 240 and a second bit line portion 242 alternately arranged along the Z direction, the first bit line portion 240 covers the second portion 224, and the second bit line portion 242 connects two adjacent first bit line portions 240; the sum of the dimensions of the first bit line portion 240 and the second portion 224 covered by the first bit line portion 240 in the X direction is greater than the dimension of the second bit line portion 242 in the X direction.

[0111] Figures 24 to 27 The steps of forming the bit line structure 244 in the remaining accommodation space S are shown below. Figures 24 to 27 The formation process of the bit line structure 244 will be described in detail.

[0112] Through Figure 23 The bit line accommodation space shown is filled with conductive material to form a Figure 24 The self-aligned bit line structure 244 is shown. In this way, a self-aligned bit line (BL) can be formed, thereby avoiding the high difficulty and high aspect ratio bit line etching process.

[0113] As mentioned above, each active layer 214 wrapped with the initial first dielectric layer 228S and the initial first insulating layer 230S has a "quasi-spherical" end; after forming the first sacrificial layer 232, the spherical end can be exposed; after removing the initial first dielectric layer 228S and the initial first insulating layer 230S at the "quasi-spherical" end, a plurality of annular spaces can be formed, and two adjacent annular spaces in the Z direction overlap and are connected, thereby forming a shape as shown in FIG. Figure 23 After the bit line accommodating space is filled with conductive material, a self-aligned bit line structure 244 can be formed. The conductive material located in the annular space is the first bit line portion 240, and the conductive material located at the overlapping and connected portion of two adjacent annular spaces is the second bit line portion 242. For a clearer illustration, Figure 25 Shown Figure 14 FIG. 2 is a partial cross-sectional view of the bit line structure 244 in the XZ plane.

[0114] It should be noted that the annular space in this article may include a circular annular space, an elliptical annular space, a square annular space or any other annular space, and the present disclosure has no limitation on this.

[0115] In some embodiments, combined Figure 24 、 Figure 26 and Figure 27As shown, the above-mentioned step S130 includes: filling the remaining accommodating space S with a conductive material to form an initial bit line structure, wherein the initial bit line structure and the first sacrificial layer 232 are alternately arranged along the X direction; removing the first sacrificial layer 232 to form a first trench S5 between two adjacent initial bit line structures; removing part of the initial bit line structure through the first trench S5; wherein the retained initial bit line structure constitutes the bit line structure 244'.

[0116] By removing the first sacrificial layer 232, a Figure 26 The first trench S5 shown in FIG. 1 exposes two sidewalls of the initial bit line structure opposite to each other along the X direction. By etching back the initial bit line structure through the first trench S5, a structure as shown in FIG. 1 can be formed. Figure 27 A bit line structure 244' is shown.

[0117] Etching back the initial bit line structure can increase the width of the first trench S5, that is, increase the distance between adjacent bit line structures 244', thereby reducing the coupling between adjacent bit line structures 244'. It can be understood that, Figure 25 The width of the bit line structure 244 formed without etching back is greater than Figure 27 After the initial bit line structure is etched back, a dielectric material may be filled to form a Figure 27 The third dielectric layer 246 is shown, and the material of the third dielectric layer 246 includes but is not limited to silicon nitride. Here, the step of etching back the initial bit line structure can also be omitted.

[0118] In some embodiments, the above-mentioned manufacturing method further includes: removing the semiconductor layer 210 between two adjacent second insulating layers 216 through a third trench to form a second gap between the two adjacent second insulating layers 216; wherein the second gap and the third trench are connected; and forming a capacitor structure in the connected second gap and third trench.

[0119] In this embodiment, after forming the bitline structure 244 / 244', the second trench 212 can be filled with an insulating material; then, the sacrificial stack is removed to open the third trench, thereby exposing the second insulating layer 216 and the semiconductor layer 210 between two adjacent second insulating layers 216. By removing the semiconductor layer 210, a second gap can be formed between the two adjacent second insulating layers 216, and the second gap and the third trench are connected; a capacitor structure is formed within the connected second gap and third trench. For example, a first electrode layer, a capacitor dielectric layer, and a second electrode layer are sequentially deposited conformally, with the first electrode layer connected to the first region of the active layer 214. Here, the second gap can expose the third portion 226, and before forming the capacitor structure, the third portion 226 can be doped to form the first region.

[0120] It should be noted that in current 3D DRAMs, a bitline layer is typically first formed in the second trench. This layer is then separated into multiple bitlines through photolithography and etching processes. However, as the number of stacked layers increases and the size decreases, the aspect ratio of the second trench increases, making it more difficult to etch multiple bitlines in a second trench with a high aspect ratio.

[0121] In an embodiment of the present disclosure, a substrate with an accommodating space is provided, and each active layer on the substrate includes a first part and a second part arranged along a third direction, and the width of the second part gradually decreases along the direction from the first part to the second part; a filling structure surrounding the first part and a first sacrificial layer covering the outer surface of the filling structure are formed in the accommodating space, the first sacrificial layer is located between two adjacent active layers along the first direction and protrudes from the surface of the filling structure toward the second part, and the remaining accommodating space between the two adjacent first sacrificial layers exposes multiple second parts arranged along the second direction; a bit line structure is formed in the remaining accommodating space, the bit line structure includes a first bit line part and a second bit line part alternately arranged along the second direction, the first bit line part covers the second part, and the second bit line part connects the two adjacent first bit line parts; the sum of the widths of the first bit line part and the second part covered by the first bit line part is greater than the width of the second bit line part. In this way, firstly, the width of the second portion gradually decreases, and a "tip" can be formed at the end of the active layer, providing more spatial flexibility for the subsequent filling of the bit line structure; secondly, the first sacrificial layer protrudes from the filling structure toward the surface of the second portion, and the remaining accommodation space between two adjacent first sacrificial layers exposes multiple second portions arranged along the second direction, which can accurately control the shape and position of the bit line structure, that is, form a self-aligned bit line (self-align BL), thereby avoiding the high difficulty and high aspect ratio bit line etching process; thirdly, the first bit line partially covers the second portion, which can increase the contact area between the bit line structure and the active layer, which is beneficial to reducing the contact resistance between the bit line structure and the active layer and improving the electrical performance; fourthly, it can simplify the manufacturing process and reduce the difficulty of bit line manufacturing, and provide a new solution for achieving high integration and small size 3D DRAM.

[0122] Based on the above-mentioned method for manufacturing a semiconductor device, an embodiment of the present disclosure provides a semiconductor device, which can be manufactured using the method in any of the above-mentioned embodiments.

[0123] Figure 28 FIG3 is a schematic diagram of a three-dimensional structure of a semiconductor device provided by an embodiment of the present disclosure. The semiconductor device includes but is not limited to a 3D DRAM.

[0124] Reference Figure 28As shown, the semiconductor device 300 includes a plurality of active layers 302 and a plurality of bitline structures 304; the plurality of active layers 302 are arranged in an array along the X-direction and the Z-direction; each active layer 302 includes a first portion 306 and a second portion 308 arranged along the Y-direction; the size of the second portion 308 in the X-direction gradually decreases along the direction from the first portion 306 to the second portion 308; the Y-direction and the X-direction intersect and are both perpendicular to the Z-direction; the plurality of bitline structures 304 are arranged along the X-direction; each bitline structure 304 includes a first bitline portion 310 and a second bitline portion 312 alternately arranged along the Z-direction; the first bitline portion 310 covers the second portion 308, and the second bitline portion 312 connects two adjacent first bitline portions 310; the sum of the sizes of the first bitline portion 310 and the second portion 308 covered by the first bitline portion 310 in the X-direction is greater than the size of the second bitline portion 312 in the X-direction.

[0125] Here, the bitline structure 304 can be formed using the self-aligned process mentioned above. Therefore, the bitline structure 304 can be a self-aligned bitline. On the one hand, this can reduce the difficulty of manufacturing the bitline structure 304; on the other hand, it can improve the alignment accuracy between the bitline structure 304 and the active layer 302. The improved alignment accuracy not only ensures a more stable and reliable electrical connection between the bitline structure 304 and the active layer 302, but also effectively reduces leakage, thereby improving the overall performance of the semiconductor device 300.

[0126] In some embodiments, reference Figure 28 As shown, the semiconductor device 300 further includes a first dielectric layer 314 extending along the X direction; wherein the first dielectric layer 314 surrounds the first regions of the plurality of active layers 302 arranged along the X direction.

[0127] The first dielectric layer 314 is used to isolate the first region from other conductive structures, preventing the first region from contacting other conductive structures and causing a short circuit. For example, the first dielectric layer 314 can isolate the first region from both the first electrode layer and the wordline structure 316. For details about the first dielectric layer 314, refer to the description of the first dielectric layer 228 above and will not be repeated here.

[0128] The first region may be one of a source and a drain. For example, the first region may be a source of a transistor, and the source is connected to the capacitor structure 324 .

[0129] In some embodiments, reference Figure 28 As shown, the semiconductor device 300 further includes a word line structure 316 , which extends along the X direction. The word line structure 316 is coupled to the channel regions of the plurality of first portions 306 arranged along the X direction.

[0130] The wordline structure 316 may include a gate dielectric layer and a gate structure. The gate dielectric layer is located between the channel region and the gate structure. Multiple gate structures arranged along the X direction are connected to each other to form a wordline. The active layer 302, the gate dielectric layer, and the gate structure may form a transistor, and the capacitor structure 324 connected to the transistor may form a memory cell. For details about the wordline structure 316, please refer to the description of the wordline structure 234 above and will not be repeated here.

[0131] It should be noted that multiple memory cells arranged along the X direction are coupled to the same word line, while multiple memory cells arranged along the Z direction are coupled to different word lines; multiple memory cells arranged along the Z direction are coupled to the same bit line structure 304, while multiple memory cells arranged along the X direction are coupled to different bit line structures 304. In this way, three-dimensional integration of the semiconductor device 300 can be achieved, which is conducive to improving storage density.

[0132] In some embodiments, reference Figure 28 As shown, the semiconductor device 300 further includes a second dielectric layer 318 , which surrounds the second region of the first portion 306 ; wherein the second dielectric layer 318 is located between the word line structure 316 and the bit line structure 304 .

[0133] Second dielectric layer 318 is used to isolate the second region from other conductive structures, preventing the second region from contacting other conductive structures and causing a short circuit. For example, second dielectric layer 318 can isolate the second region from both bitline structure 304 and wordline structure 316. For details about second dielectric layer 318, refer to the description of second dielectric layer 236 above and will not be repeated here.

[0134] The second region may be the other of a source and a drain. For example, the second region may be a drain of a transistor, and the drain is connected to the bit line structure 304 .

[0135] In some embodiments, the second portion 308 may be doped, and the doped second portion 308 and the second region may together constitute, for example, a drain of a transistor.

[0136] In other embodiments, the end of the second portion 308 relatively close to the first portion 306 may be doped, and the doped second portion 308 and the second region may together constitute, for example, a drain of a transistor. Here, the other end of the second portion 308 relatively far from the first portion 306 may react with metal to form a metal silicide, which may reduce the contact resistance between the active layer 302 and the bit line structure 304.

[0137] Of course, in other embodiments, the second portion 308 may also react entirely with the metal to generate metal silicide.

[0138] In some embodiments, reference Figure 28As shown, the semiconductor device 300 further includes a first insulating layer 320, which is located between two adjacent wordline structures 316 along the Z direction. The first insulating layer 320 can serve as a wordline isolation structure, which is used to isolate two adjacent wordline structures 316. For details about the first insulating layer 320, reference can be made to the description of the first insulating layer 230 above, and will not be repeated here.

[0139] In some embodiments, reference Figure 28 As shown, the semiconductor device 300 further includes a third dielectric layer 322, which is located between two adjacent bitline structures 304 along the X direction. The third dielectric layer 322 can serve as a bitline isolation structure, which is used to isolate two adjacent bitline structures 304. For details about the third dielectric layer 322, please refer to the description of the third dielectric layer above and will not be repeated here.

[0140] In some embodiments, the semiconductor device 300 further includes a capacitor structure 324 . The capacitor structure 324 and the bit line structure 304 are respectively located at opposite ends of the active layer 302 along the Y direction. The capacitor structure 324 is connected to the first region.

[0141] The capacitor structure 324 may include a first electrode layer, a capacitor dielectric layer and a second electrode layer. The capacitor dielectric layer is located between the first electrode layer and the second electrode layer. The first electrode layer may be connected to the source, and the second electrode layer may be connected to the common terminal.

[0142] The various structures of the semiconductor device can refer to the above embodiments. Since the semiconductor device of this embodiment is formed using the manufacturing method in any of the above embodiments, it has at least all the beneficial effects brought by the technical solutions of the embodiments of the above manufacturing methods, which will not be described one by one here.

[0143] It should be understood that “one embodiment” or “an embodiment” mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present disclosure. Therefore, “in one embodiment” or “in an embodiment” appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present disclosure, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments.

[0144] The above description is only a preferred embodiment of the present disclosure and does not limit the patent scope of the present disclosure. All equivalent structural transformations made by using the contents of the present disclosure and the drawings under the inventive concept of the present disclosure, or direct / indirect application in other related technical fields are included in the patent protection scope of the present disclosure.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: include: A substrate is provided, the substrate comprising a plurality of active layers arranged in an array along a first direction and a second direction, and accommodation spaces separating the active layers; wherein each active layer comprises a first portion and a second portion arranged along a third direction; a size of the second portion in the first direction gradually decreases from the first portion to the second portion; the third direction intersects the first direction and is perpendicular to the second direction; A filling structure surrounding the first portion and a first sacrificial layer covering an outer surface of the filling structure are formed in the accommodating space; wherein the first sacrificial layer is located between two adjacent active layers along the first direction and protrudes from the filling structure toward the surface of the second portion; the remaining accommodating space between two adjacent first sacrificial layers exposes a plurality of second portions arranged along the second direction; A bit line structure is formed in the remaining accommodating space; wherein, the bit line structure includes a first bit line portion and a second bit line portion alternately arranged along the second direction, the first bit line portion covers the second portion, and the second bit line portion connects two adjacent first bit line portions; the sum of the dimensions of the first bit line portion and the second portion covered by the first bit line portion in the first direction is greater than the dimension of the second bit line portion in the first direction.

2. The method for manufacturing a semiconductor device according to claim 1, wherein: The method of forming a filling structure surrounding the first portion in the accommodating space and a first sacrificial layer covering an outer surface of the filling structure includes: An initial first dielectric layer, an initial first insulating layer, and an initial first sacrificial layer are sequentially formed in the accommodating space; wherein the initial first dielectric layer covers the exposed surface of the accommodating space; and the initial first dielectric layer, the initial first insulating layer, and the initial first sacrificial layer together fill a first gap between two adjacent active layers along the second direction; Etching the initial first sacrificial layer and the initial first insulating layer to expose the initial first dielectric layer; wherein the retained initial first insulating layer covers the initial first dielectric layer on the active layer; and the retained initial first sacrificial layer constitutes the first sacrificial layer; removing a portion of the initial first dielectric layer to expose the second portion and at least a portion of the first portion; wherein the remaining initial first dielectric layer constitutes a first dielectric layer, and the first dielectric layer extends along the first direction and surrounds the first region of the active layer; forming a word line structure coupled to the exposed channel region of the first portion; A second dielectric layer is formed around the second region of the exposed first portion; wherein the second dielectric layer is located between the word line structure and the bit line structure.

3. The method for manufacturing a semiconductor device according to claim 2, wherein: The production method further comprises: The initial first insulating layer protruding from the surface of the second dielectric layer is removed to form a first insulating layer; wherein the first insulating layer is located between two adjacent word line structures and between two adjacent second dielectric layers.

4. The method for manufacturing a semiconductor device according to any one of claims 1 to 3, wherein: The step of forming a bit line structure in the remaining accommodation space comprises: Filling the remaining accommodating space with a conductive material to form an initial bit line structure, wherein the initial bit line structure and the first sacrificial layer are alternately arranged along the first direction; removing the first sacrificial layer to form a first trench between two adjacent initial bit line structures; A portion of the initial bit line structure is removed through the first trench; wherein the remaining initial bit line structure constitutes the bit line structure.

5. The method for manufacturing a semiconductor device according to any one of claims 1 to 3, wherein: The providing of a substrate comprises: Providing a substrate, forming an initial stacked structure and initial isolation sidewalls alternately arranged along the first direction on the substrate, wherein the initial stacked structure includes second sacrificial layers and semiconductor layers alternately stacked along the second direction; forming a plurality of second trenches extending through the initial stacked structure and the initial isolation spacer, wherein the plurality of second trenches are arranged along the third direction, and each second trench extends along the first direction; removing a portion of the second sacrificial layer between two adjacent semiconductor layers through the second trench to expose a portion of the semiconductor layer; thinning the exposed semiconductor layer along the second direction to form an initial active layer having a size smaller than that of the semiconductor layer in the second direction; A third sacrificial layer is formed between two adjacent initial active layers; wherein a size of the initial active layer in the third direction is substantially equal to a size of the third sacrificial layer in the third direction.

6. The method for manufacturing a semiconductor device according to claim 5, wherein: The providing of the substrate further comprises: removing a portion of the initial isolation spacer through the second trench to expose portions of two sidewalls of the initial active layer that are opposite to each other along the first direction; The exposed portion of the initial active layer is removed along the first direction and the third direction to form the active layer.

7. The method for manufacturing a semiconductor device according to claim 6, wherein: A size of the active layer in the third direction is smaller than a size of the initial active layer in the third direction.

8. The method for manufacturing a semiconductor device according to claim 5, wherein: The production method further comprises: forming a plurality of third trenches extending through the initial stacked structure and the initial isolation spacer, wherein the plurality of third trenches and the plurality of second trenches are alternately arranged along the third direction, and each of the third trenches extends along the first direction; removing a portion of the second sacrificial layer through the third trench, and forming a second insulating layer at a position where the second sacrificial layer is removed; The semiconductor layer between two adjacent second insulating layers is removed through the third trench to form a second gap between the two adjacent second insulating layers; wherein the second gap is connected to the third trench; A capacitor structure is formed in the communicated second gap and the third trench.

9. A semiconductor device, characterized in that: include: A plurality of active layers are arranged in an array along a first direction and a second direction; wherein each of the active layers includes a first portion and a second portion arranged along a third direction; a size of the second portion in the first direction gradually decreases along a direction from the first portion to the second portion; the third direction intersects the first direction and is perpendicular to the second direction; A plurality of bit line structures are arranged along the first direction; wherein each of the bit line structures includes a first bit line portion and a second bit line portion alternately arranged along the second direction; the first bit line portion covers the second portion, and the second bit line portion connects two adjacent first bit line portions; and the sum of the dimensions of the first bit line portion and the second portion covered by the first bit line portion in the first direction is greater than the dimension of the second bit line portion in the first direction.

10. The semiconductor device according to claim 9, wherein The semiconductor device further includes: a first dielectric layer, the first dielectric layer extending along the first direction; wherein the first dielectric layer surrounds the first regions of the plurality of active layers arranged along the first direction; a word line structure extending along the first direction; wherein the word line structure is coupled to a plurality of channel regions of the first portion arranged along the first direction; A second dielectric layer surrounds the second region of the first portion; wherein the second dielectric layer is located between the word line structure and the bit line structure.

11. The semiconductor device according to claim 10, wherein: The semiconductor device further includes: A capacitor structure, wherein the capacitor structure and the bit line structure are respectively located at two opposite ends of the active layer along the third direction; wherein the capacitor structure is connected to the first region.

Images