Integrated process method for regulating and controlling morphology of polycrystalline silicon

Abstract

The invention provides an integrated process method for regulating and controlling the morphology of polycrystalline silicon, which comprises the following steps of: forming polycrystalline silicon layers of a unit region and a peripheral region on the surface of a substrate, patterning the polycrystalline silicon layer on the unit region to form a first grid polycrystalline silicon structure, and ensuring that the height of the polycrystalline silicon layer on the peripheral region is lower than that of the grid polycrystalline silicon on the unit region; forming a compensation layer covering the polycrystalline silicon layer; performing a maskless integral etching process, taking the compensation layer as an etching barrier layer to selectively thin the polycrystalline silicon layer on the unit region until the height of the polycrystalline silicon layer on the unit region is reduced to a target value, and then removing the residual compensation layer; and patterning the polycrystalline silicon layer on the peripheral region to form a second grid polycrystalline silicon structure on the polycrystalline silicon layer. According to the method, the thickness difference rule is reasonably utilized, and a photoetching process can be reduced by adjusting the etching sequence, so that the production cost is reduced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly to an integrated process method for regulating the morphology of polysilicon. Background Art

[0002] In the manufacturing of NOR flash memory devices, traditional thinning of the CG (control gate polysilicon) layer requires lithography patterning using a lithography tool. The prior art generally follows the standard process of GPL Loop (control gate polysilicon etching) → SAS Loop (peripheral area etching) → BARC (anti-reflection coating) coating → photoresist layer lithography → etching the control gate polysilicon to reduce its height. However, due to the premature exposure of the polysilicon in the peripheral area, the BARC thickness difference is insufficient, and reliable selective etching control cannot be achieved, so additional photolithography layer processing steps have to be added.

[0003] To solve the above problems, a new integrated process method for regulating the morphology of polysilicon needs to be proposed. Summary of the Invention

[0004] In view of the above-mentioned disadvantages of the prior art, the purpose of the present invention is to provide an integrated process method for regulating the morphology of polysilicon, which is used to solve the problem in the prior art that due to the premature exposure of the polysilicon in the peripheral area, the BARC thickness difference is insufficient, reliable selective etching control cannot be achieved, and additional photolithography layer processing steps have to be added.

[0005] To achieve the above purpose and other related purposes, the present invention provides an integrated process method for regulating the morphology of polysilicon, including:

[0006] Step 1: Form a polysilicon layer in the cell area and the peripheral area on the surface of the substrate, and pattern the polysilicon layer on the cell area to form a first gate polysilicon structure, wherein the height of the polysilicon layer on the peripheral area is lower than the height of the gate polysilicon on the cell area;

[0007] Step 2: Form a compensation layer covering the polysilicon layer;

[0008] Step 3: Perform a maskless overall etching process, and selectively thin the polysilicon layer on the cell area using the compensation layer as an etching barrier layer until the height of the polysilicon layer on the cell area drops to the target value, and then remove the remaining compensation layer;

[0009] Step 4: Pattern the polysilicon layer on the peripheral area to form a second gate polysilicon structure thereon.

[0010] Preferably, the substrate in Step 1 is a silicon substrate.

[0011] Preferably, the cell area in Step 1 is the storage cell area of a non-volatile memory.

[0012] Preferably, the unit area in step one includes a first gate dielectric layer, a floating gate polysilicon layer, and an inter-pole dielectric layer stacked in sequence from bottom to top.

[0013] Preferably, the inter-pole dielectric layer in step one is composed of a first oxide layer, a nitride layer, and a second oxide layer stacked in sequence from bottom to top.

[0014] Preferably, the peripheral area in step one includes at least one peripheral device area.

[0015] Preferably, a second gate dielectric layer with a corresponding thickness is provided on the peripheral device area in step one according to the device voltage.

[0016] Preferably, after forming the first gate polysilicon structure on the polysilicon layer in the unit area in step one by patterning, steps of ion implantation and annealing are further included to form an ion implantation area.

[0017] Preferably, the material of the compensation layer in step two is a silicon-based anti-reflection coating, a spin-on carbon layer, or a combination of the two.

[0018] Preferably, the maskless overall etching process in step three is dry etching.

[0019] As described above, the integrated process method for regulating the morphology of polysilicon of the present invention has the following beneficial effects:

[0020] The present invention reasonably utilizes the law of thickness difference and can reduce one photolithography process and lower the production cost by adjusting the etching sequence. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 It shows a schematic process flow diagram of the present invention;

[0022] Figure 2 It shows a schematic diagram of forming a polysilicon layer of the present invention;

[0023] Figure 3 It shows a schematic diagram of forming a first gate polysilicon structure of the present invention;

[0024] Figure 4 It shows a schematic diagram of forming a compensation layer of the present invention;

[0025] Figure 5 It shows a schematic diagram of selectively thinning the polysilicon layer on the unit area with the compensation layer as an etching barrier layer of the present invention;

[0026] Figure 6 It shows a schematic diagram of forming a second gate polysilicon structure of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0027] The following describes the embodiments of the present invention through specific examples. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0028] Please refer to Figure 1 , the present invention provides an integrated process method for regulating the morphology of polysilicon, including:

[0029] Step 1, form a polysilicon layer 106 in the unit area and the peripheral area on the surface of the substrate 101, forming a structure as shown in Figure 2 . Use photolithography and etching methods to pattern the polysilicon layer 106 in the unit area to form the first gate polysilicon structure 1061. The height of the polysilicon layer 106 in the peripheral area is lower than the height of the gate polysilicon in the unit area, forming a structure as shown in Figure 3 . Usually, the unit area also includes structures such as doped wells and deep doped wells, and the peripheral area also includes doped wells and other structures corresponding to the devices;

[0030] In some embodiments, the substrate 101 in Step 1 is a silicon substrate.

[0031] In some embodiments, the unit area in Step 1 is the storage unit area of a non-volatile memory.

[0032] In some embodiments, the unit area in Step 1 includes a first gate dielectric layer 102, a floating gate polysilicon layer 103, and an inter-pole dielectric layer 104 stacked in sequence from bottom to top. The material of the first gate dielectric layer 102 can be an oxide layer.

[0033] In some embodiments, the inter-pole dielectric layer 104 in Step 1 is composed of a first oxide layer, a nitride layer, and a second oxide layer stacked in sequence from bottom to top.

[0034] In some embodiments, the peripheral area in Step 1 includes at least one peripheral device area, such as a high-voltage device area, a medium-voltage device area, and a low-voltage device area.

[0035] In some embodiments, a second gate dielectric layer 105 with a corresponding thickness is set on the peripheral device area in Step 1 according to the device voltage. The material of the second gate dielectric layer 105 can be an oxide layer.

[0036] In some embodiments, after forming the first gate polysilicon structure 1061 by patterning the polysilicon layer 106 in the unit area in Step 1, it further includes steps of ion implantation and annealing to form an ion implantation area 107.

[0037] Step 2: Form a compensation layer 108 covering the polysilicon layer 106 to form a structure as shown in Figure 4 shown;

[0038] In some embodiments, the material of the compensation layer 108 in Step 2 is a silicon-based anti-reflection coating, a spin-on carbon layer, or a combination of the two.

[0039] Step 3: Perform a maskless global etching process to selectively thin the polysilicon layer 106 on the cell region using the compensation layer 108 as an etching stop layer until the height of the polysilicon layer 106 on the cell region drops to the target value to form a structure as shown in Figure 5 shown, and then remove the remaining compensation layer 108;

[0040] In some embodiments, the maskless global etching process in Step 3 is a dry etching.

[0041] Step 4: Use photolithography and etching methods to pattern the polysilicon layer 106 on the peripheral region to form a second gate polysilicon structure 1062 thereon to form a structure as shown in Figure 6 shown. Compared with the prior art, the present invention can reduce one photolithography process and lower the production cost.

[0042] It should be noted that the illustrations provided in this embodiment only schematically illustrate the basic concept of the present invention. Therefore, only the components related to the present invention are shown in the drawings, rather than being drawn according to the number, shape, and size of the components in actual implementation. The type, quantity, and ratio of each component in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0043] In summary, the present invention rationally utilizes the thickness difference law and can reduce one photolithography process and lower the production cost by adjusting the etching sequence. Therefore, the present invention effectively overcomes various disadvantages in the prior art and has high industrial utilization value.

[0044] The above embodiments only exemplarily illustrate the principles and effects of the present invention and are not used to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical idea disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. An integrated process method for regulating the morphology of polysilicon, characterized in that, At least including: Step 1: Form a polysilicon layer for the cell region and the peripheral region on the substrate surface, and pattern the polysilicon layer on the cell region to form a first gate polysilicon structure, wherein the height of the polysilicon layer on the peripheral region is lower than the height of the gate polysilicon on the cell region; Step 2: Form a compensation layer covering the polysilicon layer; Step 3: Perform a maskless global etching process, and selectively thin the polysilicon layer on the cell region using the compensation layer as an etching stop layer until the height of the polysilicon layer on the cell region drops to a target value, and then remove the remaining compensation layer; Step 4: Pattern the polysilicon layer on the peripheral region to form a second gate polysilicon structure thereon.

2. The integrated process method for regulating the morphology of polysilicon according to claim 1, wherein: The substrate in Step 1 is a silicon substrate.

3. The integrated process method for regulating the morphology of polysilicon according to claim 1, characterized in that: The cell region in Step 1 is a storage cell region of a non-volatile memory.

4. The integrated process method for regulating the morphology of polysilicon according to claim 3, characterized in that: On the cell region in Step 1, there are sequentially stacked a first gate dielectric layer, a floating gate polysilicon layer, and an inter-poly dielectric layer from bottom to top.

5. The integrated process method for regulating the morphology of polysilicon according to claim 4, wherein: The inter-poly dielectric layer in Step 1 is composed of a first oxide layer, a nitride layer, and a second oxide layer sequentially stacked from bottom to top.

6. The integrated process method for regulating the morphology of polysilicon according to claim 1, wherein: The peripheral region in Step 1 includes at least one peripheral device region.

7. The integrated process method for regulating the morphology of polysilicon according to claim 6, wherein: On the peripheral device region in Step 1, a second gate dielectric layer with a corresponding thickness is set according to the device voltage.

8. The integrated process method for regulating the morphology of polysilicon according to claim 1, characterized in that: After forming the first gate polysilicon structure by patterning the polysilicon layer on the cell region in Step 1, there are also steps of ion implantation and annealing to form an ion implantation region.

9. The integrated process method for regulating the morphology of polysilicon according to claim 1, wherein: The material of the compensation layer in Step 2 is a silicon-based anti-reflection coating, a spin-on carbon layer, or a combination of the two.

10. The integrated process method for regulating the morphology of polysilicon according to claim 1, characterized in that: The maskless global etching process in Step 3 is a dry etching.

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