Resistive random access memory device and manufacturing method thereof

Abstract

The invention discloses a resistive random access memory device and a manufacturing method thereof, the resistive random access memory device comprises a substrate and a plurality of memristor units located on the main surface of the substrate, and each of the plurality of memristor units comprises a first transistor, a second transistor and a memristor structure; a first transistor and a second transistor each including a gate, a first pole, and a second pole, and having a channel region extending in a first direction perpendicular to a main surface of the substrate, in which the second pole of the first transistor is connected to the second pole of the second transistor; the memristor structure comprises a first electrode, a second electrode and a resistive layer located between the first electrode and the second electrode, and the memristor structure is located on one side of the channel region of the first transistor and the channel region of the second transistor in the second direction parallel to the main surface of the substrate. And a second transistor connected to the second pole of the first transistor and the second pole of the second transistor.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a resistive memory device and a manufacturing method thereof. Background Art

[0002] A resistive random access memory (RRAM), also known as a memristor. As a new type of non-volatile memory, it has advantages such as high speed, low power consumption, simple process, and post-process integration, and is a new type of semiconductor memory with potential application value.

[0003] In practical applications, a memristor is usually connected in series with a transistor to form a memory cell including a transistor and a memristor structure, and multiple memory cells can form a memristor array. However, traditional memristor arrays use a planar process to fabricate memory cells including memristors and transistors. For example, in a planar process, the transistor is located on the surface of the wafer, and the memristor is fabricated above the transistor; limited by the fabrication process and device structure, usually only one layer of memory cells can be fabricated on a wafer, which limits the improvement of the integration density of memristors. Summary of the Invention

[0004] According to at least one embodiment of the present disclosure, a resistive memory device is provided, including a substrate and a plurality of memristor units located on a main surface of the substrate, and each of the plurality of memristor units includes: a first transistor and a second transistor, each including a gate, a first pole, and a second pole, and having a channel region extending in a first direction perpendicular to the main surface of the substrate, wherein the second pole of the first transistor is connected to the second pole of the second transistor; and a memristor structure, including a first electrode, a second electrode, and a resistive layer located between the first electrode and the second electrode, wherein the memristor structure is located on one side of the channel regions of the first transistor and the second transistor in a second direction parallel to the main surface of the substrate, and is connected to the second pole of the first transistor and the second pole of the second transistor.

[0005] In the resistive memory device provided according to at least one embodiment of the present disclosure, the gates of the first transistor and the second transistor are connected to a word line, and the word line extends along the first direction; the first pole of the first transistor is connected to a first source line, and the first pole of the second transistor is connected to a second source line; the second pole of the first transistor and the second pole of the second transistor are connected to a bit line through the memristor structure; and the first source line, the bit line, and the second source line are each located on a side of the word line in a direction parallel to the main surface of the substrate, and extend in a direction parallel to the main surface of the substrate, and the first source line, the bit line, and the second source line are arranged along the first direction.

[0006] In the resistive memory device provided according to at least one embodiment of the present disclosure, the gates of the first transistor, the gates of the second transistor, and the word line share the same conductive pillar; the channel regions of the first transistor and the channel regions of the second transistor share the same channel layer; the first transistor and the second transistor each further include a gate dielectric layer, and the gate dielectric layer of the first transistor and the gate dielectric layer of the second transistor share the same dielectric layer; the dielectric layer surrounds and covers the sidewalls of the conductive pillar, the channel layer is located on a side of the dielectric layer away from the conductive pillar, and surrounds and covers the sidewalls of the dielectric layer.

[0007] In the resistive memory device provided according to at least one embodiment of the present disclosure, the first poles of the first transistor and the first poles of the second transistor are respectively located in two first conductive layers; the bit line is located in a second conductive layer, and the second conductive layer is located between the two first conductive layers in the first direction; at least a part of the memristor structure is located between the second conductive layer and the channel region in a direction parallel to the main surface of the substrate, the second electrode of the memristor structure is in contact with the second conductive layer, the first electrode of the memristor structure is in contact with the channel region, and the first electrode shares a first electrode layer with the second poles of the first transistor and the second transistor.

[0008] In the resistive memory device provided according to at least one embodiment of the present disclosure, the plurality of memristor units include a plurality of first memristor units stacked in the first direction, and the gates of the plurality of first transistors and the plurality of second transistors in the plurality of first memristor units are connected to the same word line, and the plurality of gates and the word line share the same conductive pillar.

[0009] In the resistive memory device provided according to at least one embodiment of the present disclosure, the first poles of two adjacent transistors in two adjacent first memristor units in the first direction are connected to each other and share the same first conductive layer.

[0010] In the resistive memory device provided according to at least one embodiment of the present disclosure, the plurality of memristor units include a first memristor unit and a second memristor unit arranged in the second direction. The word lines of the first memristor unit and the word lines of the second memristor unit extend parallel to each other in the first direction and are arranged in the second direction. The first memristor unit includes a first memristor structure, and the second memristor unit includes a second memristor structure. The first electrodes of the first memristor structure and the first electrodes of the second memristor structure are respectively located in two first electrode layers. The two first electrode layers each surround the corresponding word line in a direction parallel to the main surface of the substrate, and the second electrode of the first memristor structure and the second electrode of the second memristor structure share the same second electrode layer. The resistive change layers of the first memristor structure and the second memristor structure share the same resistive change material layer.

[0011] In the resistive memory device provided according to at least one embodiment of the present disclosure, it includes: a stacked structure, the stacked structure includes a first conductive layer and a composite structure layer alternately arranged in the first direction, and an insulating layer provided between adjacent first conductive layers and composite structure layers. Each composite structure layer includes a second conductive layer, a second electrode layer, and a resistive change material layer. The second electrode layer surrounds the second conductive layer in a plane perpendicular to the main surface of the substrate and is surrounded by the resistive change material layer. Each composite structure layer is located between two first conductive layers in the first direction; a via structure extending in the first direction through the stacked structure and including a conductive pillar, a dielectric layer, and a channel layer. The dielectric layer surrounds the sidewall of the conductive pillar, and the channel layer surrounds the sidewall of the dielectric layer; and a first electrode layer surrounding the via structure in a direction parallel to the main surface of the substrate and located between the composite structure layer and the via structure.

[0012] In the resistive memory device provided according to at least one embodiment of the present disclosure, the conductive pillar serves as the gate and word line of a plurality of transistors arranged in the first direction, the dielectric layer serves as the gate dielectric layer of the plurality of transistors, the channel layer serves as the channel region of the plurality of transistors. The plurality of transistors include a first transistor and a second transistor of a plurality of memristor units arranged in the first direction. The first conductive layer serves as the first pole and source line of the corresponding transistor in the plurality of transistors, and the second conductive layer serves as the bit line connected to the corresponding transistor and the memristor structure. The second electrode layer, the resistive change material layer, and the first electrode layer respectively serve as the second electrode, the resistive change layer, and the first electrode of the memristor structure of the corresponding memristor unit, and the first electrode layer also serves as the second pole of the first transistor and the second pole of the second transistor in the corresponding memristor unit.

[0013] According to at least one embodiment of the present disclosure, a method for manufacturing a resistive random access memory (RRAM) device is provided. The RRAM device includes a substrate and a plurality of memristor units located on a main surface of the substrate. Forming each of the plurality of memristors includes: forming a first transistor and a second transistor, each of the first transistor and the second transistor including a gate, a first pole, and a second pole, and having a channel region extending in a first direction perpendicular to the main surface of the substrate, wherein the second pole of the first transistor is connected to the second pole of the second transistor; and forming a memristor structure, the memristor structure including a first electrode, a second electrode, and a resistive switching layer located between the first electrode and the second electrode, wherein the memristor structure is located on one side of the channel regions of the first transistor and the second transistor in a second direction parallel to the main surface of the substrate, and is connected to the second pole of the first transistor and the second pole of the second transistor.

[0014] In the method for manufacturing a resistive random access memory (RRAM) device provided according to at least one embodiment of the present disclosure, it includes: forming a stacked structure on the substrate, the stacked structure including a first conductive layer and a sacrificial layer alternately arranged in the first direction, and an insulating layer disposed between adjacent first conductive layers and sacrificial layers; forming a via hole in the stacked structure, the via hole extending through the stacked structure, and a side surface of the sacrificial layer being exposed by the via hole; performing an etching process on the side surface of the sacrificial layer to form a lateral groove in the sacrificial layer; forming a first electrode layer in the lateral groove; forming a via hole structure in the via hole, the via hole structure including a conductive pillar, a dielectric layer, and a channel layer, the dielectric layer surrounding a side wall of the conductive pillar, and the channel layer surrounding a side wall of the dielectric layer; removing the sacrificial layer to form a cavity; and forming a composite structure layer in the cavity, the composite structure layer including a second conductive layer, a second electrode layer, and a resistive switching material layer, the second electrode layer surrounding the second conductive layer in a plane perpendicular to the main surface of the substrate, and being surrounded by the resistive switching material layer.

[0015] In the method for manufacturing a resistive memory device according to at least one embodiment of the present disclosure, the plurality of memristor units include a plurality of first memristor units arranged in the first direction, and the conductive pillars in the via structure serve as the gates of a plurality of first transistors and a plurality of second transistors in the plurality of first memristor units and the word lines connected to the gates, the dielectric layer serves as the gate dielectric layer of the plurality of first transistors and the plurality of second transistors, and the channel layer serves as the channel regions of the plurality of first transistors and the plurality of second transistors; at least a part of the first conductive layer serves as the first pole of the corresponding transistor in the corresponding memristor unit and the source line connected to the first pole; at least a part of the second conductive layer serves as the bit line of the corresponding memristor unit; at least a part of the second electrode layer, the resistive material layer, and the first electrode layer respectively serve as the second electrode, the resistive layer, and the first electrode of the memristor structure of the corresponding memristor unit, and the first electrode layer also serves as the second pole of the first transistor and the second pole of the second transistor in the corresponding memristor unit.

[0016] In the method for manufacturing a resistive memory device according to at least one embodiment of the present disclosure, forming the first electrode layer in the lateral groove includes: forming a first electrode material layer that lines the surface of the via and fills the lateral groove; and removing the part of the first electrode material layer that lines the surface of the via, and the remaining part of the first electrode material layer in the lateral groove forms the first electrode layer, wherein the sidewalls of the first electrode layer and the sidewalls of the first conductive layer are exposed in the via and are aligned in the first direction.

[0017] In the method for manufacturing a resistive memory device according to at least one embodiment of the present disclosure, forming the via structure in the via includes: first forming the channel layer in the via, the channel layer lining the surface of the via and contacting the first conductive layer and the first electrode layer of the stacked structure; forming the dielectric layer along the surface of the channel layer in the via; and forming the conductive pillar in the space in the via that is not filled by the channel layer and the dielectric layer.

[0018] In the method for manufacturing a resistive memory device according to at least one embodiment of the present disclosure, forming the composite structure layer in the cavity includes: forming the resistive material layer that lines the surface of the cavity and contacts the first electrode layer; forming the second electrode layer along the surface of the resistive material layer in the cavity; and forming the second conductive layer in the space in the cavity that is not filled by the resistive material layer and the second electrode layer.

[0019] The resistive memory device and its manufacturing method according to the embodiments of the present disclosure can improve the integration density and array scale of the memristor units. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] To more clearly illustrate the technical solutions of the embodiments of the present disclosure, the accompanying drawings of the embodiments will be briefly introduced below. Obviously, the accompanying drawings in the following description only relate to some embodiments of the present disclosure and do not limit the present disclosure.

[0021] Figure 1 FIG. 1 shows a schematic plan view of a resistive memory device according to some embodiments of the present disclosure.

[0022] Figure 2 FIG. 2 shows a schematic cross-sectional view of a resistive memory device according to some embodiments of the present disclosure.

[0023] Figure 3 FIG. 3 shows a schematic equivalent circuit diagram of a resistive memory device according to some embodiments of the present disclosure.

[0024] Figure 4A and Figures 4B to 11A to Figure 11B FIGS. 4 to 9 show schematic plan views and cross-sectional views of the structures of the respective steps in the manufacturing method of a resistive memory device according to some embodiments of the present disclosure. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0025] To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are some, but not all, of the embodiments of the present disclosure. All other embodiments obtained by those of ordinary skill in the art based on the described embodiments of the present disclosure without creative efforts shall fall within the scope of protection of the present disclosure.

[0026] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure shall have the ordinary meaning as understood by those of ordinary skill in the art to which the present disclosure pertains. The "first", "second", and similar terms used in the present disclosure do not denote any order, quantity, or importance, but are only used to distinguish different components. The terms such as "including" or "comprising" mean that the elements or items appearing before the term cover the elements or items listed after the term and their equivalents, without excluding other elements or items. The terms such as "connected" or "coupled" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0027] The embodiments of the present disclosure provide a resistive memory device and a manufacturing method thereof, which can significantly increase the array scale and integration density of memristor units.

[0028] For example, an embodiment of the present disclosure provides a resistive memory device, including a substrate and a plurality of memristor units located on the main surface of the substrate, and each of the plurality of memristor units includes a first transistor, a second transistor, and a memristor structure. The first transistor and the second transistor each include a gate, a first pole, and a second pole, and have a channel region extending in a first direction perpendicular to the main surface of the substrate, wherein the second pole of the first transistor is connected to the second pole of the second transistor; the memristor structure includes a first electrode, a second electrode, and a resistive change layer located between the first electrode and the second electrode, wherein the memristor structure is located on one side of the channel regions of the first transistor and the second transistor in a second direction parallel to the main surface of the substrate, and is connected to the second pole of the first transistor and the second pole of the second transistor.

[0029] In the resistive memory device of the embodiment of the present disclosure, the channel regions of the transistors extend in a direction perpendicular to the main surface of the substrate, and the memristor structure is disposed on the side of the transistor channel regions in a direction parallel to the main surface of the substrate, so that vertical stacking of the memristor units can be realized, and further, it is beneficial to increase the array scale and integration density of the memristor units in the resistive memory device.

[0030] Figure 1 Schematic plan view showing a resistive memory device according to some embodiments of the present disclosure; Figure 2 Schematic cross-sectional view showing a resistive memory device according to some embodiments of the present disclosure; for example, Figure 2 is a cross-sectional view taken along line I-I’ of Figure 1 ; Figure 1 is a plan view taken along line II-II’ of Figure 2 . Figure 3 Schematic equivalent circuit diagram showing a resistive memory device according to some embodiments of the present disclosure.

[0031] Refer to Figure 1 , Figure 2 and Figure 3, in some embodiments, the resistive memory device 500 includes a substrate 100 and a plurality of memristor units 200. The plurality of memristor units 200 are located on the main surface of the substrate 100, and the memristor unit 200 can be a 2-transistor-1-memristor (i.e., 2T1R) structure. For example, each memristor unit 200 may include a first transistor T1, a second transistor T2, and a memristor structure R. The first transistor T1 and the second transistor T2 each include a gate G, a first pole S, and a second pole D, and have a channel region CR extending in a first direction D1 perpendicular to the main surface of the substrate. In some examples, the first pole S can be a source electrode, and the second pole D is a drain electrode; in other examples, the first pole S can also be a drain electrode, and the second pole D is a source electrode. The plurality of transistors of the plurality of memristor units in the resistive memory device can include any suitable type of transistor; for example, classified based on the channel material, the plurality of transistors can be or include silicon-based transistors, compound semiconductor transistors, thin film oxide transistors, two-dimensional material transistors, etc.; for example, classified based on the conduction type, the plurality of transistors can be or include P-type transistors, N-type transistors, etc., and the present disclosure does not limit the type of transistor.

[0032] In some embodiments, the memristor structure 200 includes a first electrode E1, a second electrode E2, and a resistive layer RS located between the first electrode E1 and the second electrode E2. For example, the memristor structure 200 can be located on one side of the channel regions CR of the first transistor T1 and the second transistor T2 in a second direction D2 parallel to the main surface of the substrate, and is connected to the second pole D of the first transistor T1 and the second pole D of the second transistor T2, for example, physically and electrically connected. Herein, the second direction D2 generally refers to one or more directions parallel to the main surface of the substrate; for example, the first direction D1 can be a vertical direction, and the second direction D2 can be a horizontal direction.

[0033] In some embodiments, the gates of the first transistor and the second transistor are connected to a word line, and the word line extends along the first direction; the first pole of the first transistor is connected to a first source line, and the first pole of the second transistor is connected to a second source line; the second poles of the first transistor and the second transistor are connected to a bit line through the memristor structure; the first source line, the bit line, and the second source line are each located on the side of the word line in a direction parallel to the main surface of the substrate, extend in a direction parallel to the main surface of the substrate, and are arranged along the first direction.

[0034] For example, the gate G of the first transistor T1 and the gate G of the second transistor T2 can be connected to each other and connected to the same word line WL; the first pole S of the first transistor T2 is connected to the first source line, and the first pole S of the second transistor T2 is connected to the second source line. The first source line and the second source line can be the same source line or connected to each other, so that corresponding voltages can be applied to the first poles of the transistors through the source line at the same time; alternatively, the first source line and the second source line can also be different source lines, and corresponding voltages can be applied to the first pole of the first transistor T1 and the first pole of the second transistor T2 through the first source line and the second source line respectively. The first source line and the second source line can be collectively referred to as the source line SL.

[0035] In some embodiments, the second pole D of the first transistor T1 and the second pole D of the second transistor T2 are connected to the same bit line BL through the memristor structure R. The word line WL extends in a first direction D1 perpendicular to the main surface of the substrate. The first source line, the second source line (i.e., the two source lines SL shown in the figure) and the bit line BL are each located on the side of the word line WL in a direction parallel to the main surface of the substrate and extend in a direction parallel to the main surface of the substrate; the source line SL and the bit line DL are arranged in the first direction D1 perpendicular to the main surface of the substrate. For example, the bit line DL is located between the first source line and the second source line in the first direction D1.

[0036] The first transistor T1 and the second transistor T2 are stacked in the first direction D1 perpendicular to the main surface of the substrate. The memristor structure R is located between the first poles of the two transistors in the first direction D1 and between the bit line BL and the channel region (or the second poles of the two transistors) in the second direction D2.

[0037] In some embodiments, the gate of the first transistor, the gate of the second transistor and the word line share the same conductive column; the channel regions of the first transistor and the second transistor share the same channel layer; the first transistor and the second transistor each further include a gate dielectric layer, and the gate dielectric layers of the first transistor and the second transistor share the same dielectric layer; the dielectric layer surrounds and covers the side walls of the conductive column, and the channel layer is located on the side of the dielectric layer away from the conductive column and surrounds and covers the side walls of the dielectric layer.

[0038] In some embodiments, the first poles of the first transistor and the second transistor are respectively located in two first conductive layers; the bit line is located in the second conductive layer, and the second conductive layer is located between the two first conductive layers in the first direction; at least part of the memristor structure is located between the second conductive layer and the channel region in a direction parallel to the main surface of the substrate, the second electrode of the memristor structure is in contact with the second conductive layer, the first electrode of the memristor structure is in contact with the channel region, and the first electrode shares the first electrode layer with the second poles of the first transistor and the second transistor.

[0039] Reference Figure 1 andFigure 2 For example, the gate G of the first transistor T1, the gate G of the second transistor T2, and the word line WL share the same conductive pillar 109. That is, the conductive pillar 109 extends along a first direction D1 perpendicular to the main surface of the substrate and serves as the word line WL; some portions of the conductive pillar 109 respectively serve as the gate G of the first transistor T1 and the gate G of the second transistor T2.

[0040] For example, the channel regions CR of the first transistor T1 and the second transistor T2 are connected to each other and may share the same channel layer 107. Each of the first transistor T1 and the second transistor T2 further includes a gate dielectric layer GD located between the gate G and the channel region CR. For example, the gate dielectric layer GD of the first transistor T1 and the gate dielectric layer GD of the second transistor T2 may be connected to each other and may share the same dielectric layer 108.

[0041] In some embodiments, the dielectric layer 108 surrounds and covers the sidewalls of the conductive pillar 109 in a direction parallel to the main surface of the substrate, and the channel layer 107 is located on a side of the dielectric layer 108 away from the conductive pillar 109 in a direction parallel to the main surface of the substrate and surrounds and covers the sidewalls of the dielectric layer 108. For example, the conductive pillar 109 has a columnar structure, such as a cylindrical shape; the dielectric layer 108 and the channel layer 107 each have a hollow columnar structure, such as a hollow cylindrical structure; in a plan view, the dielectric layer 108 and the trench layer 107 each have an annular structure and successively surround the periphery of the conductive pillar 109.

[0042] Continuing to refer to Figure 1 and Figure 2 , in some embodiments, the first poles S of the first transistor T1 and the second transistor T2 are respectively located in two first conductive layers 102. The first conductive layer 102 may extend in a direction parallel to the main surface of the substrate. For example, the first pole S of each transistor and the source line SL share the same first conductive layer 102; at least a portion of the first conductive layer 102 serves as the source line SL, and a portion of the first conductive layer 102 serves as the first pole S of the transistor.

[0043] The second poles D of the first transistor T1 and the second transistor T2 are connected to each other and are connected to the same bit line BL through a memristor structure R, and the bit line BL may be located in the second conductive layer 114. The second conductive layer 114 extends in a direction parallel to the main surface of the substrate; for example, at least a portion of the second conductive layer 114 serves as the bit line BL.

[0044] For example, the second conductive layer 114 is located between the two first conductive layers 102 in a first direction D1 perpendicular to the main surface of the substrate and is spaced apart from the two first conductive layers 102 to be electrically isolated from each other.

[0045] In some embodiments, at least a portion of the second electrode E2, the resistive switching layer RS, and the first electrode E1 of the memristor structure R are located between the second conductive layer 114 (i.e., the bit line BL) and the channel layer 107 (e.g., the channel region CR of a transistor) in a direction parallel to the main surface of the substrate.

[0046] For example, the second electrode E2 of the memristor structure R is connected to the bit line BL, and the first electrode E1 of the memristor structure R is connected to the second poles D of the first transistor T1 and the second transistor T2. At least a portion of the resistive switching layer RS is located between the first electrode E1 and the second electrode E2 in a second direction. For example, the second electrode E2 is in contact with the second conductive layer 114 (i.e., the bit line BL), the first electrode E1 is in contact with the channel layer 107 (i.e., the channel region CR), and the first electrode E1 can share the first electrode layer 106 with the second poles D of the first transistor T1 and the second transistor T2. That is, the first electrode layer 106 is multiplexed as the second poles D of two transistors in the memristor cell and the first electrode E1 of the memristor structure R.

[0047] For example, the second electrode layer 113 where the second electrode E2 of the memristor structure R is located surrounds and covers the first surface and the second surface (i.e., the top surface and the bottom surface) of the second conductive layer 114 that are opposite to each other in the first direction D1 and the first sidewall and the second sidewall that are opposite to each other in the second direction D2. The resistive switching material layer 112 where the resistive switching layer RS is located is on the side of the second electrode layer 113 away from the second conductive layer 114 and surrounds and covers the second electrode layer 113. For example, it surrounds and covers the first surface and the second surface (i.e., the top surface and the bottom surface) of the second electrode layer 113 that are opposite to each other in the first direction D1 and the first sidewall and the second sidewall that are opposite to each other in the second direction D2. That is to say, the second electrode layer 113 is sandwiched between the second conductive layer 114 and the resistive switching material layer 112, surrounds the second conductive layer 114 in a plane perpendicular to the main surface of the substrate, and is surrounded by the resistive switching material layer 112.

[0048] In some embodiments, the first electrode layer 106 where the first electrode E1 of the memristor structure and the second pole D of the transistor are located is between the resistive switching material layer 112 and the channel layer 107 in the second direction D2 and can surround the channel layer 107, for example.

[0049] In some embodiments, a plurality of memristor cells include a plurality of first memristor cells stacked in a first direction perpendicular to the main surface of the substrate. The gates of the plurality of first transistors and the plurality of second transistors in the plurality of first memristor cells are connected to the same word line, and the plurality of gates and the word line share the same conductive pillar. In some embodiments, the first poles of two adjacent transistors in two adjacent first memristor cells in the first direction are connected to each other and share the same first conductive layer.

[0050] ReferenceFigure 2 A plurality of memristor units 200 are arranged in an array in a first direction D1 perpendicular to the main surface of the substrate and in a direction parallel to the main surface of the substrate. For example, the plurality of memristor units 200 may include a plurality of first memristor units 200a stacked in the first direction D1 perpendicular to the main surface of the substrate; it should be understood that the first memristor unit and the second memristor unit below are only for convenience of description to distinguish memristor units located at different positions, and the structure of each first memristor unit or second memristor unit is substantially the same as that described above for the memristor unit 200, and will not be elaborated here; in addition, Figure 2 The dashed boxes in schematically show the regions where the plurality of memristor units are located. These dashed boxes only exemplarily show the approximate regions of the corresponding memristor units, rather than limiting the scope of the corresponding memristor units, and do not indicate that there is an obvious interface between adjacent memristor units; when adjacent memristor units share a certain material layer, some parts of the material layer are used as corresponding components of the corresponding memristor units during corresponding operations, and no clear division is made for different memristor units.

[0051] In some embodiments, the gates G of the plurality of first transistors T1 and the plurality of second transistors T2 in the plurality of first memristor units 200a stacked in the first direction D1 perpendicular to the main surface of the substrate are connected to each other and connected to the same word line WL. For example, the gates G of the plurality of first memristor units 200a and the word line WL may all share the same conductive pillar 109. For example, the gate dielectric layers GD of the plurality of transistors in the plurality of first memristor units 200a all share the same dielectric layer 108, and the channel regions CR of the plurality of transistors in the plurality of first memristor units 200a all share the same channel layer 107.

[0052] In some embodiments, the first poles S of the adjacent two transistors of two adjacent first memristor units 200a in the first direction D1 are connected to each other and may share the same source line SL. For example, in the two adjacent first memristor units 200a, the first pole S of the second transistor T2 of one first memristor unit 200a is connected to the first pole S of the first transistor T1 of the other first memristor unit 200a and connected to the same source line SL. For example, the first poles S of the adjacent two transistors and the corresponding source line SL may share the same first conductive layer 102. For example, the first conductive layer 102 extends in a direction parallel to the main surface of the substrate and serves as the source line SL, and some parts of the first conductive layer 102 serve as the first poles S of the adjacent two transistors in the two adjacent first memristor units. The memristor structures R of the two adjacent first memristor units 200a are respectively located on opposite sides of the shared first conductive layer 102 in the first direction.

[0053] In some embodiments, a plurality of memristor units include a first memristor unit and a second memristor unit arranged in a second direction parallel to the main surface of the substrate. The word lines of the first memristor unit and the word lines of the second memristor unit extend parallel to each other in a first direction and are arranged in the second direction. The first memristor unit includes a first memristor structure, and the second memristor unit includes a second memristor structure; the first electrodes of the first memristor structure and the first electrodes of the second memristor structure are respectively located in two first electrode layers, and each of the two first electrode layers surrounds the corresponding word line in a direction parallel to the main surface of the substrate. The second electrodes of the first memristor structure and the second electrodes of the second memristor structure share the same second electrode layer, and the resistive change layers of the first memristor structure and the second memristor structure share the same resistive change material layer.

[0054] Continuing to refer to Figure 1 and Figure 2 , for example, a plurality of memristor units 200 include a first memristor unit 200a and a second memristor unit 200b arranged in a second direction D2 parallel to the main surface of the substrate. The word lines WL of the first memristor unit 200a and the word lines WL of the second memristor unit 200b extend parallel to each other in a first direction D1 and are arranged in the second direction D2; for example, the gates G of the plurality of transistors in the first memristor unit 200a and the word line WL share a conductive column 109, and the gates G of the plurality of transistors in the second memristor unit 200b and the word line WL share another conductive column 109; the two conductive columns 109 extend parallel to each other in the first direction D1 and are arranged in the second direction D2. The transistors of the first memristor unit 200a and the transistors of the second memristor unit 200b each have a gate dielectric layer and a channel region surrounding the corresponding conductive column, and may share the same source line SL and bit line BL.

[0055] The first memristor unit 200a includes a first memristor structure R1, and the second memristor unit 200b includes a second memristor structure R2. The first electrodes E1 (and the second poles D of the corresponding first and second transistors) of the first memristor structure R1 and the first electrodes E1 (and the second poles D of the corresponding first and second transistors) of the second memristor structure R2 are respectively located in two first electrode layers 106, and each of the two first electrode layers 106 is annular and surrounds the corresponding word line WL (i.e., the conductive column 109) in a direction parallel to the main surface of the substrate; the second electrodes E2 of the first memristor structure R1 and the second electrodes E2 of the second memristor structure R2 share the same second electrode layer 113, and the resistive change layers RS of the first memristor structure R1 and the resistive change layers RS of the second memristor structure R2 share the same resistive change material layer 112.

[0056] In some embodiments, the resistive memory device includes a stacked structure and a via structure; the stacked structure includes a first conductive layer and a composite structure layer alternately arranged in a first direction, and an insulating layer disposed between adjacent first conductive layers and composite structure layers, wherein each composite structure layer includes a second conductive layer, a second electrode layer, and a resistive material layer, the second electrode layer surrounds the second conductive layer in a plane perpendicular to the main surface of the substrate and is surrounded by the resistive material layer, and each composite structure layer is located between two first conductive layers in the first direction; the via structure extends through the stacked structure in the first direction and includes a conductive pillar, a dielectric layer, and a channel layer, the dielectric layer surrounds the sidewall of the conductive pillar, and the channel layer surrounds the sidewall of the dielectric layer; the first electrode layer surrounds the via structure in a direction parallel to the main surface of the substrate and is located between the composite structure layer and the via structure. For example, the conductive pillar serves as the gate and word line of a plurality of transistors arranged in the first direction, the dielectric layer serves as the gate dielectric layer of the plurality of transistors, the channel layer serves as the channel region of the plurality of transistors, the plurality of transistors include a first transistor and a second transistor of a plurality of memristor units arranged in the first direction; the first conductive layer serves as the first pole and source line of the corresponding transistor in the plurality of transistors, the second conductive layer serves as the bit line connected to the corresponding transistor and the memristor structure; the second electrode layer, the resistive material layer, and the first electrode layer respectively serve as the second electrode, the resistive layer, and the first electrode of the memristor structure of the corresponding memristor unit, and the first electrode layer also serves as the second pole of the first transistor and the second pole of the second transistor.

[0057] Continuing to refer to Figure 1 and Figure 2 , for example, the resistive memory device 500 includes a stacked structure 300 and a via structure 110 located on a substrate 100. The stacked structure 300 may include a first conductive layer 102 and a composite structure layer 115 alternately arranged in a first direction D1 and an insulating layer 101 disposed between adjacent first conductive layers 102 and composite structure layers 115. Each composite structure layer 115 includes a second conductive layer 114, a second electrode layer 113, and a resistive material layer 112, the second electrode layer 113 surrounds the second conductive layer 114 in a plane perpendicular to the main surface of the substrate and is surrounded by the resistive material layer 112. Each composite structure layer 115 is located between two first conductive layers 102 in the first direction D1.

[0058] The via structure 110 extends through the stacked structure 300 in the first direction D1 and includes a conductive pillar 109, a dielectric layer 108, and a channel layer 107. The dielectric layer 108 surrounds the sidewall of the conductive pillar 108, and the channel layer 107 surrounds the sidewall of the dielectric layer 108. The via structure 110 may be an overall columnar structure. For example, as Figure 1 and Figure 2As shown, a plurality of via structures 110 may be arranged in an array in the stacked structure, and each is surrounded by the respective material layers of the stacked structure in a plane parallel to the main surface of the substrate. It should be understood that the arrangement of the plurality of via structures 110 shown in the figure is only illustrative, and the present disclosure is not limited thereto. The conductive pillar 109, dielectric layer 108, and channel layer 107 of each via structure 110 may be used as the word line WL (and gate GD), gate dielectric layer GD, and channel region CR of a plurality of transistors stacked in a first direction, respectively. The plurality of transistors include a first transistor T1 and a second transistor T2 of a plurality of memristor units.

[0059] For example, the first conductive layer 102 serves as the first pole S and source line SL of the corresponding transistor, and the second conductive layer 104 serves as the bit line BL connected to the corresponding transistor and the memristor structure. The second electrode layer 113, resistive change material layer 112, and first electrode layer 106 serve as the second electrode E2, resistive change layer RS, and first electrode E1 of the memristor structure in the corresponding memristor unit, respectively, and the first electrode layer 106 may also serve as the second pole D of the first transistor T1 and the second pole D of the second transistor T2.

[0060] In some embodiments, the first electrode layer 106 is located between the composite structure layer 115 and the via structure 110 in a direction parallel to the main surface of the substrate and surrounds the via structure 110. For example, a first electrode layer 106 surrounding the via structure 110 is provided between each via structure 110 and the corresponding composite structure layer 115.

[0061] An embodiment of the present disclosure provides a manufacturing method of a resistive random access memory device. The resistive random access memory device includes a substrate and a plurality of memristor units located on the main surface of the substrate. Forming each of the plurality of memristors includes: forming a first transistor and a second transistor, each of the first transistor and the second transistor includes a gate, a first pole, and a second pole, and has a channel region extending in a first direction perpendicular to the main surface of the substrate, wherein the second pole of the first transistor is connected to the second pole of the second transistor; and forming a memristor structure, the memristor structure includes a first electrode, a second electrode, and a resistive change layer located between the first electrode and the second electrode, wherein the memristor structure is located on one side of the channel regions of the first transistor and the second transistor in a second direction parallel to the main surface of the substrate, and is connected to the second pole of the first transistor and the second pole of the second transistor.

[0062] The manufacturing method of the resistive random access memory device according to the embodiment of the present disclosure has the same technical effects as described above for the resistive random access memory device. For example, it can achieve a multiple increase in the scale and integration density of the memristor array. Moreover, the manufacturing method can control the stacking layer number of the memristor units based on product requirements without adding additional photomasks, and can greatly improve the integration density of the memristor array.

[0063] For example, in some embodiments, a method of manufacturing a resistive random access memory (RRAM) device includes: forming a stacked structure on a substrate, the stacked structure including a first conductive layer and a sacrificial layer alternately arranged in a first direction, and an insulating layer disposed between adjacent first conductive layers and sacrificial layers; forming a via in the stacked structure, the via extending through the stacked structure and exposing side surfaces of the sacrificial layer; performing an etching process on the side surfaces of the sacrificial layer to form lateral grooves in the sacrificial layer; forming a first electrode layer in the lateral grooves; forming a via structure in the via, the via structure including a conductive pillar, a dielectric layer, and a channel layer, the dielectric layer surrounding a sidewall of the conductive pillar, and the channel layer surrounding a sidewall of the dielectric layer; removing the sacrificial layer to form a cavity, and forming a composite structure layer in the cavity, the composite structure layer including a second conductive layer, a second electrode layer, and a resistive material layer, the second electrode layer surrounding the second conductive layer in a plane perpendicular to a main surface of the substrate and being surrounded by the resistive material layer.

[0064] In some embodiments, forming the first electrode layer in the lateral grooves includes: forming a first electrode material layer lining a surface of the via and filling the lateral grooves; and removing a portion of the first electrode material layer lining the surface of the via, and a remaining portion of the first electrode material layer remaining in the lateral grooves forms the first electrode layer, wherein sidewalls of the first electrode layer and sidewalls of the first conductive layer are exposed in the via and are aligned in a first direction perpendicular to a main surface of the substrate.

[0065] Figure 4A and Figures 4B to 11A and Figure 11B Schematic plan views and cross-sectional views showing intermediate structures of steps in a method of manufacturing a resistive random access memory (RRAM) device according to some embodiments of the present disclosure, wherein Figure 4A 、 5A 、6A, 7A, 8A, 9A, 10A, 11A are plan views taken along line II-II' of Figure 4B 、 5B 、6B, 7B, 8B, 9B, 10B, 11B, respectively, Figure 4B 、 5B 、6B, 7B, 8B, 9B, 10B, 11B are cross-sectional views taken along line I-I' of Figure 4A 、 5A 、6A, 7A, 8A, 9A, 10A, 11A, respectively.

[0066] Refer to Figure 4A and Figure 4B, in some embodiments, a stacked structure 300 is formed on the main surface of the substrate 100. In this step, the stacked structure 300 includes a first conductive layer 102 and a sacrificial layer 103 alternately arranged in a first direction D1 perpendicular to the main surface of the substrate, and an insulating layer 101 formed between adjacent first conductive layers 102 and sacrificial layers 103. For example, the insulating layer 101 may also be formed on the side of the first conductive layer 102 close to the substrate 100.

[0067] The substrate 100 may be a semiconductor substrate, for example, it may be or include a silicon substrate. In some embodiments, other component layers may also be provided between the substrate 100 and the stacked structure 300, such as a material layer including active devices and / or passive devices, etc. (not shown), and the present disclosure is not limited thereto.

[0068] For example, the first conductive layer 102 may include metal materials such as metal, metal compound or metal alloy, for example, it may include titanium, copper, titanium nitride, etc.; the insulating layer 101 may include insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, etc.; the material of the sacrificial layer 103 is different from the materials of the first conductive layer 102 and the insulating layer 101, and has a high etching selectivity ratio with the materials of the first conductive layer and the insulating layer. For example, the sacrificial layer 103 may include an insulating material; in some examples, the insulating layer 101 includes silicon oxide and the sacrificial layer 103 includes silicon nitride; the above materials are only illustrative, and the present disclosure is not limited thereto. The insulating layer 101, the first conductive layer 102 and the sacrificial layer 103 may each be formed by a suitable deposition process such as chemical vapor deposition, physical vapor deposition, etc.

[0069] It should be understood that the number of material layers in the stacked structure shown in the figure is only illustrative, and the present disclosure is not limited thereto. The number of material layers in the stacked structure can be set and controlled based on the number of memristor units to be stacked according to product design and requirements.

[0070] Reference Figure 5A and Figure 5B , a patterning process is performed on the stacked structure 300 to form a plurality of vias 300 in the stacked structure 300. The vias 300 extend through the stacked structure 300 and expose the sidewalls of a plurality of material layers in the stacked structure 300. For example, the side surface of the sacrificial layer 103 is exposed by the via 301. For example, the patterning process may include forming a patterned mask layer on the stacked structure 300. The patterned mask layer has a corresponding plurality of mask openings at positions where a plurality of vias are to be formed. Then, the stacked structure 300 is etched using the patterned mask layer as an etching mask to remove the portion of the stacked structure exposed by the plurality of mask openings and form a plurality of vias 301.

[0071] Reference Figure 5A and Figures 5B to 6A andFigure 6B , an etching process is performed on the sacrificial layer 103 from the side surface of the sacrificial layer 103 to form a lateral groove 302 in the sacrificial layer 103. For example, the etching process may include a wet etching process, and the etchant can contact the side surface of the sacrificial layer 103 from the via 300 and remove a part of the sacrificial layer 103. For example, a part of each sacrificial layer 103 is removed at a position corresponding to each via 301, and a lateral groove 302 is formed. For example, in the same sacrificial layer 103, a plurality of lateral grooves 302 are arranged in a direction parallel to the main surface of the substrate and are arranged in one-to-one correspondence with a plurality of vias 301; in a first direction D1 perpendicular to the main surface of the substrate, a plurality of lateral grooves 301 arranged along the first direction D1 may be provided corresponding to each via 301, and the plurality of lateral grooves 301 are respectively located in a plurality of sacrificial layers 103. That is to say, a plurality of lateral grooves 302 are arranged in a direction parallel to the main surface of the substrate and a direction perpendicular to the main surface of the substrate. In some embodiments, the removal amount of the sacrificial layer can be controlled by controlling the time of the etching process, and thus the size of the lateral groove can be controlled.

[0072] The lateral groove 302 and the via 301 are in spatial communication. As Figure 6A shown, the lateral groove 302 may be annular and is located outside the via 301 in a direction parallel to the main surface of the substrate, that is, surrounding the via 301. For example, the lateral groove 302 is recessed from the side wall of the via 301 that defines the via 301 in the stacked structure 300; the lateral groove 302 is located on one side of the sacrificial layer 103 in a direction parallel to the main surface of the substrate and is located between two insulating layers 101 on opposite sides of the sacrificial layer 103 in a first direction D1 perpendicular to the main surface of the substrate. That is to say, the lateral groove 302 is defined by the side surface of the sacrificial layer 103 and the opposite surfaces of two insulating layers 101 on opposite sides of the sacrificial layer 103. The opposite surfaces of the two insulating layers 101 include the bottom surface of one of the insulating layers 101 and the top surface of the other insulating layer 101.

[0073] Referring to Figure 7A and Figure 7B , in some embodiments, a first electrode material layer 106' is formed in the first via 301 and the lateral groove 302. The first electrode material layer 106' lines the surface of the via, covers the side walls of the plurality of material layers that define the first via 301 in the stacked structure 300, and fills the plurality of lateral grooves 302. In some embodiments, the first electrode material layer 106' may include, but is not limited to, one or more selected from the group consisting of inert metal materials such as Pt, Pd, Ir and their alloys, metal materials such as Ta, Hf, Ti, Zr, W, Ru, Al and their alloys, and semi-metallic compound materials such as TiN, TaN, polycrystalline silicon (Poly-Si), and can be formed by a suitable deposition process such as physical vapor deposition.

[0074] Reference Figure 7A and Figures 7B to 8A and Figure 8B A etching process is performed on the first electrode material layer 106' to remove a portion of the first electrode material layer 106' and form the first electrode layer 106 located in the lateral grooves 302. For example, the etching process removes the portion of the first electrode material layer 106' located in the vias 301, and leaves the portion located in the plurality of lateral grooves 302 to form a plurality of first electrode layers 106 respectively located in the plurality of lateral grooves 302. For example, the plurality of first electrode layers 106 and the plurality of lateral grooves 302 correspond one by one; the plurality of first electrode layers 106 located in different lateral grooves 302 are isolated from each other. For example, the sidewalls of the first electrode layer 106 are exposed to the vias 301 and can be substantially aligned with the sidewalls defining the vias 301 of other material layers of the stacked structure in the first direction D1.

[0075] Reference Figure 8A and Figures 8B to 9A and Figure 9B A via structure 110 is formed in the via 301. The via structure 110 includes a conductive pillar 109, a dielectric layer 108, and a channel layer 107. The dielectric layer 108 is located between the conductive pillar 109 and the channel layer 107, surrounds the conductive pillar 109, and is surrounded by the channel layer 107.

[0076] In some embodiments, forming the via structure in the via includes: first forming a channel layer in the via, the channel layer lining the surface of the via and contacting the first conductive layer and the first electrode layer of the stacked structure; forming a dielectric layer along the surface of the channel layer in the via; and forming a conductive pillar in the space in the via not filled by the channel layer and the dielectric layer.

[0077] For example, forming the through-hole structure 110 in the via 301 includes sequentially forming a channel layer 107, a dielectric layer 108, and a conductive pillar 109 in the via 301. For example, first, the channel layer 107 is formed in the via 301. The channel layer 107 lines the surface of the via 301 and contacts a plurality of material layers of the stacked structure 300 (i.e., a plurality of first conductive layers 102 and insulating layers 101) and the first electrode layer 103. Then, the dielectric layer 108 is formed along the surface of the channel layer 107 in the via 301. After that, the conductive pillar 109 is formed to fill the space in the via 301 that is not filled by the channel layer 107 and the dielectric layer 108. For example, the material of the channel layer 107 can be selected from one or more of a combination consisting of semiconductor materials such as silicon-based materials, compound semiconductor materials such as gallium arsenide and silicon carbide, oxide semiconductor materials such as indium gallium zinc oxide (IGZO), and two-dimensional materials such as graphene. The dielectric layer 108 can include dielectric materials such as silicon oxide; the conductive pillar 109 can include metallized materials such as copper, titanium, and titanium nitride. The above materials are only illustrative, and the present disclosure is not limited thereto.

[0078] Reference Figure 9A and Figures 9B to 10A and Figure 10B and, the sacrificial layer 103 is removed to form a cavity C. The sacrificial layer 103 can be removed by an etching process (e.g., wet etching), and the cavity C is formed in the region that was originally occupied by the sacrificial layer 103. For example, the etchant can enter the region where the sacrificial layer 103 is located from the side of the stacked structure 300 to remove the sacrificial layer 103. The etching process has a high etching selectivity for the sacrificial layer 103 and other adjacent material layers, so that the sacrificial layer 103 is etched and removed, while other adjacent material layers such as the insulating layer 101 and the first electrode layer 106 are substantially not etched.

[0079] Reference Figure 10A and Figures 10B to 11A and Figure 11B and, a composite structure layer 115 is formed in the cavity C. For example, the composite structure layer 115 includes a second conductive layer 114, a second electrode layer 113, and a resistive switching material layer 112. The second electrode layer 113 is sandwiched between the second conductive layer 114 and the resistive switching material layer 112, surrounds the second conductive layer 114 in a plane perpendicular to the main surface of the substrate, and is surrounded by the resistive switching material layer 112.

[0080] For example, the material of the second conductive layer 114 can be selected from the same candidate materials as the first conductive layer 102, and can be the same as or different from the material of the first conductive layer 102. For example, the second conductive layer 114 can include metallic materials such as metals, metal compounds, or metal alloys. For example, it can include metallic materials such as titanium, copper, titanium nitride, etc. The second electrode layer 113 can be selected from the same candidate materials as the first electrode layer 106, and can be the same as or different from the material of the first electrode layer 106. For example, the second electrode layer 113 can include, but is not limited to, one or more selected from the group consisting of inert metallic materials such as Pt, Pd, Ir, etc. and their alloys, metallic materials such as Ta, Hf, Ti, Zr, W, Ru, Al, etc. and their alloys, and meta-metallic compound materials such as TiN, TaN, Poly-Si, etc. The resistive change material layer 112 can include selected from the group consisting of HfO x , TaO x , TiO x , ZrO x and other binary transition metal oxides, AlO x and other metal oxides, SiO x and other non-metal oxides, and multi-metal oxides, metal-non-metal mixed oxides, perovskite oxides, etc. composed of them, and one or more selected from the combination thereof.

[0081] In some embodiments, forming the composite structure layer in the cavity includes: forming a resistive change material layer, the resistive change material layer lining the surface of the cavity and contacting the first electrode layer; forming a second electrode layer along the surface of the resistive change material layer in the cavity; and forming a second conductive layer in the space in the cavity not filled by the resistive change material layer and the second electrode layer.

[0082] For example, forming the composite structure layer 115 in the cavity C includes sequentially forming a resistive change material layer 112, a second electrode layer 113, and a second conductive layer 114 in the cavity C. For example, after forming the cavity C, first form a resistive change material layer 112 in the cavity C, the resistive change material layer 112 lining the surface of the cavity C and contacting the first electrode layer 106. Then, form a second electrode layer 113 along the surface of the resistive change material layer 112 in the cavity C; thereafter, form a second conductive layer 114 in the space in the cavity C not filled by the resistive change material layer 112 and the second electrode layer 113. That is, replace the sacrificial layer in the stacked structure with the composite structure layer 115.

[0083] Refer to Figure 11A and Figure 11B , a resistive random access memory device 500 including a plurality of memristor units 200 has been formed on the substrate 100. The related structural features of the resistive random access memory device 500 and the like can refer to the content described above regarding Figures 1 to 3 , and will not be elaborated here.

[0084] In the manufacturing method of the embodiments of the present disclosure, the number of stacked material layers can be controlled and set in the steps shown in Figure 4B to control the number of layers of the subsequently formed memristor units; moreover, in subsequent steps, a set of photomasks can be used to form multiple memristor units stacked vertically in a first direction and / or multiple memristor units arranged horizontally, so that without adding extra photomasks, the stacking layers of the memristor units can be increased, thereby greatly improving the integration density of the memristor units. Therefore, this manufacturing method can realize the three-dimensional (3D) stacking of 2T1R memristor units in the vertical direction, and multiple layers of 3D 2T1R memristor units can be formed on a single wafer, thus doubling the integration density of the memristor units.

[0085] Return to reference Figure 2 and Figure 3 , multiple memristor units 200 of the resistive random access memory device 500 can be arranged in an array in a direction perpendicular to the main surface of the substrate and in a direction parallel to the main surface of the substrate. For example, they can form a memristor array in the form of a crossbar switch matrix. The memristor array can include multiple crossed word lines, bit lines, and source lines. For example, multiple word lines WL0, WL1, WL2 (i.e., corresponding to Figure 2 multiple conductive posts 109) can extend vertically in a first direction D1 substantially parallel to each other, and multiple bit lines BL0, BL1, BL2 (corresponding to Figure 2 the second conductive layers 114 located in different layers in Figure 2 ) can extend horizontally in a second direction D2 substantially parallel to each other. Multiple source lines SL can be connected to each other or may not be connected. When selecting a memristor unit for operation, appropriate voltages are applied to the corresponding word line, bit line, and / or source line so that the voltage across the selected memristor structure reaches the operating voltage, and the conversion of the resistive state can be achieved. For example, in some examples, the conversion of the resistive state can be achieved by forming or breaking conductive filaments in the resistive switching layer of the memristor structure at the corresponding operating voltage.

[0086] For example, the operation method of the resistive random access memory device can include a forming operation, a set operation, and a reset operation. The following takes the Figure 3 memristor unit 200 in the box as the selected memristor unit as an example to illustrate the related operations of the memristor unit.

[0087] For example, during a Forming operation or a set operation, an activation signal is applied to the word line WL1. For example, in this example, the activation signal is a high-level signal; a high level is applied to the bit line BL0, and the bit line SL is at a low level; since the second electrode E2 of the memristor structure R is connected to the bit line BL, and the first electrode E1 is connected to the source line SL through a transistor, the second electrode E2 is at a high level and the first electrode E1 is at a low level (i.e., the level of the second electrode E2 is higher than that of the first electrode E1); for example, in this case, oxygen ions in the resistive switching layer RS will move towards the second electrode E2 and oxygen vacancies will be generated in the resistive switching layer RS. The accumulated oxygen vacancies form a conductive filament (CF), that is, a conductive channel is formed between the first electrode E1 and the second electrode E2, so that the resistive switching layer RS is switched from a high-resistance state to a low-resistance state.

[0088] For example, the initial state of the resistive switching layer RS is a high-resistance state. The Forming operation refers to the first programming operation performed on the resistive switching layer to convert the resistive switching layer RS from a high-resistance state to a low-resistance state. The process of the set operation is similar to that of the Forming operation, except that the operating voltage of the Forming operation may be higher, while the operating voltage of the set operation is relatively smaller.

[0089] During the Forming operation and the set operation, no voltage is applied to the word lines and bit lines of the unselected memristor cells. For example, the voltages of other word lines WL1, WL2 and bit lines BL1, BL2 are 0V. Therefore, only the voltage across the two ends of the memristor structure in the selected memristor cell 200 will reach the operating voltage.

[0090] For example, during a reset operation on the selected memristor cell 200, the bit line BL0 is at a low level, and a high level is applied to the word line WL0 and the corresponding source line SL, so that the second electrode E2 of the memristor structure is at a low level and the first electrode E1 is at a high level (i.e., the level of the first electrode E1 is higher than that of the second electrode E2), thereby attracting oxygen ions to recombine with oxygen vacancies; for example, at least some oxygen ions recombine with oxygen vacancies, causing the conductive filament to break, and further causing the resistive switching layer RS to be switched from a low-resistance state to a high-resistance state.

[0091] In the reset operation, since the adjacent transistors of adjacent memristor cells stacked in the first direction share the word line and the source line, for a memristor cell adjacent to the selected memristor cell, a high level consistent with the source line SL can be applied to the bit line (e.g., bit line BL1) of the adjacent memristor cell, so that the voltage drop across both ends of the memristor structure of the memristor cell is approximately 0, avoiding the reset of this memristor cell. In this way, the unselected memristor cells can be made unaffected by the operating voltage. In some examples, if multiple source lines SL are connected to each other, the bit lines of other unselected memristor cells stacked with the selected memristor cell in the first direction can be set similarly to make the unselected memristor cells unaffected.

[0092] In some embodiments, including two transistors in a memristor cell can increase the drive current during operation. Moreover, the two transistors in the same memristor cell are vertically stacked and share the bit line, while the adjacent transistors in adjacent memristor cells in the first direction share the source line. In this way, the number of material layers of multiple vertically stacked memristor cells can be reduced, and the integration density can be further increased.

[0093] In the resistive random access memory device and its manufacturing method according to the embodiments of the present disclosure, by implementing the vertical stacking of memristor cells, the array scale and integration density of the memristor cells can be significantly increased.

[0094] The following points need to be explained:

[0095] (1) In the drawings of the embodiments of the present disclosure, only the structures related to the embodiments of the present disclosure are involved, and other structures can refer to the general design.

[0096] (2) Without conflict, the features in the same embodiment and different embodiments of the present disclosure can be combined with each other.

[0097] The above is only the specific implementation manner of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present disclosure can easily think of changes or substitutions, which should be covered by the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A resistive random access memory (RRAM) device includes a substrate and a plurality of memristor cells located on a main surface of the substrate. Each of the plurality of memristor cells includes: A first transistor and a second transistor, each including a gate, a first pole, and a second pole, and having a channel region extending in a first direction perpendicular to the main surface of the substrate. The second pole of the first transistor is connected to the second pole of the second transistor. And A memristor structure including a first electrode, a second electrode, and a resistive switching layer located between the first electrode and the second electrode. The memristor structure is located on one side of the channel regions of the first transistor and the second transistor in a second direction parallel to the main surface of the substrate, and is connected to the second pole of the first transistor and the second pole of the second transistor.

2. The RRAM device according to claim 1, wherein The gates of the first transistor and the second transistor are connected to a word line, and the word line extends in the first direction. The first pole of the first transistor is connected to a first source line, and the first pole of the second transistor is connected to a second source line. The second poles of the first transistor and the second transistor are connected to a bit line through the memristor structure. And The first source line, the bit line, and the second source line are each located on a side of the word line in a direction parallel to the main surface of the substrate and extend in a direction parallel to the main surface of the substrate. The first source line, the bit line, and the second source line are arranged in the first direction.

3. The RRAM device according to claim 2, wherein The gates of the first transistor, the second transistor, and the word line share the same conductive pillar. The channel regions of the first transistor and the second transistor share the same channel layer. The first transistor and the second transistor each further include a gate dielectric layer, and the gate dielectric layers of the first transistor and the second transistor share the same dielectric layer. The dielectric layer surrounds and covers the sidewalls of the conductive pillar. The channel layer is located on a side of the dielectric layer away from the conductive pillar and surrounds and covers the sidewalls of the dielectric layer.

4. The RRAM device according to claim 2, wherein The first poles of the first transistor and the second transistor are respectively located in two first conductive layers. The bit line is located in a second conductive layer, and the second conductive layer is located between the two first conductive layers in the first direction. At least a portion of the memristor structure is located in a direction parallel to the main surface of the substrate between the second conductive layer and the channel region. The second electrode of the memristor structure is in contact with the second conductive layer. The first electrode of the memristor structure is in contact with the channel region, and the first electrode shares a first electrode layer with the second poles of the first transistor and the second transistor.

5. The resistive memory device according to claim 2, wherein the plurality of memristor units include a plurality of first memristor units stacked in the first direction, and gates of a plurality of first transistors and a plurality of second transistors in the plurality of first memristor units are connected to the same word line, and the plurality of gates and the word line share the same conductive pillar.

6. The resistive memory device according to claim 5, wherein first poles of adjacent two transistors of two adjacent first memristor units in the first direction are connected to each other and share the same first conductive layer.

7. The resistive memory device according to claim 2, wherein the plurality of memristor units include a first memristor unit and a second memristor unit arranged in the second direction, word lines of the first memristor unit and the second memristor unit extend in the first direction parallel to each other and are arranged in the second direction, the first memristor unit includes a first memristor structure, and the second memristor unit includes a second memristor structure; A first electrode of the first memristor structure and a first electrode of the second memristor structure are respectively located in two first electrode layers, each of the two first electrode layers surrounds the corresponding word line in a direction parallel to a main surface of the substrate, and a second electrode of the first memristor structure and a second electrode of the second memristor structure share the same second electrode layer, and a resistive layer of the first memristor structure and a resistive layer of the second memristor structure share the same resistive material layer.

8. The resistive memory device according to any one of claims 1-7, comprising: A stacked structure, the stacked structure includes a first conductive layer and a composite structure layer alternately arranged in the first direction, and an insulating layer disposed between adjacent first conductive layers and composite structure layers, wherein each composite structure layer includes a second conductive layer, a second electrode layer and a resistive material layer, the second electrode layer surrounds the second conductive layer in a plane perpendicular to the main surface of the substrate and is surrounded by the resistive material layer, and each composite structure layer is located between two first conductive layers in the first direction; A via structure, extending through the stacked structure in the first direction, and including a conductive pillar, a dielectric layer and a channel layer, the dielectric layer surrounds a side wall of the conductive pillar, and the channel layer surrounds a side wall of the dielectric layer; And A first electrode layer, surrounding the via structure in a direction parallel to the main surface of the substrate and located between the composite structure layer and the via structure.

9. The resistive memory device according to claim 8, wherein the conductive pillar serves as gates and word lines of a plurality of transistors arranged in the first direction, the dielectric layer serves as a gate dielectric layer of the plurality of transistors, the channel layer serves as a channel region of the plurality of transistors, and the plurality of transistors include a first transistor and a second transistor of a plurality of memristor units arranged in the first direction; The first conductive layer serves as a first pole and a source line of a corresponding transistor in the plurality of transistors, and the second conductive layer serves as a bit line connected to the corresponding transistor and the memristor structure. The second electrode layer, the resistive material layer, and the first electrode layer serve as the second electrode, the resistive layer, and the first electrode of the memristor structure of the corresponding memristor unit, respectively, and the first electrode layer also serves as the second pole of the first transistor and the second pole of the second transistor in the corresponding memristor unit.

10. A method for manufacturing a resistive memory device, the resistive memory device including a substrate and a plurality of memristor units located on a main surface of the substrate, and forming each of the plurality of memristors includes: Forming a first transistor and a second transistor, each of the first transistor and the second transistor including a gate, a first pole, and a second pole, and having a channel region extending in a first direction perpendicular to the main surface of the substrate, wherein the second pole of the first transistor is connected to the second pole of the second transistor; And Forming a memristor structure, the memristor structure including a first electrode, a second electrode, and a resistive layer located between the first electrode and the second electrode, wherein the memristor structure is located on one side of the channel regions of the first transistor and the second transistor in a second direction parallel to the main surface of the substrate, and is connected to the second pole of the first transistor and the second pole of the second transistor.

11. The method for manufacturing a resistive memory device according to claim 10, including: Forming a stacked structure on the substrate, the stacked structure including a first conductive layer and a sacrificial layer alternately arranged in the first direction, and an insulating layer provided between adjacent first conductive layers and sacrificial layers; Forming a via hole in the stacked structure, the via hole extending through the stacked structure, and a side surface of the sacrificial layer being exposed by the via hole; Performing an etching process on the side surface of the sacrificial layer to form a lateral groove in the sacrificial layer; Forming a first electrode layer in the lateral groove; Forming a via hole structure in the via hole, the via hole structure including a conductive pillar, a dielectric layer, and a channel layer, the dielectric layer surrounding a side wall of the conductive pillar, and the channel layer surrounding a side wall of the dielectric layer; Removing the sacrificial layer to form a cavity; And Forming a composite structure layer in the cavity, the composite structure layer including a second conductive layer, a second electrode layer, and a resistive material layer, the second electrode layer surrounding the second conductive layer in a plane perpendicular to the main surface of the substrate, and being surrounded by the resistive material layer.

12. The method for manufacturing a resistive memory device according to claim 11, wherein the plurality of memristor units include a plurality of first memristor units arranged in the first direction, and the conductive pillar in the via hole structure serves as the gate of a plurality of first transistors and a plurality of second transistors and the word line connected to the gate in the plurality of first memristor units, the dielectric layer serves as the gate dielectric layer of the plurality of first transistors and the plurality of second transistors, and the channel layer serves as the channel region of the plurality of first transistors and the plurality of second transistors; At least a part of the first conductive layer serves as the first pole of the corresponding transistor in the corresponding memristor unit and the source line connected to the first pole; At least a part of the second conductive layer serves as the bit line of the corresponding memristor cell; At least a part of the second electrode layer, the resistive switching material layer, and the first electrode layer respectively serve as the second electrode, the resistive switching layer, and the first electrode of the memristor structure of the corresponding memristor cell, and the first electrode layer also serves as the second pole of the first transistor and the second pole of the second transistor in the corresponding memristor cell.

13. The method of manufacturing a resistive random access memory device according to claim 11 or 12, wherein forming the first electrode layer in the lateral groove comprises: Forming a first electrode material layer that lines the surface of the via and fills the lateral groove; And Removing the portion of the first electrode material layer that lines the surface of the via, and the remaining portion of the first electrode material layer in the lateral groove forms the first electrode layer, Wherein the sidewalls of the first electrode layer and the first conductive layer are exposed in the via and are aligned in the first direction.

14. The method of manufacturing a resistive random access memory device according to claim 11 or 12, wherein forming the via structure in the via comprises: First forming the channel layer in the via, the channel layer lining the surface of the via and contacting the first conductive layer and the first electrode layer of the stacked structure; Forming the dielectric layer along the surface of the channel layer in the via; And Forming the conductive pillar in the space in the via that is not filled by the channel layer and the dielectric layer.

15. The method of manufacturing a resistive random access memory device according to claim 11 or 12, wherein Forming the composite structure layer in the cavity comprises: Forming the resistive switching material layer, the resistive switching material layer lining the surface of the cavity and contacting the first electrode layer; Forming the second electrode layer along the surface of the resistive switching material layer in the cavity; And Forming the second conductive layer in the space in the cavity that is not filled by the resistive switching material layer and the second electrode layer.

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