Preparation method for improving saturation voltage drop of semiconductor device

Abstract

The invention discloses a preparation method for improving saturation voltage drop of a semiconductor device, and relates to the technical field of semiconductor preparation. O2 and H2 are introduced in the propulsion process of the emitter region, the oxygen layer prevents phosphorus diffusion, maintains high emitter region concentration and improves electron injection efficiency, meanwhile, doping compensation of the base region is avoided, low base region resistance Rb and contact resistance are maintained, and saturation voltage drop is reduced. The formula beta is equal to Ic / Ib, so that beta can be increased, the specification value of beta can be reached by using the same temperature and less time, and the production capacity and delivery time are greatly helped.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and particularly to an improvement in a method for manufacturing semiconductor devices to improve the saturation voltage drop. Background Art

[0002] A BJT (Bipolar Junction Transistor) is a semiconductor device with three terminals, widely used in fields such as signal amplification, switch control, and power management of electronic circuits. Its structure is as Figure 1 shown, including a back metal layer (Bake Metal), a collector region (Collector) composed of a silicon substrate (Substrate) and an epitaxial layer (Epi), a base region (Base), an emitter region (Emitter), a dielectric layer (SiO2), and a front metal layer (Top Metal).

[0003] The saturation voltage drop (Saturation Voltage Drop) is the voltage difference between the collector (Collector) and the emitter (Emitter) when the transistor is in the saturation state, denoted as V_CE(sat). The main impacts of the saturation voltage drop are as follows: Power consumption: When the triode operates in the saturation region, the collector current Ic flowing through Vce(sat) will generate conduction loss. If the saturation voltage drop Vce(sat) is too large, it will affect heat dissipation, and heat sinks will be added to the product or the operating current will be limited, otherwise it will affect the device operating life; Low-voltage power supply scenarios: In a 3.3V operating system, for example, Vce(sat) will occupy a large voltage margin, resulting in a decrease in the actual voltage obtained by the load, thereby affecting power supply efficiency; Impact on reliability: The heat generated by a high Vce(sat) may cause thermal breakdown (especially in high-current or high-temperature environments).

[0004] To address the above problems, currently, those skilled in the art usually optimize by means such as structural parameter optimization and temperature control. The main solutions are as follows: 1. Structural parameter optimization By adjusting physical parameters such as the channel width, channel length, and doping concentration of the BJT, the carrier mobility and conduction characteristics are optimized, thereby reducing the saturation voltage drop value. For example, increasing the base doping concentration can improve the conductivity, but the balance of parameters such as the breakdown voltage needs to be weighed.

[0005] Structural parameter optimization relies on high-precision manufacturing processes, resulting in an increase in production costs, and may face physical limit challenges in the trend of miniaturization.

[0006] 2. Temperature control design Use a heat sink, heat sink or temperature compensation circuit to suppress the deterioration of the saturation voltage drop caused by temperature rise. For example, introducing a negative feedback resistor in the emitter bias circuit can partially offset the influence of temperature on the operating point.

[0007] Despite the adoption of temperature compensation measures, the saturation voltage drop may still fluctuate due to changes in parasitic parameters in high-temperature or high-power scenarios.

[0008] Therefore, how to optimize based on the existing semiconductor device manufacturing process to solve the problem that the on-state loss of the device increases and affects the voltage drop parameters is the technical problem that needs to be solved urgently in this case. Summary of the Invention

[0009] The present invention aims at the above problems and provides an optimization based on the existing manufacturing process, effectively solving the problems of large and discrete saturation voltage drops.

[0010] The technical solution of the present invention is as follows: A manufacturing method for improving the saturation voltage drop of a semiconductor device, comprising the following steps: Step 1, prepare an initial oxide layer on the provided substrate; Step 2, perform base region lithography and pre-oxidation before base region implantation; Step 3, perform implantation and drive-in processes on the base region in sequence; Step 4, perform lithography and doping processes on the emitter region in sequence; Step 5, perform a drive-in process on the emitter region; S5.1, use N2 and O2 for high-temperature junction pushing; S5.2, after cooling, introduce H2 and O2 for annealing to grow an oxide layer; Step 6, perform front metal layer preparation, passivation layer preparation and back metal layer preparation processes in sequence.

[0011] Specifically, the base region implantation process in Step 3 includes: Step 3.11, perform base region lithography according to the product design Step 3.12, perform pre-oxidation before implantation Step 3.13, perform base region corresponding dose implantation doping according to the parameters required by the product.

[0012] Specifically, the drive-in implantation process in Step 3 includes: Step 3.21, use a high temperature of 1150°C - 1200°C in the furnace tube and a gas ratio of N2:O2 = 9 slm:6 slm for high-temperature junction pushing, and the junction pushing time is determined according to the product parameters.

[0013] Specifically, the emitter region doping process in Step 4 includes: Step 4.1, perform photolithography of the emission area according to the product design; Step 4.2: perform base region doping with corresponding dose according to the parameters required by the product.

[0014] Specifically, the preparation of the front metal layer in step six includes lead hole photolithography, front metal layer sputtering and front metal layer photolithography processes.

[0015] Specifically, the preparation of the passivation layer in step six includes a passivation process and a passivation etching process.

[0016] Specifically, in step 5, the junction temperature is increased by raising the standby temperature to 1050°C.

[0017] Specifically, in step 5, when the oxide layer is grown using the H2 and O2 method, the temperature is 950°C.

[0018] The present invention introduces O2 and H2 in the propulsion process of the emitter region. Since the oxygen layer prevents phosphorus diffusion, the high emission region concentration is maintained, the electron injection efficiency is improved, and the base region doping compensation is avoided, thereby maintaining a low base region resistance R b As well as contact resistance, the saturation voltage drop is reduced. According to the formula β = Ic / Ib, β will become larger. At the same temperature, it will take less time to reach the β specification value, which will also greatly help production capacity and delivery time. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 It is a schematic diagram of the structure of the device; Figure 2 is a schematic structural diagram of the substrate; Figure 3 Schematic diagram of the structure of the initial oxide layer; Figure 4 is a schematic diagram of the base region photolithography structure; Figure 5 This is a schematic diagram of the oxidation structure before base region implantation; Figure 6 It is a schematic diagram of the base region injection structure; Figure 7 It is a schematic diagram of the base area propulsion structure; Figure 8 is a schematic diagram of the lithographic structure of the emission region; Figure 9 is a schematic diagram of the doping structure of the emitter region; Figure 10 It is a schematic diagram of the propulsion structure of the launch area; Figure 11 It is a schematic diagram of the lead hole lithography structure; Figure 12 It is a schematic diagram of the metal sputtering structure; Figure 13 It is a schematic diagram of metal lithography structure; Figure 14 It is a schematic diagram of the structure after passivation; Figure 15 It is a schematic diagram of the passivation etching structure; Figure 16 It is a schematic diagram of the back metal sputtering structure; Figure 17 It is a schematic diagram of the influence on the parameter β by using the N2 / O2 + H2 / O2 structure program / using the pure N2 program; Figure 18 It is about the influence on the parameter Vce by using the N2 / O2 + H2 / O2 structure program / using the pure N2 program (sat) Influence schematic diagram; Figure 19 It is about the influence on the parameter Vbe by using the N2 / O2 + H2 / O2 structure program / using the pure N2 program (sat) Influence schematic diagram; Figure 20 It is a schematic diagram of the N2 / O2 + H2 / O2 structure program; Figure 21 It is a schematic diagram of the pure N2 structure program. Detailed implementation manners

[0020] The embodiments of the present invention will be described in detail below. The examples of the embodiments are shown in the drawings, where the same or similar reference numerals represent the same or similar elements or elements with the same or similar functions from beginning to end. The embodiments described below with reference to the drawings are exemplary and are only used to explain the present invention and should not be construed as a limitation to the present invention.

[0021] When preparing the BJT doping and then the push process, usually a pure N2 atmosphere is used for pushing, then a certain thickness of SiO2 is deposited, and then reflow is performed for densification. During this process, dopants such as phosphorus (P) and arsenic (As) in the emitter region will diffuse freely. Phosphorus (P) will diffuse outward and laterally into the base region, neutralizing a part of the acceptor impurities, and the resistance (R b ) of the base region increases, resulting in an increase in the saturation voltage drop; the free diffusion of phosphorus (P) will also cause the Emitter - Base to vary gradually, resulting in a decrease in the emission efficiency, an increase in the resistance (R b ) of the base region, and an increase in the base current (I b ), resulting in a decrease in the current gain (β = Ic / Ib).

[0022] The theoretical formula for the saturation voltage drop is: Vce (sat) =V f +Ie·R 体 +Ie·R b +Ie·Re+Ic·R 接触 Vbe (sat)=V f +I b ·Re + I b ·R b +I b ·R 接触 Among them, Vce (sat) represents the collector - emitter saturation voltage drop, V f represents the forward voltage drop, Ie represents the emitter current, R 体 represents the bulk resistance, R b represents the base resistance, Re represents the emitter resistance, Ic represents the collector current, R 接触 represents the contact resistance, Vbe (sat) represents the base - emitter saturation voltage drop, I b represents the base current.

[0023] From Figure 1 and the above formula, it can be known that the parameters for optimizing the saturation voltage drop (Vce (sat) ) mainly include the following aspects: 1), the doping profile of the emitter - base; 2), the base resistance (R b ), since the emitter of BJT is generally the most heavily doped, the emitter resistance (R e ) can be ignored; 3), the emitter contact resistance (mainly the basic quality of metal - semiconductor); 4), the carrier lifetime.

[0024] According to the above theoretical analysis, the technical solution of this case is as follows: A preparation method for improving the saturation voltage drop of a semiconductor device, comprising the following steps: Step 1, prepare an initial oxide layer on the provided substrate, Figure 3 the top blue SiO2 in it; Step 2, as Figure 4 shown, perform base lithography and pre - oxidation before base implantation, as Figure 5 shown; Step 3, perform implantation and drive - in processes on the base in sequence; as Figure 6 - 7 described; The implantation process includes: Step 3.11, perform base lithography according to the product design Step 3.12, perform pre - oxidation before implantation Step 3.13, perform base - corresponding dose implantation doping according to the parameters required by the product. Taking the NPN transistor shown in this article as an example: implant boron element, implant energy 60keV, implant dose 2E14cm -2~8E14 cm -2 .

[0025] The pusher injection process includes: Step 3.21, using the high temperature of 1150 °C - 1200 °C in the furnace tube, and the gas ratio of N2:O2 = 9 slm:6 slm for high-temperature pushing and annealing. The pushing and annealing time is determined according to the product parameters.

[0026] Step four, the emitter region is successively subjected to photolithography and doping processes; as Figure 8 - 9 described; The emitter region doping process includes: Step 4.1, perform emitter region photolithography according to the product design; Step 4.2, perform base region corresponding dose injection doping according to the parameters required by the product (taking the NPN transistor shown in this article as an example: P injects phosphorus element, injection energy 60 keV, injection dose 2 E15 cm -2 ~8E15 cm -2 ).

[0027] Step five, perform the pusher process on the emitter region, as Figure 10 described; The process of this step: heat up from the standby temperature of 750 °C (furnace tube gas ratio: N2:O2 = 9 slm:200 sccm) to 1050 °C (furnace tube gas ratio: N2:O2 = 9 slm:6 slm). The duration of the program is mainly determined by the breakdown voltage of BVCBO required by the device. After this step, the temperature is reduced to 950 °C (furnace tube gas ratio: H2:O2 = 9 slm:6 slm). The program time is mainly determined by the thickness of the dielectric layer required by the device. The structure of N2 / O2 + H2 / O2 is used as Figure 20 described, and the structure of pure N2 is used as Figure 21 described; S5.1, perform high-temperature pushing and annealing using N2 and O2; During the high-temperature pushing and annealing process, O2 will form a very thin oxide layer with a thickness of about 2500 ± 500 Å on the silicon surface. Since the diffusion coefficients of doping impurities in Si and SiO2 are very different, generally differing by 4 orders of magnitude, this layer helps to prevent the outward diffusion and lateral diffusion of doping impurities, shields the diffusion of pure N2 atmosphere to the base region, and neutralizes a part of the acceptor impurities, thereby making the emitter region doping steeper and reducing the base region resistance R b , and also reduces surface defects and improves the carrier mobility. The pushing and annealing temperature is to raise the standby temperature to 1050 °C.

[0028] S5.2, after cooling, introduce H2 and O2 for annealing to grow the oxide layer. When using the H2 and O2 method to grow the oxide layer, the temperature is 950 °C; H2 can effectively passivate the dangling bonds and interface states on the silicon surface, reduce the surface recombination rate, increase the carrier lifetime, reduce interface traps, improve the emitter-metal contact resistance, and thus reduce Vce (sat) ; slightly re-oxidize to optimize the SiO2 / Si interface quality and improve the uniformity of parameters.

[0029] Step five is the innovative step of this case. Compared with the prior art, the advantages are as follows: Influencing factors <![CDATA[Pure N2 (original plan)]]> <![CDATA[N2 / O2 + H2 / O2 (New Solution)]]> Influence Doping profile control Generally <![CDATA[Steeper (effect of SiO2)]]> Reduce base resistance Surface passivation Relatively poor <![CDATA[H2 passivation reduces interface states]]> Reduce contact resistance Repair thermal defects Limited repair <![CDATA[O2 Repair of Lattice Damage]]> Improve parameter uniformity Oxide layer quality Not optimized <![CDATA[Optimize the interface quality of SiO2 / Si]]> Improve parameter uniformity In this case, the oxygen layer prevents phosphorus diffusion, maintains a high emitter concentration, improves the electron injection efficiency, and at the same time avoids base doping compensation, keeping the base resistance R low b . From the formula β = Ic / Ib, so β will increase. Using the same temperature, it takes less time to reach the β specification value, which will also be very helpful for production capacity and delivery time. The push-rod temperature is to raise the standby temperature to 1050 °C.

[0030] Step six is to perform the processes of front metal layer preparation, passivation layer preparation, and back metal layer preparation in sequence; The front metal layer preparation includes lead hole lithography, front metal layer sputtering, and front metal layer lithography processes, as Figure 11 - 13 shown.

[0031] The passivation layer preparation includes passivation process and passivation etching process, as Figure 14 - 15 shown.

[0032] Figure 17 is the schematic diagram of the influence of the N2 / O2 + H2 / O2 structure program / the pure N2 program on the parameter β; the left frame is the actual test value of the parameter using the pure N2 program, and the right frame is the actual test value of the parameter using the N2 / O2 + H2 / O2 structure program. It can be seen from the figure that the β value using the N2 / O2 + H2 / O2 structure program will be significantly improved.

[0033] Figure 18 is the schematic diagram of the influence of the N2 / O2 + H2 / O2 structure program / the pure N2 program on the parameter Vce (sat) influence schematic diagram; the left frame is the actual test value of the parameter using the pure N2 program, and the right frame is the actual test value of the parameter using the N2 / O2 + H2 / O2 structure program. It can be seen from the figure that the parameter has a significant decrease and the uniformity will be significantly improved.

[0034] Figure 19 is the schematic diagram of the influence of the N2 / O2 + H2 / O2 structure program / the pure N2 program on the parameter Vbe (sat)Influence schematic diagram; the left box shows the actual test values of the pure N2 program parameters, and the right box shows the actual test values of the N2 / O2 + H2 / O2 structure program parameters. It can be seen from the diagram that the parameters have decreased significantly and the uniformity has been significantly improved.

[0035] Figure 20 It is a schematic diagram of the N2 / O2 + H2 / O2 structure program. The upper part shows the program temperature process curve, and the lower part shows the process gas atmosphere and ratio.

[0036] Figure 21 It is a schematic diagram of the pure N structure program. The upper part shows the program temperature process curve, and the lower part shows the process gas atmosphere and ratio.

[0037] Regarding the content disclosed in this case, the following points need to be explained: (1) The attached drawings of the embodiments disclosed in this case only relate to the structures involved in the embodiments disclosed in this case. Other structures can refer to the general design; (2) Without conflict, the embodiments disclosed in this case and the features in the embodiments can be combined with each other to obtain new embodiments; The above is only the specific implementation manner disclosed in this case, but the protection scope of this disclosure is not limited thereto. The protection scope disclosed in this case shall be subject to the protection scope of the claims.

Claims

1. A preparation method for improving the saturation voltage drop of a semiconductor device, characterized in that, It includes the following steps: Step 1, prepare an initial oxide layer on the provided substrate; Step 2, perform base region lithography and pre-oxidation before base region implantation; Step 3, sequentially perform implantation and drive-in processes on the base region; Step 4, sequentially perform lithography and doping processes on the emitter region; Step 5, perform a drive-in process on the emitter region; S5.1, use N2 and O2 for high-temperature junction pushing; S5.2, after cooling, introduce H2 and O2 for annealing to grow an oxide layer; Step 6, sequentially perform the processes of preparing the front metal layer, the passivation layer, and the back metal layer.

2. The preparation method for improving the saturation voltage drop of a semiconductor device according to claim 1, characterized in that, The base region implantation process in Step 3 includes: Step 3.11, perform base region lithography according to the product design Step 3.12, perform pre-oxidation before implantation Step 3.13, perform base region corresponding dose implantation doping according to the parameters required by the product.

3. The preparation method for improving the saturation voltage drop of a semiconductor device according to claim 1, characterized in that, The drive-in implantation process in Step 3 includes: Step 3.21, use a high temperature of 1150°C - 1200°C in the furnace tube, with a gas ratio of N2:O2 = 9 slm:6 slm for high-temperature junction pushing, and the junction pushing time is determined according to the product parameters.

4. The preparation method for improving the saturation voltage drop of a semiconductor device according to claim 1, wherein, The emitter region doping process in Step 4 includes: Step 4.1, perform emitter region lithography according to the product design; Step 4.2, perform base region corresponding dose implantation doping according to the parameters required by the product.

5. The manufacturing method for improving the saturation voltage drop of a semiconductor device according to claim 1, wherein The preparation of the front metal layer in Step 6 includes via hole lithography, front metal layer sputtering, and front metal layer lithography processes.

6. The manufacturing method for improving the saturation voltage drop of a semiconductor device according to claim 1, characterized in that, The preparation of the passivation layer in Step 6 includes a passivation process and a passivation etching process.

7. The manufacturing method for improving the saturation voltage drop of a semiconductor device according to claim 1, wherein, The junction pushing temperature in Step 5 is to raise the standby temperature to 1050°C.

8. The preparation method for improving the saturation voltage drop of a semiconductor device according to claim 1, characterized in that, When using the H2 and O2 method to grow the oxide layer in Step 5, the temperature is 950°C.

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