A method for preparing a high-frequency response power transistor

Abstract

The present invention relates to the field of semiconductor device manufacturing technology, and in particular to a method for preparing a high-frequency response power transistor. First, an N-drift layer is grown on an N+ silicon substrate with a resistivity of >1000Ω·cm. An isolation trench with a depth of 12μm and a depth-to-width ratio of 5.9:1 is etched by ICP, and a SiO2 / Si3N4 composite dielectric layer is filled to expand the depletion layer to 18.5μm, thereby reducing the collector junction capacitance to 68pF and the breakdown voltage to 205V. Secondly, an interdigitated emitter is formed on the front side, and the back side is thinned to 100±2μm and then laser drilled. The through-holes are filled with pulse electroplated copper, and the copper pillar array compresses the loop inductance to 2.7nH. Finally, a Ti / Ni / Au transition layer is sputtered, and a diamond-copper composite substrate is hot-pressed and bonded. An 80nm TiC phase is formed at the interface, with a thermal conductivity of 635W / m·K and a thermal resistance reduced to 0.61K / W. The present invention optimizes capacitance, inductance, and thermal resistance, reducing switching losses by 57.8% and increasing power density to 51.2W / cm 2 , suitable for MHz-level high-frequency power systems.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor device manufacturing, in particular to a method for preparing a high-frequency response power triode. Background Art

[0002] Currently, silicon-based power transistors have the following technical problems in high-frequency applications:

[0003] Parasitic capacitance problem: The collector junction capacitance (Cbc) and emitter junction capacitance (Cbe) form an RC delay during high-frequency switching, causing a sharp increase in switching loss of traditional devices at frequencies above 500kHz (measured > 1.5μJ / time). Traditional planar collector junctions have concentrated edge electric fields (peak value > 2×10 5 V / cm), resulting in the collector junction capacitance (C jc ) is generally greater than 100pF. When the switching frequency exceeds 500kHz, the RC delay effect causes the switching loss to increase exponentially (measured to be greater than 1.5μJ / time). Increasing the breakdown voltage requires increasing the drift layer thickness, which further deteriorates the capacitance characteristics.

[0004] Current path inductance issues: Traditional wire bonding results in a loop inductance of 5-10 nH, causing a voltage overshoot of >0.5V at 1MHz, forcing device derating. The tortuous current path formed by wire bonding (equivalent length ≥3mm) generates a loop inductance of 5-10 nH, causing a voltage overshoot of >0.5V at 1MHz, forcing device derating. Existing copper ribbon bonding solutions can reduce inductance by 28%, but increase thermal resistance by 35% (due to mismatched thermal expansion coefficients of the copper ribbon).

[0005] Heat accumulation problem: The thermal conductivity of silicon materials (150W / m·K) is insufficient, the device thermal resistance is >1.8K / W, the junction temperature rise rate is >15℃ / μs, and the power density is limited to 30W / cm 2 The intrinsic thermal conductivity of silicon material (150W / m·K) is insufficient, and combined with the interface thermal resistance of Al2O3 ceramic substrate (24W / m·K), the overall thermal resistance of the device is greater than 1.8K / W. When the power density is greater than 30W / cm 2 When the junction temperature rises at a rate greater than 15°C / μs, it may cause thermal collapse risk. Summary of the Invention

[0006] The object of the present invention is to provide a method for preparing a high-frequency response power transistor to solve the parasitic capacitance-loop inductance-heat accumulation triangle contradiction problem of silicon-based power transistors under high-frequency working conditions proposed in the above background technology.

[0007] To achieve the above object, the present invention provides a method for preparing a high-frequency response power transistor, comprising the following steps:

[0008] S1. Preparation of capacitance optimization layer:

[0009] The N+ type silicon substrate (thickness 650±50μm) with a resistivity of >1000Ω·cm is used. Its high resistance characteristic makes the depletion layer width Expanded to more than 2.3 times that of conventional devices;

[0010] An N-type low-doped drift layer (thickness 10±0.3μm, doping concentration (5±0.2)×10 14 cm -3 ); This design makes the breakdown voltage satisfy:

[0011] ;

[0012] An isolation trench with a depth and aspect ratio of 5.9:1 is formed by inductively coupled plasma (ICP) etching technology. The trench is filled with a SiO2 / Si3N4 composite dielectric layer (thickness ratio 2:1), whose dielectric constant (pure SiO2 is 3.9) effectively blocks the electric field coupling at the collector junction edge.

[0013] S2. Set the inductor optimization structure:

[0014] An interdigitated emitter metal layer (10±0.2μm in width and 15±0.3μm in spacing) is formed on the front of the device. This geometric configuration reduces the base resistance by 40%.

[0015] After thinning the backside to 100±2μm, an ultraviolet laser (wavelength 355nm) is used to drill holes to form a through-hole array with a diameter of 10±0.3μm (hole density 400±20 holes / mm²);

[0016] The through-holes are filled with copper pillars using a pulse electrochemical copper plating process, with a surface roughness Ra < 0.08 μm. The plating solution formula is: CuSO4·5H2O 200 g / L + H2SO4 50 g / L + Cl - 50 ppm + polyethylene glycol (PEG) 300 ppm + sodium disulfide propane sulfonate (SPS) 5 ppm; pulse parameters: forward current density 18 mA / cm 2 (Pulse width 10ms), reverse current density 5mA / cm 2 (Pulse width 3ms); achieves void-free filling of micropores with a depth-to-width ratio of 10:1 (void ratio <0.1% as detected by X-ray).

[0017] S3. Set up thermal management structure:

[0018] A Ti / Ni / Au transition layer (thickness 50 / 100 / 150 nm) is sputtered on the surface of the copper column; the Ti layer forms a TiSi2 Schottky barrier with silicon ( ), contact resistance The Ni layer acts as a diffusion barrier, inhibiting the migration of copper atoms into the semiconductor region; the Au layer provides a highly active bonding surface, reducing the bonding temperature to 450°C.

[0019] Hot-press bonded diamond-copper composite heat sink substrate (diamond volume fraction 55±3%); diamond pretreatment: 40-60 μm particle size classification, surface sputtering Ti / Mo metallization layer; vacuum hot pressing process: temperature 780°C (below the melting point of copper), pressure 25 MPa, holding time 30 minutes; composite layer thermal conductivity (Determined by laser flash method).

[0020] In the present invention, the high-resistance substrate ( ) makes the depletion layer width extend to 18.5μm (the traditional device is only 7.2μm), and the capacitance value is The proportion has decreased.

[0021] Deep trench isolation penetrates the entire drift region (12μm), dividing the collector junction into multiple independent units. Finite element simulation (COMSOL Multiphysics) confirmed that this structure reduces the edge electric field strength from 2.1×10 5 V / cm decreased to 1.3×10 5 V / cm, reducing dielectric coupling capacitance by 23%.

[0022] Compared with the prior art, the present invention has the following beneficial effects:

[0023] 1. In the preparation method of the high-frequency response power transistor, first, the high-resistance substrate (ρ>1000Ω·cm) vertically extends the depletion layer to 18.5μm, combined with deep trench isolation (trench depth = drift layer thickness) to block the lateral electric field, so that C jc The capacitance dropped to 68pF (a 40.9% decrease), while the breakdown voltage increased to 205V (a 17.1% increase). This approach addresses the inverse capacitance-voltage relationship of conventional planar junctions, improving the figure of merit (FOM) by 90.6%. Furthermore, a copper pillar array (10±0.3μm diameter) verticalizes the current path, compressing the loop inductance to 2.7nH (a 62.5% decrease), eliminating turn-off voltage overshoot (measured to <0.1V). Combined with an interdigitated emitter design, switching delay is reduced by 57.9%.

[0024] 2. In the preparation method of this high-frequency response power transistor, the diamond and copper composite substrate (55 vol% diamond + Ti / Mo interface layer) achieves an ultra-high thermal conductivity of 635 W / m·K, reducing the interface thermal resistance to 22%. The Ti / Ni / Au transition layer absorbs the thermal expansion mismatch stress through the 80nm TiC interface phase (shear strength 6.5 GPa), reducing the thermal resistance to 0.61 K / W (a decrease of 67.8%) and increasing the power density to 51.2 W / cm 2 (up 67.9%).

[0025] 3. In the preparation method of the high-frequency response power transistor, the copper pillar diameter is 10μm (aspect ratio of 10:1) to achieve void-free electroplating (void rate <0.1%), combined with a 450℃ low-temperature bonding process, the thermal cycle life is >2.5×10 5 times (increased by 201%); the precise matching of drift layer thickness (10μm) and deep trench depth (12μm) avoids breakdown voltage regression. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 This is a flowchart of the overall process of Example 1 of the present invention. DETAILED DESCRIPTION

[0027] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making any creative efforts shall fall within the scope of protection of the present invention.

[0028] Example 1: This example provides a method for preparing a high-frequency response power transistor, combining Figure 1 As shown, the following steps are included:

[0029] S1. Preparation of substrate and epitaxial layer

[0030] The resistivity of an N+ type silicon single crystal with a diameter of 150 mm and a thickness of 650±10 μm was measured by the four-probe method. Epitaxial growth was performed in a reduced pressure chemical vapor deposition (RP-CVD) reactor: the reaction gas used was dichlorosilane (SiH2Cl2) and hydrogen (H2) at a molar ratio of 1:50; the temperature was controlled at 1080±5°C (with real-time feedback from a thermocouple); the pressure was set at 80±2 Torr; and the doping source was phosphine (PH3), with the flow rate calibrated to 3.5×10 -4±5% L / min; the growth rate is 1.20±0.05μm / min, the total time is 8 minutes and 20 seconds, and the N-drift layer with a thickness of 10.02±0.15μm is obtained; the doping concentration of the epitaxial layer is tested by the Hall effect: at a temperature of 300K, the carrier concentration n=(5.15±0.12)×10 14 cm -3 , migration rate .

[0031] S2. Fabrication of deep trench isolation structure

[0032] Photolithographic definition of the groove area: coating AZ 5214 photoresist 1.2μm thick, UV exposure (wavelength 365nm, energy 200 mJ / cm 2 ), after development, a window with a line width of 2.4±0.05μm is formed.

[0033] ICP etching process:

[0034] Reaction gas: SF680sccm+C4F640sccm+O25sccm;

[0035] RF power: 600W (13.56 MHz) for the upper electrode and 200W (2 MHz) for the lower electrode;

[0036] Chamber temperature: -20±2℃ (liquid nitrogen cooling);

[0037] Etching rate: 1.10±0.03μm / min, total time 10 minutes and 55 seconds;

[0038] The groove depth was measured by a step profiler, and the sidewall angle was 88.7±0.3° (verified by SEM).

[0039] Dielectric layer deposition:

[0040] PECVD deposition of SiO2: temperature 300°C, SiH4 / N2O=200 / 400sccm, thickness 300±10nm;

[0041] LPCVD deposition of Si3N4: temperature 780°C, SiH2Cl2 / NH3=50 / 150sccm, thickness 150±5nm;

[0042] Annealing treatment: N2 atmosphere, 800℃ / 30min, eliminate interface state density to <5×10 10 cm -2 .

[0043] S3, copper pillar array formation

[0044] Back thinning: Diamond grinding wheel rough grinding + chemical mechanical polishing (CMP), the final thickness is 100.5±1.2μm, the surface roughness is .

[0045] Laser through-hole processing:

[0046] Equipment: Spectra-Physics HIPPO UV laser (wavelength, 355 nm); parameters: pulse energy 0.8 mJ, repetition rate 20 kHz, scan speed 500 mm / s; aperture: entrance 10.2 ± 0.3 μm, exit 9.8 ± 0.3 μm, taper <0.5°.

[0047] Electroplated copper fill:

[0048] Pretreatment: Sputtered Ti / Cu seed layer (20 / 200 nm); Plating tank: Rotating cathode design (rotation speed 30 ± 5 rpm); Pulse waveform: Forward 18 mA / cm 2 (10ms on) → zero current (5ms) → reverse 5 mA / cm 2 (3ms); Filling results: X-ray tomography shows that the copper density deviation from the hole bottom to the hole mouth is less than 0.3%.

[0049] S4. Heat dissipation integration and packaging

[0050] Transition layer deposition: magnetron sputtering Ti / Ni / Au (thickness 50 / 100 / 150 nm), background vacuum <5×10 -6 Torr,

[0051] Diamond-copper composite sheet preparation:

[0052] Mixing: 45-55μm diamond powder (55vol%) + electrolytic copper powder (45vol%); ball milling: argon protection, speed 200rpm, time 2h; hot pressing: heating rate 10℃ / min, 780℃ holding time 30min, pressure 25MPa.

[0053] Thermal Compression Bonding:

[0054] Equipment: EVG 520IS bonder; parameters: temperature 450±5°C, pressure 15±0.5 MPa, time 10 min; interface analysis: SEM showed that the Ti layer formed a continuous TiC phase (thickness approximately 80 nm) with the diamond surface.

[0055] Example 2: The high-frequency response power transistor prepared in Example 1 was subjected to an electrothermal performance limit test.

[0056] Test conditions:

[0057] The power supply uses the Keysight B1505A power device analyzer; load: inductor Working conditions: , , , duty cycle 50%

[0058] Thermal environment: water cooling plate temperature T c =25±0.5℃.

[0059] Table 1 Test results

[0060]

[0061] Example 3: For the high-frequency response power transistor prepared in Example 1, the structural parameter boundary verification is performed.

[0062] Table 2 Copper pillar diameter optimization experiment

[0063]

[0064] Table 3 Influence of deep groove depth

[0065]

[0066] When the trench depth is greater than the drift layer thickness, the breakdown voltage will fall back because the depletion region penetrates into the substrate.

[0067] Comparative Example 1: This comparative example provides a traditional bonding wire packaging method. The differences between this comparative example and Example 1 are specifically shown in Table 4.

[0068] Table 4

[0069]

[0070] Traditional bond wire packaging uses a tortuous path to create a large current loop (equivalent length 3mm). This inductive effect results in switching losses as high as 1.82μJ. Furthermore, the alumina substrate's insufficient thermal conductivity (24W / m·K) causes localized hotspots (thermal resistance 2.05K / W). This solution utilizes vertical copper pillar interconnects (100μm in length) and diamond composite heat sinks (635W / m·K). This not only reduces switching losses by 62.1%, but also increases power density by 75% through a three-dimensional thermal management channel. This dual electromagnetic and thermal path overcomes the space limitations of traditional packaging.

[0071] Comparative Example 2: This comparative example provides an isolation structure without deep trenches. The differences between this comparative example and Example 1 are specifically shown in Table 5.

[0072] Table 5

[0073]

[0074] The planar collector junction exhibits a high capacitance (115pF) due to concentrated electric fields at the edges, and even the use of a high-resistance substrate (Comparative Example 5) fails to fundamentally improve this. The deep trench isolation structure of the present invention, which blocks the lateral electric field through a SiO2 / Si3N4 composite dielectric, reduces the capacitance by 40.9% to 68pF, while simultaneously increasing the breakdown voltage by 17.1%. This demonstrates that the trench depth must be equal to the drift layer thickness (a 12μm deep trench matches a 10μm drift layer) to shift the electric field distribution from concentrated at the edges to uniform across the entire region.

[0075] Comparative Example 3: Based on Example 1, this comparative example modified the copper pillar diameter to 15 μm and the spacing to 45 μm. The specific differences between this comparative example and Example 1 are shown in Table 6.

[0076] Table 6

[0077]

[0078] When the copper pillar diameter increased to 15μm (a 50% deviation from the optimal value), the current loop area expanded due to the decrease in cell density, causing the loop inductance to surge 40.7% to 3.8nH. More seriously, the aspect ratio dropped to 6.7:1, causing plating voids (0.5%) and a 28% degradation in thermomechanical reliability. This demonstrates that a 10μm diameter meets the process limit for pulse plating to fill voids (aspect ratio of 10:1) while minimizing inductance.

[0079] Comparative Example 4: Based on Example 1, this comparative example modified the amount of diamond to 30 vol% and the amount of copper to 70 vol%. The specific differences between this comparative example and Example 1 are shown in Table 7.

[0080] Table 7

[0081]

[0082] Low diamond volume fractions (30%) lack a continuous thermal network, resulting in a thermal conductivity of only 320 W / m·K and a high interfacial thermal resistance of 68%. This invention, by combining a 55% diamond content with Ti / Mo metallization, establishes efficient phonon transmission channels between diamond particles (thermal conductivity of 635 W / m·K), reducing the interfacial thermal resistance to 22%. This design surpasses the value predicted by effective medium theory (the formula calculates a limit of 520 W / m·K), and is the key to achieving exceptional thermal performance through interfacial nanostructures.

[0083] Comparative Example 5: This comparative example adopts a preparation method in which a high-resistance substrate is not combined with a deep trench. The differences between this comparative example and Example 1 are specifically shown in Table 8.

[0084] Table 8

[0085]

[0086] While using a high-resistance substrate alone can vertically expand the depletion layer (breakdown voltage 185V), the lack of lateral electric field control reduces the capacitance to only 92pF. The present invention combines deep trench isolation with a high-resistance substrate to simultaneously expand the depletion region vertically and horizontally (confirmed by COMSOL simulation), further reducing the capacitance to 68pF and boosting the breakdown voltage to 205V. This three-dimensional depletion region manipulation improves the figure of merit (FOM) by 90.6%, demonstrating the strong nonlinear synergy between the two technologies.

[0087] Comparative Example 6: This comparative example adopts a preparation method of direct bonding without a transition layer. The differences between this comparative example and Example 1 are specifically shown in Table 9.

[0088] Table 9

[0089]

[0090] Direct bonding without a transition layer requires a high temperature of 600°C and generates a brittle Cu2O phase (up to 2μm thick), resulting in an interface thermal resistance of up to 8.7mm. 2 ·K / W. The Ti / Ni / Au gradient transition layer of the present invention forms an 80nm TiC interface phase at a low temperature of 450℃, which not only achieves high phonon transmission (thermal resistance 3.2 mm 2 K / W), and absorbs thermal stress through plastic deformation (shear strength increases by 85.7%). This low-temperature reaction-nanointerface design solves the challenge of heterogeneous integration of diamond and copper.

[0091] The above shows and describes the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The above embodiments and descriptions are merely preferred examples of the present invention and are not intended to limit the present invention. Various changes and improvements may be made to the present invention without departing from the spirit and scope of the present invention. Such changes and improvements fall within the scope of the present invention. The scope of protection claimed in the present invention is defined by the appended claims and their equivalents.

Claims

1. A method for preparing a high-frequency response power transistor, characterized in that: The following steps are involved: S1, using an N+ type silicon substrate with a resistivity of >1000Ω·cm and a thickness of 600-700μm, growing an N- type drift layer on the front of the substrate with a thickness of 9.7-10.3μm and a doping concentration of 4.8-5.2×10 14 cm -3 ); ICP etching is used to form an isolation trench with a depth of 11.5-12.5 μm and a depth-to-width ratio of 5.9:

1. The trench is filled with a SiO2 / Si3N4 composite dielectric layer with a thickness ratio of 2:

1. S2. Form an interdigitated emitter metal layer on the front of the device, with a finger width of 9.8-10.2μm and a spacing of 14.7-15.3μm; After the backside is thinned to 98-102μm, laser drilling is performed to form a through-hole array with a diameter of 9.7-10.3μm, with a hole density of 380-420 holes / mm 2 ; Pulse electroplating of copper to fill through-holes forms copper pillars, and the plating solution contains polyethylene glycol and sodium disulfide dipropane sulfonate; S3, sputtering a Ti / Ni / Au transition layer on the surface of the copper pillar; Hot-press bonding of diamond-copper composite heat dissipation substrate, diamond volume fraction: 52-58%, Ti / Mo metallization layer sputtered on diamond surface, bonding temperature: 445-455℃, pressure: 1.5-15.5MPa.

2. The method for preparing a high-frequency response power transistor according to claim 1, wherein: In the above-mentioned S1, the depth of the isolation trench is 1.2 times the thickness of the drift layer.

3. The method for preparing a high-frequency response power transistor according to claim 1, wherein: In S1, the composite dielectric layer is composed of 290-310 nm SiO2 deposited by PECVD and 145-155 nm Si3N4 deposited by LPCVD.

4. The method for preparing a high-frequency response power transistor according to claim 1, wherein: In S1, the growth conditions of the drift layer are: reduced pressure chemical vapor deposition, a reaction gas molar ratio of SiH2Cl2:H2=1:50, a temperature of 1075-1085°C, and a pressure of 78-82 Torr; Doping source PH3 flow rate 3.5×10 -4 ±5% L / min, growth rate 1.15-1.250μm / min.

5. The method for preparing a high-frequency response power transistor according to claim 1, wherein: In S2, the pulse electroplating adopts a rotating cathode design.

6. The method for preparing a high-frequency response power transistor according to claim 1, wherein: When the diamond-copper composite heat dissipation substrate is prepared, the particle size of the diamond powder is 45-55 μm.

7. The method for preparing a high-frequency response power transistor according to claim 1, wherein: In the S2, the through hole taper is less than 0.5°, the inlet diameter is 9.9-10.5 μm, and the outlet diameter is 9.5-10.1 μm.

8. The method for preparing a high-frequency response power transistor according to claim 1, wherein: In S2, the laser drilling adopts an ultraviolet laser with a wavelength of 355 nm, a pulse energy of 0.8 mJ, and a repetition frequency of 20 kHz.

9. The method for preparing a high-frequency response power transistor according to claim 1, wherein: In S3, a TiC interface phase is formed during the hot pressing bonding process.

10. The method for preparing a high-frequency response power transistor according to claim 1, wherein: In S2, after the copper pillars are filled, the void ratio is less than 0.1% as detected by X-ray.

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