NMOS (N-channel metal oxide semiconductor) device structure and forming method of NMOS device structure

Abstract

The invention discloses an NMOS device structure and a forming method of the NMOS device structure, the NMOS device structure comprises an SOI substrate, the SOI substrate comprises a top silicon layer, a source region, a drain region and a body contact region are distributed in the top silicon layer, the drain region is adjacent to the source region, the body contact region is adjacent to the source region, and the drain region and the body contact region are respectively located at different sides of the source region; the first isolation structure is located in the top silicon layer between the adjacent source region and body contact region, the surface of the first isolation structure is flush with the surface of the top silicon layer, the first isolation structure separates the adjacent source region and body contact region, and the height of the first isolation structure is smaller than the thickness of the top silicon layer; the gate structure is located on the surface of the top silicon layer, and the source region and the drain region are located on the two sides of the gate structure respectively. Parasitic devices can be reduced, the suppression effect of the floating body effect is improved, and the integration level of the devices is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductors, and particularly to an NMOS device structure and a method for forming the NMOS device structure. Background Art

[0002] Compared with bulk silicon devices, PD-SOI devices (partially depleted SOI devices) fabricated on SOI substrates are widely used in fields such as radio frequency and MEMS due to their superior performance such as good device isolation, no latch-up effect, and reduced coupling effects between active and passive devices and the substrate.

[0003] However, the Kink effect caused by the floating body effect of PD-SOI devices is harmful in analog circuits. To suppress the floating body effect, the body is usually connected to a fixed potential to control the change of the body potential, and this method is called body contact.

[0004] As Figure 1 and Figure 2 shown, in the traditional T-shaped gate structure body contact, P+ is ion-implanted downward from the top part area of the T-shaped gate 10 to form a P+ implantation area 20, and the P+ implantation area 20 is connected to the P-type body area 30 under the T-shaped gate 10. When the MOS device works, the hole carriers accumulated in the P-type body area 30 are discharged through the P+ implantation area 20 to achieve the purpose of reducing the body area potential. However, there are large parasitic capacitances and parasitic resistances between the additional T-shaped gate extension area and the underlying oxide and the top silicon layer, resulting in device performance delay and reducing the circuit performance. Summary of the Invention

[0005] The technical problem solved by the present invention is to provide an NMOS device structure and a method for forming the NMOS device structure to reduce parasitic devices, improve the suppression effect of the floating body effect, and improve device integration.

[0006] To solve the above technical problem, the technical solution of the present invention provides an NMOS device structure, including: an SOI substrate, the SOI substrate includes a top silicon layer, source regions, drain regions, and body contact regions are distributed in the top silicon layer, the drain regions are adjacent to the source regions, the body contact regions are adjacent to the source regions, and the drain regions and the body contact regions are respectively located on different sides of the source regions; a first isolation structure, located in the top silicon layer between adjacent source regions and body contact regions, and the surface of the first isolation structure is flush with the surface of the top silicon layer, the first isolation structure separates the adjacent source regions and body contact regions, and the height of the first isolation structure is less than the thickness of the top silicon layer; a gate structure, located on the surface of the top silicon layer, and the source regions and the drain regions are respectively located on both sides of the gate structure.

[0007] Optionally, the SOI substrate further includes a bottom silicon layer and a buried oxide layer of SOI located between the top silicon layer and the bottom silicon layer; the NMOS device structure further includes: a back buried oxide layer located within the top silicon layer, with a first spacing between the back buried oxide layer and the buried oxide layer of SOI, and the width of the back buried oxide layer being greater than the width of the first isolation structure, such that the first isolation structure is located on the top surface of the back buried oxide layer.

[0008] Optionally, it further includes: a second isolation structure penetrating through the top silicon layer, and the second isolation structure surrounds the source region, the drain region, and the body contact region.

[0009] Optionally, the source region and the drain region are arranged along a first direction, the body contact region includes a first type of body contact region, the first type of body contact region and the source region are arranged along a second direction, the first isolation structure includes a first type of first isolation structure located between the source region and the first type of body contact region, and the first type of first isolation structure is flush with or extends beyond the boundary of the source region in the first direction to separate the source region from the adjacent first type of body contact region, and the second direction is perpendicular to the first direction.

[0010] Optionally, the first type of body contact region is also adjacent to the drain region, and the first type of first isolation structure is flush with or extends beyond the drain region in the first direction.

[0011] Optionally, the gate structure includes a first part of the gate and a second part of the gate that are connected and form an "L" - shaped structure, the first part of the gate extends along the first direction, the second part of the gate extends along the second direction, the source region and the drain region are located on both sides of the first part of the gate, the second part of the gate is located on the surface of the first type of first isolation structure adjacent to the drain region, and the second part of the gate extends beyond the boundary of the drain region in the first direction.

[0012] Optionally, the number of the first type of body contact regions is 2, and along the second direction, the first type of body contact regions are respectively located on both sides of the source region.

[0013] Optionally, the body contact region includes a second type of body contact region, the second type of body contact region, the source region, and the drain region are arranged in sequence along the first direction, the first isolation structure includes a second type of first isolation structure located between the source region and the second type of body contact region, and the second type of first isolation structure is flush with or extends beyond the boundary of the source region in the second direction to separate the source region from the adjacent second type of body contact region.

[0014] Correspondingly, the technical solution of the present invention further provides a method for forming an NMOS device structure, including: providing an SOI substrate, where the SOI substrate includes a top silicon layer; forming a first isolation structure in the top silicon layer, the surface of the first isolation structure is flush with the surface of the top silicon layer, and the height of the first isolation structure is less than the thickness of the top silicon layer; after forming the first isolation structure, forming a source region, a drain region, and a body contact region in the SOI substrate respectively, the drain region is adjacent to the source region, the body contact region is adjacent to the source region, and the drain region and the body contact region are respectively located on different sides of the source region, the first isolation structure is located between the adjacent source region and the body contact region, and the first isolation structure separates the adjacent source region and the body contact region; after forming the source region, the drain region, and the body contact region, forming a gate structure on the surface of the top silicon layer, and the source region and the drain region are respectively located on both sides of the gate structure.

[0015] Optionally, the SOI substrate further includes a bottom silicon layer and an SOI buried oxide layer located between the top silicon layer and the bottom silicon layer; the method for forming the first isolation structure includes: forming a patterned first mask structure on the top silicon layer; using the first mask structure as a mask to perform ion implantation on the top silicon layer; after performing ion implantation on the top silicon layer, performing an annealing step to form a post-buried oxide layer in the top silicon layer, there is a first distance between the post-buried oxide layer and the SOI buried oxide layer, and there is a second distance between the post-buried oxide layer and the surface of the top silicon layer; after forming the post-buried oxide layer, forming a patterned second mask structure on the top silicon layer; using the second mask structure as a mask to etch the top silicon layer until the top surface of the post-buried oxide layer is exposed, and forming a first isolation groove in the top silicon layer; forming the first isolation structure in the first isolation groove; the method for forming the NMOS device structure further includes: using the second mask structure as a mask, when etching the top silicon layer to form the first isolation groove, etching the top silicon layer until the top surface of the SOI buried oxide layer is exposed to form a second isolation groove; forming a second isolation structure in the second isolation groove, and the second isolation structure surrounds the source region, the drain region, and the body contact region. Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0016] In the NMOS device structure and the method for forming the NMOS device structure provided by the technical solution of the present invention, the drain region and the body contact region are respectively located on different sides of the source region. The first isolation structure is located in the top silicon layer between the adjacent source region and the body contact region. The surface of the first isolation structure is flush with the surface of the top silicon layer. The first isolation structure separates the adjacent source region and the body contact region, and the height of the first isolation structure is less than the thickness of the top silicon layer. Therefore, on the one hand, the first isolation structure separates the adjacent source region and the body contact region. On the other hand, the lower part of the first isolation structure provides a sufficient channel for the holes to be exported between the source region and the body contact region, so as to achieve a good suppression effect on the floating body effect. On this basis, since the above structure is adopted to suppress the floating body effect, therefore, while suppressing the floating body effect, the generation of parasitic devices is reduced or even avoided. Especially compared with the structure of the traditional T-shaped gate, the NMOS device structure provided by the present technical solution greatly reduces or even avoids the parasitic capacitance and parasitic resistance formed between the gate and the top silicon layer, the parasitic MOS transistor formed by the T-shaped gate, the active region and the oxide layer therebetween, and the parasitic diode existing in the T-shaped gate (with reverse ion implantation up and down). Thus, not only the suppression effect of the floating body effect is improved, but also the device performance is greatly enhanced due to the reduction of parasitic devices. In addition, compared with the T-shaped gate that requires reverse ion implantation (N-type and P-type), the size of the first isolation structure is smaller. Therefore, it is also beneficial to improve the integration degree. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 is a schematic structural diagram of a PD-SOI device;

[0018] Figure 2 is Figure 1 a schematic cross-sectional structure diagram along the A1-A2 direction in;

[0019] Figures 3 to 13 is a schematic structural diagram of each step in the method for forming the NMOS device structure in an embodiment of the present invention;

[0020] Figure 14 is a schematic top view structural diagram of the NMOS device structure in another embodiment of the present invention;

[0021] Figure 15 is a schematic top view structural diagram of the NMOS device structure in still another embodiment of the present invention.

[0022] Reference numerals in the drawings:

[0023] 100 - SOI substrate; 101 - bottom silicon layer; 102 - buried oxide layer; 103 - top silicon layer; 104 - metal silicide layer; 110 - oxidation protection layer; 120 - first mask structure; 130 - post - buried oxide layer; 140 - second mask structure; 141 - hard mask layer; 142 - second photoresist layer; 150 - first isolation groove; 151 - first isolation structure; 1511 - first type of first isolation structure; 1512 - second type of first isolation structure; 160 - second isolation groove; 161 - second isolation structure; 170, 270 - gate structure; 271 - first part of the gate; 272 - second part of the gate; 181 - first conductive structure; 182 - second conductive structure; 183 - third conductive structure; 184 - fourth conductive structure; S - source region; D - drain region; B - body contact region; B1 - first type of body contact region; B2 - second type of body contact region; X - first direction; Y - second direction. Detailed implementation manners

[0024] As described in the background art, in the existing PD - SOI device structure, there are large parasitic capacitance and parasitic resistance between the body contact and the bottom silicon of the SOI substrate, resulting in circuit device delay and reduced RF performance.

[0025] To solve the above - mentioned technical problems, the technical solution of the present invention provides an NMOS device structure and a method for forming the same. The drain region and the body contact region are both adjacent to the source region, the drain region and the body contact region are respectively located on different sides of the source region, the gate structure is located on the surface of the top silicon layer, and on the basis that the source region and the drain region are respectively located on both sides of the gate structure, by setting a first isolation structure in the top silicon layer between the adjacent source region and the body contact region, the surface of the first isolation structure is flush with the surface of the top silicon layer, separating the adjacent source region and the body contact region, and the height of the first isolation structure is less than the thickness of the top silicon layer, so as to reduce parasitic devices, improve the suppression effect of the floating body effect, and improve device integration.

[0026] To make the above - mentioned objects, features and beneficial effects of the present invention more obvious and understandable, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0027] The terms "first", "second", "third", "fourth", etc. (if any) in the description, claims and drawings of the present invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device comprising a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices. In addition, directional terms such as above, below, up, down, upward, downward, left, right, etc. are used relative to the exemplary embodiments as shown in the figures, with the upward or upper direction towards the top of the corresponding figure and the downward or lower direction towards the bottom of the corresponding figure.

[0028] Figures 3 to 13 are schematic structural diagrams of the steps in the method for forming an NMOS device structure in an embodiment of the present invention.

[0029] Please refer to Figure 3 , and provide an SOI substrate 100.

[0030] Among them, the SOI substrate 100 may include a bottom silicon layer 101, a buried oxide layer 102, and a top silicon layer 103 stacked in sequence.

[0031] Next, a first isolation structure 151 is formed in the top silicon layer 103. The following Figures 4 to 9 details the specific steps of forming the first isolation structure 151 in detail.

[0032] Please refer to Figure 4 , and form an oxidation protection layer 110 on the surface of the SOI substrate 100.

[0033] In this embodiment, the material of the oxidation protection layer 110 may be silicon oxide.

[0034] In other embodiments, the oxidation protection layer 110 may not be formed either.

[0035] Please continue to refer to Figure 4 , and form a patterned first mask structure 120 on the surface of the oxidation protection layer 110.

[0036] In this embodiment, the material of the first mask structure 120 may include photoresist.

[0037] Specifically, the method for forming the first mask structure 120 includes: forming a photoresist material layer of the first mask structure 120 on the surface of the oxidation protection layer 110; irradiating and developing the photoresist material layer of the first mask structure 120 through a photo mask to form the patterned first mask structure 120.

[0038] Since the oxidation protection layer 110 is formed on the surface of the SOI substrate 100 before forming the first mask structure 120, on the one hand, the oxidation protection layer 110 plays a role in protecting the surface of the SOI substrate 100 during the formation of the first mask structure 120. On the other hand, the oxidation protection layer 110 can also serve as an ion implantation barrier during the subsequent formation of the buried oxide layer 130, so as to precisely control the ion implantation depth, thereby forming the buried oxide layer 130 at the expected depth.

[0039] Please refer to Figure 5 , using the first mask structure 120 as a mask, perform ion implantation on the top silicon layer 103.

[0040] Specifically, in the process of ion implanting the top silicon layer 103, the implanted ions are oxygen ions. Moreover, by adjusting the thickness of the aforementioned oxidation protection layer 110 and the ion implantation energy, the implantation depth of the oxygen ions is controlled, and by adjusting the ion implantation dose, the implanted ion concentration is controlled.

[0041] It should be noted that since the subsequently formed buried oxide layer 130 needs to have a spacing both from the surface of the top silicon layer 103 and from the SOI buried oxide layer 102, the oxygen ions implanted here are required to have a preset depth within the top silicon layer 103 and be at a distance from the surface of the SOI buried oxide layer 102. In the actual preparation process, by adjusting the thickness of the oxidation protection layer 110 and controlling the implantation energy of the ion implantation process, etc., the purpose of ensuring that the implanted oxygen ions have a preset depth within the top silicon layer 103 and are at a distance from the surface of the SOI buried oxide layer 102 can be achieved.

[0042] Please refer to Figure 6 , after ion implanting the top silicon layer 103, perform an annealing step to form the buried oxide layer 130 within the top silicon layer 103.

[0043] Through the annealing step, the oxygen ions implanted in the top silicon layer 103 can react with silicon to form the buried oxide layer 130. Specifically, the material of the buried oxide layer 130 may include silicon oxide.

[0044] In this embodiment, there is a spacing greater than 0 nanometers between the surface of the back buried oxide layer 130 and the top silicon layer 103 and the SOI buried oxide layer 102. Among them, the spacing between the back buried oxide layer 130 and the SOI buried oxide layer 102 is the first spacing, and the spacing between the back buried oxide layer 130 and the surface of the top silicon layer 103 is the second spacing.

[0045] Since the back buried oxide layer 130 is formed in the top silicon layer 103 and has a spacing from both the surface of the top silicon layer 103 and the SOI buried oxide layer 102, that is to say, the back buried oxide layer 130 has a certain depth in the top silicon layer 103, but at the same time has a certain distance from the SOI buried oxide layer 102. Therefore, by the blocking at the back buried oxide layer 130, when etching the top silicon layer 103, a groove that stops at the back buried oxide layer 130 can be formed. Thus, the same photomask can be used to etch the top silicon layer 103 subsequently to simultaneously form the first isolation groove 150 with different depths and other STI isolation grooves (such as the second isolation groove 160). Thus, the formation process of the first isolation structure 151 is simplified, and the preparation of the NMOS device structure can be realized with simple process steps.

[0046] In one embodiment, the first spacing accounts for more than 1% of the thickness of the top silicon layer 103.

[0047] In one embodiment, the annealing temperature of the annealing process in this annealing step is greater than 1000 °C, and the annealing duration is greater than 0.5 hours.

[0048] In this embodiment, before the annealing step, the first mask structure 120 is removed and a cleaning step is performed. Among them, the process of removing the first mask structure 120 may include an ashing process, etc.

[0049] Next, please refer to Figure 7 , a patterned second mask structure 140 is formed on the top silicon layer 103.

[0050] In this embodiment, the second mask structure 140 may include: a hard mask layer 141 and a second photoresist layer 142 located on the surface of the hard mask layer 141. Since the second mask structure 140 is a composite layer composed of the hard mask layer 141 (HardMask) with a relatively high hardness and the second photoresist layer 142, it helps to improve the accuracy of subsequent pattern transfer, and first isolation grooves 150 and second isolation grooves 160 with more precise dimensions and better morphologies can be formed subsequently.

[0051] Among them, the material of the hard mask layer 141 may be a material with a relatively high hardness such as silicon nitride.

[0052] Specifically, the method for forming the second mask structure 140 may include: forming a hard mask material layer (not shown) on the surface of the oxidation protection layer 110; forming an initial second photoresist layer (not shown) on the surface of the hard mask material layer; irradiating and developing the initial second photoresist layer through a photomask to form a patterned second photoresist layer 142; using the second photoresist layer 142 as a mask to etch the hard mask material layer until the surface of the oxidation protection layer 110 is exposed, and transferring the pattern of the second photoresist layer 142 to the hard mask material layer to form a hard mask layer 141.

[0053] In other embodiments, the hard mask layer 141 may not be formed.

[0054] In this embodiment, since the oxidation protection layer 110 is formed on the surface of the top silicon layer 103 before forming the patterned second mask structure 140 on the top silicon layer 103, the oxidation protection layer 110 can also play a role in protecting the surface of the SOI substrate 100 when etching the hard mask material layer.

[0055] Please refer to Figure 8 , using the second mask structure 140 as a mask, etching the top silicon layer 103 until the top surface of the buried oxide layer 130 is exposed, and forming a first isolation groove 150 in the top silicon layer 103.

[0056] Among them, the first isolation groove 150 is used to provide space for forming the first isolation structure 151 subsequently.

[0057] In this embodiment, the groove width W2 of the first isolation groove 150 (as shown in Figure 8 ) is smaller than the width W1 of the buried oxide layer 130 (as shown in Figure 8 ), so as to ensure that the first isolation structure 151 formed in the first isolation groove 150 subsequently can be accurately located on the top surface of the buried oxide layer 130. That is to say, the projection of the first isolation structure 151 on the surface of the SOI substrate 100 is located within the projection of the buried oxide layer 130 on the surface of the SOI substrate 100.

[0058] In this embodiment, while forming the first isolation groove 150, using the second mask structure 140 as a mask, etching the top silicon layer 103 outside the upper part of the buried oxide layer 130 until the top surface of the SOI buried oxide layer 102 is exposed, and forming a second isolation groove 160.

[0059] Among them, the second isolation groove 160 is used to provide space for forming the second isolation structure 161 subsequently.

[0060] Thus, through the buried oxide layer 130, first isolation grooves 150 and second isolation grooves 160 with different depths can be formed in the same etching process using the same photomask.

[0061] In one embodiment, using the second mask structure 140 as a mask, the process of etching the top silicon layer 103 may include at least one of a dry etching process and a wet etching process.

[0062] In this embodiment, after forming the first isolation groove 150 and the second isolation groove 160, the second photoresist layer 142 is removed.

[0063] Next, please refer to Figure 9 , a first isolation structure 151 is formed in the first isolation groove 150.

[0064] Wherein, the height H1 of the first isolation structure 151 is less than the thickness H2 of the top silicon layer 103.

[0065] In this embodiment, while forming the first isolation structure 151, a second isolation structure 161 is formed in the second isolation groove 160, thereby further simplifying the manufacturing process of the NMOS device structure.

[0066] In this embodiment, the bottom of the second isolation structure 161 is connected to the SOI buried oxide layer 102, and the second isolation structure 161 surrounds the source region S, the drain region D, and the body contact region B. That is to say, the second isolation structure 161 is used for isolation between devices.

[0067] Specifically, the method of forming the first isolation structure 151 in the first isolation groove 150 and the second isolation structure 161 in the second isolation groove 160 may include: depositing an isolation material layer (not shown) in the first isolation groove 150, the second isolation groove 160, and on the surface of the hard mask layer 141, and the surface of the isolation material layer is higher than the surface of the hard mask layer 141; using a chemical mechanical polishing process (CMP) to polish the isolation material layer, the hard mask layer 141, and the oxidation protection layer 110 until the surface of the SOI substrate 100 is exposed.

[0068] Wherein, the formation process of the isolation material layer may be a chemical vapor deposition process (CVD) or a physical vapor deposition process (PVD).

[0069] In other embodiments, the post-buried oxide layer 130 may not be formed, and the first isolation groove 150 and the second isolation groove 160 are respectively formed, and the first isolation structure 151 and the second isolation structure 161 are respectively formed.

[0070] In addition, the materials of both the first isolation structure 151 and the second isolation structure 161 are dielectric materials.

[0071] Next, please refer to Figures 10 to 13 , Figure 10 is Figure 11 , Figure 12 and Figure 13 a top view structural schematic diagram ofFigure 11 is Figure 10 a schematic cross-sectional structure view along direction A1 - A2 in Figure 12 is Figure 10 a schematic cross-sectional structure view along direction A3 - A4 in , and Figures 3 to 9 both are Figure 12 in the same view direction as Figure 13 is Figure 10 a schematic cross-sectional structure view along direction A5 - A6 in . A source region S, a drain region D, and a body contact region B are respectively formed in the SOI substrate 100.

[0072] Among them, the drain region D is adjacent to the source region S, the body contact region B is adjacent to the source region S, and the drain region D and the body contact region B are respectively located on different sides of the source region S. In addition, the first isolation structure 151 is located between the adjacent source region S and the body contact region B, and the surface of the first isolation structure 151 is flush with the surface of the top silicon layer 103 and separates the adjacent source region S and the body contact region B.

[0073] Specifically, the projection boundary of the first isolation structure 151 on the surface of the top silicon layer 103 extends beyond the boundary of the source region S.

[0074] In addition, the source region S and the drain region D are heavily doped with N-type, and the body contact region B is heavily doped with P-type.

[0075] Please continue to refer to Figures 10 to 13 , after the source region S, the drain region D, and the body contact region B are formed, a gate structure 170 is formed on the surface of the top silicon layer 103, and the source region S and the drain region D are respectively located on both sides of the gate structure 170.

[0076] Furthermore, the gate structure 170 may include: a gate oxide layer (not shown), and a gate electrode (not shown) located on the surface of the gate oxide layer.

[0077] In this embodiment, the drain region D and the body contact region B are respectively located on different sides of the source region S, and the first isolation structure 151 is located in the top silicon layer 103 between the adjacent source region S and the body contact region B. The surface of the first isolation structure 151 is flush with the surface of the top silicon layer 103. The first isolation structure 151 separates the adjacent source region S and the body contact region B. The height of the first isolation structure 151 is less than the thickness of the top silicon layer 103. Therefore, on the one hand, the first isolation structure 151 separates the adjacent source region S and the body contact region B. On the other hand, the bottom of the first isolation structure 151 provides sufficient channels for extracting holes between the source region S and the body contact region B, thereby achieving a good effect of suppressing the floating body effect. On this basis, since the above structure is used to suppress the floating body effect, while suppressing the floating body effect, the generation of parasitic devices is reduced or even avoided. In particular, compared with the traditional T-gate structure, the NMOS device structure of this embodiment greatly reduces or even avoids parasitic devices such as the parasitic capacitance and parasitic resistance formed between the gate and the top silicon, the parasitic MOS tube formed by the T-gate and the active area and the oxide layer therebetween, and the parasitic diode existing in the T-gate (which has inverted ion implantation on the top and bottom). Therefore, not only is the suppression effect of the floating body effect improved, but the device performance is also greatly improved due to the reduction of parasitic devices.

[0078] Moreover, compared to the T portion of the T-type gate that requires inverted (N-type and P-type) ion implantation, since the size of the first isolation structure 151 (i.e., the groove width W2 of the first isolation groove 150) is defined through the photolithography step, the area occupied in the second direction Y is reduced, thereby also being beneficial to improving the integration.

[0079] Please continue to refer to Figures 10 to 13 After forming the gate structure 170 , a plurality of first conductive structures 181 , a plurality of second conductive structures 182 , a plurality of third conductive structures 183 and a plurality of fourth conductive structures 184 are formed.

[0080] The first conductive structure 181 is located on the surface of the body contact region B, the second conductive structure 182 is located on the surface of the source region S, the third conductive structure 183 is located on the surface of the drain region D, and the fourth conductive structure 184 is located on the surface of the gate structure 170 .

[0081] In one embodiment, before forming the first conductive structure 181, the second conductive structure 182, the third conductive structure 183, and the fourth conductive structure 184, a metal silicide layer 104 is formed on the surface of a part of the source region S, the surface of a part of the drain region D, the top surface of the gate structure 170, and the surface of a part of the body contact region B, so that the bottoms of the first conductive structure 181, the second conductive structure 182, the third conductive structure 183, and the fourth conductive structure 184 contact the metal silicide layer 104, thereby further reducing the resistance and improving the electrical characteristics. The material of the metal silicide layer is, for example, nickel silicide (NiSi) or CoSi, etc.

[0082] Correspondingly, an embodiment of the present invention further provides an NMOS device structure formed by the above method. Please continue to refer to Figures 10 to 13 , which may include: an SOI substrate 100, a first isolation structure 151, and a gate structure 170.

[0083] Among them, the SOI substrate 100 may include a bottom silicon layer 101, a buried oxide layer 102, and a top silicon layer 103 stacked in sequence.

[0084] In this embodiment, a source region S, a drain region D, and a body contact region B are distributed in the top silicon layer 103. The source region S and the drain region D are N-type heavily doped, and the body contact region B is P-type heavily doped. Among them, the drain region D is adjacent to the source region S, the body contact region B is adjacent to the source region S, and the drain region D and the body contact region B are respectively located on different sides of the source region S.

[0085] In this embodiment, the first isolation structure 151 is located in the top silicon layer 103 between adjacent source regions S and body contact regions B. The surface of the first isolation structure 151 is flush with the surface of the top silicon layer 103. Moreover, the first isolation structure 151 separates adjacent source regions S and body contact regions B. In addition, the height H1 of the first isolation structure 151 is less than the thickness H2 of the top silicon layer 103.

[0086] Specifically, the projection boundary of the first isolation structure 151 on the surface of the top silicon layer 103 extends beyond the boundary of the source region S.

[0087] In this embodiment, the gate structure 170 is located on the surface of the top silicon layer 103, and the source region S and the drain region D are respectively located on both sides of the gate structure 170.

[0088] In this embodiment, the drain region D and the body contact region B are located on different sides of the source region S respectively. The first isolation structure 151 is located in the top silicon layer 103 between adjacent source regions S and body contact regions B. The surface of the first isolation structure 151 is flush with the surface of the top silicon layer 103. The first isolation structure 151 separates adjacent source regions S and body contact regions B. Moreover, the height of the first isolation structure 151 is less than the thickness of the top silicon layer 103. Therefore, on the one hand, the first isolation structure 151 separates adjacent source regions S and body contact regions B. On the other hand, the space below the first isolation structure 151 provides sufficient channels for holes to be exported between the source region S and the body contact region B, thus being able to achieve a good effect of suppressing the floating body effect. On this basis, since the above structure is adopted to suppress the floating body effect, while suppressing the floating body effect, the generation of parasitic devices is reduced or even avoided. Especially compared with the structure of the traditional T-shaped gate, the NMOS device structure of this embodiment greatly reduces or even avoids parasitic capacitance and parasitic resistance formed between the gate and the top silicon layer, parasitic MOS transistors formed by the T-shaped gate, the active region and the oxide layer therebetween, and parasitic diodes existing in the T-shaped gate (with reverse ion implantation on its own upper and lower parts), etc. parasitic devices. Thus, not only the suppression effect of the floating body effect is improved, but also the device performance is greatly enhanced due to the reduction of parasitic devices. In addition, compared with the T-shaped gate that requires reverse (N-type and P-type) ion implantation, the size of the first isolation structure 151 is smaller. Therefore, it is also beneficial to improve the integration degree.

[0089] In this embodiment, the NMOS device structure may further include: a back buried oxide layer 130.

[0090] Wherein, the back buried oxide layer 130 is located in the top silicon layer 103. There is a first spacing between the back buried oxide layer 130 and the SOI buried oxide layer 102. There is a second spacing between the back buried oxide layer 130 and the surface of the top silicon layer 103. Both the first spacing and the second spacing are greater than 0 nanometers.

[0091] In one embodiment, the first spacing accounts for more than 1% of the thickness of the top silicon layer 103.

[0092] In addition, the width W1 of the back buried oxide layer 130 is greater than the width of the first isolation structure 151 (i.e., Figure 8 the groove width W2 of the first isolation groove 150 shown in

[0093] In this embodiment, the NMOS device structure may further include: a second isolation structure 161.

[0094] In this embodiment, the second isolation structure 161 penetrates the top silicon layer 103 and is connected to the SOI buried oxide layer 102 at the bottom. In addition, the second isolation structure 161 surrounds the source region S, the drain region D and the body contact region B. That is, the second isolation structure 161 is used for isolation between devices.

[0095] In this embodiment, the NMOS device structure may further include: a plurality of first conductive structures 181, a plurality of second conductive structures 182, a plurality of third conductive structures 183, and a plurality of fourth conductive structures 184.

[0096] Among them, the first conductive structure 181 is located on the surface of the body contact region B, the second conductive structure 182 is located on the surface of the source region S, the third conductive structure 183 is located on the surface of the drain region D, and the fourth conductive structure 184 is located on the surface of the gate structure 170.

[0097] In one embodiment, a metal silicide layer 104 is provided on the surfaces of a part of the source region S, a part of the drain region D, a part of the gate structure 170, and a part of the body contact region B, so that the bottoms of the first conductive structure 181, the second conductive structure 182, the third conductive structure 183, and the fourth conductive structure 184 are in contact with the metal silicide layer 104.

[0098] In this embodiment, the source region S and the drain region D are arranged along the first direction X. And, for the sake of easy understanding, the body contact region B and the first isolation structure 151 located on different sides of the source region S will be divided hereinafter for specific description.

[0099] In this embodiment, the body contact region B may include a first type of body contact region B1, and the first type of body contact region B1 is arranged along the second direction Y with the source region S. Correspondingly, the first isolation structure 151 may include a first type of first isolation structure 1511, and the first type of first isolation structure 1511 is located between the source region S and the first type of body contact region B1, and, the first type of first isolation structure 1511 extends beyond the boundary of the source region S in the first direction X. Wherein, the second direction Y is perpendicular to the first direction X.

[0100] In this embodiment, since the first type of first isolation structure 1511 extends beyond the boundary of the source region S in the first direction X, therefore, the separation between the source region S and the first type of body contact region B1 is further ensured.

[0101] In other embodiments, the first type of first isolation structure 1511 is flush with the boundary of the source region S in the first direction X.

[0102] Furthermore, the first type of body contact region B1 is also adjacent to the drain region D. Therefore, the area of the body contact region B is enlarged. Thus, on the one hand, it is easier for the first conductive structure 181 to align with the body contact region B, improving the device reliability; on the other hand, it provides positions for forming a larger number of first conductive structures 181, which is beneficial to improving the electrical performance of the device.

[0103] Correspondingly, the first type of first isolation structure 1511 is also flush with or extends beyond the drain region D in the first direction X to separate the adjacent first type of body contact region B1 from the drain region D, thereby further reducing parasitic devices.

[0104] In this embodiment, the number of the first type of body contact regions B1 is one.

[0105] In this embodiment, the gate structure 170 may include a gate oxide layer (not shown) and a gate electrode (not shown) located on the surface of the gate oxide layer. Among them, the material of the gate electrode includes N-type heavily doped polysilicon.

[0106] In this embodiment, the gate structure 170 is a straight structure extending along the second direction Y. Therefore, there is no additional T-shaped extension. Thus, compared with the traditional T-shaped gate structure body contact, the parasitic capacitance can be greatly reduced and the suppression effect of the floating body effect can be improved.

[0107] Furthermore, one end of the gate structure 170 extends to the surface of the first type of first isolation structure 1511, the other end of the gate structure 170 extends beyond the other side boundary of the source region S and the drain region D relative to the first type of first isolation structure 1511, and the fourth conductive structure 184 is located on the surface of the other end of the gate structure 170.

[0108] In another embodiment, please refer to Figure 14 , the numbers of the first type of body contact regions B1 and the first type of first isolation structures 1511 are both two, and the gate structure 270 is used to replace the gate structure 170.

[0109] Specifically, the first type of body contact regions B1 are both provided on both sides of the source region S along the second direction Y, and a first type of first isolation structure 1511 is provided between each side of the source region S along the second direction Y and the adjacent first type of body contact region B1. Therefore, while reducing parasitic devices and improving the suppression effect of the floating body effect, the area of the body contact region B is further enlarged. Thus, on the one hand, the first conductive structure 181 is more easily aligned with the body contact region B, improving the device reliability; on the other hand, positions are provided for forming a larger number of first conductive structures 181, which is beneficial to improving the electrical performance of the device.

[0110] In addition, the gate structure 270 may include a first part gate 271 and a second part gate 272 that are connected and form an "L" - shaped structure. The first part gate 271 extends along the first direction X, and the second part gate 272 extends along the second direction Y.

[0111] Among them, the source region S and the drain region D are located on both sides of the first partial gate 271, the second partial gate 272 is located on the surface of the first type of first isolation structure 1511 adjacent to the drain region D, the second partial gate 272 extends beyond the boundary of the drain region D in the first direction X, and the fourth conductive structure 184 is located at the surface where the second partial gate 272 extends beyond the boundary of the drain region D. Therefore, on the one hand, through the first type of first isolation structure 1511 under the second partial gate 272, the formation of parasitic devices between the second partial gate 272 and the substrate is avoided. On the other hand, through the different shapes of the gate structure 270, the flexibility of the position of the fourth conductive structure 184 is increased.

[0112] In yet another embodiment, please refer to Figure 15 , compared with Figure 14 the embodiment shown, the body contact region B further includes a second type of body contact region B2, and the second type of body contact region B2, the source region S, and the drain region D are arranged in sequence along the first direction X. Thus, the area of the body contact region B is further expanded.

[0113] Correspondingly, the first isolation structure 151 may further include a second type of first isolation structure 1512, and the second type of first isolation structure 1512 is located between the source region S and the second type of body contact region B2, and the second type of first isolation structure 1512 is flush with or extends beyond the boundary of the source region S in the second direction Y to isolate the source region S from the adjacent second type of body contact region B2.

[0114] In another other embodiment, the body contact region B may also only include the second type of body contact region B2. Correspondingly, the first isolation structure 151 only includes the second type of first isolation structure 1512. Thus, the position of the body contact region B is flexible, which is convenient for the structural design of the device.

[0115] It should be noted that, for the convenience of understanding and illustration, Figure 10 , Figure 14 and Figure 15 all use blue dashed lines to represent the N+ region (N-type heavily doped region), red dashed lines to represent the P+ region (P-type heavily doped region), and black dashed lines to represent the position of the buried oxide layer 130 that is blocked. In addition, Figure 10 , Figure 14 and Figure 15 do not show the second isolation structure 161 and the metal silicide layer 104.

[0116] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be subject to the scope defined by the claims.

Claims

1. An NMOS device structure, characterized in that Comprising: An SOI substrate, the SOI substrate includes a top silicon layer, source regions, drain regions and body contact regions are distributed in the top silicon layer, the drain regions are adjacent to the source regions, the body contact regions are adjacent to the source regions, and the drain regions and the body contact regions are respectively located on different sides of the source regions; A first isolation structure, located in the top silicon layer between adjacent source regions and body contact regions, and the surface of the first isolation structure is flush with the surface of the top silicon layer, the first isolation structure separates the adjacent source regions and the body contact regions, and the height of the first isolation structure is less than the thickness of the top silicon layer; A gate structure, located on the surface of the top silicon layer, and the source regions and the drain regions are respectively located on both sides of the gate structure.

2. The NMOS device structure according to claim 1, characterized in that, The SOI substrate further includes a bottom silicon layer and an SOI buried oxide layer located between the top silicon layer and the bottom silicon layer; The NMOS device structure further includes: a back buried oxide layer, the back buried oxide layer is located in the top silicon layer, there is a first spacing between the back buried oxide layer and the SOI buried oxide layer, and the width of the back buried oxide layer is greater than the width of the first isolation structure, so that the first isolation structure is located on the top surface of the back buried oxide layer.

3. The NMOS device structure according to claim 1, wherein Further comprising: A second isolation structure penetrating the top silicon layer, the second isolation structure surrounds the source regions, the drain regions and the body contact regions.

4. The NMOS device structure according to claim 1, characterized in that, The source regions and the drain regions are arranged along a first direction, the body contact regions include first type body contact regions, the first type body contact regions and the source regions are arranged along a second direction, the first isolation structure includes a first type first isolation structure located between the source regions and the first type body contact regions, the first type first isolation structure is flush with or extends beyond the boundary of the source regions in the first direction to separate the source regions from adjacent first type body contact regions, and the second direction is perpendicular to the first direction.

5. The NMOS device structure according to claim 4, wherein The first type body contact regions are also adjacent to the drain regions, and the first type first isolation structure is flush with or extends beyond the drain regions in the first direction.

6. The NMOS device structure according to claim 5, characterized in that, The gate structure includes a first part gate and a second part gate connected to form an "L" shaped structure, the first part gate extends along the first direction, the second part gate extends along the second direction, the source regions and the drain regions are located on both sides of the first part gate, the second part gate is located on the surface of the first type first isolation structure adjacent to the drain regions, and, the second part gate extends beyond the boundary of the drain regions in the first direction.

7. The NMOS device structure according to claim 4, wherein The number of the first type body contact regions is 2, and along the second direction, the first type body contact regions are respectively located on both sides of the source regions.

8. The NMOS device structure according to claim 1 or 4, characterized in that, The body contact regions include second type body contact regions, the second type body contact regions, the source regions and the drain regions are arranged in sequence along the first direction, the first isolation structure includes a second type first isolation structure located between the source regions and the second type body contact regions, the second type first isolation structure is flush with or extends beyond the boundary of the source regions in the second direction to separate the source regions from adjacent second type body contact regions.

9. A method for forming an NMOS device structure, characterized in that, Comprising: Providing an SOI substrate, the SOI substrate includes a top silicon layer; A first isolation structure is formed within the top silicon layer, the surface of the first isolation structure being flush with the surface of the top silicon layer, and the height of the first isolation structure being less than the thickness of the top silicon layer; After forming the first isolation structure, a source region, a drain region, and a body contact region are respectively formed within the SOI substrate. The drain region is adjacent to the source region, the body contact region is adjacent to the source region, and the drain region and the body contact region are respectively located on different sides of the source region. The first isolation structure is located between the adjacent source region and the body contact region, and the first isolation structure separates the adjacent source region and the body contact region; After forming the source region, the drain region, and the body contact region, a gate structure is formed on the surface of the top silicon layer, and the source region and the drain region are respectively located on both sides of the gate structure.

10. The method for forming the NMOS device structure according to claim 9, wherein The SOI substrate further includes a bottom silicon layer and an SOI buried oxide layer located between the top silicon layer and the bottom silicon layer; The method for forming the first isolation structure includes: forming a patterned first mask structure on the top silicon layer; using the first mask structure as a mask to perform ion implantation on the top silicon layer; after performing ion implantation on the top silicon layer, performing an annealing step to form a post-buried oxide layer within the top silicon layer. There is a first spacing between the post-buried oxide layer and the SOI buried oxide layer, and there is a second spacing between the post-buried oxide layer and the surface of the top silicon layer; after forming the post-buried oxide layer, forming a patterned second mask structure on the top silicon layer; using the second mask structure as a mask to etch the top silicon layer until the top surface of the post-buried oxide layer is exposed, and forming a first isolation groove within the top silicon layer; forming the first isolation structure within the first isolation groove; The method for forming the NMOS device structure further includes: using the second mask structure as a mask, when etching the top silicon layer to form the first isolation groove, also etching the top silicon layer until the top surface of the SOI buried oxide layer is exposed to form a second isolation groove; forming a second isolation structure within the second isolation groove, and the second isolation structure surrounds the source region, the drain region, and the body contact region.

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