Body tied to source mosfet

Abstract

MOSFET structures and corresponding methods that mitigate or eliminate the floating body effect in a MOSFET while reducing parasitic gate-source capacitance CGS and improving the FT of the device. This invention addresses the floating body effect by reshaping a conductive body tie region and eliminating or reducing any body tie extension at the source side of a MOSFET to improve CGS. One embodiment includes a body region and a body tie region implanted within a source region in direct contact with a first side of the body region without a body tie extension. Another embodiment includes a body region, a gate structure including a drain-side extension, and a body tie region implanted within a source region in direct contact with a first side of the body region, wherein the drain-side extension of the gate structure is sized to block implantation of the body tie region within a drain region.

Description

Attorney Docket No.: P3113 -PCTBody Tied to Source MOSFETCROSS REFERENCE TO RELATED APPLICATIONS

[0001] The present application claims priority to U.S. Provisional Patent Application No.63 / 761,475, filed on February 21, 2025, the contents of which are incorporated herein by reference in their entirety.BACKGROUND(1) Technical Field

[0002] This invention relates to electronic integrated circuits, and more particularly to electronic integrated circuits that include metal-oxide-semiconductor field-effect transistors (MOSFETs).(2) Background

[0003] Virtually all modem electronic products - including laptop computers, mobile telephones, and electric cars - utilize metal MOSFET integrated circuits (ICs), and in many cases MOSFET ICs fabricated using a semiconductor-on-insulator (SOI) process, such as silicon-on-insulator, or germanium-on-insulator, or silicon / germanium-on-insulator (e.g., a SiGe alloy or a layer of Ge on a layer of Si formed on an insulator).

[0004] FIG. 1A is a stylized top plan view of a prior art IC structure 100 for a single N-type MOSFET device. FIG. IB is a stylized cross-sectional view along line Xl-Xl of FIG. 1A. FIG. IC is a stylized cross-sectional view along line X2-X2 of FIG. 1A. FIG. ID is a stylized cross-sectional view along line X3-X3 of FIG. 1A.

[0005] As shown in the example in FIG. 1A, an N+ source S, a gate structure G, and an N+ drain D overlay an active layer 102 of semiconductor material such as crystalline silicon, Si (contacts to the source S, the gate structure G, and the drain D have been omitted to reduce clutter). The gate structure G overlies a body region B (shown in FIGS. IB- ID) of P- material or intrinsicAttorney Docket No.: P3113 -PCTSi which separates the N+ source S from the N+ drain D. Also shown in FIG. 1 A is the top side of a P+ body tie region 103 within the active layer 102. The P+ body tie region 103 is spaced from the main portion of the gate structure G but is electrically connected to the main body region B beneath the gate structure G by a body tie extension 105 of the body region B (and therefore the body tie extension 105 has the same doping as the body region B). The body tie extension 105 is overlaid by the gate structure G and thus the gate structure G forms a “T” shape as shown. The body tie extension 105 of the body region B is shown in FIG. IB in dotted outline to indicate that the X-dimension of the body region B is greater along line Xl-Xl than along lines X2-X2 and X3-X3 of FIG. 1A.

[0006] As shown in the cross-sectional drawings (FIGS. 1B-1D), the IC structure 100 includes the active layer 102, an insulating buried-oxide (BOX) layer 104, and a substrate 106 (note that the dimensions for the elements of the IC structure 100 are not to scale; some dimensions have been exaggerated for clarity or emphasis). The substrate 106 is typically a semiconductor material such as silicon or high-resistivity silicon, but may be other materials such as glass or sapphire. The BOX layer 104 is a dielectric, and is often SiO2 formed as a “top” surface of the silicon substrate 106; for some substrates (e.g, glass or sapphire), the BOX layer 104 may be omitted. For some applications, such as in bulk silicon MOSFET designs, the BOX layer 104 may be omitted. For some applications, one or more additional layers or regions may be included, such as a trap-rich layer or the like between the BOX layer 104 and the substrate 106. A trap-rich Si layer mitigates parasitic surface conduction and improves device performance at high frequencies.

[0007] The active layer 102 may include some combination of implants and / or layers that include dopants, dielectrics, polysilicon, conductors, passivation, and other materials to form active and / or passive electronic components and / or mechanical structures. For example, FIG. IB shows the N+ source S and the N+ drain D within the active layer 102, with the gate structure G situated on a surface of the active layer 102 proximate to the body region B. The gate structure G is positioned with respect to the body region B so as to be able to control current flow through the body region B between the source S and the drain D.

[0008] The illustrated gate structure G includes a conductive layer 108 atop an insulating gate oxide (GOX) layer 110. The conductive layer 108 may be, for example, N+ polysilicon or a metal,Attorney Docket No.: P3113 -PCTalthough a portion 109 of the gate structure G generally becomes P+ polysilicon when the P+ body tie region 103 is implanted. In the illustrated example, the gate structure G is surrounded by dielectric spacers 112, which may be fabricated with multiple lateral dielectric layers. The body region B (doped to be P- in this example) is defined within the active layer 102 situated below the gate structure G and between the source S and the drain D. A P-type MOSFET device has a similar structure, but with opposite polarities for the dopants.

[0009] The BOX layer 104 and the active layer 102 (which may include one or more MOSFETs) may be collectively referred to as a “device region” or “substructure” for convenience (noting that other structures or regions may intrude into the substructure in particular IC designs). A superstructure 114 of various elements, regions, and structures may be fabricated in known fashion on or above the substructure in order to implement particular functionality (the superstructure 114 is omitted in FIGS. IC and ID to reduce clutter). The superstructure 114 may include, for example, conductive interconnections from the illustrated MOSFET to other components (including other MOSFETs) and / or external contacts, passivation layers and regions, and protective coatings.

[0010] The cross-sections of FIG. 1 shown in FIGS. IC and ID include optional halo implants 116 and lightly-doped drain (LDD) regions 118, which improve the maximum voltage handling capability of a MOSFET. A halo implant mitigates punch-through while an LDD region mitigates avalanche breakdown. For an N-type MOSFET, the halo implants 116 are pocket regions implanted with a P or P+ type dopant that increases a sub-surface electric field to reduce so-called punch-through (or short channel) conduction between the source S and the drain D, thus increasing breakdown voltage. LDD regions 118 are lightly-doped with N type material to extend the source S and drain D underneath the gate G (“LDD” is somewhat of a misnomer, since an LDD region can exist on the source-side of a MOSFET). The LDD regions 118 reduce high electric fields caused by an applied voltage at the drain D, thereby increasing the drain-channel breakdown voltage. The halo implants 116 and lightly-doped drain (LDD) regions 118 do not appear in the cross-section of FIG. IB because of the presence of the body tie extension 105 and the overlying portion of the gate structure G.Attorney Docket No.: P3113 -PCT

[0011] Due to the insulating BOX layer 104 and / or an insulating substrate 106 (e.g., sapphire), impact ionization and tunneling occurring at high electric field strengths near the drain D cause holes to accumulate within the body region B, resulting in the well-known floating body effect. In essence, under some operational conditions, extra carriers in floating-body SOI MOSFETs can pile up in the body region B near the source S. This will change the threshold voltage of the transistor and create a parasitic bipolar junction transistor (BJT) or diode near the source S. These parasitic devices will turn on at a certain point and create nonlinearities in transistor current, which is called the kink effect. The floating body effect significantly degrades the output conductance (GDS) and the safe operating area (SOA) of the device (a device SOA is defined by a set of voltage, current, and temperature values within which a MOSFET device operates reliably). Higher GDS results in worse linearity.

[0012] By tying the body region B to the source S, device conductance nonlinearity is completely or substantially eliminated. Thus, a conventional remedy for the floating body effect in a MOSFET is a body-tied-to-source (BTS) configuration in which the body region B is electrically connected through the body tie extension 105 and the conductive body tie region 103 to the terminal for the source region S. For example, as shown in FIGS. 1 A-1B, for an N-type FET, a P+ body tie (BT) region 103 along with a P- body tie extension 105 is implemented to reduce the floating body effect.

[0013] However, a BTS configuration of the type shown in FIGS. 1A-1B (as well as similar configurations with multiple body tie regions 103 and body tie extensions 105) cause the device gate capacitance CGG to increase and also reduces the effective gate width W. In particular, a typical body tie extension 105 and overlying portion of the gate structure G are fairly long (e.g., about 390nm) and create a high parasitic gate-source capacitance CGS, with the conductive active layer 102 and conductive layer 108 of the gate structure G, separated by the insulating GOX layer 110, forming the capacitor structure. CGG is approximately equal to CGS + CGD (the parasitic gatedrain capacitance), but CGS is the dominant term (CGS > GGD). For example, FIGS. 2A-2C are graphs showing examples of measured GGG, CGD, and CGS as a function of VGS at two different values of VDS for an example MOSFET having a gate length of about 80nm and a conventional BTS configuration of the type shown in FIGS. 1A-1B. As should be clear, CGS is much greater than CGD.Attorney Docket No.: P3113 -PCT

[0014] As a result of high CGS, a MOSFET exhibits lower device FT (the unity current gain transit frequency), since FT is inversely proportional to CGG (and thus to CGS). Lower FT implies some frequency limitations and as a result application limitations for such devices.

[0015] Accordingly, there is a need to provide for a BTS configuration in a MOSFET that mitigates or eliminates the floating body effect while reducing the parasitic gate-source capacitance CGS of the device and improving FT. The present invention addresses that need.Attorney Docket No.: P3113 -PCTSUMMARY

[0016] The present invention encompasses novel MOSFET integrated circuit devices and methods of making such devices that mitigate or eliminate the floating body effect in such a device while reducing the parasitic gate-source capacitance CGS and improving the FT of the device. This invention addresses the floating body effect by reshaping the conductive body tie region and eliminating or reducing any body tie extension at the source side of a MOSFET to improve CGS. Measured results show up to 35% lower CGS and 40% higher FT which can be translated to higher gain and lower noise at higher frequencies. Accordingly, such devices are excellent candidates for a variety of applications, particularly low-noise amplifier (LNA) applications, especially in the range 3 to 30 gigahertz range.

[0017] A first MOSFET embodiment includes a body region, a gate structure positioned with respect to the body region so as to be able to control current flow through the body region, a source region positioned adjacent to a first side of the body region, a drain region positioned adjacent to a second side of the body region, and a body tie region implanted within the source region in direct contact with the first side of the body region.

[0018] A second MOSFET embodiment includes a body region, a gate structure positioned with respect to the body region so as to be able to control current flow through the body region and including a drain-side extension, a source region positioned adjacent to a first side of the body region, a drain region positioned adjacent to a second side of the body region, and a body tie region implanted within the source region in direct contact with the first side of the body region, wherein the drain-side extension of the gate structure is sized to block implantation of the body tie region within the drain region.

[0019] A third MOSFET embodiment includes a body region, a gate structure positioned with respect to the body region so as to be able to control current flow through the body region and including a drain-side extension and a source-side body tie extension, a source region positioned adjacent to a first side of the body region, a drain region positioned adjacent to a second side of the body region, and a body tie region implanted within the source region, wherein the drain-side extension of the gate structure is sized to block implantation of the body tie region within the drainAttorney Docket No.: P3113 -PCTregion, and wherein the source-side body tie extension of the gate structure is sized to span a gap between the body region and the body tie region.

[0020] The details of one or more embodiments of the invention are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the invention should be apparent from the description and drawings, and from the claims.Attorney Docket No.: P3113 -PCTDESCRIPTION OF THE DRAWINGS

[0021] FIG. 1A is a stylized top plan view of a prior art IC structure for a single N-type MOSFET device.

[0022] FIG. IB is a stylized cross-sectional view along line XI -XI of FIG. 1 A.

[0023] FIG. IC is a stylized cross-sectional view along line X2-X2 of FIG. 1 A.

[0024] FIG. ID is a stylized cross-sectional view along line X3-X3 of FIG. 1A.

[0025] FIGS. 2A-2C are graphs showing examples of measured GGG, CGD, and CGS as a function of VGS at two different values of VDS for an example MOSFET having a gate length of about 80nm and a conventional BTS configuration of the type shown in FIGS. 1A and IB.

[0026] FIG. 3A is a stylized top plan view of a first embodiment of a novel IC structure for a single N-type MOSFET device.

[0027] FIG. 3B is a stylized cross-sectional view along line X4-X4 of FIG. 3 A.

[0028] FIG. 4A is a stylized top plan view of a second embodiment of a novel IC structure for a single N-type MOSFET device.

[0029] FIG. 4B is a stylized cross-sectional view along line X5-X5 of FIG. 4A.

[0030] FIG. 5A is a stylized top plan view of a third embodiment of a novel IC structure for a single N-type MOSFET device.

[0031] FIG. 5B is a stylized cross-sectional view along line X6-X6 of FIG. 5 A.

[0032] FIGS. 6A-6D are graphs of various DC characteristics of a conventional MOSFET having a gate length LG of 80nm.

[0033] FIGS. 7A-7D are graphs of various DC characteristics of a MOSFET of the type shown in FIGS. 4A-4B having a gate length LG of 80nm.Attorney Docket No.: P3113 -PCT

[0034] FIGS. 8A and 8B are graphs of FT as a function of current density Jd for a conventional MOSFET at two different values of VDS.

[0035] FIGS. 9A and 9B are graphs of FT as a function of current density Jd for an example of a “New BTS” MOSFET at the same two different values of VDS shown in FIGS. 8A and 8B.

[0036] FIG. 10 is a simplified graph of minimum noise figure NFmin as a function of frequency for a conventional MOSFET and an example “New BTS” MOSFET, each having a gate length LG of 60nm and the other illustrated parameter values.

[0037] FIG. 11 is a graph of drain-source current IDS as a function of VDS for an 80nm asymmetrical conventional MOSFET (dotted line) and an 80nm “New BTS” MOSFET (solid line).

[0038] FIGS. 12A-12D are stylized cross-sectional views of example fabrication stages of one example method of fabricating a “New BTS” MOSFET in accordance with the teachings of this disclosure.

[0039] FIG. 13 is a process flowchart showing another representation of an example fabrication process for a “New BTS” MOSFET that is suitable for some contemporary IC front-end-of-line (FEOL) foundries.

[0040] FIG. 14 is a top plan view of a substrate that may be, for example, a printed circuit board or chip module substrate (e.g., a thin-film tile).

[0041] Like reference numbers and designations in the various drawings indicate like elements unless the context requires otherwise.Attorney Docket No.: P3113 -PCTDETAILED DESCRIPTION

[0042] The present invention encompasses novel MOSFET integrated circuit devices and methods of making such devices that mitigate or eliminate the floating body effect in such a device while reducing the parasitic gate-source capacitance CGS and improving the FT of the device. This invention addresses the floating body effect by reshaping the conductive body tie region and eliminating or reducing any body tie extension at the source side of a MOSFET to improve CGS. Measured results show up to 35% lower CGS and 40% higher FTwhich can be translated to higher gain and lower noise at higher frequencies. Accordingly, such devices are excellent candidates for a variety of applications, particularly low-noise amplifier (LNA) applications, especially in the range 3 to 30 gigahertz range.

[0043] The use of a BTS configuration is of a special importance - a body tie region eliminates or substantially mitigates the floating body effect; mitigates turn-on of the parasitic bipolar devices inherent in a MOSFET; improves the breakdown voltage of the FET; improves electro-static discharge (ESD) protection for the FET; improves device and circuitry performance and capability, and in particular improves circuit linearity, reliability, and power consumption in analog and digital circuitry, especially for such devices as radio frequency (RF) and mmWave switches, LNAs, and power amplifiers. In many embodiments, the body tie region is tied (electrically coupled) to the source S, and thus the device will have equal potential between the body region B and the source S. However, in some embodiments, the body tie region may be separately biased in order to manipulate the body region B potential independently of the source S.

[0044] FIG. 3A is a stylized top plan view of a first embodiment of a novel IC structure 300 for a single N-type MOSFET device. FIG. 3B is a stylized cross-sectional view along line X4-X4 of FIG. 3 A. As shown in the example in FIG. 3 A, an N+ source S, a gate structure G, and an N+ drain D overlay an active layer 102 of semiconductor material such as crystalline silicon, Si (contacts to the source S, the gate structure G, and the drain D have been omitted to reduce clutter). The gate structure G overlies a body region B (shown in FIG. 3B) of P- material or intrinsic Si which separates the N+ source S from the N+ drain D. Also shown in FIG. 3A is the top side of a P+ body tie region 303 within the active layer 102. The P+ body tie region 303 is directly (physically and electrically) connected to the body region B beneath the gate structure G without a body tie extension. Accordingly, the gate structure G does not overlay the P+ body tie regionAttorney Docket No.: P3113 -PCT303, as more clearly shown in FIG. 3B, and does not extend over the source S. Thus, the parasitic gate-source capacitance CGS of the device is reduced compared to a conventional design, and consequently FT is increased.

[0045] For some fabrication processes, it may be difficult to align the mask for implantation of the P+ body tie region 303 such that the P+ implant material forms the body region B but does not overlap the drain D of the device. Accordingly, some embodiments of the invention include a drain-side extension of the gate structure. For example, FIG. 4A is a stylized top plan view of a second embodiment of a novel IC structure 400 for a single N-type MOSFET device. FIG. 4B is a stylized cross-sectional view along line X5-X5 of FIG. 4A. As shown in the example in FIGS.4A and 4B, the body region B and an overlying portion of the gate structure G extend into the drain D by an X-dimension distance of LEXT, forming a drain-side extension 401. The drain-side extension 401 has a Y-dimension width WEXT that is greater than (and approximately centered on) the width WBTof a corresponding P+ body tie region 403. The P+ body tie region 403 is directly (physically and electrically) connected to the body region B beneath the gate structure G without a body tie extension. Note that the conductive layer 108 generally may be, for example, N+ polysilicon or a metal, but a portion 109 is preferably P+ polysilicon by design and intentionally overlaps the conductive layer 108 in order not to create a gap / barrier between the P+ body tie region 403 and the conductive layer 108 (e.g., due to misalignment of masks while implanting the body tie region 403).

[0046] The drain-side extension 401 of the gate structure G should be sized to block formation of the body tie region 403 within the drain region. Thus, if the mask for implanting the P+ body tie region 403 overlaps the gate structure G up to or slightly into the drain D of the device (as suggested by the dotted-line portion of the P+ body tie region 403), P+ dopant will be blocked by the drain-side extension 401 from contacting the drain D. Accordingly, while increasing manufacturability, the gate structure G does not overlay the P+ body tie region 403, as more clearly shown in FIG. 4B, does not extend over the source S, and only slightly extends over the drain D. Thus, the dominant parasitic gate-source capacitance CGS of the device is reduced compared to a conventional design, and consequently FT is increased.Attorney Docket No.: P3113 -PCT

[0047] The values of LEXT and WEXTOF the drain-side extension 401 may be adjusted as needed to accommodate the precision of mask alignment available for a particular manufacturing process. For one selected manufacturing process, LEXT is about 45nm and WEXT is sized to be about 120nm greater than WBT (e.g. , creating side margins for the drain-side extension 401 of about 60nm each).

[0048] For increased manufacturability, it may be useful to accommodate even greater imprecision of mask alignment for a particular manufacturing process. For example, FIG. 5A is a stylized top plan view of a third embodiment of a novel IC structure 500 for a single N-type MOSFET device. FIG. 5B is a stylized cross-sectional view along line X6-X6 of FIG. 5A. As shown in the example in FIGS. 5 A and 5B, the device includes a drain-side extension 401, as in the embodiment shown in FIGS. 4A-4B. In addition, a short source-side tab 505 having an X-dimension of LTAB is included to span a possible gap of N+ source S material between the body region B and the P+ body tie region 503. The source-side tab 505 comprises a short body tie extension of the body region B and is overlaid by the gate structure G. The length of the sourceside tab 505 should be sufficient to contact the drain-side edge of the body tie region 503 if the mask for the body tie region 503 is misaligned with respect to the gate structure G. Again note that the conductive layer 108 generally may be, for example, N+ polysilicon or a metal, but a portion 109 is preferably P+ polysilicon by design and intentionally overlaps the conductive layer 108 in order not to create a gap / barrier between the P+ body tie region 503 and the conductive layer 108 (e.g., due to misalignment of masks while implanting the body tie region 503).

[0049] If the mask for implanting the P+ body tie region 503 overlaps the gate structure G up to or slightly into the drain D of the device, P+ dopant will be blocked by the drain-side extension 401 from contacting the drain D. Further, if the drain-side edge of the mask for implanting the P+ body tie region 503 does not reach to the main body of the gate structure G, such that an N+ gap occurs, the source-side tab 505 helps to ensure that the P+ body tie region 503 is electrically connected to the body region B. Accordingly, while increasing manufacturability, the gate structure G does not substantially extend over the source S and only slightly extends over the drain D. Thus, the dominant parasitic gate-source capacitance CGS of the device is still reduced compared to a conventional design and consequently FT is increased while improving manufacturability.Attorney Docket No.: P3113 -PCT

[0050] The values of LEXT and WEXTOF the drain-side extension 401 may be adjusted as needed to accommodate the precision of mask alignment available for a particular manufacturing process. For one selected manufacturing process, LEXT is about 45nm and WEXT is sized to be about 120nm greater than WBT (e.g. , creating side margins for the drain-side extension 401 of about 60nm each). The value of LTAB may vary from just greater than 0 to about lOOnm, and is preferably about 30 to 50nm.

[0051] The DC characteristics of a MOSFET made in accordance with the present invention are substantially similar to a conventional MOSFET. For example, FIGS. 6A-6D are graphs of various DC characteristics of a conventional MOSFET having a gate length LG of 80nm, and FIGS.7A-7D are graphs of various DC characteristics of a MOSFET of the type shown in FIGS. 4A-4B having a gate length LG of 80nm.

[0052] FIGS. 6A and 7A show drain-source current IDS as a function of drain-source voltage VDS for gate-source voltage VGS = 0. IV to 1 ,2V in 0. IV steps.

[0053] FIGS. 6B and 7B show the log of the absolute value of IDS as a function of VGS for VDS = 0. IV and 1.2V.

[0054] FIGS. 6C and 7C show transconductance Gm as a function of VGS for VDS = 0.1 V to 1.2V in 0.1V steps.

[0055] FIGS. 6D and 7D show drain-source output transconductance GDS as a function of VDS for VDS = 0. IV to 1 ,2V in 0. IV steps.

[0056] As another example, the DC characteristics measured for a conventional MOSFET having a gate length LG of HOnm were substantially similar to the DC characteristics of a MOSFET of the type shown in FIGS. 4A-4B having a gate length LG of 1 lOnm; the graphs of such characteristics look very similar to FIGS. 6A-6D and 7A-7D and are accordingly not repeated here.

[0057] While the DC characteristics for a conventional MOSFET are substantially similar to the DC characteristics of a MOSFET made in accordance with the present invention, for similar gate lengths, the RF performance of a MOSFET made in accordance with the present invention is significantly improved. For example, TABLE 1 shows measured values of FT, FMAX, and CGS forAttorney Docket No.: P3113 -PCTconventional symmetric MOSFETs and the novel MOSFETs (also symmetric) at two different gate lengths LG and two different values of VDS. At the embedded percentages show, the novel MOSFETs (labeled “New BTS”) exhibit significantly lower CGS and significantly increased FT compared to the conventional designs (FMAX is also significantly increased for the 80nm version of the “New BTS” MOSFET).TABLE 1

[0058] In some applications, such as power amplifiers, it has been found useful to create “asymmetric” MOSFETs which exhibit a higher breakdown voltage BVDSS and reduced hot carrier injection (HCI) issues compared to symmetric MOSFETs. HCI is a phenomenon where a charge carrier (electron or hole) gains sufficient kinetic energy to overcome a potential barrier necessary to break an interface state. The charge carriers can become trapped in the gate dielectric of a MOSFET and may permanently change the switching characteristics of the transistor. HCI is one of the mechanisms that adversely affects the reliability of MOSFETs. In some asymmetric MOSFETs, halo / LDD dopants may be implanted at two different angles and only from the source side of the device. For example, the tilt angle 0 may be about 30° for halo implants, and about 10° for LDD implants. Tilted implantation of dopants for halo implants and LDD regions made only from the source S side of a MOSFET, such that the gate structure G “shadows” the drain D side, results in the halo implants and LDD regions on the drain D side underlapping the gate structure. The resulting underlap junction on the drain D side improves BVDSS and reduces HCI events due to the graded junction on the drain-side of the gate structure G.

[0059] Asymmetric MOSFETs with the BTS configuration shown in FIG. 4A-4B exhibit even better RF characteristics than the conventional MOSFET design shown in FIGS. 1A-1D. For example, a first “New BTS” asymmetric MOSFET design having an 80nm gate length has up toAttorney Docket No.: P3113 -PCTabout a 30% higher FT / FMAX and about a 30% lower CGS than an 80nm conventional MOSFET design. A second “New BTS” asymmetric MOSFET design having a 1 lOnm gate length has up to nearly a 40% higher FT and about a 30% lower CGS than a 110 nm conventional MOSFET design. TABLE 2 shows measured values of FT, FMAX, and CGS for these example “New BTS” asymmetric MOSFET designs compared to a conventional symmetric MOSFET at two different values of VDS.TABLE 2

[0060] FIGS. 8A and 8B are graphs of FT as a function of current density Jd for a conventional MOSFET at two different values of VDS. FIGS. 9A and 9B are graphs of FT as a function of current density Jd for an example of a “New BTS” MOSFET at the same two different values of VDS shown in FIGS. 8A and 8B. As the graphs indicate, the “New BTS” MOSFET exhibits higher values of FT at lower current densities than the conventional MOSFET.Attorney Docket No.: P3113 -PCT

[0061] The higher values of FT exhibited by “New BTS” MOSFETs (as much as about 40% higher than comparably-sized conventional MOSFETs) means higher gain at higher frequencies. This translates to lower noise at higher frequencies, which makes such devices excellent candidates for high frequency LNA applications. For example, FIG. 10 is a simplified graph of minimum noise figure NFmin as a function of frequency for a conventional MOSFET and an example “New BTS” MOSFET, each having a gate length LG of 60nm and the other illustrated parameter values. As the graph indicates, the NFmin values for the “New BTS” MOSFET are significantly better than for the conventional MOSFET.

[0062] As should be apparent from FIGS. 1A-1D, an asymmetrical conventional MOSFET design may partially block halo and LDD source-side implants between the P+ body tie region 103 and the gate structure G, which can result in poor DIBL (drain induced barrier lowering) and BVdss (drain-source breakdown voltage) characteristics. For example, FIG. 11 is a graph of drainsource current IDS as a function of VDS for an 80nm asymmetrical conventional MOSFET (dotted line) and an 80nm “New BTS” MOSFET (solid line). The “New BTS” MOSFET exhibits better BVdss characteristics, 4.5V versus 3.7V. In addition, other measurements show that the “New BTS” MOSFET also has lower DIBL (37mV versus 83mV for the example devices) and better IDS versus VDS characteristics.

[0063] A number of different processes may be used to fabricate the IC architectures described in this disclosure. For example, FIGS. 12A-12D are stylized cross-sectional views of example fabrication stages of one example method of fabricating a “New BTS” MOSFET in accordance with the teachings of this disclosure.

[0064] FIG. 12A shows a portion of an active layer 102 formed on a BOX layer 104 (e.g., SiO2), which is in turn formed on top of a substrate 106 (e.g., Si). Additionally, isolation structures 1202 and a doped semiconductor P-well 1204 have been formed. The isolation structures 1202 may be, for example, shallow trench isolation (STI) structures formed, for example, from SiO2. In some embodiments, the active layer 102 may be formed directly on top of a bulk Si substrate or on top of a sapphire or other insulating substrate, thus omitting the BOX layer 104.

[0065] FIG. 12A also shows a formed gate structure G. The gate structure G may be fabricated, as one example, by forming a thin sacrificial oxide layer, such as by thermal oxidation of the topAttorney Docket No.: P3113 -PCTportion of at least the P-well 1204 (which is P- Si in this example, but may be intrinsic Si). The sacrificial oxide layer helps to clean the surface of the P-well 1204 and is subsequently etched away, such as by washing with hydrofluoric acid (HF) or buffered HF. After removal of the thin sacrificial oxide layer, a gate oxide (GOX) layer 110 may be formed (e.g., by thermal oxidation) on the top surface of at least the P-well 1204. A layer of gate material 108 (e.g., polysilicon) may be deposited on the resulting GOX layer 110. The gate material 108 and GOX layer 110 may then be patterned (masked and etched) to define a core section of the gate structure G. The remaining gate material 108 has an X-dimension that essentially defines the gate length LG of the device. In some embodiments, the masking and etching of the gate material 108 and GOX layer 110 may be separate steps. In alternative embodiments, the gate material 108 may be regarded as a “dummy” gate that can be replaced in later process steps with other materials, such as a replacement metal gate or an engineered semiconductor material.

[0066] For embodiments of the type shown in FIGS. 3A-3B, since the P+ body tie region 303 is directly connected to the body region B beneath the gate structure G without the need for a body tie extension, the gate structure G need not be extended as shown in FIGS. 4A-4B and 5A-5B. For embodiments of the types shown in FIGS. 4A-4B or 5A-5B, the gate material 108 and GOX layer 110 are masked so as to extend into the drain side of the device to form a drain-side extension 401, as best shown in FIGS. 4A and 5A. For embodiments of the type shown in FIGS. 5A-5B, the gate material 108 and GOX layer 110 are masked so as to form a drain-side extension 401 and a short source-side tab 505, as best shown in FIG. 5A.

[0067] A layer of spacer material 112 (e.g., SiO ) may be formed about the sides of the core section of the gate structure G by deposition of spacer material and then masking and etching, essentially resulting in the gate structure G shown in FIG. 12A. In some embodiments, the initial spacer material may be laterally extended at a later stage (e.g., after formation of halo implants 116 and / or LDD regions 118, as shown in FIG. 12B) to final spacers 112, for example, by another round of spacer material deposition, masking, and etching.

[0068] FIG. 12B shows that optional halo implants 116 and / or LDD regions 118 may be fabricated within the active layer 102 near the side edges of the gate structure G. Halo implant 116 dopants may be, for example, P-type dopants such as boron (B), aluminum (Al), indium (In), orAttorney Docket No.: P3113 -PCTdifluoroboron (BF2). LDD region 118 dopants may be, for example, N-type dopants such as phosphorous (P), arsenic (As), and / or antimony (Sb). In asymmetric MOSFETS, halo implants 116 and / or LDD regions 118 may be formed primarily or only on one side of the gate structure G.

[0069] FIG. 12C shows that the source S and drain D may be implanted on either side of the gate structure G using suitable patterning to protect areas not to be implanted at this stage. Since this example is for an N-type MOSFET, the dopant is N+ material. Note that areas not to be implanted would be suitably masked (this caution applies to all steps).

[0070] FIG. 12D shows that a body tie region 1206 is implanted on the source-side of the gate structure G using suitable patterning to protect areas not to be implanted at this stage. Since this example is for an N-type MOSFET, the dopant is P+ material. In the illustrated example, a portion 109 of the gate structure G is doped with P+ material (but not so in the case of the embodiment shown in FIGS. 3A-3B). The body tie region 1206 corresponds to the body tie region 303 of FIGS.3A-3B, the body tie region 403 of FIGS. 4A-4B, and the body tie region 503 of FIGS. 5A-5B. For embodiments of the types shown in FIGS. 4A-4B and 5A-5B, the drain-side extension 401 provides a tolerance for drain-side misalignment of the mask for the body tie region 1206. For embodiments of the type shown in FIGS. 5A-5B, the short source-side tab 505 provides a tolerance for source-side misalignment of the mask for the body tie region 1206. A single MOSFET may include one or more BTS configurations of the types described in this disclosure.

[0071] Additional steps may include, for example, formation of a patterned dielectric (e.g., SiO2 or SisN-i), which in turn may be overlaid with a salicide block (SAB) layer, such as silicon nitride (SiN), to prevent subsequent formation of self-aligned silicides (also known as “salicides”) on protected structures / regions. Additional steps may also include, for example, formation of conductive contacts to the source S, the drain D, and the conductive layer 108 of the gate structure G. Such contacts may be salicides.

[0072] It should be appreciated that fabrication of a novel “New BTS” MOSFETs in accordance with the present invention, as well as variants, may be accomplished using alternative additive and / or subtractive process steps. Further, the fabrications steps may be performed in any feasible order. For example, the order of the steps illustrated in FIGS. 12C and 12D may be reversed in some embodiments - that is, the P+ implantation of the P+ body tie region 1206 mayAttorney Docket No.: P3113 -PCTbe performed before the N+ implantation of the source S and drain D. The same BTS configuration concepts and fabrication processes may be applied to fabricating “New BTS” MOSFETs in bulk silicon, high-resistivity silicon, SOI without a trap rich layer, etc.

[0073] Embodiments of the present invention encompass variations of the disclosed structures. For example, while the illustrated novel structures have been essentially symmetric devices, asymmetric devices may be fabricated using the same techniques. Compared to symmetric MOSFET devices, MOSFET devices having LDD region asymmetry generally provide better ON-state performance for parameters like Idiin / Idsat and voltage responsivity, Rv, and also improved breakdown voltage BVDSS.

[0074] As another example, while the disclosed embodiments show enhancement mode N-type MOSFETs, the teachings of this disclosure regarding “New BTS” MOSFETs may be applied to enhancement mode P-type MOSFETs, depletion mode N-type MOSFETs, and depletion mode P-type MOSFETs. A number of different processes may be used to fabricate the improved MOSFET devices referenced in this disclosure, including Extended Drain MOS (EDMOS) FETs and Laterally-Diffused MOS (LDMOS) FETs.

[0075] “New BTS” MOSFETs may be combined on a single IC with MOSFETs having a conventional BTS configuration. “New BTS” MOSFETs may be used in processes such as singlelayer transfers and double-layer transfers in order to gain access to the backside of the IC for further processing and / or to form 3-D stackings of ICs.

[0076] The various regions of the illustrated “New BTS” MOSFETs may having different dopant concentrations. For example, “New BTS” MOSFETs may include undoped regions as well as heavily doped (x+), intermediately doped (x), and lightly doped (x-) regions, where x is the polarity type and can be P-type (“P”) or N-type (“N”). Thus, for example, the designation “N-means a lesser concentration of N-type dopant than the designation “N+”. A lightly doped region may have a dopant concentration of about 1015 / cm3, an intermediately doped region may have a dopant concentration of about 1018 / cm3, and a heavily doped region may have a dopant concentration of about 1021 / cm3. Providing other dopant concentrations for the different doped regions may also be useful. For example, the doping concentrations for the different types of doped regions may be relative and depend on a selected fabrication process.Attorney Docket No.: P3113 -PCT

[0077] FIG. 13 is a process flowchart 1300 showing another representation of an example fabrication process for a “New BTS” MOSFET that is suitable for some contemporary IC front-end-of-line (FEOL) foundries. Note that some conventional steps, such as planarization, passivation, details of masking and etching, and superstructure formation have been omitted as known to those of ordinary skill in the art. The illustrated process includes:• If needed, thinning the semiconductor active layer (e.g., Si, Ge, SiGe, SiC, or the like) formed on a substrate to a suitable thickness (Step 1302).• Forming shallow trench isolation (STI) regions (Step 1304).• Forming a doped well which will become the body region B Step (1306).• Performing gate oxidation (Step 1308).• Depositing gate material (e.g., P+ poly-Si), patterning (e.g , masking and etching) to define a gate structure G, and forming gate structure spacers (Step 1310). The shape of the gate structure G may include a drain-side extension 401 and may also include a short sourceside tab 505 (e.g., where LTAB = lOOnm or less).• Optionally, patterning halo and / or LDD regions and implanting dopant (Step 1312).• Patterning source S and drain D regions and implanting a suitable dopant (Step 1314)• Patterning one or more body contact regions in electrical contact directly with the body region B or through a respective short source-side tab 505; slightly overlapping the gate structure G on the drain side is permissible if the body contact regions do not extend beyond respective drain-side extensions 401 (Step 1316).• Depositing a salicide block layer and patterning to define contact regions (Step 1318).• Depositing salicide (e.g., NiSi) in the defined contact regions and annealing (Step 1320).

[0078] Note that not all steps that may be performed during the manufacture of a novel MOSFET device as part of an IC are shown in the drawings. Such steps may vary between ICAttorney Docket No.: P3113 -PCTfoundries and may include (but are not limited to) substrate thinning, planarization, special implantations, annealing, formation of ohmic contacts, and formation of additional temporary or permanent structures (e.g., drift regions, substrate contacts, passivation layers, salicide blocks, replacement metal gate (RMG)), etc. After formation of a basic MOSFET structure, back-end-of-line (BEOL) processes may be applied, such as fabrication of electrical contacts (pads), vias, insulating layers (dielectrics), metallization layers, and bonding sites for die-to-package connections.

[0079] Circuits and devices in accordance with the present invention may be used alone or in combination with other components, circuits, and devices. Embodiments of the present invention may be fabricated as integrated circuits (ICs), which may be encased in IC packages and / or in modules for ease of handling, manufacture, and / or improved performance. In particular, IC embodiments of this invention are often used in modules in which one or more of such ICs are combined with other circuit components or blocks (e.g., fdters, amplifiers, passive components, and possibly additional ICs) into one package. The ICs and / or modules are then typically combined with other components, often on a printed circuit board, to form part of an end-product such as a cellular telephone, laptop computer, or electronic tablet, or to form a higher-level module which may be used in a wide variety of products, such as vehicles, test equipment, medical devices, etc. Through various configurations of modules and assemblies, such ICs typically enable a mode of communication, often wireless communication.

[0080] As one example of further integration of embodiments of the present invention with other components, FIG. 14 is a top plan view of a substrate 1400 that may be, for example, a printed circuit board or chip module substrate e.g., a thin-film tile). In the illustrated example, the substrate 1400 includes multiple ICs 1402a-1402d having terminal pads 1404 which would be interconnected by conductive vias and / or traces on and / or within the substrate 1400 or on the opposite (back) surface of the substrate 1400 (to avoid clutter, the surface conductive traces are not shown and not all terminal pads are labelled). The ICs 1402a-1402d may embody, for example, signal switches, active and / or passive fdters, amplifiers (including one or more low-noise amplifiers), and other circuitry. For example, IC 1402b may incorporate one or more instances of a “New BTS” MOSFET like the devices described in this disclosure.Attorney Docket No.: P3113 -PCT

[0081] The substrate 1400 may also include one or more passive devices 1406 embedded in, formed on, and / or affixed to the substrate 1400. While shown as generic rectangles, the passive devices 1406 may be, for example, filters, capacitors, inductors, transmission lines, resistors, antennae elements, transducers (including, for example, MEMS-based transducers, such as accelerometers, gyroscopes, microphones, pressure sensors, e / c.), batteries, etc., interconnected by conductive traces on or in the substrate 1400 to other passive devices 1406 and / or the individual ICs 1402a-1402d.

[0082] The front or back surface of the substrate 1400 may be used as a location for the formation of other structures. For example, one or more antennae may be formed on or affixed to the front or back surface of the substrate 1400; one example of a front-surface antenna 1408 is shown, coupled to an IC die 1402b, which may include RF front-end circuitry. Thus, by including one or more antennae on the substrate 1400, a complete radio may be created.

[0083] Embodiments of the present invention are useful in a wide variety of larger radio frequency (RF) circuits and systems for performing a range of functions, including (but not limited to) impedance matching circuits, RF power amplifiers, RF low-noise amplifiers (LNAs), phase shifters, attenuators, antenna beam-steering systems, charge pump devices, RF switches, high performance envelope tracking circuits, high performance average power tracking circuits, etc. Such functions are useful in a variety of applications, such as radar systems (including phased array and automotive radar systems), radio systems (including cellular radio systems), and test equipment.

[0084] Radio system usage includes wireless RF systems (including base stations, relay stations, and hand-held transceivers) that use various technologies and protocols, including various types of orthogonal frequency-division multiplexing (“OFDM”), quadrature amplitude modulation (“QAM”), Code-Division Multiple Access (“CDMA”), Time-Division Multiple Access (“TDMA”), Wide Band Code Division Multiple Access (“W-CDMA”), Global System for Mobile Communications (“GSM”), Long Term Evolution (“LTE”), 5G, 6G, and WiFi (e.g., 802.1 la, b, g, ac, ax, be) protocols, as well as other radio communication standards and protocols.

[0085] The term “MOSFET”, as used in this disclosure, includes any field effect transistor (FET) having an insulated gate whose voltage or charge level determines the conductivity of theAttorney Docket No.: P3113 -PCTtransistor, and encompasses insulated gates having a metal or metal -like, insulator, and / or semiconductor structure. The terms “metal” or “metal-like” include at least one electrically conductive material (such as aluminum, copper, or other metal, or highly doped polysilicon, graphene, or other electrical conductor), “insulator” includes at least one insulating material (such as silicon oxide or other dielectric material), and “semiconductor” includes at least one semiconductor material.

[0086] As used in this disclosure, the term “radio frequency” (RF) refers to a rate of oscillation in the range of about 3 kHz to about 300 GHz. This term also includes the frequencies used in wireless communication systems. An RF frequency may be the frequency of an electromagnetic wave or of an alternating voltage or current in a circuit.

[0087] With respect to the figures referenced in this disclosure, the dimensions for the various elements are not to scale; some dimensions may be greatly exaggerated vertically and / or horizontally for clarity or emphasis. In addition, references to orientations and directions (e.g., “top”, “bottom”, “above”, “below”, “lateral”, “vertical”, “horizontal”, etc.) are relative to the example drawings, and not necessarily absolute orientations or directions.

[0088] Various embodiments of the invention can be implemented to meet a wide variety of specifications. Unless otherwise noted above, selection of suitable component values is a matter of design choice. Various embodiments of the invention may be implemented in any suitable integrated circuit (IC) technology (including but not limited to MOSFET structures), or in hybrid or discrete circuit forms. Integrated circuit embodiments may be fabricated using any suitable substrates and processes, including but not limited to standard bulk silicon, high-resistivity bulk CMOS, silicon-on-insulator (SOI), and silicon-on-sapphire (SOS). Unless otherwise noted above, embodiments of the invention may be implemented in other transistor technologies, such as BiCMOS, LDMOS, BCD, FinFET, GAAFET, and SiC-based device technologies, using 2-D, 2.5-D, and 3-D structures. However, embodiments of the invention are particularly useful when fabricated using an SOI or SOS based process, or when fabricated with processes having similar characteristics. Fabrication in CMOS using SOI or SOS processes enables circuits with low power consumption, the ability to withstand high power signals during operation due to FET stacking, good linearity, and high frequency operation (i.e., radio frequencies up to and exceeding 300 GHz).Attorney Docket No.: P3113 -PCTMonolithic TC implementation is particularly useful since parasitic capacitances generally can be kept low (or at a minimum, kept uniform across all units, permitting them to be compensated) by careful design.

[0089] A number of embodiments of the invention have been described. It is to be understood that various modifications may be made without departing from the spirit and scope of the invention. For example, some of the steps described above may be order independent, and thus can be performed in an order different from that described. Further, some of the steps described above may be optional. Various activities described with respect to the methods identified above can be executed in repetitive, serial, and / or parallel fashion.

[0090] It is to be understood that the foregoing description is intended to illustrate and not to limit the scope of the invention, which is defined by the scope of the following claims, and that other embodiments are within the scope of the claims. In particular, the scope of the invention includes any and all feasible combinations of one or more of the processes, machines, manufactures, or compositions of matter set forth in the claims below. (Note that the parenthetical labels for claim elements are for ease of referring to such elements, and do not in themselves indicate a particular required ordering or enumeration of elements; further, such labels may be reused in dependent claims as references to additional elements without being regarded as starting a conflicting labeling sequence).

Claims

Attorney Docket No.: P3113 -PCTCLAIMSWHAT IS CLAIMED IS:

1. A MOSFET including:(a) a body region;(b) a gate structure positioned with respect to the body region so as to be able to control current flow through the body region;(c) a source region positioned adjacent to a first side of the body region;(d) a drain region positioned adjacent to a second side of the body region; and(e) a body tie region implanted within the source region in direct contact with the first side of the body region.

2. The MOSFET of claim 1, wherein the body region is doped to have a first semiconductor characteristic, the source region is doped to have a second semiconductor characteristic, the drain region is doped to have a third semiconductor characteristic, and the body tie region is doped to have a fourth semiconductor characteristic.

3. The MOSFET of claim 2, wherein the first semiconductor characteristic is P-type, the second and third semiconductor characteristics are N+ type, and the fourth semiconductor characteristic is P+ type.

4. The MOSFET of claim 1, wherein the MOSFET is formed in and on an active layer that is formed on an insulating layer supported by a substrate.

5. The MOSFET of claim 1, wherein the MOSFET is an N-type MOSFET.

6. The MOSFET of claim 1, wherein the MOSFET is a symmetric MOSFET.

7. The MOSFET of claim 1, wherein the MOSFET is an asymmetric MOSFET.

8. The MOSFET of claim 1, wherein the body tie region is electrically biased independently of the source region.Attorney Docket No.: P3113 -PCT9. A MOSFET including:(a) a body region;(b) a gate structure positioned with respect to the body region so as to be able to control current flow through the body region and including a drain-side extension;(c) a source region positioned adjacent to a first side of the body region;(d) a drain region positioned adjacent to a second side of the body region; and(e) a body tie region implanted within the source region in direct contact with the first side of the body region;wherein the drain-side extension of the gate structure is sized to block implantation of the body tie region within the drain region.

10. The MOSFET of claim 9, wherein the body region is doped to have a first semiconductor characteristic, the source region is doped to have a second semiconductor characteristic, the drain region is doped to have a third semiconductor characteristic, and the body tie region is doped to have a fourth semiconductor characteristic.

11. The MOSFET of claim 10, wherein the first semiconductor characteristic is P-type, the second and third semiconductor characteristics are N+ type, and the fourth semiconductor characteristic is P+ type.

12. The MOSFET of claim 9, wherein the MOSFET is formed in and on an active layer that is formed on an insulating layer supported by a substrate.

13. The MOSFET of claim 9, wherein the MOSFET is an N-type MOSFET.

14. The MOSFET of claim 9, wherein the MOSFET is a symmetric MOSFET.

15. The MOSFET of claim 9, wherein the MOSFET is an asymmetric MOSFET.

16. The MOSFET of claim 9, wherein the body tie region is electrically biased independently of the source region.Attorney Docket No.: P3113 -PCT17. AMOSFET including:(a) a body region;(b) a gate structure positioned with respect to the body region so as to be able to control current flow through the body region and including a drain-side extension and a sourceside body tie extension;(c) a source region positioned adjacent to a first side of the body region;(d) a drain region positioned adjacent to a second side of the body region; and(e) a body tie region implanted within the source region;wherein the drain-side extension of the gate structure is sized to block implantation of the body tie region within the drain region; andwherein the source-side body tie extension of the gate structure is sized to span a gap between the body region and the body tie region.

18. The MOSFET of claim 17, wherein the body region is doped to have a first semiconductor characteristic, the source region is doped to have a second semiconductor characteristic, the drain region is doped to have a third semiconductor characteristic, and the body tie region is doped to have a fourth semiconductor characteristic.

19. The MOSFET of claim 18, wherein the first semiconductor characteristic is P-type, the second and third semiconductor characteristics are N+ type, and the fourth semiconductor characteristic is P+ type.

20. The MOSFET of claim 17, wherein the MOSFET is an N-type MOSFET.

21. The MOSFET of claim 17, wherein the MOSFET is a symmetric MOSFET.

22. The MOSFET of claim 17, wherein the MOSFET is an asymmetric MOSFET.

23. The MOSFET of claim 17, wherein the body tie region is electrically biased independently of the source region.Attorney Docket No.: P3113 -PCT24. A method of fabricating a MOSFET and including:(a) fabricating a body region;(b) positioning a gate structure with respect to the body region so as to be able to control current flow through the body region;(c) positioning a source region adjacent to a first side of the body region;(d) positioning a drain region adjacent to a second side of the body region; and(e) implanting a body tie region within the source region in direct contact with the first side of the body region.

25. The method of claim 24, further including doping the body region to have a first semiconductor characteristic, doping the source region to have a second semiconductor characteristic, doping the drain region to have a third semiconductor characteristic, and doping the body tie region to have a fourth semiconductor characteristic.

26. The method of claim 25, wherein the first semiconductor characteristic is P-type, the second and third semiconductor characteristics are N+ type, and the fourth semiconductor characteristic is P+ type.

27. The method of claim 24, further including forming the MOSFET in and on an active layer that is formed on an insulating layer supported by a substrate.

28. The method of claim 24, wherein the MOSFET is an N-type MOSFET.

29. The method of claim 24, wherein the MOSFET is a symmetric MOSFET.

30. The method of claim 24, wherein the MOSFET is an asymmetric MOSFET.

31. The method of claim 24, further including electrically biasing the body tie region independently of the source region.

32. A method of fabricating a MOSFET and including:(a) fabricating a body region;(b) positioning a gate structure with respect to the body region so as to be able to control current flow through the body region, the gate structure including a drain-side extension; (c) positioning a source region adjacent to a first side of the body region;Attorney Docket No.: P3113 -PCT(d) positioning a drain region adjacent to a second side of the body region; and(e) implanting a body tie region within the source region in direct contact with the first side of the body region;wherein the drain-side extension of the gate structure is sized to block implantation of the body tie region within the drain region.

33. The method of claim 32, further including doping the body region to have a first semiconductor characteristic, doping the source region to have a second semiconductor characteristic, doping the drain region to have a third semiconductor characteristic, and doping the body tie region to have a fourth semiconductor characteristic.

34. The method of claim 33, wherein the first semiconductor characteristic is P-type, the second and third semiconductor characteristics are N+ type, and the fourth semiconductor characteristic is P+ type.

35. The method of claim 32, further including forming the MOSFET in and on an active layer that is formed on an insulating layer supported by a substrate.

36. The method of claim 32, wherein the MOSFET is an N-type MOSFET.

37. The method of claim 32, wherein the MOSFET is a symmetric MOSFET.

38. The method of claim 32, wherein the MOSFET is an asymmetric MOSFET.

39. The method of claim 32, further including electrically biasing the body tie region independently of the source region.

40. A method of fabricating a MOSFET and including:(a) fabricating a body region;(b) positioning a gate structure with respect to the body region so as to be able to control current flow through the body region, the gate structure including a drain-side extension and a source-side body tie extension;(c) positioning a source region adjacent to a first side of the body region;(d) positioning a drain region adjacent to a second side of the body region; and(e) implanting a body tie region within the source region;Attorney Docket No.: P3113 -PCTwherein the drain-side extension of the gate structure is sized to block implantation of the body tie region within the drain region; andwherein the source-side body tie extension of the gate structure is sized to span a gap between the body region and the body tie region.

41. The method of claim 40, further including doping the body region to have a first semiconductor characteristic, doping the source region to have a second semiconductor characteristic, doping the drain region to have a third semiconductor characteristic, and doping the body tie region to have a fourth semiconductor characteristic.

42. The method of claim 41, wherein the first semiconductor characteristic is P-type, the second and third semiconductor characteristics are N+ type, and the fourth semiconductor characteristic is P+ type.

43. The method of claim 40, further including forming the MOSFET in and on an active layer that is formed on an insulating layer supported by a substrate.

44. The method of claim 40, wherein the MOSFET is an N-type MOSFET.

45. The method of claim 40, wherein the MOSFET is a symmetric MOSFET.

46. The method of claim 40, wherein the MOSFET is an asymmetric MOSFET.

47. The method of claim 40, further including electrically biasing the body tie region independently of the source region.

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