Cascode switch system and method of operation thereof, half-bridge circuit

Abstract

A common-source cascode switching system and its operation method, as well as a half-bridge circuit, are disclosed. The common-source cascode switching system includes a JFET and a MOSFET coupled in series between the drain and source terminals, and a driving circuit. The driving circuit includes: a JFET driver that receives an input signal and outputs a JFET drive signal to a capacitor coupled in series with the gate of the JFET; a switch coupled between the gate and source terminals of the JFET and configured to respond to the input signal; and a comparator for comparing the JFET gate voltage with a threshold. The driving circuit also includes a MOSFET driver circuit to drive the MOSFET in a MOSFET on state during an input signal on state, and to drive the MOSFET in either a MOSFET off state or a MOSFET on state during an input signal off state in response to a comparison signal from the comparator.

Description

Technical Field

[0001] This disclosure relates in general to integrated circuit technology, and more specifically to switching circuits. Background Technology

[0002] Power electronics can be used to control the conversion and distribution of electricity. For example, a switching power converter can be used to generate a direct current ("DC") voltage from an alternating current ("AC") voltage by switching the current flowing through a magnetic element, such as an inductor. Conversely, an inverter can be used to convert a DC voltage to an AC voltage. In these and other forms of power electronics, power switches can be used to control the conversion and flow of power through the power conversion system and to the electronic circuitry powered by the device.

[0003] Common-source cascode switches can be used as power switches in power conversion systems to drive high currents and withstand large voltages. The inventors of the embodiments of this disclosure have recognized that common-source cascode switches can suffer from unstable oscillations and drain voltage overshoot due to inductive loads and the turn-off characteristics of the switches. The inventors of the embodiments of this disclosure have also recognized that such drain voltage overshoot can damage components of the common-source cascode switch unless additional and expensive RC snubber circuitry (R-Csnubber) is used to limit it across the drain-to-source of the common-source cascode switch. The embodiments of this disclosure address one or more of these challenges. Summary of the Invention

[0004] According to a first aspect, a common-source cascode switching system is provided, the system comprising: a common-source cascode switch and a driving circuit. The common-source cascode switch includes: a JFET coupled between a drain terminal and a common-source cascode node of the switch; and a MOSFET coupled between the common-source cascode node and a source terminal of the switch. The driving circuit includes: a JFET driver configured to receive an input signal and output a JFET drive signal to a capacitor series coupled between the JFET driver and the gate of the JFET; a switch coupled between the gate and the source terminal of the JFET, configured to respond to the input signal; a comparator configured to compare a JFET gate voltage with a threshold; and a MOSFET driver circuit configured to: drive the MOSFET in a MOSFET on state during an on state of the input signal; and drive the MOSFET in either a MOSFET off state or a MOSFET on state during an off state of the input signal, in response to a comparison signal from the comparator.

[0005] According to a second aspect, a half-bridge circuit is provided, the half-bridge circuit comprising: a first cascode switching system forming a high-side switch of the half-bridge circuit; and a second cascode switching system forming a low-side switch of the half-bridge circuit. Each of the first and second cascode switching systems includes a cascode switch and a driving circuit. The cascode switch includes: a JFET coupled between a drain terminal and a cascode node of the cascode switch; and a MOSFET coupled between the cascode node and a source terminal of the cascode switch. The driving circuit includes: a JFET driver configured to receive an input signal and output a JFET drive signal to a capacitor series coupled between the JFET driver and the gate of the JFET; a switch coupled between the gate and the source terminal of the JFET, the switch being configured to respond to the input signal; a comparator configured to compare the JFET gate voltage with a threshold; and a MOSFET driver circuit configured to: drive the MOSFET in a MOSFET on state during an on state of the input signal; and drive the MOSFET in either a MOSFET off state or a MOSFET on state during an off state of the input signal, in response to a comparison signal from the comparator.

[0006] According to a third aspect, a method for operating a common-source common-gate switching system is provided, the method comprising: receiving a turn-on command; driving a JFET to a JFET-on state in response to the turn-on command; driving a MOSFET to a MOSFET-on state in response to the turn-on command; charging a capacitor series coupled to the gate of the JFET in response to the turn-on command; receiving a turn-off command; driving the JFET with a voltage stored across the capacitor in response to the turn-off command; comparing the JFET gate voltage with a threshold voltage to generate a comparison signal; and driving the MOSFET in response to the comparison signal. Attached Figure Description

[0007] A more complete understanding of this embodiment can be obtained by referring to the following description taken in conjunction with the accompanying drawings, in which similar reference numerals indicate similar features.

[0008] Figure 1 A schematic diagram of a common-source, common-gate switching system according to an embodiment of the present disclosure is shown.

[0009] Figure 2A schematic diagram of an example comparator according to an embodiment of the present disclosure is shown.

[0010] Figure 3 A graph illustrating example waveforms within a common-source cascode switching system according to an embodiment of this disclosure is provided.

[0011] Figure 4 The operation of an example method according to an embodiment of this disclosure is illustrated. Detailed Implementation

[0012] Details of one or more embodiments are set forth in the following description and accompanying drawings. Other features will be apparent from the description, the drawings, and the claims. The disclosed embodiments should not be construed as or otherwise used to limit the scope of this disclosure, including the claims. Furthermore, those skilled in the art will understand that the following description has broad application, and the discussion of any embodiment is intended to be an example of that embodiment and is not intended to imply that the scope of this disclosure, including the claims, is limited to that embodiment.

[0013] Various terms are used to refer to specific system components. Different companies may use different names to refer to a component, and this disclosure is not intended to distinguish between components with different names but the same form and function. In the following discussion and in the claims, the terms "comprising" and "including" are used in an open form, and therefore, these terms should be interpreted as meaning "including but not limited to". Additionally, the term "coupled" is intended to indicate either an indirect connection or a direct connection. Thus, if a first device is coupled to or is coupled to a second device, the connection between the first device and the second device can be made through a direct connection or through an indirect connection via other devices and connections.

[0014] Figure 1 A schematic diagram of a common-source cascode switching system 100 according to an embodiment of the present disclosure is illustrated. The common-source cascode switching system 100 can be implemented in a suitable manner according to the operation described in the present disclosure. In some embodiments, the common-source cascode switching system 100 may include a common-source cascode switch 110, a capacitor 120, and a drive circuit 140. As described in more detail below, the drive circuit 140 may be configured to drive the common-source cascode switch 110 in response to an input signal IN.

[0015] The common-source cascode switch 110 may include a junction field-effect transistor (“JFET”) 102 and a metal-oxide-semiconductor field-effect transistor (“MOSFET”) 104. For example... Figure 1As shown, JFET 102 may be coupled between the drain terminal 111 and the cascode node 112 of cascode switch 110. For example, JFET 102 may have a drain coupled to the drain terminal 111 of cascode switch 110 and a source coupled to the cascode node 112. JFET 102 may be a depletion-mode device that can be normally turned on when the gate-to-source voltage is zero volts and driven off when the gate-to-source voltage is below a threshold of, for example, -4 volts, -6 volts, -8 volts, -12 volts or less. For illustrative purposes, the embodiment of JFET 102 is described below with a gate-to-source threshold of, for example, -12 volts. MOSFET 104 may be coupled between the cascode node 112 and the source terminal 113 of cascode switch 110. For example, MOSFET 104 may have a drain coupled to the source of JFET 102 at cascode node 112, and a source coupled to the source terminal 113 of cascode switch 110. MOSFET 104 may be an enhancement-mode device that can be normally turned off when the gate-to-source voltage is zero volts and driven to turn on when the gate-to-source voltage is above a positive threshold.

[0016] The cascode switch 110 and the cascode switching system 100, as a whole, can be used in high-side and low-side switching applications. For example, in a half-bridge circuit application, a first instance of the cascode switching system 100 can form the high-side switch of the half-bridge circuit, and a second instance of the cascode switching system 100 can form the low-side switch of the half-bridge circuit. The internal circuitry of the drive circuit 140 can be referenced from the source terminal 113, which can act as the low-voltage power rail for both the cascode switch 110 and the drive circuit 140. For example, as... Figure 1 As shown, the internal circuitry of drive circuitry 140, including JFET driver 142, switch 144, and driver 180, is referenced from source terminal 113. In embodiments where the cascode switching system 100 acts as a low-side switch, source terminal 113 may be coupled to ground, and the internal circuitry of drive circuitry 140 may therefore reference ground. And in embodiments where the cascode switching system 100 acts as a high-side switch, source terminal 113 may be coupled to a floating switch node, and the internal circuitry of drive circuitry 140 may therefore reference a floating switch node. For such low-side or high-side applications, a supply voltage VSUPPLY may also be supplied to the internal circuitry of drive circuitry 140 at a voltage level sufficiently higher than the voltage at source terminal 113 to power drive circuitry 140 and drive JFET 102 and MOSFET 104.

[0017] In some embodiments, MOSFET 104 may be an N-type MOSFET (“NMOS” or “NMOS transistor”). Additionally, in some embodiments, MOSFET 104 may be a silicon MOSFET formed on a silicon substrate. MOSFET 104 may also be implemented in other semiconductor technologies, including silicon carbide (“SiC”) or gallium arsenide (“GaN”). In some embodiments, JFET 102 may be a silicon carbide JFET formed on a silicon carbide substrate. JFET 102 may also be adapted to be formed using any other semiconductor technology that produces a JFET with current density and voltage isolation properties suitable for acting as a lower voltage-rated MOSFET in a cascode structure. Furthermore, in some embodiments, JFET 102 and MOSFET 104 may be co-packaged in a multi-die integrated circuit package. For example, JFET 102 may be implemented as a silicon carbide JFET, MOSFET 104 may be implemented as a silicon MOSFET 104, and the silicon carbide-based die and silicon-based die on which JFET 102 and MOSFET 104 are respectively implemented may be co-packaged together in a multi-die integrated circuit package. In addition, in some implementations, the JFET 102, MOSFET 104 and drive circuit 140 may be co-packaged with or separately from the capacitor 120 in a multi-die integrated circuit package.

[0018] In conjunction with capacitor 120, drive circuitry 140 can be configured to drive JFET 102 and MOSFET 104 in response to an input signal IN received at input terminal 101. In some embodiments, input signal IN may be a pulse-width modulation (PWM) input signal for turning on and off the cascode switch 110. Depending on the application, drive circuitry 140 may be configured to receive an input signal where a logic high level indicates an on command and a logic low level indicates an off command, or vice versa, where a logic low level indicates an on command and a logic high level indicates an off command. For illustrative purposes, the following embodiments describe a logic high level of input signal IN as indicating an on command or the on state of input signal IN, and a logic low level of input signal IN as indicating an off command or the off state of input signal IN.

[0019] The drive circuit 140 can be implemented in any suitable manner according to the operation described in this disclosure. For example... Figure 1 As shown, the drive circuit 140 may include a JFET driver 142, a switch 144, a comparator 150, and a MOSFET driver circuit 160.

[0020] JFET driver 142 can be configured to receive input signal IN and output JFET drive signal JDRIV to capacitor 120 series coupled between JFET driver 142 and the gate of JFET 102. When input signal IN is at a logic high level (on state), JFET driver 142 can output high JFET drive signal JDRIV at the level of voltage supply VSUPPLY. In some embodiments, VSUPPLY can be, for example, +8V, +12V, +15V or greater, relative to the voltage at source terminal 113 and depending on the gate threshold of JFET 102 and / or MOSFET 104. For illustrative purposes, the embodiment is described below with a VSUPPLY of +15V relative to the voltage at source terminal 113.

[0021] like Figure 1 As shown, switch 144 may be coupled between the gate and source terminal 113 of JFET 102. In some embodiments, switch 144 coupled between the gate and source terminal 113 of JFET 102 may include a PMOS transistor. In other embodiments, switch 144 may include an NMOS transistor or any other suitable switching device. Switch 144 may be configured to respond to an input signal IN. For example, a logic high state of the input signal IN may drive switch 144 to turn on, thereby coupling the gate of JFET 102 to the source terminal 113. Thus, switch 144 may pull down the JFET gate voltage JGATE to the voltage level of the source terminal 113. As mentioned above, JFET 102 may be a depletion-mode device that is normally turned on when the gate-to-source voltage is zero volts. Therefore, switch 144 may drive JFET 102 into the JFET on state in response to a logic high level (on state) of the input signal IN. Furthermore, as described directly below, the MOSFET driver circuit 160 can also drive the MOSFET 104 to the MOSFET ON state in response to a logic high level (ON state) of the input signal IN.

[0022] MOSFET driver circuit 160 may include logic circuitry 170 and driver 180. Logic circuitry 170 may be configured to receive a JFET drive signal JDRIVIVE and a comparison signal JGATE_COMP. Logic circuitry 170 may include a buffer 171, an inverter 172, an AND gate 173, and a latch 174. In some embodiments, latch 174 may be a set-reset latch. Buffer 171 may receive the JFET drive signal JDRIVIVE and output the signal to the set input of latch 174. Therefore, when JFET driver 142 drives the JFET drive signal JDRIVIVE high in response to a logic high level (on state) of input signal IN, latch 174 may output a logic high signal. Driver 180 may be coupled to drive the gate of MOSFET 104 in response to the logic circuitry output from latch 174. For example, in response to a logic high signal from latch 174, driver 180 may output a high MOSFET drive signal MDRIVE to drive MOSFET 104 into the MOSFET ON state. Therefore, MOSFET driver circuit 160 can drive MOSFET 104 into the MOSFET ON state during the ON state of the input signal. In some embodiments, driver 180 may be powered by the same VSUPPLY as JFET driver 142. In other embodiments, such as Figure 1 As shown, the driver 180 may be powered by a low-voltage supply VSUPPLY_LV, which may have a voltage of, for example, +5 volts relative to the source terminal 113 or any other voltage level suitable for driving the MOSFET 104.

[0023] In summary, in response to a logic high level (on state) of the input signal IN, JFET 102 can be driven into the JFET on state, and MOSFET 104 can be driven into the MOSFET on state. Furthermore, a voltage can be formed across the first terminal 121 and the second terminal 122 of capacitor 120. For example, in response to a logic high level (on state) of the input signal IN, switch 144 can maintain the JFET gate voltage JGATE at the second terminal 122 of capacitor 120 at the voltage level of the source terminal 113. Simultaneously, JFET driver 142 can output a JFET drive signal JDRIVE to the first terminal 121 of capacitor 120, for example, at a level of +15 volts relative to the voltage at the source terminal 113. As explained directly below, the voltage formed across capacitor 120 can be used to drive JFET 102 into the off state in response to a subsequent logic low level (off state) of the input signal IN.

[0024] When the input signal IN transitions from a logic high level (on state) to a logic low level (off state), the JFET driver 142 can output a low JFET drive signal JDRIVE at the voltage level of the source terminal 113. Furthermore, in response to the logic low level (off state) of the input signal IN, the switch 144 can be turned off, thereby placing the second terminal 122 of the capacitor 120 and the gate of the JFET 102 in a high-impedance state. Through this transition, the capacitor 120 can maintain a relative +15 volt from the first terminal 121 to the second terminal 122. Therefore, when JDRIVE at the first terminal 121 transitions from +15 volts to zero volts relative to the source terminal 113, the capacitor 120 can force the JFET gate voltage JGATE at the second terminal 122 to transition from zero volts to -15 volts relative to the source terminal 113. As described above, the JFET 102 can be a depletion-mode device with, for example, a gate-to-source threshold voltage of -12 volts. Therefore, the -15 volt applied to the gate of JFET 102 by capacitor 120 can drive JFET 102 into the JFET off state. Therefore, the drive circuit 140 can directly drive JFET 102 into the JFET off state in response to the logic low level (off state) of the input signal IN, together with capacitor 120.

[0025] In some embodiments, the capacitance of capacitor 120 may be at least 10nF, 20nF, 40nF, 100nF, or greater. The size of capacitor 120 may be configured, for example, to prevent the JFET gate voltage JGATE established by capacitor 120 from being significantly reduced due to parasitic gate-to-drain capacitance or parasitic gate-to-source capacitance. Therefore, in some embodiments, the capacitance of capacitor 120 may be at least 10 times the gate capacitance of JFET 102. For example, the capacitance of capacitor 120 may be 10, 20, 40, 100, or more times the gate capacitance of JFET 102.

[0026] Comparator 150 can be configured to compare the JFET gate voltage JGATE with a threshold VTH to generate a comparison signal JGATE_COMP. Therefore, when the input signal is at a logic low level (off state), comparator 150 can be used to provide an indication of whether the JFET gate voltage JGATE is sufficient to drive JFET 102 into the JFET off state. As described in more detail below, MOSFET driver circuitry 160 can drive MOSFET 104 into either a MOSFET off state or a MOSFET on state in response to the comparison signal JGATE_COMP from comparator 150 during the off state of the input signal IN. If the JFET gate voltage JGATE is sufficient to drive JFET 102 into the JFET off state during the off state of the input signal IN, MOSFET driver circuitry 160 can put MOSFET 104 into the MOSFET on state to save switching losses. Conversely, if the JFET gate voltage JGATE is insufficient to drive JFET 102 into the JFET off state during the off state of the input signal IN, the MOSFET driver circuit 160 can drive MOSFET 104 into the MOSFET off state to ensure that the conductive path of the cascode switch 110 is turned off as a whole.

[0027] like Figure 1 As shown, the reset input to latch 174 can be coupled to the output of AND gate 173. The first input to AND gate 173 can be coupled to the output of inverter 172, which inverts the JFET drive signal JDRIVIVE. Therefore, when JDRIVIVE is low in response to a logic low (off state) of input signal IN, the first input to AND gate 173 can be high. Under such conditions during the off state of input signal IN, AND gate 173 can pass the comparison signal JGATE_COMP at its second input to the output of AND gate 173.

[0028] Comparator 150 compares the JFET gate voltage JGATE with a threshold VTH. In some embodiments, the threshold of comparator 150 may be set to or near, for example, -12 volts to match the -12 volt gate-to-source threshold voltage of JFET 102. In embodiments where JFET 102 has different gate-to-source threshold voltages, the threshold of comparator 150 may be adjusted accordingly. Thus, the comparison signal JGATE_COMP provides an indication of whether the JFET gate voltage JGATE is sufficient to drive JFET 102 into a JFET off state when the input signal IN is at a logic low level (off state).

[0029] If the JFET gate voltage JGATE is, for example, -15 volts, and is therefore sufficiently below the example -12 volt threshold of JFET 102 to keep JFET 102 in the off state, comparator 150 can output a logic low compare signal JGATE_COMP. Therefore, the output of AND gate 173 can remain low, preventing the reset input of latch 174 from being triggered. Thus, driver 180 can keep MOSFET 104 in the on state. Conversely, if the JFET gate voltage JGATE is, for example, -11 volts and has not reached the -12 volt threshold, comparator 150 can output a logic high compare signal JGATE_COMP. The output of AND gate 173 can therefore go high, triggering the reset input of latch 174. Latch 174 can then output a low signal to driver 180, which in turn drives MOSFET 104 in the off state.

[0030] In summary, the MOSFET driver circuit 160 can be configured to drive the MOSFET 104 in the MOSFET ON state during the ON state of the input signal IN, in response to a comparator signal JGATE_COMP from comparator 150 indicating that the JFET gate voltage is sufficient to drive the JFET 102 in the JFET ON state. The MOSFET driver circuit 160 can also be configured to drive the MOSFET 104 in the MOSFET OFF state during the ON state of the input signal IN, in response to a comparator signal JGATE_COMP from comparator 150 indicating that the JFET gate voltage JGATE is insufficient to drive the JFET in the JFET ON state.

[0031] The operation of the cascode switching system 100 described herein offers several advantages. First, by directly driving the gate of JFET 102, the parasitic gate-to-drain capacitance of JFET 102 helps slow the switching transition of cascode switch 110, thereby reducing transient voltage spikes that may occur at the drain of cascode switch 110 due to, for example, switching of an inductive load. Furthermore, by directly driving the gate of JFET 102, the turn-on and turn-off times of JFET 102 and cascode switch 110 as a whole can be further controlled. For example, in some embodiments, cascode switching system 100 may also include a resistor series coupled between capacitor 120 and the gate of JFET 102. In such implementations, the resistor helps slow down the turn-on and turn-off speeds of the JFET 102 and the cascode switch 110 as a whole, thereby further reducing transient voltage spikes that can be caused at the drain of the cascode switch 110 due to, for example, switching of an inductive load. Additionally, the operation of the cascode switch system 100 as described herein reduces switching losses while still maintaining safe operation of the cascode switch 110. For example, if the JFET gate voltage JGATE is sufficient to drive the JFET 102 to the JFET off state during the off state of the input signal IN, the MOSFET driver circuit 160 can put the MOSFET 104 in the MOSFET on state to save the switching losses that would otherwise be associated with driving the gate of the MOSFET 104 high and low to turn the MOSFET 104 on and off. Conversely, if the JFET gate voltage JGATE is insufficient to drive JFET 102 into the JFET off state during the off state of the input signal IN, the MOSFET driver circuit 160 can drive MOSFET 104 into the MOSFET off state to ensure that the conductive path of the cascode switch 110 is turned off as a whole and thereby maintains the safe operation of the cascode switch 110.

[0032] Figure 2 A schematic diagram illustrating a comparator 200 according to an embodiment of the present disclosure is shown. The comparator 200 may represent a reference... Figure 1 The described implementation of comparator 150. For example... Figure 2 As shown, comparator 200 may include current source 202, transistor 204, transistor 206, buffer 208, resistor 210 and Zener diode 212.

[0033] Comparator 200 can be configured to compare the JFET gate voltage JGATE with a threshold. Figure 2 In the embodiment shown, the reverse breakdown voltage of the Zener diode 212 can provide a threshold, against which the JFET gate voltage JGATE is compared.

[0034] Transistor 204 may be a P-type MOSFET (“PMOS”), and transistor 206 may be an N-type MOSFET (“NMOS”). The source of transistor 204 may be coupled to receive current from current source 202, and the drain of transistor 204 may be coupled to the drain of transistor 206. The source of transistor 206 may be coupled to the intermediate node between Zener diode 212 and resistor 210. The gates of transistors 204 and 206 may be wired to a low position, for example, as referenced above. Figure 1 The source terminal 113 of the described cascode switching system 100 can serve as the low voltage rail of the cascode switching system 100.

[0035] When JGATE drops below the negative breakdown voltage of Zener diode 212, Zener diode 212 pulls the voltage at the source of transistor 206 down to a negative voltage, thereby turning on transistor 206. When transistor 206 is on, transistors 204 and 206 can absorb current from current source 202, thereby reducing the voltage at the input of buffer 208. Buffer 208 can then output a logic low compare signal JGATE_COMP, indicating that the JFET gate voltage JGATE is sufficient to drive JFET 102 into the JFET off state.

[0036] If JGATE does not reach a negative voltage below the negative breakdown voltage of Zener diode 212, Zener diode 212 will not conduct, and the voltage at the source of transistor 206 will match the voltage at the gate of transistor 206. Therefore, transistor 206 can block current from current source 202, thereby causing the voltage at the input of buffer 208 to go high. Buffer 208 can then output a logic high comparator signal JGATE_COMP, indicating that the JFET gate voltage JGATE is insufficient to drive JFET 102 into the JFET off state.

[0037] Figure 3 A graph illustrating an example waveform within a common-source cascode switching system 100 according to an embodiment of the present disclosure is provided. Specifically, Figure 3 This illustration demonstrates how the JFET drive signal JDRIVIVE, the JFET gate voltage JGATE, the comparator signal JGATE_COMP, and the MOSFET drive signal MDRIVE respond to the repeated cycle of the input signal IN as the supply voltage VSUPPLY increases over time. For simplicity, Figure 3 The waveform in the example illustrates the aforementioned signal in an example application where the cascode switching system 100 is implemented as a low-side switch, wherein the source terminal 113 of the cascode switching system 100 is maintained at zero volts at ground.

[0038] like Figure 3 As shown, the input signal IN can cycle between a logic high (ON) state and a logic low (OFF) state. When the input signal is in the logic high (ON) state, the JFET drive signal JDRIV can be at a high voltage equal to the voltage supply level VSUPPLY, and the JFET gate voltage JGATE can be forced to zero volts. When the input signal IN transitions to the logic low (OFF) state, it forces the JFET drive signal JDRIV down to zero volts. (See above reference...) Figure 1 As described, when the JFET drive signal JDRIV transitions from high to low, capacitor 120 can maintain a voltage across the first terminal 121 and the second terminal 122. Therefore, when the input signal IN transitions to a logic low off state and the JFET drive signal JDRIV transitions from a high voltage level equal to VSUPPLY to zero volts, capacitor 120 can force the JFET gate voltage JGATE to transition from zero volts to a negative voltage with the same magnitude as VSUPPLY.

[0039] As referenced above Figure 1 As described, comparator 150 compares the JFET gate voltage JGATE with a threshold corresponding to the gate-to-source threshold of JFET 102. For example, the threshold of comparator 150 can be set to -12 volts to correspond to the -12 volt gate-to-source threshold of the depletion mode JFET 102. Therefore, the comparison signal JFET_COMP from comparator 150 can indicate whether the negative voltage applied to the gate of JFET 102 during the off state of the input signal IN has a magnitude sufficient to drive JFET 102 into the JFET off state.

[0040] exist Figure 3During time t1, VSUPPLY may be less than +12 volts. Therefore, the negative voltage applied to the gate of JFET 102 by capacitor 120 during the off-state of input signal IN within time t1 may not have a sufficiently negative value to drive JFET 102 into the off-state. Therefore, comparator 150 may output a logic high-level comparator signal JGATE_COMP to indicate that the JFET gate voltage is insufficient to drive JFET into the off-state throughout time t1. In response to the comparator signal JGATE_COMP, MOSFET driver circuit 160 may output a low MOSFET drive signal MDRIVE during each off-state of input signal IN throughout time t1. Therefore, MOSFET driver circuit 160 may drive MOSFET 104 into the off-state during each off-state of input signal IN throughout time t1. Therefore, even when the supply voltage is insufficient to generate a sufficiently negative voltage to drive JFET 102 into the off-state, MOSFET driver circuit 160 can ensure that the conductive path of cascode switch 110 is turned off during the off-state of input signal IN.

[0041] Moving to time t2, the supply voltage VSUPPLY exceeds +12 volts. Therefore, the amount of negative voltage applied to the gate of JFET 102 by capacitor 120 during the off-state of input signal IN can exceed the -12 volt threshold required to drive JFET 102 into the off-state. Therefore, during time t2, JFET 102 can be cyclically driven to turn on and off after input signal IN. Furthermore, during time t2, comparator 150 can output a logic-low comparison signal JGATE_COMP to indicate that the JFET gate voltage JGATE during the off-state of input signal IN is sufficient to drive JFET 102 into the off-state. In response to the comparison signal JGATE_COMP, MOSFET driver circuit 160 can maintain the MOSFET drive signal MDRIVE at a high level throughout time t2. Therefore, MOSFET 104 can be driven into the MOSFET on-state throughout time t2. Since JFET 102 cyclically turns on and off in response to input signal IN during time t2, it may not be necessary to also cyclically turn the MOSFET on and off. Furthermore, by keeping MOSFET 104 in the ON state throughout time t2, the switching losses associated with turning on and off MOSFET 104 can be avoided, thereby improving the efficiency of the system in which the cascode switching system 100 is implemented.

[0042] Figure 4An example method 400 for operating a common-source cascode switching system according to an embodiment of this disclosure is illustrated. Method 400 can be performed by any suitable mechanism, such as capacitor 120, drive circuit 140, JFET driver 142, switch 144, comparator 150, MOSFET driver circuit 160, and / or any suitable combination thereof. Method 400 can be used with... Figure 4 The steps shown can be performed in fewer or more steps. Furthermore, steps in method 400 can be omitted, repeated, performed in parallel, or combined with... Figure 4 The steps shown may be executed sequentially or recursively, but the order in which they are shown may differ. Although one or more steps of method 400 are shown in order, they may be executed simultaneously or in a reordered manner.

[0043] Step 402 may include receiving a turn-on command. For example, as referenced above. Figure 1 As described, the drive circuit 140 and JFET driver 142 can specifically receive the input signal IN. In some embodiments, the input signal IN can be a PWM input signal used to turn the cascode switch 110 on and off. Also as referenced above... Figure 1 As described, a high logic level of the input signal IN can indicate the on state of the input signal or be used to turn on the cascode switch 110.

[0044] Step 404 may include driving the JFET into the JFET ON state in response to a turn-on command. (See above reference.) Figure 1 As described, JFET 102 can be a depletion-mode device that is normally turned on at a zero-volt gate-to-source voltage. In response to a logic high level of the input signal IN, switch 144 can couple the gate of JFET 102 to the source terminal of cascode switch 110, thereby driving JFET 102 into the JFET-on state.

[0045] Step 406 may include driving the MOSFET into a MOSFET-on state in response to a turn-on command. For example, in response to a logic high level of the input signal IN indicating a turn-on command, the JFET driver 142 may output a high JFET drive signal JDRIVE. (See above reference...) Figure 1 As described, the MOSFET driver circuit 160 can receive a JFET drive signal JDRIVIVE. Specifically, a high JFET drive signal JDRIVIVE can set latch 174, causing driver 180 to output a high MOSFET drive signal MDRIVE to drive MOSFET 104 into the MOSFET ON state. Therefore, the MOSFET driver circuit 160 can drive MOSFET 104 into the MOSFET ON state in response to a logic high state of the input signal IN indicating a turn-on command.

[0046] Step 408 may include charging a capacitor series coupled to the gate of the JFET in response to a turn-on command. For example, as referenced above. Figure 1 As described, and in response to a logic high level of the input signal IN indicating a turn-on command, switch 144 couples the second terminal 122 of capacitor 120 to the source terminal 113, while JFET driver 142 charges the first terminal 121 of capacitor 120 to a positive voltage, for example, +15 volts relative to the source terminal 113.

[0047] Step 410 may include receiving a shutdown command. For example, as referenced above. Figure 1 As described, the drive circuit 140 and JFET driver 142 can specifically receive the input signal IN. In some embodiments, the input signal IN can be a PWM input signal used to turn the cascode switch 110 on and off. Also as referenced above... Figure 1 As described, a logic low level of the input signal IN can indicate the off state of the input signal or a turn-off command for turning off the cascode switch 110.

[0048] Step 412 may include driving the JFET with the voltage stored across the capacitor in response to a turn-off command. For example, as referenced above. Figure 1 As described, when the input signal IN transitions from a logic high level (on state) to a logic low level (off state), the JFET driver 142 can output a low JFET drive signal JDRIV at the voltage level of the source terminal 113. Furthermore, switch 144 can be turned off, thereby placing the second terminal 122 of capacitor 120 and the gate of JFET 102 in a high-impedance state. Through this transition, capacitor 120 can maintain a relative +15 volt from the first terminal 121 to the second terminal 122. Therefore, when JDRIV at the first terminal 121 transitions from +15 volts to zero volts relative to the source terminal 113, capacitor 120 can force the JFET gate voltage JGATE at the second terminal 122 to transition from zero volts to -15 volts relative to the source terminal 113. In summary, the JFET driver 142 and capacitor 120 together can drive the gate of JFET 102 with a negative voltage that is quantitatively equal to the positive voltage supplying the JFET driver 142.

[0049] Step 414 may include comparing the JFET gate voltage with a threshold to generate a comparison signal. For example, as referenced above. Figure 1As described, comparator 150 compares the JFET gate voltage JGATE with a threshold to generate a comparison signal JGATE_COMP. The threshold of comparator 150 can be configured to correspond to the gate-to-source threshold of JFET 102. Therefore, the comparison signal JGATE_COMP indicates whether the JFET gate voltage JGATE is sufficient to drive JFET 102 into a JFET off state in response to a turn-off command.

[0050] Step 416 may include driving the MOSFET in response to a comparison signal. For example, as referenced above. Figure 1 As explained, driving MOSFET 104 in response to the comparator signal JGATE_COMP may include: driving MOSFET 102 into a MOSFET ON state in response to the comparator signal JGATE_COMP indicating that the JFET gate voltage JGATE is sufficient to drive JFET 104 into a JFET ON state. Alternatively, driving MOSFET 104 in response to the comparator signal JGATE_COMP may include: driving MOSFET 104 into a MOSFET OFF state in response to the comparator signal JGATE_COMP indicating that the JFET gate voltage JGATE is insufficient to drive JFET into a JFET OFF state.

[0051] Although examples have been described above, other modifications and variations can be made from this disclosure without departing from the spirit and scope of these examples. The description of the various embodiments above exemplifies the principles of the invention. Based on the above disclosure, many variations and modifications will become apparent to those skilled in the art. The following claims are intended to encompass all such variations and modifications.

Claims

1. A common-source cascode switching system, the common-source cascode switching system comprising: Common source cascode switch and drive circuit, The common-source common-gate switch includes: JFET, the JFET being coupled between the drain terminal of the cascode switch and the cascode node; and MOSFET, the MOSFET being coupled between the common-source gate node and the source terminal of the common-source gate switch; The driving circuit includes: A JFET driver, configured to receive an input signal and output a JFET drive signal to a capacitor series coupled between the JFET driver and the gate of the JFET; A switch coupled between the gate and the source terminal of the JFET, the switch being configured to respond to the input signal; A comparator configured to compare the JFET gate voltage with a threshold; and A MOSFET driver circuit configured to: drive the MOSFET to a MOSFET ON state during the ON state of the input signal; and drive the MOSFET to either a MOSFET OFF state or a MOSFET ON state in response to a comparison signal from the comparator during the OFF state of the input signal.

2. The common-source cascode switching system of claim 1, wherein the MOSFET driver circuit is configured to drive the MOSFET into the MOSFET on state during the off state of the input signal, in response to a comparison signal from the comparator indicating that the JFET gate voltage is sufficient to drive the JFET into a JFET off state.

3. The common-source cascode switching system of claim 1, wherein the MOSFET driver circuit is configured to drive the MOSFET in the MOSFET off state during the off state of the input signal in response to a comparison signal from the comparator indicating that the JFET gate voltage is insufficient to drive the JFET in the JFET off state.

4. The common-source common-gate switching system according to claim 1, wherein the capacitance of the capacitor is at least 10 times the gate capacitance of the JFET.

5. The common-source common-gate switching system according to claim 1, wherein the capacitance of the capacitor is at least 10nF.

6. The common-source cascode switching system according to claim 1, wherein the common-source cascode switching system further comprises a resistor coupled in series between the capacitor and the gate of the JFET.

7. The common-source cascode switching system according to claim 1, wherein: The JFET is a silicon carbide JFET; and The MOSFET is a silicon MOSFET.

8. The common-source common-gate switching system according to claim 1, wherein the JFET, the MOSFET and the driving circuit are co-packaged in a multi-die integrated circuit package.

9. The common-source cascode switching system of claim 1, wherein the switch coupled between the gate and the source terminal of the JFET comprises a PMOS transistor.

10. The common-source cascode switching system according to claim 1, wherein the MOSFET driver circuit comprises: Logic circuitry configured to receive the JFET drive signal and the comparison signal; and A driver, coupled to drive the gate of the MOSFET in response to a logic circuit output.

11. A half-bridge circuit, the half-bridge circuit comprising: A first common-source cascode switching system forms the high-side switch of the half-bridge circuit; and The second common-source cascode switching system forms the low-side switch of the half-bridge circuit; and Each of the first common-source cascode switching system and the second common-source cascode switching system includes a common-source cascode switch and a driving circuit. The common-source common-gate switch includes: JFET, the JFET being coupled between the drain terminal of the cascode switch and the cascode node; and MOSFET, the MOSFET being coupled between the common-source gate node and the source terminal of the common-source gate switch; The driving circuit includes: A JFET driver, configured to receive an input signal and output a JFET drive signal to a capacitor series coupled between the JFET driver and the gate of the JFET; A switch coupled between the gate and the source terminal of the JFET, the switch being configured to respond to the input signal; A comparator configured to compare a JFET gate voltage with a threshold voltage; and A MOSFET driver circuit configured to: drive the MOSFET to a MOSFET ON state during the ON state of the input signal; and drive the MOSFET to either a MOSFET OFF state or a MOSFET ON state in response to a comparison signal from the comparator during the OFF state of the input signal.

12. The half-bridge circuit of claim 11, wherein the MOSFET driver circuit is configured to drive the MOSFET in the MOSFET on state during the off state of the input signal, in response to a comparison signal from the comparator indicating that the JFET gate voltage is sufficient to drive the JFET in the JFET off state.

13. The half-bridge circuit of claim 11, wherein the MOSFET driver circuit is configured to drive the MOSFET in the MOSFET off state during the off state of the input signal in response to a comparison signal from the comparator indicating that the JFET gate voltage is insufficient to drive the JFET in the JFET off state.

14. A method for operating a common-source cascode switching system, the method comprising: Receive the conduction command; In response to the turn-on command, the JFET is driven into the JFET on state; In response to the turn-on command, the MOSFET is driven into the MOSFET on state; In response to the turn-on command, the capacitor series coupled to the gate of the JFET is charged; Receive shutdown command; The JFET is driven with the voltage stored across the capacitor in response to the shutdown command; The JFET gate voltage is compared with a threshold to generate a comparison signal; as well as The MOSFET is driven in response to the comparison signal.

15. The method of claim 14, wherein driving the MOSFET in response to the comparison signal comprises: In response to the comparison signal indicating that the JFET gate voltage is sufficient to drive the JFET to the JFET off state, the MOSFET is driven to the MOSFET on state.

16. The method of claim 14, wherein driving the MOSFET in response to the comparison signal comprises: In response to the comparison signal indicating that the JFET gate voltage is insufficient to drive the JFET into the JFET off state, the MOSFET is driven into the MOSFET off state.

17. The method of claim 14, wherein the capacitance of the capacitor is at least 10 times the gate capacitance of the JFET.

18. The method of claim 14, wherein the capacitance of the capacitor is at least 10 nF.

19. The method of claim 14, wherein: The JFET is a silicon carbide JFET; and The MOSFET is a silicon MOSFET.

20. The method of claim 14, wherein the JFET and the MOSFET are co-packaged in a multi-die integrated circuit package.

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