Metal oxide semiconductor field effect transistor and manufacturing method therefor

Abstract

The present application relates to a metal oxide semiconductor field effect transistor and a manufacturing method therefor. The metal oxide semiconductor field effect transistor comprises: a source region (142) having a first conductivity type; a drift region (130) having the first conductivity type; a first well region (120) having the first conductivity type, and located below the drift region (130) and connected to the drift region (130); a drain trench structure extending downward from the drift region (130) into the first well region (120), the drain trench structure comprising an insulating dielectric layer (145) located on a sidewall of a first trench, and a conductive material (146) located in the first trench and laterally surrounded by the insulating dielectric layer (145), and at least a portion of the drift region (130) being located between the source region (142) and the drain trench structure; and a gate (152) located on the drift region (130).

Description

Metal-oxide-semiconductor field-effect transistor and its manufacturing method

[0001] Related applications

[0002] This application claims priority to Chinese patent application filed on December 27, 2024, with application number 202411959720.0 and entitled "Metal-Oxide-Semiconductor Field-Effect Transistor and Method for Manufacturing the Same Thereof", the entire contents of which are incorporated herein by reference. Technical Field

[0003] This application relates to the field of semiconductor device technology, and in particular to a metal-oxide-semiconductor field-effect transistor (MOSFET), and also to a method for manufacturing a MOSFET. Background Technology

[0004] The statements herein are provided only as background information in connection with this application and do not necessarily constitute prior art.

[0005] Currently, the high-current, low-loss power devices used in the BCD (Bipolar-CMOS-DMOS) process platform occupy excessively large chip areas. One exemplary approach is to reduce the specific on-resistance of the device by increasing the drift region concentration. However, under the guidance of the RESURF (Reducing Surface Electric Field) concept, regardless of the drift region concentration, the drift region length is always limited to a withstand voltage (BV) of 10-30V per micrometer. Summary of the Invention

[0006] Therefore, it is necessary to provide a metal-oxide-semiconductor field-effect transistor that can achieve high withstand voltage with a shorter drift region length and a method for manufacturing the same.

[0007] A metal-oxide-semiconductor field-effect transistor (MOSFET) includes: a source region having a first conductivity type; a drift region having a first conductivity type; a first well region having a first conductivity type, located below the drift region and connected to the drift region; a drain trench structure extending downward from the drift region into the first well region, the drain trench structure including an insulating dielectric layer located on the sidewalls of the first trench, and a conductive material located in the first trench and surrounded laterally by the insulating dielectric layer; the drift region being at least partially located between the source region and the drain trench structure; and a gate located on the drift region.

[0008] In one embodiment, the metal-oxide-semiconductor field-effect transistor further includes a drain lead-out region located in the first well region and at the bottom of the drain trench structure, the drain lead-out region being in direct contact with the conductive material, the drain lead-out region having a first conductivity type and a doping concentration greater than that of the first well region.

[0009] In one embodiment, the metal-oxide-semiconductor field-effect transistor further includes a second well region having a second conductivity type, and the source region is located in the second well region; the second conductivity type is the opposite of the first conductivity type.

[0010] In one embodiment, the metal-oxide-semiconductor field-effect transistor further includes a second conductivity type region, in which the first well region is located; the first well region includes a first deep well and a second deep well located below and connected to the first deep well, wherein the length of the second deep well in the conductive channel length direction is less than the length of the first deep well in the conductive channel length direction.

[0011] In one embodiment, the metal-oxide-semiconductor field-effect transistor further includes an isolation trench structure located on the side of the second well region away from the gate, the isolation trench structure including insulating material located in the second trench.

[0012] In one embodiment, the metal-oxide-semiconductor field-effect transistor further includes a first buried layer that extends laterally from below the first well region to the isolation trench structure, the first buried layer having a first conductivity type.

[0013] In one embodiment, the metal-oxide-semiconductor field-effect transistor is an N-channel LDMOSFET, the first conductivity type is N-type, and the second conductivity type is P-type.

[0014] In one embodiment, the metal-oxide-semiconductor field-effect transistor further includes a second buried layer located in the first buried layer, the second buried layer extending laterally from below the isolation trench structure to below the first well region, and the second buried layer being in direct contact with the isolation trench structure, the second buried layer having a first conductivity type and a doping concentration greater than that of the first buried layer; the first well region being in direct contact with the first buried layer.

[0015] A method for manufacturing a metal-oxide-semiconductor field-effect transistor (MOSFET) includes: forming a first well region having a first conductivity type; forming a drift region connected to the first well region on the first well region, the drift region having a first conductivity type; forming a drain trench structure extending downward from the drift region into the first well region; the drain trench structure including an insulating dielectric layer located on the sidewalls of the first trench, and a conductive material located in the first trench and surrounded laterally by the insulating dielectric layer; forming a gate and a source region; the gate being formed on the drift region, and the source region having a first conductivity type.

[0016] In one embodiment, prior to the step of forming the first well region, the method further includes forming a first buried layer and a second buried layer in the substrate, the first buried layer and the second buried layer having a first conductivity type, and the doping concentration of the second buried layer being greater than that of the first buried layer; the step of forming the first well region includes: forming a first epitaxial layer on the substrate; forming the first well region in the first epitaxial layer; the step of forming a drift region connected to the first well region on the first well region includes: forming a second epitaxial layer on the first epitaxial layer; forming the drift region in the second epitaxial layer.

[0017] In one embodiment, the first well region includes a first deep well and a second deep well of a first conductivity type. The step of forming the first well region includes: forming a second deep well and a drain lead-out region located in the second deep well in a substrate, the drain lead-out region having a first conductivity type and a doping concentration greater than that of the first well region; in the step of forming a drain trench structure extending downward from the drift region into the first well region, the formed conductive material is in direct contact with the drain lead-out region; forming a first epitaxial layer on the substrate; forming a first deep well connected to the second deep well in the first epitaxial layer; the step of forming a drift region connected to the first well region on the first well region includes: forming a second epitaxial layer on the first epitaxial layer; forming the drift region in the second epitaxial layer.

[0018] Details of one or more embodiments of this application are set forth in the following drawings and description. Other features, objects, and advantages of this application will become apparent from the specification, drawings, and claims. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the disclosed drawings without creative effort.

[0020] Figure 1 is a schematic diagram of an exemplary LDMOS device.

[0021] Figure 2 is a schematic diagram of the LDMOS structure in one embodiment of the voltage-resistant structure of this application applied to a high-voltage LDMOS.

[0022] Figure 3 is a schematic diagram of the LDMOS structure in one embodiment of the voltage withstand structure of this application applied to a fully isolated low-voltage LDMOS.

[0023] Figure 4 is a schematic diagram of the LDMOS structure in another embodiment of the voltage withstand structure of this application applied to a fully isolated low-voltage LDMOS.

[0024] Figure 5 is a microscope photograph of the drain trench structure in one embodiment of this application.

[0025] Figure 6 is a flowchart of a method for manufacturing a metal-oxide-semiconductor field-effect transistor according to an embodiment of this application. Detailed Implementation

[0026] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Preferred embodiments of the invention are shown in the drawings. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0027] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the specification of this invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0028] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this invention, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion.

[0029] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0030] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0031] Embodiments of the invention are described herein with reference to cross-sectional views that serve as schematic diagrams of ideal embodiments (and intermediate structures). Thus, variations in the shape shown can be anticipated due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing processes. For example, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, the buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes are not intended to show the actual shapes of the regions of the device and are not intended to limit the scope of the invention.

[0032] The semiconductor terminology used in this article is the technical terminology commonly used by those skilled in the art. For example, for P-type and N-type impurities, in order to distinguish the doping concentration, P+ type represents heavily doped P-type, P type represents moderately doped P-type, P- type represents lightly doped P-type, N+ type represents heavily doped N-type, N type represents moderately doped N-type, and N- type represents lightly doped N-type.

[0033] The breakdown voltage (BV) of LDMOS (Laterally Diffused Metal-Oxide-Semiconductor Field-Effect Transistor) is mainly limited by two directions: the lateral surface and the longitudinal breakdown. In an exemplary high-voltage LDMOS device, the longitudinal breakdown can be achieved by the N-type drift region of a certain depth and the substrate, while the lateral surface electric field generally needs to be extended by lengthening the drift region as the breakdown voltage increases, as shown in Figure 1.

[0034] This application provides a metal-oxide-semiconductor field-effect transistor that converts lateral withstand voltage to longitudinal withstand voltage. Most of the voltage is borne by the insulating dielectric layer on the deep trench sidewall of the drain, thereby greatly reducing the drift region area without affecting the device's voltage withstand voltage (BV). Simulation verification shows that the drift region withstand voltage of this device can reach more than 300V per micrometer.

[0035] Figure 2 is a schematic diagram of the LDMOS structure in one embodiment of the voltage withstand structure of this application applied to a high voltage LDMOS, and Figure 3 is a schematic diagram of the LDMOS structure in one embodiment of the voltage withstand structure of this application applied to a fully isolated low voltage LDMOS. The structures shown in Figures 2 and 3 are symmetrical from left to right, so some structures are only labeled on one side.

[0036] The LDMOS shown in Figures 2 and 3 both include a source region 142, a drift region 130, a first well region 120, a gate 152, and a drain trench structure. The source region 142, drift region 130, and first well region 120 have a first conductivity type. The first well region 120 is located below and connected to the drift region 130. The drain trench structure extends downward from the drift region 130 into the first well region 120. The drain trench structure includes an insulating dielectric layer 145 located on the sidewalls of the first trench, and a conductive material 146 located in the first trench and laterally surrounded by the insulating dielectric layer 145. The drift region 130 is at least partially located between the source region 142 and the drain trench structure. The gate 152 is located on the drift region 130, above the region between the source region 142 and the drain trench structure. The devices shown in Figures 2 and 3 are N-channel LDMOSFETs, with the first conductivity type being N-type and the second conductivity type being P-type. In other embodiments, the devices may also be P-channel LDMOSFETs, with the first conductivity type being P-type and the second conductivity type being N-type.

[0037] When a high voltage is applied to the drain of the aforementioned metal-oxide-semiconductor field-effect transistor, the device bears most of the high voltage through the insulating dielectric layer 145 of the drain trench structure. Therefore, the voltage borne by the part of the drift region 130 near the device surface is relatively small, and a high withstand voltage can be obtained without setting the drift region 130 to be long.

[0038] In one embodiment of this application, the metal-oxide-semiconductor field-effect transistor further includes a drain lead-out region 144 located in the first well region 120 and near the bottom of the drain trench structure. The drain lead-out region 144 is in direct contact with the conductive material 146 in the drain trench structure, and further, the drain lead-out region 144 and the conductive material 146 form an ohmic contact. The drain lead-out region 144 has a first conductivity type and a doping concentration greater than that of the first well region 120.

[0039] In one embodiment of this application, the metal-oxide-semiconductor field-effect transistor (MOSFET) further includes a second well region 132. The second well region 132 has a second conductivity type, and a source region 142 is located within the second well region 132. In one embodiment of this application, the MOSFET further includes a body lead-out region 143 located within the second well region 132, and the body lead-out region 143 has a second conductivity type. In one embodiment of this application, the MOSFET further includes an LDD region 141 located within the second well region 132. The LDD region 141 is connected to the source region 142 and is located on the side of the source region 142 closest to the gate 152. The LDD region 141 has a first conductivity type, and its doping concentration is lower than that of the source region 142. In one embodiment of this application, the MOSFET further includes sidewalls 151 located on both sides of the gate 152.

[0040] In one embodiment of this application, the metal-oxide-semiconductor field-effect transistor further includes an isolation trench structure 125. The isolation trench structure 125 is located on the side of the second well region 132 away from the gate 152, and includes insulating material located within the second trench. In the embodiment shown in FIG2, the second trench and the first trench are formed in the same process step, and the isolation trench structure 125 has the same depth as the drain trench structure.

[0041] In one embodiment of this application, the metal-oxide-semiconductor field-effect transistor further includes a second conductivity type region 110. A first well region 120 is located in the second conductivity type region 110.

[0042] Referring to Figure 2, in the embodiment of high-voltage LDMOS, the first well region 120 includes a first deep well 122 and a second deep well 124 located below and connected to the first deep well 122. The length of the second deep well 124 in the conductive channel length direction is less than the length of the first deep well 122 in the conductive channel length direction, which is the X-axis direction in Figures 2 and 3. The drain trench structure needs to be deep enough to achieve high longitudinal breakdown voltage, therefore the first well region 120 needs to have sufficient junction depth. On the other hand, the second conductivity type region 110 below the drift region 130 needs to be large enough to assist in the depletion of the drift region 130. Therefore, the first well region 120 is configured to include the first deep well 122 and the second deep well 124. The second deep well 124 is smaller in size, which allows the second conductivity type region 110 to be larger, ensuring both the high longitudinal breakdown voltage requirement of the drain and the auxiliary depletion effect on the drift region 130. For a process platform with a critical dimension (CD) of 0.18 micrometers, the drift region length of the high-voltage LDMOS device shown in Figure 2 can be reduced to less than 2 micrometers.

[0043] Referring to Figure 3, in the fully isolated low-voltage LDMOS embodiment, the metal-oxide-semiconductor field-effect transistor further includes a first buried layer 112. The first buried layer 112 extends laterally from below the first well region 120 to the isolation trench structure 125, and has a first conductivity type. The first buried layer 112 forms a PN junction with the second conductivity type region 110, providing electrical isolation, and together with the isolation trench structure 125, forms a cylindrical electrical isolation structure serving as the bottom of the "cylinder". In the embodiment shown in Figure 3, the top of the first buried layer 112 is in direct contact with the first well region 120; in other embodiments, the first buried layer 112 and the first well region 120 may also be separated by the second conductivity type region 110, as shown in Figure 4.

[0044] In the embodiment shown in Figure 3, the metal-oxide-semiconductor field-effect transistor further includes a second buried layer 114 located within the first buried layer 112. The second buried layer 114 extends laterally from below the isolation trench structure to below the first well region 120, and is in direct contact with the isolation trench structure. The second buried layer 114 has a first conductivity type and a doping concentration greater than that of the first buried layer 112. A higher concentration of the second buried layer 114 provides better electrical isolation. The LDMOS shown in Figure 3 can realize devices with a breakdown voltage of 40-120V. Because of the lower breakdown voltage, the drain trench structure of the fully isolated low-voltage LDMOS does not require a very deep depth; the depth of the drain trench structure is shallower than that of the isolation trench structure 125. Figure 5 is a microscopic photograph of the drain trench structure and its surroundings in one embodiment of this application.

[0045] In the embodiments shown in Figures 2 and 3, the first well region 120, drift region 130, and LDD region 141 are N-type regions, the first buried layer 112 in Figure 3 is also an N-type region, the source region 142 and drain lead-out region 144 are N+ regions, the second buried layer 114 in Figure 3 is also an N+ region, the second conductivity type region 110 and the second well region 132 are P-type regions, the body lead-out region 143 is a P+ region, and the conductive material 146 is a tungsten plug.

[0046] This application provides a method for manufacturing a metal-oxide-semiconductor field-effect transistor (MOSFET), which can be used to manufacture the MOSFET described in any of the foregoing embodiments. Figure 6 is a flowchart of a method for manufacturing a MOSFET according to an embodiment of this application, including the following steps:

[0047] S610 forms the first well region.

[0048] The first well region 120 has a first conductivity type.

[0049] For an embodiment of forming a fully isolated low-voltage LDMOS, step S610 involves forming a first epitaxial layer on the substrate, followed by forming a first well region 120 within the first epitaxial layer. Specifically, the first well region 120 and drain lead-out region 144 can be formed in the first epitaxial layer by photolithography and ion implantation, followed by well push-in. In one embodiment of this application, before step S610, a step of forming a first buried layer 112 in the substrate is included. In another embodiment of this application, before step S610, a step of forming a second buried layer 114 in the substrate is included. The first buried layer 112 and the second buried layer 114 have a first conductivity type, and the doping concentration of the second buried layer 114 is greater than that of the first buried layer 112. Both the first buried layer 112 and the second buried layer 114 can be formed by ion implantation.

[0050] In an embodiment for forming a high-voltage LDMOS, step S610 involves forming a second deep well 124 and a drain lead-out region 144 located in the second deep well 124 in the substrate, and then forming a first epitaxial layer on the substrate, in which a first deep well 122 connected to the second deep well 124 is formed. The first well region 120 consists of the first deep well 122 and the second deep well 124 of a first conductivity type, and the second deep well 124 and the first deep well 122 can be formed by ion implantation.

[0051] S620, a drift region connected to the first well region is formed on the first well region.

[0052] In one embodiment of this application, step S620 includes forming a second epitaxial layer on the first epitaxial layer, and then forming a drift region 130 in the second epitaxial layer.

[0053] S630 forms a drain trench structure that extends downward from the drift region into the first well region.

[0054] The drain trench structure includes an insulating dielectric layer 145 located on the sidewall of a first trench, and a conductive material 146 formed in the first trench in a subsequent step, which is laterally surrounded by the insulating dielectric layer 145. The bottom of the conductive material 146 is in direct contact with the drain lead-out region 144. In one embodiment of this application, step S630 further includes forming a second trench and filling the second trench with an insulating dielectric to form an isolation trench structure 125. The bottom of the isolation trench structure 125 extends into a first buried layer 112, and a second buried layer 114 is in direct contact with the isolation trench structure.

[0055] S640 forms the gate and source regions.

[0056] This includes forming a source region 142 of a first conductivity type by ion implantation, and forming a gate 152 on the drift region 130. In one embodiment of this application, step S640 further includes forming structures such as a second well region 132, a body lead-out region 143, and an LDD region 141, wherein the source region 142, the body lead-out region 143, and the LDD region 141 are formed in the second well region 132. The second well region 132 and the body lead-out region 143 have a second conductivity type, and the LDD region 141 has a first conductivity type.

[0057] In the above-described method for manufacturing a metal-oxide-semiconductor field-effect transistor, when a high voltage is applied to the drain, the insulating dielectric layer 145 of the drain trench structure bears most of the high voltage. Therefore, the portion of the drift region 130 near the device surface bears a smaller voltage, and a high withstand voltage can be obtained without making the drift region 130 longer.

[0058] The manufacturing method of the metal oxide semiconductor field-effect transistor in this application is based on the same inventive concept as the metal oxide semiconductor field-effect transistor. For details not specifically described in the manufacturing method of the metal oxide semiconductor field-effect transistor, please refer to the above introduction of the metal oxide semiconductor field-effect transistor.

[0059] It should be understood that although the steps in the flowchart of this application are shown sequentially as indicated by the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowchart of this application may include multiple steps or multiple stages, which are not necessarily completed at the same time, but may be executed at different times, and the execution order of these steps or stages is not necessarily sequential, but may be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0060] In the description of this specification, references to terms such as "some embodiments," "other embodiments," and "ideal embodiments" indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0061] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0062] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A metal-oxide-semiconductor field-effect transistor, characterized in that, include: The source region has the first type of conductivity. The drift region has the first type of conductivity. A first well region, having a first conductivity type, is located below the drift region and connected to the drift region; A drain trench structure extends downward from the drift region into the first well region. The drain trench structure includes an insulating dielectric layer located on the sidewall of the first trench and a conductive material located in the first trench and surrounded from the side by the insulating dielectric layer. The drift region is at least partially located between the source region and the drain trench structure; as well as The gate is located on the drift region.

2. The metal-oxide-semiconductor field-effect transistor according to claim 1, characterized in that, It also includes a drain lead-out region located in the first well region and at the bottom of the drain trench structure, the drain lead-out region being in direct contact with the conductive material, the drain lead-out region having a first conductivity type and a doping concentration greater than that of the first well region.

3. The metal-oxide-semiconductor field-effect transistor according to claim 1, characterized in that, It also includes a second well region having a second conductivity type, and the source region is located in the second well region; the second conductivity type is the opposite of the first conductivity type.

4. The metal-oxide-semiconductor field-effect transistor according to claim 3, characterized in that, It also includes a second conductivity type region, in which the first well region is located; the first well region includes a first deep well and a second deep well located below and connected to the first deep well, wherein the length of the second deep well in the conductive channel length direction is less than the length of the first deep well in the conductive channel length direction.

5. The metal-oxide-semiconductor field-effect transistor according to claim 3, characterized in that, It also includes an isolation trench structure located on the side of the second well region away from the gate, the isolation trench structure including insulating material located in the second trench.

6. The metal-oxide-semiconductor field-effect transistor according to claim 5, characterized in that, It also includes a first buried layer that extends laterally from below the first well region to the isolation trench structure, the first buried layer having a first conductivity type.

7. The metal-oxide-semiconductor field-effect transistor according to claim 6, characterized in that, The metal-oxide-semiconductor field-effect transistor is an N-channel LDMOSFET, with the first conductivity type being N-type and the second conductivity type being P-type.

8. The metal-oxide-semiconductor field-effect transistor according to claim 6, characterized in that, The metal-oxide-semiconductor field-effect transistor further includes a second buried layer located in the first buried layer. The second buried layer extends laterally from below the isolation trench structure to below the first well region, and the second buried layer is in direct contact with the isolation trench structure. The second buried layer has a first conductivity type and a doping concentration greater than that of the first buried layer.

9. The metal-oxide-semiconductor field-effect transistor according to claim 6, characterized in that, The first trap area is in direct contact with the first buried layer.

10. The metal-oxide-semiconductor field-effect transistor according to claim 6, characterized in that, The depth of the drain trench structure is shallower than the depth of the isolation trench structure.

11. A method for manufacturing a metal-oxide-semiconductor field-effect transistor, comprising: A first well region is formed, the first well region having a first conductivity type; A drift region connected to the first well region is formed on the first well region, the drift region having a first conductivity type; A drain trench structure is formed that extends downward from the drift region into the first well region; The drain trench structure includes an insulating dielectric layer located on the sidewall of the first trench, and a conductive material located in the first trench and surrounded from the side by the insulating dielectric layer. as well as A gate and a source region are formed; the gate is formed on the drift region, and the source region has a first conductivity type.

12. The method for manufacturing a metal-oxide-semiconductor field-effect transistor according to claim 11, characterized in that, Prior to the step of forming the first well region, the method further includes the step of forming a first buried layer in the substrate, the first buried layer having a first conductivity type; After the drift region is formed and before the gate and source regions are formed, the method further includes the step of forming a second trench and filling the second trench with an insulating medium to form an isolation trench structure. The bottom of the isolation trench structure extends into the first buried layer.

13. The method for manufacturing a metal-oxide-semiconductor field-effect transistor according to claim 12, characterized in that, Before the step of forming the first well region, the method further includes the step of forming a second buried layer in the substrate; the doping concentration of the second buried layer is greater than that of the first buried layer, and the second buried layer is in direct contact with the isolation trench structure.

14. The method for manufacturing a metal-oxide-semiconductor field-effect transistor according to claim 13, characterized in that, The step of forming the first well region includes: A first epitaxial layer is formed on the substrate; and The first well region is formed in the first epitaxial layer; The step of forming a drift region connected to the first well region on the first well region includes: A second epitaxial layer is formed on the first epitaxial layer; and The drift region is formed in the second epitaxial layer.

15. The method for manufacturing a metal-oxide-semiconductor field-effect transistor according to claim 11, characterized in that, The first well region includes a first deep well and a second deep well of a first conductivity type, and the step of forming the first well region includes: A second deep well and a drain lead-out region located in the second deep well are formed in the substrate. The drain lead-out region has a first conductivity type and a doping concentration greater than that of the first well region. In the step of forming a drain trench structure extending downward from the drift region into the first well region, the formed conductive material is in direct contact with the drain lead-out region. A first epitaxial layer is formed on the substrate; and A first deep well connected to the second deep well is formed in the first epitaxial layer; The step of forming a drift region connected to the first well region on the first well region includes: A second epitaxial layer is formed on the first epitaxial layer; and The drift region is formed in the second epitaxial layer.

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