Display panel, manufacturing method of display panel and display device
Through patterning of the conductive layer and active layer and the use of composite etching liquid, the problems of metal copper diffusion and etching time are solved, the process accuracy and transistor performance of the display panel are improved, and the border area width is reduced.
Patent Information
- Application Number
- CN202510507821.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-21
- Publication Date
- 2025-08-01
AI Technical Summary
In large-size display panels, metal copper has low resistance and low cost, but it is easy to diffuse into the active layer during high-temperature processes to form defects, resulting in deterioration of the electrical performance of the device. At the same time, the etching time is long, which cannot meet the process refinement requirements.
By simultaneously patterning the conductive layer and the active layer, the edges of the conductive layer are retracted compared to the ipsilateral edges of the active layer, and etched in combination with a composite etching liquid to avoid drilling the conductive layer from the bottom of the active layer, ensuring that the edge retracting width of the conductive layer is within 1 micron to 1.3 microns.
It improves the missing key sizes, improves the process accuracy of the display panel, enhances the transistor's mobility and current driving capabilities, reduces the frame area width, and improves the screen-to-body ratio.
Smart Images
Figure CN120417486A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of display technologies, and particularly to a display panel, a manufacturing method thereof, and a display device. Background Art
[0002] Large size, high frame rate processing, and high transmittance in the visible light range have significant advantages and broad application prospects in fields such as active matrix liquid crystal displays and active matrix organic light-emitting diodes. As the size of the display panel increases, it is necessary to reduce the capacitance-resistance delay effect of the metal traces. Metal copper is widely used because of its low resistance and low cost. However, copper ions are likely to diffuse into the active layer during subsequent high-temperature processes, forming defects and deteriorating the electrical performance of the device. To prevent the influence of copper ion diffusion on the device performance, molybdenum, titanium, or molybdenum-titanium alloy is generally used as the barrier layer material in the industry to avoid the influence of copper ion diffusion.
[0003] However, in the actual manufacturing process, since the etching rate of the etching solution for molybdenum, titanium, or molybdenum-titanium alloy is relatively slow, the etching time is long, the CD Loss is large, and the critical dimension of the metal layer is missing significantly, which cannot meet the refined requirements of the display panel for the manufacturing process.
[0004] Therefore, it is necessary to provide a display panel, a manufacturing method thereof, and a display device to improve this defect. Summary of the Invention
[0005] Embodiments of the present application provide a display panel, a manufacturing method thereof, and a display device, which can solve the problem of missing critical dimensions.
[0006] To achieve the above object, according to the first aspect of the present application, a display panel is provided, including:
[0007] A substrate;
[0008] An active layer disposed on one side of the substrate;
[0009] A conductive layer disposed on the side of the active layer away from the substrate;
[0010] Wherein, the edge of the conductive layer is indented inward compared with the edge of the active layer, and the inward indentation width of the edge of the conductive layer compared with the same-side edge of the active layer is greater than or equal to 1 micron and less than or equal to 1.3 microns.
[0011] Optionally, the conductive layer includes a first sub-conductive layer and a second sub-conductive layer, and the second sub-conductive layer is disposed on the surface of the first sub-conductive layer away from the active layer;
[0012] Wherein, the ratio of the thickness of the first sub-conductive layer to the thickness of the second sub-conductive layer is greater than or equal to 0.015 and less than or equal to 0.072.
[0013] Optionally, the side edge of the first sub-conductive layer is continuously arranged with the side of the second sub-conductive layer.
[0014] Optionally, the angle between the side and the bottom surface of the first sub-conductive layer is a first angle, the angle between the side and the bottom surface of the second sub-conductive layer is a second angle, and the first angle is the same as the second angle.
[0015] Optionally, the first angle is greater than or equal to 40 degrees and less than or equal to 70 degrees.
[0016] Optionally, the angle between the side and the bottom surface of the active layer is a third angle, and the third angle is less than the first angle.
[0017] Optionally, the third angle is greater than or equal to 30 degrees and less than or equal to 50 degrees.
[0018] Optionally, the orthographic projection of the conductive layer on the active layer is located within the active layer.
[0019] Optionally, the conductive layer includes a source electrode and a drain electrode, the active layer includes a first active portion, and the source electrode and the drain electrode are spaced apart on the surface of the first active portion away from the substrate;
[0020] Wherein, along the channel length direction of the first active portion, the distance between the source electrode and the drain electrode is greater than or equal to 3 micrometers and less than or equal to 3.5 micrometers.
[0021] Optionally, the display panel includes a display area and a border area arranged around the display area, the conductive layer includes a plurality of fan-out traces, and the fan-out traces are arranged in the border area;
[0022] Wherein, the active layer includes a plurality of second active portions, and the orthographic projection of the fan-out traces on the active layer is located within the second active portions.
[0023] Optionally, along the line width direction of the fan-out traces, the center distance between two adjacent fan-out traces is greater than or equal to 7 micrometers and less than or equal to 8 micrometers.
[0024] Optionally, the thickness of the first sub-conductive layer is greater than or equal to 120 micrometers and less than or equal to 180 micrometers, and the thickness of the second sub-conductive layer is greater than or equal to 2500 micrometers and less than or equal to 8000 micrometers.
[0025] Optionally, the etching selectivity of the material of the first sub-conductive layer is less than the etching selectivity of the material of the second sub-conductive layer.
[0026] Optionally, the material of the first sub-conductive layer includes any one of molybdenum, molybdenum-titanium alloy, and molybdenum-niobium alloy, and the material of the second sub-conductive layer includes copper.
[0027] Optionally, the display panel further includes a gate, and the gate is disposed between the active layer and the substrate.
[0028] Optionally, the material of the active layer includes an oxide semiconductor material.
[0029] According to a second aspect of the present application, there is provided a method for manufacturing a display panel, and the method for manufacturing the display panel includes:
[0030] Forming a semiconductor material layer on one side of a substrate;
[0031] Forming a conductive material layer on a side of the semiconductor material layer away from the substrate;
[0032] Forming a photoresist layer on the conductive material layer;
[0033] Performing a first exposure and development process on the photoresist layer using a photomask to form a first photoresist pattern;
[0034] Performing a first etching on the conductive material layer and the semiconductor material layer simultaneously to form a conductive portion and an active layer, and sides of the conductive portion are continuous with sides of the active layer;
[0035] Performing a second exposure and development process on the first photoresist pattern using the photomask to form a second photoresist pattern;
[0036] Performing a second etching on the conductive portion to form a conductive layer;
[0037] Wherein, an inward shrinkage width of an edge of the conductive layer compared with a same-side edge of the corresponding active layer is greater than or equal to 1 micrometer and less than or equal to 1.3 micrometers.
[0038] Optionally, the conductive layer includes a first sub-conductive layer and a second sub-conductive layer, and the second sub-conductive layer is disposed on a surface of the first sub-conductive layer away from the active layer;
[0039] Wherein, a ratio of a thickness of the first sub-conductive layer to a thickness of the second sub-conductive layer is greater than or equal to 0.015 and less than or equal to 0.072.
[0040] Optionally, the step of simultaneously performing the first etching on the conductive material layer and the semiconductor material layer using the first photoresist pattern includes:
[0041] Etching the conductive material layer and the semiconductor material layer using a composite etching solution;
[0042] Among them, the materials of the composite etching solution include hydrofluoric acid, hydrogen peroxide, sulfuric acid, and nitric acid.
[0043] According to the third aspect of the present application, a display device is provided, including the display panel as described above.
[0044] In the display panel of the embodiment of the present application, by simultaneously performing patterning on the conductive layer and the active layer, the side surfaces of the conductive layer after patterning are made continuous with the side surfaces of the active layer, so as to avoid the etching solution drilling into the conductive layer from the bottom of the active layer during the second patterning process. In this way, the inward shrinkage width of the edge of the conductive layer compared to the same-side edge of the active layer can be reduced to 1 to 1.3 micrometers, thereby improving the situation of critical dimension missing.
[0045] Other features and advantages of the present application will be described in detail in the subsequent specific implementation section. BRIEF DESCRIPTION OF THE DRAWINGS
[0046] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative efforts.
[0047] In order to more comprehensively understand the present application and its beneficial effects, the following will be described in conjunction with the drawings, where the same reference numerals represent the same parts in the following description.
[0048] Figure 1 It is a top view of the display panel provided by the embodiment of the present application;
[0049] Figure 2 It is a cross-sectional view of the display panel provided by the embodiment of the present application along the Figure 1 indicated A-A' direction;
[0050] Figure 3 It is a cross-sectional view of the display panel provided by the embodiment of the present application along the Figure 1 indicated B-B' direction;
[0051] Figure 4 It is a schematic structural diagram of another display panel provided by the embodiment of the present application;
[0052] Figure 5 It is a flowchart of the manufacturing method of the display panel provided by the embodiment of the present application;
[0053] Figures 6a to 6e It is a schematic diagram of the manufacturing method of the display panel provided by the embodiment of the present application;
[0054] Figure 7 Schematic diagram of the display device provided for the embodiment of the present application. Specific embodiments
[0055] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present application without creative efforts shall fall within the protection scope of the present application.
[0056] The embodiment of the present application provides a display panel, which includes a substrate, an active layer, and a conductive layer. The active layer is disposed on one side of the substrate, and the conductive layer is disposed on the side of the active layer away from the substrate. The edge of the conductive layer is indented inward compared to the edge of the active layer, and the indentation width of the edge of the conductive layer compared to the same-side edge of the active layer is greater than or equal to 1 micron and less than or equal to 1.3 microns.
[0057] In the embodiment of the present application, by simultaneously patterning the conductive layer and the active layer, the side surface of the patterned conductive layer is made continuous with the side surface of the active layer, avoiding the etching solution from drilling and etching the conductive layer from the bottom of the active layer during the second patterning process, so that the indentation width of the edge of the conductive layer compared to the same-side edge of the active layer can be reduced to 1 micron to 1.3 microns, thereby improving the situation of critical dimension missing.
[0058] Please refer to Figure 1 and Figure 2 , Figure 1 Top view of the display panel provided for the embodiment of the present application, Figure 2 Cross-sectional view of the display panel provided for the embodiment of the present application along the Figure 1 A-A' direction shown. The display panel includes a display area AA and a border area BA disposed outside the display area AA. The display panel 100 includes a substrate 1, an active layer 2, and a conductive layer 3. The active layer 2 is disposed on one side of the substrate 1, and the conductive layer 3 is disposed on the side of the active layer 2 away from the substrate 1.
[0059] Please refer to Figure 2 , the conductive layer 3 is a double-layer conductive structure. The conductive layer 3 includes a first sub-conductive layer 31 and a second sub-conductive layer 32. The first sub-conductive layer 31 is disposed on the surface of the active layer 2 away from the substrate 1, and the second sub-conductive layer 32 is disposed on the surface of the first sub-conductive layer 31 away from the active layer 2.
[0060] Please refer to Figure 2, the edge of the conductive layer 3 is set to be indented inward compared to the edge of the active layer 2, and the inward indentation width d1 of the edge of the conductive layer 3 compared to the same-side edge of the active layer 2 is greater than or equal to 1 micron and less than or equal to 1.3 microns.
[0061] In the embodiments of the present application, by performing the first patterning process on the active layer 2 and the conductive layer 3 simultaneously, and then performing the second patterning process on the conductive layer 3 alone. After the first patterning process is performed on the source layer 2 and the conductive layer 3 simultaneously, the side surfaces of the active layer 2 and the conductive layer 3 are continuous. In this way, it can be avoided that during the second patterning process, the etching solution drills through the conductive layer 3 from the bottom of the active layer 2, so that the situation of critical dimension missing can be improved, and the inward indentation width of the edge of the conductive layer 3 compared to the same-side edge of the active layer 2 can be reduced from 1.4 to 1.7 microns to 1 to 1.3 microns, thereby improving the manufacturing precision of the display panel.
[0062] In some embodiments, the ratio of the thickness of the first sub-conductive layer 31 to the thickness of the second sub-conductive layer 32 is greater than or equal to 0.015 and less than or equal to 0.072.
[0063] It should be noted that since the etching selectivity of the material of the first sub-conductive layer 31 is less than that of the material of the second sub-conductive layer 32, if the ratio of the thickness of the first sub-conductive layer 31 to the thickness of the second sub-conductive layer 32 is too small, it means that the thickness of the first sub-conductive layer 31 is small, and the first sub-conductive layer 31 cannot provide good adhesion for the second sub-conductive layer 32, and the second sub-conductive layer 32 is prone to the problem of film layer separation, and there is also the problem of poor effect of blocking copper diffusion. If the ratio of the thickness of the first sub-conductive layer 31 to the thickness of the second sub-conductive layer 32 is too large, it means that the thickness of the first sub-conductive layer 31 is too large, which will make the etching time of the first sub-conductive layer 31 longer, resulting in a smaller improvement in critical dimension missing.
[0064] In this embodiment, by reducing the thickness of the first sub-conductive layer 31 in the conductive layer 3, the ratio of the thickness of the first sub-conductive layer 31 to the thickness of the second sub-conductive layer 32 is greater than or equal to 0.015 and less than or equal to 0.072, so that the etching time of the first sub-conductive layer 31 can be reduced, and thus the situation of critical dimension missing of the active layer 2 and the conductive layer 3 can be improved.
[0065] In some embodiments, the material of the first sub-conductive layer 31 includes any one of molybdenum, molybdenum-titanium alloy, and molybdenum-niobium alloy, and the material of the second sub-conductive layer 32 includes copper.
[0066] In some embodiments, please refer to Figure 1, the thickness of the first sub-conductive layer 31 is greater than or equal to 120 microns and less than or equal to 180 microns, and the thickness of the second sub-conductive layer 32 is greater than or equal to 2500 microns and less than or equal to 8000 microns. For example, the thickness of the first sub-conductive layer 31 can be 120 microns, 140 microns, 160 microns, or 180 microns, etc., and the thickness of the second sub-conductive layer 32 can be 2500 microns, 3000 microns, 5000 microns, 7000 microns, or 8000 microns, etc.
[0067] It should be noted that the etching selectivity of the material of the first sub-conductive layer 31 is less than that of the material of the second sub-conductive layer 32. If the thickness of the first sub-conductive layer 31 is too large, the etching time of the first sub-conductive layer 31 is longer, resulting in a smaller improvement in the critical dimension loss; if the thickness of the first sub-conductive layer 31 is too small, the first sub-conductive layer 31 cannot provide good adhesion for the second sub-conductive layer 32, and the second sub-conductive layer 32 is prone to film separation problems, and the effect of blocking copper diffusion is also poor. By limiting the thickness of the first sub-conductive layer 31 between 120 microns and 180 microns, and limiting the thickness of the second sub-conductive layer 32 between 2500 microns and 8000 microns, not only can the film separation problem of the second sub-conductive layer 32 be prevented, and the copper in the second sub-conductive layer 32 can be blocked from diffusing to the active layer 2, but also the critical dimension loss of the active layer 2 and the conductive layer 3 can be improved.
[0068] In some embodiments, the side surface of the first sub-conductive layer 31 is continuously arranged with the side surface of the second sub-conductive layer 32.
[0069] Please refer to Figure 2 , taking the plane where the first sub-conductive layer 31 is located as the horizontal plane, the side surface of the first sub-conductive layer 31 is inclined with respect to the bottom surface of the first sub-conductive layer 31, and the side surface of the second sub-conductive layer 32 is inclined with respect to the bottom surface of the second sub-conductive layer 32. The continuous arrangement of the side surface of the first sub-conductive layer 31 and the side surface of the second sub-conductive layer 32 means that the side surface of the first sub-conductive layer 31 and the side surface of the second sub-conductive layer 32 are connected and on the same inclined plane. In this way, steps can be avoided at the connection of the side surfaces of the first sub-conductive layer 31 and the second sub-conductive layer 32, the flatness of the film layer subsequently deposited on the conductive layer 3 can be improved, and the situation that the subsequently deposited film layer generates cracks at the side surfaces of the first sub-conductive layer 31 and the second sub-conductive layer 32 and causes display abnormalities can be avoided.
[0070] In some embodiments, please refer to Figure 2 , the included angle between the side surface and the bottom surface of the first sub-conductive layer 31 is the first included angle a1, the included angle between the side surface and the bottom surface of the second sub-conductive layer 32 is the second included angle a2, and the first included angle a1 is the same as the second included angle a2.
[0071] In some embodiments, the first included angle a1 is greater than or equal to 40 degrees and less than or equal to 70 degrees. For example, the first included angle a1 is 40 degrees, 45 degrees, 50 degrees, 55 degrees, 60 degrees, 65 degrees, or 70 degrees, etc.
[0072] In some embodiments, referring to Figure 1 , the included angle between the side surface and the bottom surface of the active layer 2 is the third included angle, and the third included angle a3 is less than the first included angle a1.
[0073] It should be noted that the conductive layer 3 needs to be etched twice. The first time is to perform patterning simultaneously with the active layer 2. During the second etching, the etching solution will etch the conductive layer 3 again, increasing the degree of etching of the conductive layer 3, and the included angle between the side surface and the bottom surface of the conductive layer 3 also increases accordingly.
[0074] In some embodiments, referring to Figure 2 , the third included angle is greater than or equal to 30 degrees and less than or equal to 50 degrees. For example, the third included angle can be 30 degrees, 35 degrees, 40 degrees, 45 degrees, or 50 degrees, etc. In this way, the slope angle of the active layer 2 can be made smaller, and the smaller slope angle has lower requirements for the manufacturing precision of the display panel, so that the manufacturing yield of the active layer 2 can be ensured to be relatively high.
[0075] In some embodiments, referring to Figure 2 , the orthographic projection of the conductive layer 3 on the active layer 2 is located within the active layer 2.
[0076] It should be noted that in the actual manufacturing process, the active layer 2 is patterned together with the conductive layer 3 after the formation of the conductive layer 3. Using the mask of the conductive layer 3 to pattern the active layer 2 can save one mask. After the etching of the active layer 2 is completed, the conductive layer 3 needs to be patterned for the second time. The area of the conductive layer 3 should be smaller than the area of the active layer 2, and the orthographic projection of the conductive layer 3 on the active layer 2 is located within the active layer 2.
[0077] In some embodiments, referring to Figure 2 , the conductive layer 3 includes a patterned source electrode 301 and a drain electrode 302. Both the source electrode 301 and the drain electrode 302 are double-layer conductive structures formed by laminating a first sub-conductive layer 31 and a second sub-conductive layer 32. The active layer 2 includes a patterned first active portion 21. The source electrode 301 and the drain electrode 302 are arranged at intervals on the surface of the first active portion 21 away from the substrate 1.
[0078] Referring to Figure 2, the first active portion 21, the source electrode 301, and the drain electrode 302 are all part of a transistor. The first active portion 21 includes a channel portion, and the channel portion is located between the source electrode 301 and the drain electrode 302. Along the channel length direction of the first active portion 21, the distance d2 between the source electrode 301 and the drain electrode 302 is greater than or equal to 3 microns and less than or equal to 3.5 microns. The distance d2 between the source electrode 301 and the drain electrode 302 is the channel length of the channel portion of the first active portion 21.
[0079] In this embodiment, by simultaneously patterning the conductive layer and the active layer, the side surface of the patterned conductive layer is made continuous with the side surface of the active portion, avoiding the etching solution from drilling the conductive layer from the bottom of the active layer during the second patterning process, thereby improving the situation of missing critical dimensions. The width of the source electrode 301 and the drain electrode 302 can be increased, and thus the distance d2 between the source electrode 301 and the drain electrode 302 can be reduced. In this way, the channel length of the transistor can be reduced, thereby improving the mobility of the transistor, further improving the switching speed of the transistor, and increasing the current driving ability of the transistor.
[0080] In some embodiments, please refer to Figure 1 and Figure 3 , Figure 3 is a cross-sectional view of the display panel provided by the embodiment of the present application along the Figure 1 shown B-B' direction. The conductive layer 3 includes a plurality of fan-out traces 303. The fan-out traces 303 are disposed in the border area BA. The fan-out traces 303 are connected between the bonding area and the display area AA. The active layer 2 includes a plurality of second active portions 22. The orthographic projection of the fan-out traces 303 on the active layer 2 is located within the second active portions 22.
[0081] In some embodiments, please refer to Figure 1 and Figure 3 , along the line width direction of the fan-out traces 303, the center distance d3 between two adjacent fan-out traces 303 is greater than or equal to 7 microns and less than or equal to 8 microns. For example, the center distance d3 between two adjacent fan-out traces 303 is 7 microns, 7.2 microns, 7.4 microns, 7.6 microns, 7.8 microns, or 8 microns, etc.
[0082] In this embodiment, by simultaneously patterning the conductive layer and the active layer, the side surface of the patterned conductive layer is made continuous with the side surface of the active portion, avoiding the etching solution from drilling the conductive layer from the bottom of the active layer during the second patterning process, thereby improving the situation of missing critical dimensions. The center distance between any two adjacent fan-out traces 303 in the border area BA can be reduced. In this way, the space occupied by the fan-out traces 303 can be reduced, and thus the width of the border area of the display panel can be reduced, improving the screen-to-body ratio of the display panel.
[0083] In some embodiments, please refer toFigure 4 , Figure 4 It is a schematic structural diagram of another display panel provided by an embodiment of the present application. The display panel 100 includes a gate 4, and the gate 4 is disposed between the active layer 2 and the substrate 1.
[0084] Please refer to Figure 4 . The transistor is a back-channel etching structure. The gate 4 is disposed on the side of the active layer 2 close to the substrate 1, and the conductive layer 3 is disposed on the surface of the active layer 2 away from the gate 4. The conductive layer 3 is the source-drain layer.
[0085] In some embodiments, please refer to Figure 4 . The display panel 100 is a liquid crystal display panel. The display panel 100 includes a first electrode layer 5, a gate 4, a gate insulating layer 6, an active layer 2, a conductive layer 3, a passivation layer 7, and a second electrode layer 8 that are sequentially stacked on the substrate 1.
[0086] It should be noted that Figure 4 only the relative positional relationship of the gate 4, the active layer 2, and the conductive layer 3 in the display panel is schematically shown, and it does not represent the structure of the display panel in actual application. In actual application, the display panel can also be replaced with the structure of other liquid crystal display panels to achieve the same or similar functions.
[0087] In actual application, the type of the display panel is not limited to the liquid crystal display panel in the above embodiments. The display panel can also be an organic light-emitting diode display panel, a mini light-emitting diode display panel, or a micro light-emitting diode display panel.
[0088] According to the display panel provided by the above embodiments of the present application, the embodiments of the present application also provide a method for manufacturing a display panel. Please refer to Figure 5 , Figures 6a to 6e , Figure 5 It is a flowchart of the method for manufacturing a display panel provided by an embodiment of the present application. Figures 6a to 6e It is a schematic diagram of the method for manufacturing a display panel provided by an embodiment of the present application. The method for manufacturing a display panel includes:
[0089] Step S1: Form a semiconductor material layer 20 on one side of the substrate 1;
[0090] Step S2: Form a conductive material layer 30 on the side of the semiconductor material layer 20 away from the substrate 1;
[0091] Step S3: Form a photoresist layer 9 on the conductive material layer 30;
[0092] Step S4: Use a photomask to perform exposure and development processing on the photoresist layer 9 to form a first photoresist pattern 91;
[0093] Step S5: Perform the first etching on the conductive material layer 30 and the semiconductor material layer 20 simultaneously to form a conductive portion 300 and an active layer 2, with the side surface of the conductive portion 300 being continuous with the side surface of the active layer 2.
[0094] Step S6: Use a photomask to thin the first photoresist pattern 91 to form a second photoresist pattern 92.
[0095] Step S7: Perform the second etching on the conductive portion 300 to form a conductive layer 3.
[0096] In some embodiments, the material of the active layer 2 is an oxide semiconductor material, and the oxide semiconductor material may include any one of indium gallium zinc oxide, indium zinc oxide, tin-doped zinc oxide, aluminum-doped indium oxide, etc.
[0097] In the embodiments of the present application, please refer to Figures 6a to 6e , during the first etching, by etching the conductive material layer 30 and the semiconductor material layer 20 simultaneously, the side surface of the formed conductive portion 300 is made continuous with the side surface of the active layer 2, so as to prevent the etching solution from drilling and etching the conductive portion 300 from the bottom of the active layer 2 during the second patterning process, enabling the inward shrinkage width of the edge of the conductive layer 3 compared to the same-side edge of the active layer 2 to be reduced to 1 to 1.3 micrometers, thereby improving the situation of critical dimension loss.
[0098] Please refer to Figure 6a , before forming the semiconductor material layer 20 on the substrate 1, a gate 4 and a gate insulating layer 6 have already been formed on the substrate 1, and the semiconductor material layer 20 is formed on the surface of the gate insulating layer 6 away from the substrate 1.
[0099] Please refer to Figure 6a , the conductive material layer 30 is a bilayer structure, and the conductive material layer 30 includes a first sub-conductive material layer 30a and a second sub-conductive material layer 30b, and the second sub-conductive material layer 30b is formed on the surface of the first sub-conductive material layer 30a away from the substrate 1.
[0100] As Figure 6e shown, the conductive layer 3 formed by etching the conductive material layer 30 is also a bilayer conductive structure, and the conductive layer 3 includes a first sub-conductive layer 31 and a second sub-conductive layer 32, and the second sub-conductive layer 32 is disposed on the surface of the first sub-conductive layer 31 away from the substrate 1.
[0101] In some embodiments, the material of the first sub-conductive layer 31 includes any one of molybdenum, molybdenum-titanium alloy, and molybdenum-niobium alloy, and the material of the second sub-conductive layer 32 includes copper.
[0102] In some embodiments, the ratio of the thickness of the first sub-conductive layer 31 to the thickness of the second sub-conductive layer 32 is greater than or equal to 0.015 and less than or equal to 0.072.
[0103] In some embodiments, referring to Figure 1 , the thickness of the first sub-conductive layer 31 is greater than or equal to 120 microns and less than or equal to 180 microns, and the thickness of the second sub-conductive layer 32 is greater than or equal to 2500 microns and less than or equal to 8000 microns. For example, the thickness of the first sub-conductive layer 31 can be 120 microns, 140 microns, 160 microns, or 180 microns, etc., and the thickness of the second sub-conductive layer 32 can be 2500 microns, 3000 microns, 5000 microns, 7000 microns, or 8000 microns, etc.
[0104] In some embodiments, step S5 includes: etching the conductive material layer 30 and the semiconductor material layer 20 using a composite etching solution. The composite etching solution can etch the conductive material layer 30 and the semiconductor material layer 20 simultaneously, so that the edge of the conductive portion 300 formed by the first etching is continuous with the edge of the active layer 2, avoiding the edge of the active layer 2 being indented inward compared to the edge of the conductive portion 300. In this way, when performing the second etching, the etching solution can be prevented from drilling and etching the conductive portion 300 from the bottom of the active layer 2, thereby reducing the missing critical dimension from 3.5 microns to 1.9 microns, and further improving the situation of missing critical dimensions and enhancing the process precision of the display panel.
[0105] In some embodiments, the composite etching solution material includes hydrofluoric acid, hydrogen peroxide, sulfuric acid, and nitric acid.
[0106] In some embodiments, the material of the composite etching solution includes: hydrofluoric acid with a mass fraction of less than 0.1%, hydrogen peroxide with a mass fraction greater than or equal to 15% and less than or equal to 25%, sulfuric acid with a mass fraction greater than or equal to 2% and less than or equal to 7%, nitric acid with a mass fraction greater than or equal to 2% and less than or equal to 7%, and water with a mass fraction greater than or equal to 60% and less than or equal to 80%.
[0107] In some embodiments, referring to Figure 6c and Figure 6d , before performing the second etching on the conductive portion 300, the first photoresist pattern 91 is thinned using a photomask. Specifically, through ashing, the portion of the first photoresist pattern 91 corresponding to the channel of the transistor is removed to form a second photoresist pattern 92. When performing the second etching, the portion of the conductive portion 300 not covered by the photoresist 9 is etched away to obtain Figure 6e the conductive layer 3 shown in
[0108] According to the display panel provided in the above embodiments of the present application, an embodiment of the present application further provides a display device. Please refer to Figure 7 , Figure 7 which is a schematic diagram of the display device provided in the embodiment of the present application. The display device 1000 includes a display panel 100 and a housing 200, and the display panel 100 is disposed on the housing 200. The display panel 100 can be the display panel provided in any of the above embodiments. The display device provided in the embodiment of the present application can achieve the same technical effects as the display panel provided in any of the above embodiments, which will not be elaborated here.
[0109] Beneficial effects of the embodiments of the present application: The embodiments of the present application provide a display panel, a manufacturing method of the display panel, and a display device. The display panel includes a substrate, an active layer, and a conductive layer. The active layer is disposed on one side of the substrate, and the conductive layer is disposed on the side of the active layer away from the substrate. By simultaneously patterning the conductive layer and the active layer, the side surface of the patterned conductive layer is continuous with the side surface of the active layer, avoiding the etching solution from drilling the conductive layer from the bottom of the active layer during the second patterning process, so that the inward shrinkage width of the edge of the conductive layer compared to the same-side edge of the active layer can be reduced to 1 to 1.3 microns, thereby improving the situation of critical dimension missing.
[0110] In the description of the present application, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more features. In the description of the present application, "a plurality" means two or more, unless otherwise specifically defined.
[0111] In the above embodiments, the descriptions of the various embodiments have their own emphases. For the parts not detailed in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.
[0112] Among the embodiments, embodiments, and related technical features of the present application, they can be combined and replaced with each other without conflict.
[0113] The above are only the preferred embodiments of the present application and do not impose any form of limitation on the present application. However, any simple modification, equivalent change, and modification made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application still fall within the scope of the technical solution of the present application.
Claims
1. A display panel, characterized in that, Comprising: A substrate; An active layer disposed on one side of the substrate; A conductive layer disposed on the side of the active layer away from the substrate; Wherein, the edge of the conductive layer is indented inward compared to the edge of the active layer, and the indentation width of the edge of the conductive layer compared to the same-side edge of the active layer is greater than or equal to 1 μm and less than or equal to 1.3 μm.
2. The display panel according to claim 1, wherein The conductive layer includes a first sub-conductive layer and a second sub-conductive layer, and the second sub-conductive layer is disposed on the surface of the first sub-conductive layer away from the active layer; Wherein, the ratio of the thickness of the first sub-conductive layer to the thickness of the second sub-conductive layer is greater than or equal to 0.015 and less than or equal to 0.
072.
3. The display panel according to claim 2, wherein The side surface of the first sub-conductive layer is continuously disposed with the side surface of the second sub-conductive layer.
4. The display panel according to claim 2, wherein The angle between the side surface and the bottom surface of the first sub-conductive layer is a first angle, the angle between the side surface and the bottom surface of the second sub-conductive layer is a second angle, and the first angle is the same as the second angle.
5. The display panel according to claim 4, characterized in that, The first angle is greater than or equal to 40 degrees and less than or equal to 70 degrees.
6. The display panel according to claim 4, wherein The angle between the side surface and the bottom surface of the active layer is a third angle, and the third angle is less than the first angle.
7. The display panel according to claim 6, wherein The third angle is greater than or equal to 30 degrees and less than or equal to 50 degrees.
8. The display panel according to claim 1, wherein The orthographic projection of the conductive layer on the active layer is located within the active layer.
9. The display panel according to claim 1, wherein The conductive layer includes a source electrode and a drain electrode, the active layer includes a first active portion, and the source electrode and the drain electrode are spaced apart on the surface of the first active portion away from the substrate; Wherein, along the channel length direction of the first active portion, the distance between the source electrode and the drain electrode is greater than or equal to 3 μm and less than or equal to 3.5 μm.
10. The display panel according to claim 1, wherein The display panel includes a display area and a border area disposed around the display area, the conductive layer includes a plurality of fan-out traces, and the fan-out traces are disposed in the border area; Wherein, the active layer includes a plurality of second active portions, and the orthographic projection of the fan-out traces on the active layer is located within the second active portions.
11. The display panel according to claim 10, wherein, Along the line width direction of the fan-out traces, the center distance between two adjacent fan-out traces is greater than or equal to 7 μm and less than or equal to 8 μm.
12. The display panel according to claim 2, wherein The thickness of the first sub-conductive layer is greater than or equal to 120 μm and less than or equal to 180 μm, and the thickness of the second sub-conductive layer is greater than or equal to 2500 μm and less than or equal to 8000 μm.
13. The display panel according to claim 2, wherein, The etching selectivity of the material of the first sub-conductive layer is less than the etching selectivity of the material of the second sub-conductive layer.
14. The display panel according to claim 2, characterized in that, The material of the first sub-conductive layer includes any one of molybdenum, molybdenum-titanium alloy, and molybdenum-niobium alloy, and the material of the second sub-conductive layer includes copper.
15. The display panel according to claim 1, characterized in that, The display panel further includes a gate (4), and the gate (4) is disposed between the active layer (2) and the substrate (1).
16. The display panel according to claim 1, characterized in that, The material of the active layer includes an oxide semiconductor material.
17. A manufacturing method of a display panel, characterized in that, The manufacturing method of the display panel includes: Forming a semiconductor material layer on one side of the substrate; Forming a conductive material layer on the side of the semiconductor material layer away from the substrate; Forming a photoresist layer on the conductive material layer; Performing exposure and development processing on the photoresist layer using a photomask to form a first photoresist pattern; Perform a first etching on the conductive material layer and the semiconductor material layer simultaneously using the first photoresist pattern to form a conductive portion and an active layer, with the side surface of the conductive portion being continuous with the side surface of the active layer; Use the photomask to thin the first photoresist pattern to form a second photoresist pattern; Perform a second etching on the conductive portion using the second photoresist pattern to form a conductive layer; Wherein, the inward contraction width of the edge of the conductive layer compared to the same-side edge of the corresponding active layer is greater than or equal to 1 micron and less than or equal to 1.3 microns.
18. The manufacturing method of the display panel according to claim 17, wherein, The conductive layer includes a first sub-conductive layer and a second sub-conductive layer, and the second sub-conductive layer is disposed on the surface of the first sub-conductive layer away from the active layer; Wherein, the ratio of the thickness of the first sub-conductive layer to the thickness of the second sub-conductive layer is greater than or equal to 0.015 and less than or equal to 0.
072.
19. The manufacturing method of the display panel according to claim 17, wherein, The step of performing the first etching on the conductive material layer and the semiconductor material layer simultaneously using the first photoresist pattern includes: Etch the conductive material layer and the semiconductor material layer using a composite etching solution; Wherein, the materials of the composite etching solution include hydrofluoric acid, hydrogen peroxide, sulfuric acid, and nitric acid.
20. A display device, characterized in that, It includes a display panel according to any one of claims 1 to 16.