Display device

Abstract

Provided is a display device in which defects caused by external light reflection in a non-display area are minimized. The display device includes a display panel and a touch unit disposed on the display panel. The display panel may include: a substrate including a display area and a non-display area disposed around the display area; an insulator including a valley portion defined as an opening disposed along an outer side of the display area in the non-display area; and a display unit disposed in the display area and including a light emitting element electrically connected to the thin film transistor. The touch unit may include an anti-reflection unit overlapping the valley portion and configured to reduce a reflectivity of external light.

Description

[0001] This application is a divisional application of a patent application with an application date of December 27, 2019, an application number of 201911376922.1, and an invention title of "Display Device". Technical Field

[0002] Example embodiments of the present disclosure relate to a display device, and more particularly, to a display device in which defects caused by external light reflection in a non-display area are minimized. Background Art

[0003] Among various display devices, organic light-emitting display devices have bright colors, wide viewing angles, excellent contrast ratios, and fast response speeds, and thus have received much attention as next-generation display devices.

[0004] Generally, an organic light-emitting display device includes thin-film transistors and organic light-emitting diodes formed on a substrate, and the organic light-emitting diodes operate by emitting light in response to current supplied by the thin-film transistors. The organic light-emitting display device can be used as a display unit for a miniaturized product such as a mobile phone, or as a display unit for a large product such as a television.

[0005] The organic light-emitting display device may include a display area in which pixels are arranged and a non-display area located outside the display area. Since the non-display area of the organic light-emitting display device is generally formed along the edge of the substrate, a structure for preventing external moisture from passing through is arranged. The formation of these structures for preventing external moisture from passing through may cause problems, such as an example where external light may be reflected by the structure and light leakage may occur inside the non-display area. Summary of the Invention

[0006] Example embodiments of the present disclosure include a display device in which defects caused by external light reflection in a non-display area are minimized. However, it should be understood that the example embodiments described herein should be considered only in a descriptive sense and not for limiting the present disclosure.

[0007] Additional aspects will be set forth in part in the description that follows and, in part, will be obvious from the description, or may be learned by practice of the example embodiments presented.

[0008] According to an exemplary embodiment of the present disclosure, a display device includes a display panel and a touch unit disposed on the display panel. The display panel may include: a substrate including a display area and a non-display area disposed around the display area; an insulator including valleys defined as openings disposed along the outer side of the display area in the non-display area; and a display unit disposed in the display area and including a light-emitting element electrically connected to a thin-film transistor. The touch unit may include an anti-reflection unit that overlaps with the valleys and is configured to reduce the reflectance of external light.

[0009] The touch unit may be directly disposed on the display panel and may include: sensing electrodes corresponding to the display area; and signal lines corresponding to the non-display area and electrically connected to the sensing electrodes.

[0010] The sensing electrodes may include: a first conductive layer; a second conductive layer disposed on the first conductive layer; a first insulating layer disposed between the first conductive layer and the second conductive layer; and a second insulating layer disposed on the second conductive layer.

[0011] The anti-reflection unit may include a material that is the same as the material of the second conductive layer.

[0012] The sensing electrodes may have a mesh shape.

[0013] The sensing electrodes may include a first sensing electrode and a second sensing electrode intersecting the first sensing electrode, and the signal lines may include: a first signal line connected to the first sensing electrode; and a second signal line connected to the second sensing electrode.

[0014] At least a portion of the signal lines may overlap with the valleys.

[0015] The anti-reflection unit may include at least a portion of the signal lines.

[0016] The touch unit may further include: a dummy layer to which no electrical signal is applied, the dummy layer being disposed outside the signal lines and at least a portion of the dummy layer overlapping with the valleys.

[0017] The anti-reflection unit may include at least a portion of the dummy layer.

[0018] The touch unit may further include: an anti-static discharge line disposed outside the signal lines and at least a portion of the anti-static discharge line overlapping with the valleys.

[0019] The anti-reflection unit may include at least a portion of the anti-static discharge line.

[0020] The touch unit may further include: a protection line disposed at the outermost portion of the signal lines and configured to prevent signal interference to the signal lines, and at least a portion of the protection line overlapping with the valleys.

[0021] The anti-reflection unit may include at least a part of the protective line.

[0022] The width of the anti-reflection unit may be greater than the width of the valley portion.

[0023] The light-emitting element may include: a pixel electrode; a common electrode disposed on the pixel electrode; and an emission layer disposed between the pixel electrode and the common electrode. The display panel may further include: a packaging unit disposed on the common electrode, the packaging unit including: a first inorganic packaging layer; a second inorganic packaging layer disposed on the first inorganic packaging layer; and an organic packaging layer disposed between the first inorganic packaging layer and the second inorganic packaging layer. The touch unit may be disposed on the second inorganic packaging layer.

[0024] The common electrode may extend to a part of the non-display area and may cover the valley portion.

[0025] The display area of the display panel may include a rounded corner portion.

[0026] A partial area of the touch unit may have a predetermined curvature to correspond to the shape of the display area.

[0027] The insulator may further include: a first insulating layer; and a second insulating layer disposed on the first insulating layer. The valley portion may include a first opening defined in the first insulating layer and a second opening defined in the second insulating layer.

[0028] The display unit may further include: a planarization layer disposed on the thin-film transistor to cover the thin-film transistor; and a pixel defining layer disposed on the planarization layer and including an opening defining an emission area of the light-emitting element, wherein the first insulating layer may include a material the same as that of the planarization layer, and the second insulating layer may include a material the same as that of the pixel defining layer.

[0029] The insulator may further include: a first insulating layer; a second insulating layer disposed on the first insulating layer; and a third insulating layer disposed on the second insulating layer. The valley portion may include: a first opening defined in the first insulating layer; a second opening defined in the second insulating layer; and a third opening defined in the third insulating layer.

[0030] The display unit may further include: a first planarization layer disposed on the thin-film transistor to cover the thin-film transistor; a second planarization layer disposed on the first planarization layer; and a pixel defining layer disposed on the second planarization layer and including an opening defining an emission area of the light-emitting element, wherein the first insulating layer may include a material the same as that of the first planarization layer, the second insulating layer may include a material the same as that of the second planarization layer, and the third insulating layer may include a material the same as that of the pixel defining layer.

[0031] The valley portion may be around the outer portion of the display area in the plan view and may have a shape in which at least one side of the valley portion is open.

[0032] The valley portion may have a stepped structure with two or more steps.

[0033] The inner surface of the valley portion may have a conical inclined surface.

[0034] According to an exemplary embodiment of the present disclosure, a display device includes: a substrate including a display area and a non-display area disposed around the display area; a display unit disposed in the display area and including a light-emitting element electrically connected to a thin-film transistor; an insulating member extending from the display area and including a valley portion defined as an opening disposed along the outer side of the display area, and at least a part of the insulating member is disposed in the non-display area; a packaging unit including at least one inorganic layer and at least one organic layer and disposed on the light-emitting element to package the light-emitting element; and a touch unit disposed on the packaging unit and including sensing electrodes corresponding to the display area, signal lines corresponding to the non-display area and connected to the sensing electrodes, and a dummy layer disposed on one side of the signal lines, the dummy layer being stacked with the valley portion.

[0035] The sensing electrodes may include a plurality of first sensing electrodes and a plurality of second sensing electrodes, the signal lines may include a plurality of first signal lines respectively connected to the plurality of first sensing electrodes and a plurality of second signal lines respectively connected to the plurality of second sensing electrodes, and the dummy layer may be disposed between the first signal line disposed at the outermost portion among the plurality of first signal lines and the second signal line disposed at the outermost portion among the plurality of second signal lines.

[0036] According to an exemplary embodiment of the present disclosure, a display device includes: a substrate including a display area and a non-display area disposed around the display area; a display unit disposed in the display area and including a light-emitting element electrically connected to a thin-film transistor; an insulating member extending from the display area and including a valley portion defined as an opening disposed along the outer side of the display area, and at least a part of the insulating member is disposed in the non-display area; a packaging unit including at least one inorganic layer and at least one organic layer and disposed on the light-emitting element to package the light-emitting element; and a touch unit disposed on the packaging unit and including an anti-reflection unit configured to reduce the reflectance of external light, wherein, in the plan view, the anti-reflection unit may at least include a first portion stacked with the whole of the valley portion and a second portion surrounding the first portion and not stacked with the valley portion.

[0037] The touch unit may include: sensing electrodes corresponding to a display area; and signal lines corresponding to a non-display area and electrically connected to the sensing electrodes; wherein, the anti-reflection unit may include at least one of a part of the signal lines, a part of the protection lines, a part of the static-discharge prevention lines, and a part of the dummy layer disposed on one side of the signal lines. Description of the Drawings

[0038] These and / or other aspects of the present disclosure will become apparent and be more readily understood from the following description of embodiments in conjunction with the accompanying drawings, in which:

[0039] Figure 1 is a plan view of a display device according to an exemplary embodiment of the present disclosure;

[0040] Figure 2 is Figure 1 a cross-sectional view of the display device of

[0041] Figure 3 is Figure 1 a plan view of a display panel of the display device of

[0042] Figure 4 is an equivalent circuit diagram of a pixel according to an exemplary embodiment of the present disclosure;

[0043] Figure 5 is a cross-sectional view of a stacked structure of a display panel and a touch unit in a display device according to an exemplary embodiment of the present disclosure;

[0044] Figure 6 is a plan view of a touch unit of a display device according to an exemplary embodiment of the present disclosure;

[0045] Figure 7 is a cross-sectional view of a display panel of a display device according to an exemplary embodiment of the present disclosure;

[0046] Figure 8 is Figure 7 a cross-sectional view of a part of the display area of

[0047] Figure 9 is a cross-sectional view of a display panel of a display device according to an exemplary embodiment of the present disclosure;

[0048] Figure 10 and Figure 11 are cross-sectional views of a part of a display device according to exemplary embodiments of the present disclosure;

[0049] Figure 12 is a cross-sectional view of a part of a display device according to an exemplary embodiment of the present disclosure; and

[0050] Figures 13 to 18It is a plan view of a part of a display device according to an exemplary embodiment of the present disclosure.

[0051] Since Figures 1 to 18 The accompanying drawings in [the document] are for illustrative purposes, and thus the elements in the drawings do not have to be drawn to scale. For example, some elements may be enlarged or exaggerated for clarity purposes. Detailed Description

[0052] Since the disclosure allows for various changes and many embodiments, the exemplary embodiments of the present disclosure will be shown in the accompanying drawings and described in detail in the written description. When referring to the exemplary embodiments described with reference to the accompanying drawings, the effects and features of the present disclosure and the methods for realizing them will be apparent. However, the present disclosure can be implemented in many different forms and should not be construed as limited to the specific exemplary embodiments set forth herein.

[0053] Hereinafter, the present disclosure will be described more fully with reference to the accompanying drawings in which exemplary embodiments of the present disclosure are shown. When describing with reference to the accompanying drawings, like reference numerals in the drawings denote like or corresponding elements, and thus their repeated description will be omitted.

[0054] As used herein, the term “and / or” includes any combination and all combinations of one or more of the associated listed items.

[0055] When an expression such as “at least one of...” is after a list of elements, the expression modifies the entire list of elements and not a single element in the list.

[0056] It will be understood that although the terms “first,” “second,” etc. may be used herein to describe various components, these components should not be limited by these terms. These components are only used to distinguish one component from another.

[0057] As used herein, unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “the” are also intended to include the plural forms.

[0058] It will also be understood that the terms “comprises / including” and / or its variations as used herein specify the presence of stated features and / or components, but do not preclude the presence or addition of one or more other features and / or their components.

[0059] It will be understood that when a layer, region, or component is referred to as being “formed on” another layer, region, or component, the layer, region, or component can be formed directly or indirectly on the other layer, region, or component. That is, for example, there may be intermediate layers, regions, or components.

[0060] In the following examples, the x-axis, y-axis, and z-axis are not limited to the three axes of a rectangular coordinate system and can be interpreted in a broader sense. For example, the x-axis, y-axis, and z-axis can be perpendicular to each other, or can represent different directions that are not perpendicular to each other. In addition, the x-axis, y-axis, and z-axis can respectively correspond to a first direction D1, a second direction D2, and a third direction D3.

[0061] When implementing a certain exemplary embodiment differently, the specific process order can be executed in a different order from that described. For example, two consecutively described processes can be executed substantially simultaneously or in an order opposite to the described order.

[0062] Figure 1 is a plan view of a display device 1 according to an exemplary embodiment of the present disclosure.

[0063] Referring to Figure 1 , the display device 1 according to an exemplary embodiment of the present disclosure includes a display area DA for displaying an image and a non-display area NDA adjacent to the display area DA. The non-display area NDA is an area where no image is displayed. The display area DA can be surrounded by the non-display area NDA. Images such as photos, moving image images or time, and icons can be displayed in the display area DA.

[0064] Although the exemplary embodiment of the present disclosure shows a display device 1 including a flat display surface, the present disclosure is not limited thereto. For example, the display device 1 can include a curved display surface or a three-dimensional display surface. A three-dimensional display surface in which an image is generated within a display volume rather than on a fixed surface can include a plurality of display areas, such as a polyhedral surface. The plurality of display areas can be positioned in different directions.

[0065] Although the display device 1 according to the present exemplary embodiment can include a flexible display device, the present disclosure is not limited thereto. The display device 1 according to the exemplary embodiment of the present disclosure can include a rigid display device 1. The present exemplary embodiment has shown the display device 1 applicable to a mobile phone as an example. Electronic modules, camera modules, power modules, etc. mounted on a main board can be arranged together with the display device 1 in a bracket / case to form a mobile phone. The display device 1 according to the exemplary embodiment of the present disclosure is applicable not only to large electronic devices such as televisions and monitors as examples, but also to small and medium-sized electronic devices such as tablet computers, car navigation devices, game console controllers, and smart watches as examples.

[0066] As Figure 1As shown, the display area DA of the display device 1 may generally have a quadrilateral shape. The four corner portions DA-C of the display area DA may have a circular shape with a predetermined curvature. Accordingly, a partial area of the touch unit TU to be described may have a predetermined curvature corresponding to the shape of the display area DA. The non-display area NDA may surround the display area DA and may also have a quadrilateral shape with four rounded corners. However, the present disclosure is not limited thereto, and the display area DA and the non-display area NDA may have various shapes and may be designed relatively.

[0067] Figure 2 is Figure 1 a cross-sectional view of the display device 1 and is simply shown to illustrate the stacked relationship of the functional panels and / or functional units constituting the display device 1.

[0068] Referring Figure 2 , the display device 1 according to an exemplary embodiment of the present disclosure may include a display panel DP, a touch unit TU, a polarization unit PU, and a window unit WU that may be sequentially formed. However, the present disclosure is not limited thereto. At least some of the elements of the display panel DP, the touch unit TU, the polarization unit PU, and the window unit WU may be formed by a continuous process or may be bonded to each other by an adhesive member. As an example, Figure 2 shows an optically clear adhesive OCA as the adhesive member. The adhesives described below may include general adhesives or binders. The optically clear adhesive OCA may be formed of a pre-coated film or formed of a liquid paste. Generally, the optically clear adhesive OCA may require a light transmittance and may provide impact resistance. In an exemplary embodiment of the present disclosure, the polarization unit PU and the window unit WU may be replaced by different elements or may be omitted.

[0069] The touch unit TU is directly disposed on the display panel DP. In this specification, when an element B is directly disposed on an element A, no separate adhesive layer / adhesive member is disposed between the element A and the element B. After forming the element A, the element B is formed on the substrate surface of the element A by a continuous process.

[0070] The display module DM may be defined by including the display panel DP and the touch unit TU directly disposed on the display panel DP. The optically clear adhesive OCA is disposed between the display module DM and the polarization unit PU and between the polarization unit PU and the window unit WU, respectively.

[0071] The display panel DP generates an image, and the touch unit TU obtains coordinate information of an external input (e.g., a touch event). The display module DM according to an exemplary embodiment of the present disclosure may further include a protection member disposed on the rear surface of the display panel DP. The protection member and the display panel DP may be bonded to each other by an adhesive member.

[0072] The display panel DP according to an exemplary embodiment of the present disclosure may include a light-emitting display panel and is not particularly limited. For example, in the exemplary embodiment of the present disclosure, the display panel DP may include an organic light-emitting display panel or a quantum dot light-emitting display panel. The emission layer of the organic light-emitting display panel may include an organic light-emitting material. The emission layer of the quantum dot light-emitting display panel may include quantum dots and quantum rods. The quantum dots and quantum rods may be small semiconductor particles having a size of several nanometers. Hereinafter, the display panel DP is described as an organic light-emitting display panel.

[0073] The polarization unit PU reduces the reflectance of external light incident from above the window unit WU. The polarization unit PU according to an exemplary embodiment of the present disclosure may include a retarder and a polarizer. The retarder may include a film-type retarder or a liquid crystal-type retarder. The retarder may include a λ / 2 retarder and / or a λ / 4 retarder. In the exemplary embodiment of the present disclosure, the polarization unit PU may include a two-layer retarder, where the first retarder has a λ / 2 retardation value and the second retarder is located below the first retarder and has a λ / 4 retardation value. In addition, the polarizer may include a film-type polarizer or a liquid crystal-type polarizer. The film-type polarizer may include a stretchable synthetic resin film, and the liquid crystal-type polarizer may include liquid crystals arranged in a predetermined arrangement. The film-type polarizer may be a uniaxially stretched film or a biaxially stretched film. Each of the retarder and the polarizer may further include a protective film. For example, the polarizer may be interposed between two protective films. The retarder and the polarizer themselves or their protective films may be defined as the substrate layer of the polarization unit PU.

[0074] The structures of the display panel DP and the touch unit TU are described in detail below.

[0075] Figure 3 is Figure 1 a plan view of the display panel DP of the display device 1.

[0076] Referring to Figure 3 , the display panel DP includes a display unit 10, a first scan driver 20, a second scan driver 30, a terminal unit 40, a data driver 50, a driving voltage supply line 60, and a common voltage supply line 70 disposed on a substrate 100.

[0077] The substrate 100 may include materials such as glass, metal, or organic materials having silicon oxide (SiO2) as a main component. In the exemplary embodiment of the present disclosure, the substrate 100 may include a flexible material. For example, although the substrate 100 may include a flexible plastic material such as polyimide, the present disclosure is not limited thereto.

[0078] In an exemplary embodiment of the present disclosure, the plastic material may include, for example, polyethersulfone (PES), polyarylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyacrylate, polyimide (PI), polycarbonate (PC), triacetyl cellulose (TAC), cellulose acetate propionate (CAP), cycloolefin polymer, and cycloolefin copolymer.

[0079] The display unit 10 includes pixels P each connected to a scan line SL extending in a first direction D1, a data line DL, and a driving voltage line PL extending in a second direction D2 intersecting the first direction D1. For example, the scan lines SL may be spaced apart from each other in the second direction D2 and extend in the first direction D1, while the data lines DL and the driving voltage lines PL may be spaced apart from each other in the first direction D1 and extend in the second direction D2.

[0080] Each pixel P emits light of, for example, red, green, blue, or white. In an exemplary embodiment of the present disclosure, each pixel P may include an organic light emitting diode. The display unit 10 generates a predetermined image by the light emitted from the pixels P. The display area DA is defined by the pixels P. In an exemplary embodiment of the present disclosure, the pixels P may be arranged in a matrix shape, but the present disclosure is not limited thereto. For example, the pixels P may be arranged in a pentile matrix shape or a diamond shape. In this specification, the non-display area NDA is an area in which no pixels P are arranged and is an area where no image is generated.

[0081] Although the display unit 10 generally has a quadrilateral shape, the present disclosure is not limited thereto. For example, in various exemplary embodiments of the present disclosure, the display unit 10 may be provided in a polygonal shape, a circular shape, an oval shape, or a shape corresponding to a part of these shapes. In this exemplary embodiment, the display unit 10 as a whole has a quadrilateral shape and may have a circular corner portion where each edge is curved. For example, the display area DA of the display panel DP may include a circular corner portion. The substrate 100 on which the display unit 10 is provided may have a curved edge in at least a part of the outer edge area. The display unit 10 may have a flat surface or a curved surface.

[0082] Both the first scan driver 20 and the second scan driver 30 are disposed in the non-display area NDA of the substrate 100, generate scan signals, and transmit the scan signals to each pixel P through the scan lines SL. In an exemplary embodiment of the present disclosure, the first scan driver 20 may be disposed on the left side of the display unit 10, and the second scan driver 30 may be disposed on the right side of the display unit 10. Although this exemplary embodiment shows a structure in which the first scan driver 20 and the second scan driver 30 are respectively disposed on two opposite sides of the display unit 10, according to the exemplary embodiment of the present disclosure, the scan driver may be disposed on only one side of the display unit 10.

[0083] The terminal unit 40 is disposed at one end of the substrate 100 and includes a plurality of terminals 41, 42, 44, and 45. The terminal unit 40 is not covered by an insulating layer and is exposed, and may be electrically connected to a controller such as a flexible printed circuit board or an integrated circuit (IC) chip, etc.

[0084] The controller changes a plurality of video signals transmitted from the outside into a plurality of video data signals, and transmits the changed video signals to the data driver 50 through the terminal 41. In addition, the controller may receive a vertical synchronization signal, a horizontal synchronization signal, and a clock signal, generate control signals for controlling the driving of the first scan driver 20, the second scan driver 30, and the data driver 50, and transmit the relevant control signals to the relevant components. For example, the control signals provided by the controller to the first scan driver 20 and the second scan driver 30 may include a vertical synchronization signal for controlling the operations of the first scan driver 20 and the second scan driver 30 and at least one clock signal for determining the output timing of the signals. The controller transmits the driving voltage ELVDD and the common voltage ELVSS to the driving voltage supply line 60 and the common voltage supply line 70 through the terminals 42 and 45, respectively.

[0085] The data driver 50 is disposed in the non-display area NDA of the substrate 100, generates data signals, and transmits the data signals to each pixel P through the data lines DL. The data driver 50 may be disposed on one side of the display unit 10, for example, between the terminal unit 40 and the display unit 10.

[0086] The driving voltage supply line 60 is disposed in the non-display area NDA. For example, the driving voltage supply line 60 may be disposed between the data driver 50 and the display unit 10. The driving voltage supply line 60 supplies the driving voltage ELVDD to the pixel P. The driving voltage supply line 60 may extend in the first direction D1 and may be connected to a plurality of driving voltage lines PL disposed in the first direction D1 and extending in the second direction D2.

[0087] The common voltage supply line 70 is disposed in the non-display area NDA and supplies a common voltage ELVSS to the common electrode 230 of the organic light-emitting diode of the pixel P (see Figures 7 to 9 ). For example, the common voltage supply line 70 has an annular shape with one side of the common voltage supply line 70 open and may extend along the edge of the substrate 100 except for the terminal unit 40. For example, the annular shape of the common voltage supply line 70 may have an open side where the terminal unit 40 is disposed.

[0088] The valley portion VP may be disposed in the non-display area NDA along the outer side of the display area DA. The valley portion VP may be disposed between the display unit 10 and the common voltage supply line 70. The valley portion VP overlaps with the first scan driver 20 and the second scan driver 30 in a partial area of the valley portion VP (see Figure 7 ), but the present disclosure is not limited thereto. For example, the valley portion VP may not overlap with the first scan driver 20 and the second scan driver 30. In the present specification, when an element A is described as overlapping with an element B, the element A overlaps with the element B in the third direction D3. In an exemplary embodiment of the present disclosure, the valley portion VP may be disposed between the emission control driver and the first scan driver 20 and the second scan driver 30.

[0089] The valley portion VP may have an annular shape with one side of the valley portion VP open and may not be formed in a partial area facing the data driver 50. For example, the valley portion VP may surround the outer portion of the display area DA in a plan view and may have a shape with at least one side of the valley portion VP open. The valley portion VP is designed to block impurities introduced into the display area DA by removing a part of the insulating layer ILL extending into the non-display area NDA (see Figure 7 ). The insulating layer ILL may also be referred to as an insulator. Since a plurality of wirings are disposed on the side facing the data driver 50, impurities can be easily blocked. On the contrary, it is not easy to block impurities in the remaining areas. Therefore, the valley portion VP as in the present exemplary embodiment can be provided. Accordingly, the insulator may include the valley portion VP, and the valley portion VP is defined as an opening disposed along the outer side of the display area DA in the non-display area NDA. For example, the valley portion VP is an opening formed in the insulator.

[0090] Figure 4 is an equivalent circuit diagram of the pixel P according to an exemplary embodiment of the present disclosure.

[0091] Referring to Figure 4 , each pixel P includes a pixel circuit PC connected to the scan line SL and the data line DL and a light-emitting diode (e.g., an organic light-emitting diode OLED) connected to the pixel circuit PC.

[0092] The pixel circuit PC includes a driving thin film transistor T1, a switching thin film transistor T2, and a storage capacitor Cst. The switching thin film transistor T2 is connected to a scan line SL and a data line DL, and transmits a data signal input through the data line DL to the driving thin film transistor T1 in response to a scan signal Sn input through the scan line SL.

[0093] The storage capacitor Cst is connected to the switching thin film transistor T2 and a driving voltage line PL, and stores a voltage corresponding to the difference between the voltage transmitted from the switching thin film transistor T2 and the driving voltage ELVDD supplied to the driving voltage line PL. For example, the storage capacitor Cst may include a first electrode coupled to the switching thin film transistor T2 and a second electrode receiving the driving voltage ELVDD. In addition, the storage capacitor Cst may be charged with a voltage corresponding to the data signal received from the switching thin film transistor T2.

[0094] The driving thin film transistor T1 is connected to the driving voltage line PL and the storage capacitor Cst, and may control a driving current flowing through the organic light emitting diode OLED from the driving voltage line PL in response to the voltage value stored in the storage capacitor Cst. The organic light emitting diode OLED may emit light with a predetermined brightness by using the driving current.

[0095] Although Figure 4 the pixel circuit PC including two thin film transistors T1 and T2 and one storage capacitor Cst is shown, the present disclosure is not limited thereto. For example, in an exemplary embodiment of the present disclosure, the pixel P may include a pixel circuit PC including three or more thin film transistors and two or more capacitors.

[0096] Figure 5 is a cross-sectional view of a stacked structure of a display panel DP and a touch unit TU in a display device 1 according to an exemplary embodiment of the present disclosure, Figure 6 is a plan view of the touch unit TU of the display device 1 according to an exemplary embodiment of the present disclosure.

[0097] Figure 5 shows a cross-section of a stacked structure of the display panel DP and the touch unit TU. Figure 5 The display panel DP is simply shown to illustrate the stacking relationship of the touch unit TU. As Figure 2 shown, a polarization unit PU and a window unit WU may be stacked on the touch unit TU.

[0098] The touch unit TU may have a multi-layer structure. The touch unit TU includes sensing electrodes, signal lines connected to the sensing electrodes, and at least one insulating layer. For example, the touch unit TU may be directly disposed on the display panel DP, and may include sensing electrodes corresponding to the display area DA and signal lines corresponding to the non-display area NDA and electrically connected to the sensing electrodes. For example, the sensing electrodes may be mainly disposed in the display area DA, and the signal lines may be mainly disposed in the non-display area NDA. The touch unit TU may sense an external pressure by using, for example, a capacitive method. In the present disclosure, the operation method of the touch unit TU is not particularly limited. In an exemplary embodiment of the present disclosure, the touch unit TU may sense an external pressure by using an electromagnetic induction method or a pressure sensing method.

[0099] As Figure 5 shown, the touch unit TU according to an exemplary embodiment of the present disclosure may include a first conductive layer CL1, a first insulating layer IL1, a second conductive layer CL2, and a second insulating layer IL2. Each of the first conductive layer CL1 and the second conductive layer CL2 may have a single-layer structure or a stacked multi-layer structure. The conductive layer having a single-layer structure may include a metal layer or a transparent conductive layer. The metal layer may include, for example, one of molybdenum (Mo), silver (Ag), titanium (Ti), copper (Cu), aluminum (Al), and their alloys. The transparent conductive layer may include a transparent conductive oxide, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), and indium tin zinc oxide (ITZO) as examples. In addition, the transparent conductive layer may include a conductive polymer (such as poly(3,4-ethylenedioxythiophene) (PEDOT)), metal nanowires, and graphene.

[0100] The conductive layer having a multi-layer structure may include a multi-metal layer. The multi-metal layer may have, for example, a three-layer structure of titanium / aluminum / titanium (Ti / Al / Ti). The conductive layer having a multi-layer structure may include at least one metal layer and at least one transparent conductive layer.

[0101] Each of the first conductive layer CL1 and the second conductive layer CL2 includes a plurality of patterns. Hereinafter, it is described that the first conductive layer CL1 includes a first conductive pattern, and the second conductive layer CL2 includes a second conductive pattern. Each of the first conductive pattern and the second conductive pattern may include a sensing electrode and a signal line. On the other hand, the sensing electrodes may all include the first conductive layer CL1 and / or the second conductive layer CL2 located in the display area DA. For example, in the display area DA, the sensing electrode may include the first conductive layer CL1, the second conductive layer CL2 disposed on the first conductive layer CL1, the first insulating layer IL1 disposed between the first conductive layer CL1 and the second conductive layer CL2, and the second insulating layer IL2 disposed on the second conductive layer CL2.

[0102] The stacked structure and material of the sensing electrodes can be determined by considering the sensing sensitivity. The RC delay affects the sensing sensitivity. Since the sensing electrodes including a metal layer have a lower resistance than the sensing electrodes including a transparent conductive layer, the RC value can be reduced. Therefore, the charging time of the capacitor defined between the sensing electrodes can be reduced. Compared with the sensing electrodes including a metal layer, the sensing electrodes including a transparent conductive layer are not visible to the user and have an increased input area and thus an increased capacitance.

[0103] To prevent the sensing electrodes including a metal layer from being visible to the user, as described below, the sensing electrodes including a metal layer can have a mesh shape. In addition, the thickness of a thin film encapsulation layer such as the encapsulation unit 150 (see Figure 7 ) to be described can be adjusted such that the noise generated by the elements of the display element layer does not affect the touch unit TU. Each of the first insulating layer IL1 and the second insulating layer IL2 can have a single-layer or multi-layer structure. Each of the first insulating layer IL1 and the second insulating layer IL2 can include an inorganic material, an organic material, or a composite material.

[0104] At least one of the first insulating layer IL1 and the second insulating layer IL2 can include an inorganic layer. The inorganic layer can include at least one of, for example, aluminum oxide (Al2O3), titanium oxide (TiO2), silicon oxide (SiO2), silicon oxynitride (SiON), zirconium oxide (ZrO2), and hafnium oxide (HfO2).

[0105] At least one of the first insulating layer IL1 and the second insulating layer IL2 can include an organic layer. The organic layer can include at least one of, for example, acrylic resin, methacrylic resin, polyisoprene, vinyl resin, epoxy resin, urethane resin, cellulose resin, silicone resin, polyimide resin, polyamide resin, and perylene resin.

[0106] As Figure 6 shown, the touch unit TU can include first sensing electrodes IE1-1, IE1-2, IE1-3, IE1-4, and IE1-5, first signal lines SL1-1, SL1-2, SL1-3, SL1-4, and SL1-5 (hereinafter collectively referred to as "SL1") respectively connected to the first sensing electrodes IE1-1, IE1-2, IE1-3, IE1-4, and IE1-5, second sensing electrodes IE2-1, IE2-2, IE2-3, and IE2-4, and second signal lines SL2-1, SL2-2, SL2-3, and SL2-4 (hereinafter collectively referred to as "SL2") respectively connected to the second sensing electrodes IE2-1, IE2-2, IE2-3, and IE2-4.

[0107] The touch unit TU may further include optical dummy electrodes disposed in a boundary region between the first sensing electrodes IE1-1, IE1-2, IE1-3, IE1-4, and IE1-5 and the second sensing electrodes IE2-1, IE2-2, IE2-3, and IE2-4.

[0108] Since the thin film encapsulation layer includes at least one organic encapsulation layer 152 described with reference to Figure 7 below, the thin film encapsulation layer can provide a relatively flat substrate surface. Accordingly, even if the elements of the touch unit TU are formed through a continuous process, the defect rate can be reduced. Since the first sensing electrodes IE1-1, IE1-2, IE1-3, IE1-4, and IE1-5 and the second sensing electrodes IE2-1, IE2-2, IE2-3, and IE2-4 are disposed in the display area DA with a reduced step difference, the first sensing electrodes IE1-1, IE1-2, IE1-3, IE1-4, and IE1-5 and the second sensing electrodes IE2-1, IE2-2, IE2-3, and IE2-4 can have a uniform thickness. Here, the step difference may refer to the vertical portion of the step between steps. The vertical portion may have a vertical surface or an inclined surface. Stress applied to a region overlapping with the step difference between the first sensing electrodes IE1-1, IE1-2, IE1-3, IE1-4, and IE1-5 and the second sensing electrodes IE2-1, IE2-2, IE2-3, and IE2-4 can be reduced. Optionally or additionally, the first signal lines SL1-1, SL1-2, SL1-3, SL1-4, and SL1-5 and the second signal lines SL2-1, SL2-2, SL2-3, and SL2-4 may be disposed in the non-display area NDA with a reduced step difference, so that they can have a uniform thickness. Stress applied to a region overlapping with the step difference between the first signal lines SL1-1, SL1-2, SL1-3, SL1-4, and SL1-5 and the second signal lines SL2-1, SL2-2, SL2-3, and SL2-4 can be reduced.

[0109] The first sensing electrodes IE1-1, IE1-2, IE1-3, IE1-4, and IE1-5 intersect the second sensing electrodes IE2-1, IE2-2, IE2-3, and IE2-4 with each other. The first sensing electrodes IE1-1, IE1-2, IE1-3, IE1-4, and IE1-5 may be arranged to be spaced apart from each other in the second direction D2, and each of the first sensing electrodes IE1-1, IE1-2, IE1-3, IE1-4, and IE1-5 may extend in the first direction D1. The second sensing electrodes IE2-1, IE2-2, IE2-3, and IE2-4 may be arranged to be spaced apart from each other in the first direction D1, and each of the second sensing electrodes IE2-1, IE2-2, IE2-3, and IE2-4 may extend in the second direction D2.

[0110] Each of the first sensing electrodes IE1-1, IE1-2, IE1-3, IE1-4, and IE1-5 includes a first sensor SP1 and a first connector CP1. Each of the second sensing electrodes IE2-1, IE2-2, IE2-3, and IE2-4 includes a second sensor SP2 and a second connector CP2. Two first sensors SP1 respectively arranged at two opposite ends of the first sensing electrodes IE1-1, IE1-2, IE1-3, IE1-4, and IE1-5 among the first sensors SP1 may have a size smaller than the size of the first sensor SP1 arranged at the center (for example, half of the size). Two second sensors SP2 respectively arranged at two opposite ends of the second sensing electrodes IE2-1, IE2-2, IE2-3, and IE2-4 among the second sensors SP2 may have a size smaller than the size of the second sensor SP2 arranged at the center (for example, half of the size).

[0111] Although Figure 6 The first sensing electrodes IE1-1, IE1-2, IE1-3, IE1-4, and IE1-5 and the second sensing electrodes IE2-1, IE2-2, IE2-3, and IE2-4 according to an exemplary embodiment of the present disclosure are shown, but their shapes are not limited. In the exemplary embodiment of the present disclosure, the first sensing electrodes IE1-1, IE1-2, IE1-3, IE1-4, and IE1-5 and the second sensing electrodes IE2-1, IE2-2, IE2-3, and IE2-4 may have a shape in which a sensor and a connector are not distinguished (for example, a bar shape). Although the first sensor SP1 and the second sensor SP2 having a rhombus shape are shown as examples, the present disclosure is not limited thereto. For example, the first sensor SP1 and the second sensor SP2 may have other polygonal shapes.

[0112] The first sensors SP1 within each of the first sensing electrodes IE1-1, IE1-2, IE1-3, IE1-4, and IE1-5 are aligned in the first direction D1, and the second sensors SP2 within each of the second sensing electrodes IE2-1, IE2-2, IE2-3, and IE2-4 are aligned in the second direction D2. Each first connector CP1 connects adjacent first sensors SP1 to each other, and each second connector CP2 connects adjacent second sensors SP2 to each other.

[0113] The first signal lines SL1-1, SL1-2, SL1-3, SL1-4, and SL1-5 are respectively connected to one end of the first sensing electrodes IE1-1, IE1-2, IE1-3, IE1-4, and IE1-5. The second signal lines SL2-1, SL2-2, SL2-3, and SL2-4 are connected to two opposite ends of the second sensing electrodes IE2-1, IE2-2, IE2-3, and IE2-4. However, the present disclosure is not limited thereto. For example, in an exemplary embodiment of the present disclosure, the first signal lines SL1-1, SL1-2, SL1-3, SL1-4, and SL1-5 may also be connected to two opposite ends of the first sensing electrodes IE1-1, IE1-2, IE1-3, IE1-4, and IE1-5. In addition, in an exemplary embodiment of the present disclosure, the second signal lines SL2-1, SL2-2, SL2-3, and SL2-4 may be respectively connected to only one end of the second sensing electrodes IE2-1, IE2-2, IE2-3, and IE2-4.

[0114] Compared with the touch unit TU including the second signal lines SL2-1, SL2-2, SL2-3, and SL2-4 respectively connected to only one end of the second sensing electrodes IE2-1, IE2-2, IE2-3, and IE2-4, according to Figure 6 In the exemplary embodiment shown, the second signal lines SL2-1, SL2-2, SL2-3, and SL2-4 are connected to two opposite ends of the second sensing electrodes IE2-1, IE2-2, IE2-3, and IE2-4, so the sensing sensitivity can be enhanced. Since the second sensing electrodes IE2-1, IE2-2, IE2-3, and IE2-4 are longer than the first sensing electrodes IE1-1, IE1-2, IE1-3, IE1-4, and IE1-5, a voltage drop of the detection signal (or transmission signal) occurs, thus reducing the sensing sensitivity. According to this exemplary embodiment, by providing the detection signal (or transmission signal) through the second signal lines SL2-1, SL2-2, SL2-3, and SL2-4 connected to two opposite ends of the second sensing electrodes IE2-1, IE2-2, IE2-3, and IE2-4, the voltage drop of the detection signal (or transmission signal) can be prevented, thereby preventing the reduction of the sensing sensitivity.

[0115] In an exemplary embodiment of the present disclosure, different from Figure 6 as shown in, the first sensing electrodes IE1-1 to IE1-n may be formed to be longer than the second sensing electrodes IE2-1 to IE2-m (e.g., m>n), and by connecting the first signal lines SL1-1 to SL1-n to two opposite ends of the first sensing electrodes IE1-1 to IE1-n to prevent voltage drops of detection signals (or transmission signals), a reduction in sensing sensitivity can be prevented.

[0116] The first signal lines SL1-1, SL1-2, SL1-3, SL1-4, and SL1-5 and the second signal lines SL2-1, SL2-2, SL2-3, and SL2-4 may each be connected to a pad (also referred to as a "bond pad" or "landing pad") unit PD located on one side. The pad unit PD may be aligned in a pad region PDA.

[0117] In an exemplary embodiment of the present disclosure, the positions of the first signal lines SL1-1, SL1-2, SL1-3, SL1-4, and SL1-5 and the second signal lines SL2-1, SL2-2, SL2-3, and SL2-4 may be exchanged with each other. For example, different from Figure 6 as shown in, the first signal lines SL1-1, SL1-2, SL1-3, SL1-4, and SL1-5 may be arranged on the left side, and the second signal lines SL2-1, SL2-2, SL2-3, and SL2-4 may be arranged on the right side.

[0118] As Figure 6 shown in, the first sensing electrodes IE1-1, IE1-2, IE1-3, IE1-4, and IE1-5 and the second sensing electrodes IE2-1, IE2-2, IE2-3, and IE2-4 may have a mesh shape. Since the first sensing electrodes IE1-1, IE1-2, IE1-3, IE1-4, and IE1-5 and the second sensing electrodes IE2-1, IE2-2, IE2-3, and IE2-4 have a mesh shape, the parasitic capacitance between the electrodes of the display panel DP (see Figure 5 ) and the first sensing electrodes IE1-1, IE1-2, IE1-3, IE1-4, and IE1-5 and the second sensing electrodes IE2-1, IE2-2, IE2-3, and IE2-4 can be reduced. In addition, as described below, since the first sensing electrodes IE1-1, IE1-2, IE1-3, IE1-4, and IE1-5 and the second sensing electrodes IE2-1, IE2-2, IE2-3, and IE2-4 do not overlap with the emission region PXA (see Figure 8) are stacked, so that the first sensing electrodes IE1-1, IE1-2, IE1-3, IE1-4, and IE1-5 and the second sensing electrodes IE2-1, IE2-2, IE2-3, and IE2-4 are not visible to the user of the display device.

[0119] The first sensing electrodes IE1-1, IE1-2, IE1-3, IE1-4, and IE1-5 and the second sensing electrodes IE2-1, IE2-2, IE2-3, and IE2-4 having a mesh shape may include, for example, one of silver (Ag), aluminum (Al), copper (Cu), chromium (Cr), nickel (Ni), and titanium (Ti) that can be processed at low temperatures, but the present disclosure is not limited thereto. Due to the above-described low-temperature process, even if the touch unit TU is formed by a continuous process, damage to the organic light-emitting diode OLED (see Figure 7 ) can be prevented.

[0120] The static electricity discharge line ESL may be disposed outside the first signal lines SL1-1, SL1-2, SL1-3, SL1-4, and SL1-5 and the second signal lines SL2-1, SL2-2, SL2-3, and SL2-4, that is, at the outermost part of the touch unit TU. No signal is applied to the static electricity discharge line ESL, but a constant voltage is applied to the static electricity discharge line ESL.

[0121] Figure 7 is a cross-sectional view of a display panel DP of a display device 1 according to an exemplary embodiment of the present disclosure. Figure 7 is a cross-sectional view taken along line A-A' of Figure 3 .

[0122] Referring to Figure 7 , the display device 1 includes a display area DA and a non-display area NDA (see Figures 1 to 3 ). The substrate 100 may include regions corresponding to the display area DA and the non-display area NDA.

[0123] Referring to Figure 7 of the display area DA, a buffer layer 101 may be formed on the substrate 100. The buffer layer 101 may block foreign substances or moisture that penetrate through the substrate 100. For example, the buffer layer 101 may include an inorganic material such as silicon oxide (SiO

[0124] , , x , x ), silicon nitride (SiN x ), and / or silicon oxynitride (SiON), and may include a single layer or multiple layers.

[0124] The thin film transistor 130, the storage capacitor, and the organic light emitting diode OLED, which is electrically connected to the thin film transistor 130 and the storage capacitor and serves as the light emitting diode 200, may be located above the substrate 100. The thin film transistor 130, the storage capacitor, and the organic light emitting diode OLED are disposed at positions corresponding to the display area DA.

[0125] Figure 7 The thin film transistor 130 may correspond to one of the thin film transistors provided to the pixel circuit PC described with reference to Figure 4 For example, the driving thin film transistor T1.

[0126] The thin film transistor 130 includes a semiconductor layer 134 and a gate electrode 136. The semiconductor layer 134 may include, for example, polysilicon. The semiconductor layer 134 may include a channel region 131 that overlaps with the gate electrode 136, a source region 132 and a drain region 133 that are respectively disposed on two opposite sides of the channel region 131, and the source region 132 and the drain region 133 are doped with impurities having a concentration higher than that of the impurities in the channel region 131. Here, the impurities may include N-type impurities or P-type impurities. For example, the N-type impurities may include, for example, phosphorus (P), arsenic (As), or antimony (Sb), and the P-type impurities may include, for example, aluminum (Al), boron (B), or indium (In). The source region 132 and the drain region 133 may be respectively understood as the source electrode and the drain electrode of the thin film transistor 130.

[0127] Although this exemplary embodiment describes the case where the semiconductor layer 134 includes polysilicon, the present disclosure is not limited thereto. For example, in the exemplary embodiment of the present disclosure, the semiconductor layer 134 may include amorphous silicon or an organic semiconductor material.

[0128] The gate insulating layer 103 may be disposed between the semiconductor layer 134 and the gate electrode 136. The gate insulating layer 103 may include an inorganic insulating layer, and the inorganic insulating layer includes SiON, SiO x and / or SiN x and may include a single layer or multiple layers. Alternatively, the gate insulating layer 103 may include a high-k dielectric material, and the high-k dielectric material may have a dielectric constant higher than that of silicon oxide (SiO x ). For example, the high-k dielectric material may include, for example, hafnium oxide (HfO2), hafnium silicon oxide (HfSiO4), lanthanum oxide (La2O3), zirconium oxide (ZrO2), zirconium silicon oxide (ZrSiO4), tantalum oxide (Ta2O5), titanium oxide (TiO2), barium strontium titanium oxide (BaSrTi2O6), barium titanate (BaTiO3), strontium titanate (SrTiO3), yttrium oxide (Y2O3), aluminum oxide (Al2O3), lead scandium tantalum oxide (Pb(Sc,Ta)O3), and lead zinc niobate (Pb(Zn 1 / 3 Nb2 / 3 )at least one of O3).

[0129] The interlayer insulating layer 107 may be disposed on the gate electrode 136. The interlayer insulating layer 107 may include an inorganic insulating layer containing SiON, SiO x and / or SiNx, and may include a single layer or multiple layers.

[0130] The thin film transistor 130 may include a source electrode 138S and a drain electrode 138D respectively connected to the source region 132 and the drain region 133 of the semiconductor layer 134. The source electrode 138S and the drain electrode 138D may be electrically connected to the source region 132 and the drain region 133 of the semiconductor layer 134 respectively through contact holes passing through the gate insulating layer 103 and the interlayer insulating layer 107.

[0131] Each of the source electrode 138S and the drain electrode 138D may include at least one of Al, Cu, and Ti, and may include a single layer or multiple layers. In an exemplary embodiment of the present disclosure, each of the source electrode 138S and the drain electrode 138D may have a multilayer structure of titanium nitride / aluminum / titanium nitride (TiN / Al / TiN).

[0132] In the present exemplary embodiment, the data line DL (see Figure 4 ) and the driving voltage line PL (see Figure 4 ) may be formed on the same layer as the layer on which the source electrode 138S and the drain electrode 138D are disposed, and may include the same material as the source electrode 138S and the drain electrode 138D.

[0133] The thin film transistor 130 may be covered by a protective layer 109. The protective layer 109 may prevent wirings including metals (such as aluminum (Al)) that may be damaged by an etchant from being exposed to an etching environment during the process of manufacturing the display device 1. The protective layer 109 may extend to the non-display area NDA.

[0134] The planarization layer 113 is disposed on the protective layer 109 and includes an organic insulating material. The organic insulating material may include, for example, imide-based polymers, general polymers such as polymethyl methacrylate (PMMA) and polystyrene (PS), polymer derivatives having phenolic groups, acrylic polymers, aryl ether polymers, amide polymers, fluorine polymers, parylene polymers, vinyl alcohol polymers, or blends thereof. In an exemplary embodiment of the present disclosure, the planarization layer 113 may include polyimide.

[0135] The pixel electrode 210 is disposed on the planarization layer 113. The pixel defining layer 120 is disposed on the pixel electrode 210 and may include openings corresponding to each sub-pixel. The pixel defining layer 120 may define a pixel region, that is, an emission region PXA may be defined by an opening including at least a central portion of the exposed pixel electrode 210 (see Figure 8 ). In addition, the pixel defining layer 120 may prevent arcing or the like between the pixel electrode 210 and the common electrode 230 by increasing the distance between the edge of the pixel electrode 210 and the common electrode 230. The pixel defining layer 120 may include, for example, an organic material such as polyimide or a silicon-containing material such as hexamethyldisiloxane (HMDSO).

[0136] The intermediate layer 220 is disposed between the pixel electrode 210 and the common electrode 230 and may include a low molecular weight material or a polymer material.

[0137] When the intermediate layer 220 includes a low molecular weight material, the intermediate layer 220 may have a structure in which a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), an electron injection layer (EIL), etc. are stacked in a single structure or a composite structure. The emission layer (EML) may generate color light corresponding to the pixel and may be interposed between the hole transport layer (HTL) and the electron transport layer (ETL). The intermediate layer 220 may include various organic materials, such as, for example, copper phthalocyanine (CuPc), N,N'-bis(naphthalen-1-yl)-N,N'-diphenylbenzidine (NPB), and tris(8-hydroxyquinoline)aluminum (Alq3). These layers may be formed by vacuum deposition.

[0138] When the intermediate layer 220 includes a polymer material, the intermediate layer 220 may have a structure including an HTL and an EML. In this case, the HTL may include PEDOT, and the EML may include a polymer material such as poly(p-phenylene vinylene) (PPV)-like materials and / or polyfluorene-like materials.

[0139] The structure of the intermediate layer 220 is not limited thereto and may be various structures. For example, at least one of the layers constituting the intermediate layer 220 may be formed as an integral body with the common electrode 230. Alternatively, the intermediate layer 220 may include a patterned layer corresponding to each of the plurality of pixel electrodes 210.

[0140] The common electrode 230 may be disposed in the display area DA and may be disposed on the entire surface of the display area DA. For example, the common electrode 230 may be formed as an integral body to cover a plurality of pixels. The common electrode 230 may extend to a part of the non-display area NDA and may cover the valley portion VP.

[0141] In an exemplary embodiment of the present disclosure, the display unit 10 may be disposed in the display area DA and may include a light-emitting element, such as a light-emitting diode 200, electrically connected to the thin-film transistor 130. The light-emitting element may include a pixel electrode 210, a common electrode 230 disposed on the pixel electrode 210, and an emission layer (EML) disposed between the pixel electrode 210 and the common electrode 230. The pixel defining layer 120 may be disposed on the planarization layer 113 and include an opening that defines the emission area PXA of the light-emitting element (see Figure 8 ).

[0142] The encapsulation unit 150 may completely cover the display area DA and extend into the non-display area NDA to cover a part of the non-display area NDA. The encapsulation unit 150 may extend outside the common voltage supply line 70 and may be disposed on the common electrode 230.

[0143] The encapsulation unit 150 may include a first inorganic encapsulation layer 151, a second inorganic encapsulation layer 153, and an organic encapsulation layer 152 disposed between the first inorganic encapsulation layer 151 and the second inorganic encapsulation layer 153. In this case, the encapsulation unit 150 extending outside the common voltage supply line 70 includes the first inorganic encapsulation layer 151 and the second inorganic encapsulation layer 153. The organic encapsulation layer 152 may not extend outside the common voltage supply line 70. In an exemplary embodiment of the present disclosure, the encapsulation unit 150 may include at least one inorganic layer and at least one organic layer and may be disposed on a light-emitting element, such as a light-emitting diode 200, to encapsulate the light-emitting element.

[0144] The touch unit TU may be disposed on the encapsulation unit 150 (see Figure 8 ). For example, the touch unit TU may be directly disposed on the encapsulation unit 150. Depending on the situation, an inorganic insulating layer may be disposed on the encapsulation unit 150, and the touch unit TU may be directly disposed on the inorganic insulating layer (see Figures 10 to 12 ).

[0145] Referring to Figure 8 , a structure corresponding to the display area DA of the display panel DP and the touch unit TU is shown.

[0146] The touch unit TU includes a first conductive layer 310, a second conductive layer 320 disposed above the first conductive layer 310, a first insulating layer 312 disposed between the first conductive layer 310 and the second conductive layer 320, and a second insulating layer 322 disposed on the second conductive layer 320. The first conductive layer 310 and the second conductive layer 320 may respectively correspond to Figure 5 's first conductive layer CL1 and second conductive layer CL2, and the first insulating layer 312 and the second insulating layer 322 may respectively correspond to Figure 5The first insulating layer IL1 and the second insulating layer IL2.

[0147] The first conductive layer 310 and the second conductive layer 320 may correspond to Figure 6 The first sensing electrodes IE1-1, IE1-2, IE1-3, IE1-4, and IE1-5. As described above, since the first sensing electrodes IE1-1, IE1-2, IE1-3, IE1-4, and IE1-5 and the second sensing electrodes IE2-1, IE2-2, IE2-3, and IE2-4 do not overlap with the emission region PXA, the first sensing electrodes IE1-1, IE1-2, IE1-3, IE1-4, and IE1-5 and the second sensing electrodes IE2-1, IE2-2, IE2-3, and IE2-4 are not visible to the user. The first conductive layer 310 and the second conductive layer 320 may be electrically connected to each other through contact holes defined in the first insulating layer 312 in some regions.

[0148] Referring to Figure 7 In the non-display area NDA, a plurality of dummy pixels DPX may be adjacent to the light-emitting diodes 200. The dummy pixels DPX do not actually emit light and may include, for example, a patterned intermediate layer. The dummy pixels DPX may be located between the display area DA and the driving circuit area DPC-A.

[0149] The driving circuit area DPC-A is located in the non-display area NDA. For example, the first scan driver 20 is disposed in the driving circuit area DPC-A. The first scan driver 20 may include a thin-film transistor TFT-P and wirings connected to the thin-film transistor TFT-P. The thin-film transistor TFT-P may be formed during the same process as the thin-film transistor TFT forming the pixel circuit PC. The thin-film transistor TFT-P may be covered by a protective layer 109. The buffer layer 101, the gate insulating layer 103, the interlayer insulating layer 107, and the protective layer 109 may extend into the non-display area NDA. The buffer layer 101, the gate insulating layer 103, the interlayer insulating layer 107, and the protective layer 109 may all include an inorganic insulating material. The planarization layer 113 may be disposed on the protective layer 109 and may include an organic insulating material.

[0150] The first scan driver 20 may be covered by the protective layer 109. The protective layer 109 may prevent wirings including metals (such as aluminum (Al)) that may be damaged by an etchant from being exposed to an etching environment during the process of manufacturing the display device 1. Figure 7 It is shown in that the protective layer 109 is also disposed in the display area DA.

[0151] The protective layer 109 may include an inorganic material (such as SiO x 、SiN xFor example, SiN and / or SiON, and may include a single layer or multiple layers. In an exemplary embodiment of the present disclosure, the protective layer 109 may include SiN x . The protective layer 109 may have a thickness in the range of about to about .

[0152] The first dam unit DM1 and the second dam unit DM2 are disposed on the protective layer 109. In a plan view, the first dam unit DM1 and the second dam unit DM2 may surround the outside of the display area DA. For example, the first dam unit DM1 may surround the outside of the display area DA, and the second dam unit DM2 may surround the outside of the first dam unit DM1. The first dam unit DM1 and the second dam unit DM2 may prevent the organic encapsulation layer 152 of the encapsulation unit 150 from overflowing to the outside of the substrate 100.

[0153] The first dam unit DM1 may be located above the common voltage supply line 70, and the second dam unit DM2 may be located on one side of the first dam unit DM1 to cover one end of the common voltage supply line 70. One end 75A of the conductive layer 75 may be disposed between the first dam unit DM1 and the common voltage supply line 70. The conductive layer 75 may electrically connect the common voltage supply line 70 and the common electrode 230 to allow the common voltage to be transmitted to the common electrode 230. Here, one end 75A of the conductive layer 75 may include a portion of the conductive layer 75 that is directly connected to the common voltage supply line 70 and extends to the said one end of the common voltage supply line 70.

[0154] Although Figure 7 shows that the first dam unit DM1 has a double-layer structure and the second dam unit DM2 has a triple-layer structure, the present disclosure is not limited thereto. For example, in an exemplary embodiment of the present disclosure, the first dam unit DM1 and the second dam unit DM2 may have a single-layer structure or a structure of three or more layers.

[0155] The insulating layer ILL is disposed on the protective layer 109. The insulating layer ILL may include a first insulating layer ILL1 and a second insulating layer ILL2. The first insulating layer ILL1 may be disposed on the protective layer 109, and the second insulating layer ILL2 may be disposed on top of the first insulating layer ILL1. The conductive layer 75 may be located between the first insulating layer ILL1 and the second insulating layer ILL2.

[0156] The first insulating layer ILL1 may be an extension of the planarization layer 113 in the display area DA, and the second insulating layer ILL2 may be an extension of the pixel defining layer 120 in the display area DA. Accordingly, the first insulating layer ILL1 and the planarization layer 113 may be formed in the same process, and the second insulating layer ILL2 and the pixel defining layer 120 may be formed in the same process. Accordingly, the first insulating layer ILL1 may include layers and materials identical to those of the planarization layer 113, and the second insulating layer ILL2 may include layers and materials identical to those of the pixel defining layer 120.

[0157] The valley portion VP may be defined as a part of the insulating layer ILL. The valley portion VP may be formed by removing a part of the first insulating layer ILL1 and the second insulating layer ILL2. Since the insulating layer ILL includes, for example, an organic insulating material, the insulating layer ILL is vulnerable to penetration of external moisture. Accordingly, impurities that may be introduced into the display area DA through the insulating layer ILL may be blocked by removing a part of the insulating layer ILL outside the display area DA.

[0158] Although Figure 7 shows the valley portion VP disposed on the driving circuit area DPC-A, the present disclosure is not limited thereto. For example, in an exemplary embodiment of the present disclosure, the valley portion VP may not overlap with the driving circuit area DPC-A.

[0159] The touch unit TU is also disposed above the valley portion VP. Refer to Figure 10 for a detailed description of the touch unit TU corresponding to the non-display area NDA disposed above the valley portion VP.

[0160] Figure 9 is a cross-sectional view of a display panel DP' of a display device 1 according to an exemplary embodiment of the present disclosure. Figure 9 is Figure 7 a modified exemplary embodiment of Figure 9 which is Figure 7 different from Figure 7 in the structure of the display element layer below the light emitting diode 200. Hereinafter, the repeated description with reference to

[0161] is omitted, and the differences are mainly described. Figure 9 Referring to x the display area DA of x , the storage capacitor 140 includes a first storage capacitor plate 144 and a second storage capacitor plate 146 stacked on each other. The first interlayer insulating layer 105 may be disposed between the first storage capacitor plate 144 and the second storage capacitor plate 146. The first interlayer insulating layer 105 is a layer having a predetermined dielectric constant, and may include an inorganic insulating layer containing, for example, SiON, SiO

[0162] Figure 9 Illustrated is a case where the storage capacitor 140 is stacked with the thin film transistor 130 and the first storage capacitor plate 144 serves as the gate electrode 136 of the thin film transistor 130. However, the present disclosure is not limited thereto. For example, in an exemplary embodiment of the present disclosure, the storage capacitor 140 may not be stacked with the thin film transistor 130, and the first storage capacitor plate 144 may be a separate element independent of the gate electrode 136 of the thin film transistor 130.

[0163] The second interlayer insulating layer 107 may be disposed on the storage capacitor 140. The second interlayer insulating layer 107 may include an inorganic insulating layer containing, for example, SiON, SiO x and / or SiN x and may include a single layer or multiple layers.

[0164] The driving voltage line PL (see Figure 3 and Figure 4 ) may be disposed on the first planarization layer 111. The first planarization layer 111 may be disposed on the protective layer 109 and may include an organic insulating material. The driving voltage line PL may include at least one of Al, Cu, and Ti and may include a single layer or multiple layers. In an exemplary embodiment of the present disclosure, the driving voltage line PL may have a multilayer structure of Ti / Al / Ti.

[0165] Figure 9 Illustrated is a structure in which a lower driving voltage line PL1 disposed below the first planarization layer 111 is also provided. The lower driving voltage line PL1 may be electrically connected to the driving voltage line PL through a contact hole passing through the first planarization layer 111 to prevent a voltage drop of the driving voltage ELVDD provided through the driving voltage line PL.

[0166] The lower driving voltage line PL1 may include the same material as that of the data line DL. For example, the lower driving voltage line PL1 and the data line DL may include at least one of Al, Cu, and Ti and may include a single layer or multiple layers. In an exemplary embodiment of the present disclosure, the lower driving voltage line PL1 and the data line DL may have a multilayer structure of Ti / Al / Ti or titanium nitride / aluminum / titanium (TiN / Al / Ti).

[0167] The first planarization layer 111 includes an organic insulating material. The organic insulating material may include, for example, imide polymers, general polymers such as polymethyl methacrylate (PMMA) and polystyrene (PS), polymer derivatives having phenolic groups, acrylic polymers, aryl ether polymers, amide polymers, fluorine polymers, parylene polymers, vinyl alcohol polymers, or blends thereof. In an exemplary embodiment of the present disclosure, the first planarization layer 111 may include polyimide.

[0168] The driving voltage line PL is covered by the second planarization layer 113. The second planarization layer 113 may include an organic insulating material such as imide polymers, general polymers (such as polymethyl methacrylate (PMMA) and polystyrene (PS)), polymer derivatives having phenolic groups, acrylic polymers, aryl ether polymers, amide polymers, fluorine polymers, parylene polymers, vinyl alcohol polymers, or blends thereof. In an exemplary embodiment of the present disclosure, the second planarization layer 113 may include polyimide.

[0169] The pixel electrode 210 is disposed on the second planarization layer 113. The pixel defining layer 120 may be disposed on the pixel electrode 210 and may define an emission region PXA by including openings corresponding to each sub-pixel (i.e., openings that at least expose the central portion of the pixel electrode 210).

[0170] Referring Figure 9 to the non-display area NDA, the first dam unit DM1 and the second dam unit DM2 are disposed on the outermost portion of the substrate 100 in the non-display area NDA. In a plan view, the first dam unit DM1 and the second dam unit DM2 may surround the outside of the display area DA. For example, the first dam unit DM1 may surround the outside of the display area DA, and the second dam unit DM2 may surround the outside of the first dam unit DM1.

[0171] The first dam unit DM1 and the second dam unit DM2 may prevent the organic encapsulation layer 152 of the encapsulation unit 150 from overflowing to the outside of the substrate 100. Although Figure 9 it is shown in that the first dam unit DM1 has a three-layer structure and the second dam unit DM2 has a four-layer structure in, the present disclosure is not limited thereto. For example, in an exemplary embodiment of the present disclosure, the first dam unit DM1 and the second dam unit DM2 may have a single-layer structure, a double-layer structure, or a structure of five or more layers.

[0172] The first dam unit DM1 may be located above the common voltage supply line 70, and the second dam unit DM2 may be located on one side of the first dam unit DM1 to cover one end of the common voltage supply line 70. The connection line 72 may be arranged between the first dam unit DM1 and the common voltage supply line 70. For example, the connection line 72 may include the same material as the driving voltage line PL of the display area DA.

[0173] The conductive layer 75 may be arranged between the second insulating layer ILL2 and the third insulating layer ILL3. One end 75A of the conductive layer 75 may extend to the second dam unit DM2. One side of the conductive layer 75 may contact the common electrode 230 extending to the non-display area NDA, and the other side of the conductive layer 75 may contact the connection line 72 to electrically connect the common voltage supply line 70 and the common electrode 230, thereby transmitting the common voltage to the common electrode 230.

[0174] The insulating layer ILL is arranged on the protective layer 109 and may include a first insulating layer ILL1, a second insulating layer ILL2, and a third insulating layer ILL3. The first insulating layer ILL1 may be arranged on the protective layer 109, the second insulating layer ILL2 may be arranged on the first insulating layer ILL1, and the third insulating layer ILL3 may be arranged above the second insulating layer ILL2.

[0175] The first insulating layer ILL1 may include an extension of the first planarization layer 111 of the display area DA, the second insulating layer ILL2 may include an extension of the second planarization layer 113 of the display area DA, and the third insulating layer ILL3 may include an extension of the pixel defining layer 120 of the display area DA. Therefore, the first insulating layer ILL1 and the first planarization layer 111 may be formed in the same process, the second insulating layer ILL2 and the second planarization layer 113 may be formed in the same process, and the third insulating layer ILL3 and the pixel defining layer 120 may be formed in the same process. Therefore, the first insulating layer ILL1 may include the same layers and materials as the layers and materials of the first planarization layer 111, the second insulating layer ILL2 may include the same layers and materials as the layers and materials of the second planarization layer 113, and the third insulating layer ILL3 may include the same layers and materials as the layers and materials of the pixel defining layer 120.

[0176] The valley portion VP may be defined as a partial area of the insulating layer ILL and may be formed by removing a part of the first insulating layer ILL1, the second insulating layer ILL2, and the third insulating layer ILL3. Since the insulating layer ILL includes, for example, an organic insulating material, the insulating layer ILL is vulnerable to the penetration of external moisture. Therefore, impurities that may penetrate into the display area DA through the insulating layer ILL can be blocked by removing a part of the insulating layer ILL outside the display area DA.

[0177] Although it is shown in Figure 9 that the valley part VP is disposed above the driving circuit region DPC-A, the present disclosure is not limited thereto. For example, in an exemplary embodiment of the present disclosure, the valley part VP may be formed not to overlap with the driving circuit region DPC-A.

[0178] The touch unit TU is disposed above the valley part VP. Refer to Figure 10 for a detailed description of the valley part VP and the touch unit TU corresponding to the non-display region NDA located above the valley part VP.

[0179] Figure 10 and Figure 11 are cross-sectional views of a part of the display device 1 according to an exemplary embodiment of the present disclosure. Figure 12 is a cross-sectional view of a part of the display device 1 according to an exemplary embodiment of the present disclosure. Figure 10 and Figure 11 correspond to Figure 7 the valley part VP of Figure 12 correspond to Figure 9 the valley part VP of

[0180] Figures 10 to 12 [[ID=३०]]shows a structure in which the touch unit TU is disposed above the encapsulation unit 150 and the inorganic layer 160 is disposed between the touch unit TU and the encapsulation unit 150. Alternatively, the touch unit TU may be directly disposed on the second inorganic encapsulation layer 153. The polarization unit PU may be disposed on the touch unit TU.

[0181] Refer to Figure 10 and Figure 11 The valley part VP may be located in the insulating layer ILL. The valley part VP is formed by removing a part of the insulating layer ILL. The part where the valley part VP is formed may be defined as the valley region VPA.

[0182] The valley part VP may include a first opening OP1 defined in the first insulating layer ILL1 and a second opening OP2 defined in the second insulating layer ILL2. The width WO2 of the second opening OP2 may be greater than the width WO1 of the first opening OP1. Therefore, the valley part VP may have a stepped structure with two or more steps. The valley part VP may have, for example, an irregular shape or a stepped shape.

[0183] The inner surface of each of the first opening OP1 and the second opening OP2 constituting the valley part VP may be disposed in a conical inclined surface. Since it is difficult to form the inner surface of the opening at an exact 90° during the process of patterning the opening in the insulating layer, the inner surface of most openings has a conical inclined surface.

[0184] Because of the shape of the valley portion VP, light introduced from the outside is reflected by the inclined surface and / or the step difference of the valley portion VP, and thus the polarization of the light is changed. Therefore, light leakage occurs in which the light is not absorbed by the polarization unit PU and leaks to the outside.

[0185] The display device 1 according to the exemplary embodiment can prevent light leakage in which polarized light leaks to the outside due to the valley portion VP by covering the valley portion VP with the antireflection unit 330 of the touch unit TU disposed above the display panel DP.

[0186] The antireflection unit 330 may include layers and materials that are the same as those of the first conductive layer 310 (see Figure 8 ) and / or the second conductive layer 320 (see Figure 8 ) of the touch unit TU. Although Figure 10 and Figure 11 show a structure in which the antireflection unit 330 includes layers and materials that are the same as those of the second conductive layer 320 of the touch unit TU, the present disclosure is not limited thereto. For example, in the exemplary embodiment of the present disclosure, the antireflection unit 330 may include layers and materials that are the same as those of the first conductive layer 310 of the touch unit TU. In addition, in the exemplary embodiment of the present disclosure, the antireflection unit 330 may be arranged in a double layer and may include layers and materials that are the same as those of the first conductive layer 310 and the second conductive layer 320 of the touch unit TU.

[0187] The width W2 of the antireflection unit 330 may be greater than the width W1 of the valley portion VP. Since the antireflection unit 330 is designed to cover the valley portion VP from the influence of external light, it is preferable that the antireflection unit 330 has a width larger than the width of the valley portion VP. As a comparative example, it may be assumed that the width W2 of the antireflection unit 330 is the same as the width W1 of the valley portion VP. In this case, the obliquely incident light cannot be blocked, and thus light leakage may occur. In other words, the antireflection unit 330 not only needs to overlap with the entire valley portion VP, but also needs to surround an additional area of the portion overlapping with the valley portion VP to block the obliquely incident light. For example, in the exemplary embodiment of the present disclosure, in a plan view, the antireflection unit 330 may at least include a first portion that overlaps with the entire valley portion VP and a second portion that surrounds the first portion and does not overlap with the valley portion VP.

[0188] Figure 10 shows a case where the antireflection unit 330 is provided as a separate dummy layer DML (see Figures 13 to 15 ), Figure 11 shows a case where the antireflection unit 330 is provided as a wiring unit (for example, signal lines, protection lines GDL, antistatic discharge lines ESL, etc. that will be described in detail with reference to Figures 13 to 18 ) (see Figures 16 to 18The case of an extension part of ( )). In an exemplary embodiment of the present disclosure, the antireflection unit 330 may include at least one of a part of a signal line, a part of a guard line GDL, a part of an electrostatic discharge line ESL, and a part of a dummy layer DML disposed on one side of the signal line.

[0189] Referring to Figure 6 , in an exemplary embodiment of the present disclosure, the dummy layer DML may be disposed between a first signal line (e.g., SL1-1) disposed at the outermost part among a plurality of first signal lines (e.g., SL1-1, SL1-2, SL1-3, SL1-4, and SL1-5) and a second signal line (e.g., SL2-1) disposed at the outermost part among a plurality of second signal lines (e.g., SL2-1, SL2-2, SL2-3, and SL2-4).

[0190] Referring to Figure 12 , the valley portion VP is located in the insulating layer ILL. The valley portion VP is formed by removing a part of the insulating layer ILL, and the portion where the valley portion VP is formed may be defined as a valley region VPA.

[0191] The valley portion VP may include a first opening OP1 defined in the first insulating layer ILL1, a second opening OP2 defined in the second insulating layer ILL2, and a third opening OP3 defined in the third insulating layer ILL3. The width WO2 of the second opening OP2 may be greater than the width WO1 of the first opening OP1, and the width WO3 of the third opening OP3 may be greater than the width WO2 of the second opening OP$. Therefore, the valley portion VP may have a stepped structure with three or more steps. In addition, the inner surface of each of the first opening OP1 to the third opening OP3 constituting the valley portion VP may be provided in a conical inclined surface.

[0192] The width W2 of the antireflection unit 330 may be greater than the width W1 of the valley portion VP. Since the antireflection unit 330 is designed to cover the valley portion VP from the influence of external light, it is preferable that the antireflection unit 330 has a width greater than the width of the valley portion VP. Therefore, the obliquely incident light can be blocked and light leakage does not occur.

[0193] The antireflection unit 330 may include one or more layers identical to one or more layers of the first conductive layer 310 (see Figure 8 ) and / or the second conductive layer 320 (see Figure 8 ) of the touch unit TU and one or more materials identical to one or more materials of the first conductive layer 310 (see Figure 8 ) and / or the second conductive layer 320 (see Figure 8 ) of the touch unit TU. Similarly Figure 11 , Figure 12Shows a structure in which the antireflection unit 330 may include layers and materials that are the same as those of the second conductive layer 320 of the touch unit TU. In addition, although Figure 12 shows a case where the antireflection unit 330 is provided as a separate dummy layer DML, as Figure 11 shown, the antireflection unit 330 may be provided as an extension of, for example, a signal line, a guard line GDL, an electrostatic discharge line ESL, etc. In an exemplary embodiment of the present disclosure, at least a part of the signal line may overlap with the valley portion VP, and the antireflection unit 330 may include at least a part of the signal line.

[0194] Figures 13 to 18 Is a plan view of a part of the display device 1 according to an exemplary embodiment of the present disclosure. Figures 13 to 18 May respectively roughly correspond to Figure 6 parts AA, BB, CC, DD, and EE, and Figure 16 and Figure 17 both roughly correspond to Figure 6 part DD. Therefore, in each plan view of Figures 13 to 18 , the thickness, shape, and position of each component may be changed. Specifically, the width of the signal wiring may be changed according to the density of the signal wiring. For example, in a region where the density of the signal wiring is low, each signal wiring may have a relatively large width. In a region where the density of the signal wiring is high, each signal wiring may have a relatively small width.

[0195] Referring to Figures 13 to 18 , the antireflection unit 330 may include at least a part of the dummy layer DML, the electrostatic discharge line ESL, and the guard line GDL. Figures 13 to 15 Shows a case where the dummy layer DML is provided as the antireflection unit 330, Figure 16 and Figure 18 shows a case where the electrostatic discharge line ESL is provided as the antireflection unit 330, Figure 17 shows a case where the guard line GDL is provided as the antireflection unit 330.

[0196] Figure 13 May roughly correspond to Figure 6 the upper right end, that is, part AA. In addition, Figure 13 the line B-B' of Figure 10 or Figure 12 may correspond to the cross section of

[0197] Referring to Figure 13 , the dummy layer DML is disposed between the first signal line SL1 and the electrostatic discharge line ESL. The dummy layer DML may have an isolated structure without being connected to any wiring.

[0198] Referring toFigure 6 The upper right end of the touch unit TU can be understood as the part where at least the first signal lines SL1-1, SL1-2, SL1-3, SL1-4, and SL1-5 are arranged. In addition, the upper right end of the touch unit TU can be the part where at least the second signal lines SL2-1, SL2-2, SL2-3, and SL2-4 are arranged. Only the first signal line SL1-1 and the second signal line SL2-1 can be arranged in the corner area at the upper right end of the touch unit TU. The first signal line SL1-1 is arranged at the outermost part among the multiple first signal lines (e.g., SL1-1, SL1-2, SL1-3, SL1-4, and SL1-5), and the second signal line SL2-1 is arranged at the outermost part among the multiple second signal lines (e.g., SL2-1, SL2-2, SL2-3, and SL2-4). Therefore, compared with the corner area where the first signal lines SL1-1, SL1-2, SL1-3, SL1-4, and SL1-5 or the second signal lines SL2-1, SL2-2, SL2-3, and SL2-4, which are set as multiple signal lines, are densely arranged, the valley part VP is directly exposed at the corner area of the upper right end of the touch unit TU. Therefore, in the corner area at the upper right end of the touch unit TU, a dummy layer DML can also be provided between the first signal line SL1 and the antistatic discharge line ESL and between the second signal line SL2 and the antistatic discharge line ESL.

[0199] In Figure 13 the dummy layer DML is not arranged as a whole to prevent reflection, but has a shape in which multiple blocks are discontinuously arranged. In an exemplary embodiment of the present disclosure, the dummy layer DML can be formed as a whole according to the area of the region where the dummy layer DML is arranged.

[0200] A part of the dummy layer DML can be set as the antireflection unit 330, and the remaining part of the dummy layer DML can be set to adjust the wiring density in the region between the first signal line SL1 and the antistatic discharge line ESL.

[0201] The antireflection unit 330 can include the dummy layer DML. In Figure 13 the valley part VP located in the valley area VPA is arranged to extend in the second direction D2 and is located on one side of the antistatic discharge line ESL. Since the valley part VP is covered by the dummy layer DML, the problem that the valley part VP is visible to the outside due to external light reflection can be prevented.

[0202] Although in Figure 13A separate dummy layer DML is shown covering the valley portion VP on the valley portion VP, but the present disclosure is not limited thereto. For example, in an exemplary embodiment of the present disclosure, when the valley portion VP is adjacent to the antistatic discharge line ESL, a part of the antistatic discharge line ESL may extend to cover the valley portion VP.

[0203] Figure 14 may roughly correspond to Figure 6 the upper left end of, that is, part BB. In addition, Figure 15 may roughly correspond to Figure 6 the lower left end of, that is, part CC. Figure 14 and Figure 15 the line B-B' of may correspond to Figure 10 or Figure 12 the cross-section of.

[0204] Referring to Figure 14 and Figure 15 , the dummy layer DML is disposed between the second signal lines SL2-1, SL2-2, SL2-3, and SL2-4 and the antistatic discharge line ESL. The dummy layer DML may be disposed only on the valley portion VP as shown in Figure 14 , and may be disposed to fill the space between the second signal lines SL2-1, SL2-2, SL2-3, and SL2-4 and the antistatic discharge line ESL as shown in Figure 15 .

[0205] The antireflection unit 330 may include the dummy layer DML or a part of the dummy layer DML. Similar to the cross-section of Figure 10 or Figure 12 , the antireflection unit 330 may be stacked with the valley portion VP. As described above, the antireflection unit 330 may prevent the valley portion VP from being seen from the outside due to external light reflection by covering the valley portion VP.

[0206] Figure 16 may roughly correspond to Figure 6 the lower right end of, that is, part DD. In addition, Figure 16 the line C-C' of may correspond to Figure 11 the cross-section of.

[0207] Referring to Figure 16 , the antireflection unit 330 may include the antistatic discharge line ESL. Although the valley portion VP partially overlaps with the antistatic discharge line ESL, a partial area of the valley portion VP does not overlap with the antistatic discharge line ESL. In this case, a part of the antistatic discharge line ESL extends to cover the valley portion VP. For example, at least a part of the antistatic discharge line ESL may overlap with the valley portion VP. In other words, the valley portion VP may be covered by a part of the antistatic discharge line ESL.

[0208] InFigure 11 Among them, the wiring unit may include at least one of, for example, signal lines, a guard line GDL, and an electrostatic discharge line ESL. The wiring unit may include a bilayer including a first conductive layer 310 and a second conductive layer 320. The first conductive layer 310 and the second conductive layer 320 constituting the wiring unit may be connected to each other through contact holes defined in the first insulating layer 312.

[0209] The antireflection unit 330 may be provided by extending the second conductive layer 320 of the wiring unit. In Figure 16 Among them, a part of the second conductive layer 320 of the electrostatic discharge line ESL extends in the first direction D1 to completely cover the valley portion VP.

[0210] Figure 17 is Figure 16 a modified exemplary embodiment and shows a case where the antireflection unit 330 includes the guard line GDL. Figure 17 may roughly correspond to Figure 6 the lower right end of

[0211] The guard line GDL may be disposed at the outermost portion (i.e., one side of the first signal line SL1-1) of the first signal lines SL1-1, SL1-2, ……, SL1-5. The guard line GDL may prevent the signals of the first signal lines SL1-1, SL1-2, ……, SL1-5 from being interfered by the signals of other wirings. For example, the guard line GDL may prevent signal interference to the signal line SL1. Alternatively, the guard line GDL may be disposed at the outermost portion of the second signal lines SL2-1, SL2-2, ……, SL2-4 and disposed between the first signal lines SL1-1, SL1-2, ……, SL1-5 and the second signal lines SL2-1, SL2-2, ……, SL2-4.

[0212] Since the guard line GDL is disposed at the outermost portion of the first signal lines SL1-1, SL1-2, ……, SL1-5, a part of the guard line GDL may extend and may be used as the antireflection unit 330 as shown in Figure 17 Among them. The guard line GDL may extend in the first direction D1 to the valley portion VP. As described above with reference to Figure 11 and Figure 16 The guard line GDL is provided as a bilayer including the first conductive layer 310 and the second conductive layer 320, and a part of the second conductive layer 320 may extend to overlap with the valley portion VP. For example, at least a part of the guard line GDL may overlap with the valley portion VP, and the antireflection unit 330 may include at least a part of the guard line GDL. In other words, the valley portion VP may be covered by a part of the guard line GDL.

[0213] In view of the above description, a portion of the signal line, the protective line GDL, and / or the anti-static discharge line ESL of the wiring unit adjacent to the valley portion VP may extend and may be used as the anti-reflection unit 330 according to the position of the valley portion VP.

[0214] Figure 18 can roughly correspond to Figure 6 the upper right end of, that is, the portion EE.

[0215] Referring to Figure 18 as described with reference to Figure 6 the upper right end of the touch unit TU can be understood as the portion where at least the first signal lines SL1-1, SL1-2, SL1-3, SL1-4, and SL1-5 are arranged, and can also be understood as the portion where at least the second signal lines SL2-1, SL2-2, SL2-3, and SL2-4 are arranged. Therefore, as shown in Figure 18 the dummy layer DML can be arranged wider inside the anti-static discharge line ESL.

[0216] The anti-reflection unit 330 may include the anti-static discharge line ESL. As in Figure 18 the anti-static discharge line ESL may be completely superimposed on the valley portion VP. Therefore, as described above, the anti-reflection portion 330 can prevent the problem that the valley portion VP is seen from the outside due to external light reflection by covering the valley portion VP.

[0217] Because the light introduced from the outside is reflected by the inclined surface and / or the step difference of the valley portion VP due to the shape of the valley portion VP and thus the polarization of the light is changed, light leakage may occur in which the light is not absorbed by the polarization unit PU and leaks to the outside.

[0218] The display device 1 according to the present exemplary embodiment can prevent light leakage in which polarized light leaks to the outside due to the valley portion VP by covering the valley portion VP with the anti-reflection unit 330 of the touch unit TU arranged above the display panel DP.

[0219] Although only the display device has been mainly described so far, the present disclosure is not limited thereto. For example, a method of manufacturing a display device also falls within the scope of the present disclosure.

[0220] According to the exemplary embodiment of the present disclosure, a display device in which defects caused by external light reflection in the non-display area are minimized can be realized. However, the scope of the present disclosure is not limited by this effect.

[0221] Although the present disclosure has been described with reference to example embodiments shown in the accompanying drawings, these example embodiments are provided only as examples, and those of ordinary skill in the art will understand that various changes in form and detail may be made therein without departing from the spirit and scope of the present disclosure as defined by the appended claims and their equivalents.

Claims

1. A display device, the display device comprising: a display panel, a touch unit disposed on the display panel, and a window disposed above the touch unit, wherein the display panel comprises: a substrate including a display area and a non-display area disposed around the display area; an insulator including a valley portion defined as an opening disposed along the outer side of the display area in the non-display area; a display unit disposed in the display area and including a light-emitting element electrically connected to a thin-film transistor; and a thin-film encapsulation layer on the display unit, and wherein the touch unit comprises: a wiring layer superposed with the valley portion and disposed between the thin-film encapsulation layer and the window.

2. The display device according to claim 1, wherein, The touch unit is directly disposed on the display panel and comprises: sensing electrodes corresponding to the display area; and signal lines corresponding to the non-display area and electrically connected to the sensing electrodes.

3. The display device according to claim 2, wherein, The sensing electrodes comprise: a first conductive layer; a second conductive layer disposed above the first conductive layer; a first insulating layer disposed between the first conductive layer and the second conductive layer; and a second insulating layer disposed on the second conductive layer.

4. The display device according to claim 3, wherein, The wiring layer comprises a material the same as that of the second conductive layer.

5. The display device according to claim 2, wherein, The touch unit further comprises: an anti-static discharge line disposed on the outer side of the signal lines, and at least a part of the anti-static discharge line is superposed with the valley portion.

6. The display device according to claim 5, wherein, The wiring layer comprises at least a part of the anti-static discharge line.

7. The display device according to claim 5, wherein, A constant voltage is applied to the anti-static discharge line.

8. The display device according to claim 5, wherein the display device further includes a dummy layer between the outside of the signal line and the static electricity discharge prevention line, where The dummy layer is separated from the signal lines and the anti-static discharge line.

9. The display device according to claim 8, wherein, The anti-static discharge line is completely superposed with the valley portion.

10. The display device according to claim 1, wherein, The width of the wiring layer is greater than the width of the valley portion.

11. The display device according to claim 1, wherein, The thin-film encapsulation layer comprises: a first inorganic encapsulation layer; a second inorganic encapsulation layer disposed above the first inorganic encapsulation layer; and an organic encapsulation layer disposed between the first inorganic encapsulation layer and the second inorganic encapsulation layer, and wherein the touch unit is disposed on the second inorganic encapsulation layer.

12. The display device according to claim 1, the display device further comprising a polarization unit between the touch unit and the window.

13. The display device according to claim 1, wherein, The insulator comprises an organic insulating material.

14. A display device, the display device comprising: a substrate including a display area and a non-display area disposed around the display area; a display unit disposed in the display area and including a light-emitting element electrically connected to a thin-film transistor; an insulator extending from the display area and including a valley portion defined as an opening disposed along the outer side of the display area, and at least a part of the insulator is disposed in the non-display area; a thin-film encapsulation layer including at least one inorganic layer and at least one organic layer, and disposed on the light-emitting element to encapsulate the light-emitting element; A touch unit is disposed on the thin film encapsulation layer and includes a sensing electrode corresponding to the display area, a signal line corresponding to the non-display area and connected to the sensing electrode, and an anti-static discharge line disposed outside the signal line, and at least a part of the anti-static discharge line overlaps with the valley portion.

15. The display device according to claim 14, wherein, A constant voltage is applied to the anti-static discharge line.

16. The display device according to claim 14, further comprising a dummy layer between the outside of the signal line and the static electricity discharge prevention line, wherein, The dummy layer is separated from the signal line and the anti-static discharge line.

17. The display device according to claim 16, wherein, The anti-static discharge line completely overlaps with the valley portion.

18. The display device according to claim 14, wherein, The width of the anti-static discharge line is greater than the width of the valley portion.

19. The display device according to claim 14, further comprising a window disposed above the touch unit and a polarization unit between the touch unit and the window.

20. The display device according to claim 14, wherein, The insulating member includes an organic insulating material.

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