Display panel and display device

Abstract

The invention relates to a display panel and a display device, and relates to the technical field of display, the display panel comprises pixel rows arranged along a first direction and pixel columns arranged along a second direction, and the pixel rows and the pixel columns comprise a plurality of sub-pixels; each sub-pixel comprises a light-emitting layer and a cathode layer, the cathode layer is located on one side of the light-emitting layer, and the cathode layer comprises cathode blocks; the sub-pixels comprise a first color sub-pixel and a second color sub-pixel, the cathode block corresponding to the first color sub-pixel is connected with the first signal line, the cathode block corresponding to the second color sub-pixel is connected with the second signal line, and the voltage of the first signal line is different from that of the second signal line. Therefore, through the patterning design of the cathode, the cathode voltage of the sub-pixels with different colors can be independently adjusted, the transmittance of the display panel can be improved, the power consumption is reduced, and the brightness uniformity and the Jinjin color cast are improved.

Description

Technical Field

[0001] The present disclosure relates to the field of display technologies, and particularly to a display panel and a display device. Background Art

[0002] With the increasing integration of products, it has become increasingly difficult to design high-performance products in limited space. From the CRT (Cathode Ray Tube) era to the LCD (Liquid Crystal Display) era, and then to the current OLED (Organic Light-Emitting Diode) era and light-emitting diode display era, the display industry has undergone decades of development and has changed rapidly. The display industry has become closely related to our lives. Display technologies are indispensable in traditional electronic devices such as mobile phones, tablets, TVs, and PCs, as well as in current smart wearable devices, VR, in-vehicle displays, and other electronic devices.

[0003] With the development of display technologies, users have higher and higher requirements for display products. How to reduce the power consumption of the display panel and improve the transmittance has become one of the technical problems to be solved urgently at present. Summary of the Invention

[0004] To solve the above technical problems, the present disclosure provides a display panel and a display device for reducing the power consumption of the display panel and improving the transmittance.

[0005] In a first aspect, the present disclosure provides a display panel, including: a display area, the display area including pixel rows arranged along a first direction and pixel columns arranged along a second direction, the first direction intersecting with the second direction; the pixel rows and the pixel columns including a plurality of sub-pixels;

[0006] The sub-pixels include a light-emitting layer and a cathode layer, the cathode layer being located on one side of the light-emitting layer; the cathode layer includes cathode blocks and cathode lines for connecting the cathode blocks;

[0007] The sub-pixels include pixel apertures, the sub-pixels include first-color sub-pixels and second-color sub-pixels, the cathode blocks corresponding to the first-color sub-pixels being connected to a first signal line, the cathode blocks corresponding to the second-color sub-pixels being connected to a second signal line, and the voltages of the first signal line and the second signal line being different.

[0008] In a second aspect, the present disclosure provides a display device including the display panel as described in the first aspect.

[0009] The technical solutions provided by the embodiments of the present disclosure have the following advantages compared with the prior art: In the display panel and the display device provided by the present disclosure, the cathode layer includes cathode blocks and cathode lines. The cathode lines are used to connect the cathode blocks. By patterning the cathode layer, the cathode blocks corresponding to different color sub-pixels are independent of each other, so as to reduce the light shielding of the non-emitting area by the cathode layer and improve the transmittance of the display panel. The sub-pixel includes a pixel opening. The sub-pixel includes a first color sub-pixel and a second color sub-pixel. The cathode block corresponding to the first color sub-pixel is connected to a first signal line, and the cathode block corresponding to the second color sub-pixel is connected to a second signal line. The voltages of the first signal line and the second signal line are different. In this way, by connecting the cathode blocks corresponding to different color sub-pixels to different signal lines, the cathode voltage corresponding to each color sub-pixel can be matched according to the luminous efficiency of the different color sub-pixels. Compared with the increase in power consumption and the aggravation of color deviation caused by all sub-pixels sharing a common cathode, the embodiments of the present disclosure can reduce the power consumption of the display panel and improve the brightness uniformity. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The accompanying drawings herein are incorporated into the specification and form a part of the specification, showing embodiments consistent with the present disclosure and, together with the specification, are used to explain the principles of the present disclosure.

[0011] To more clearly illustrate the technical solutions in the embodiments of the present disclosure or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, for those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0012] Figure 1 It shows a schematic diagram of the evaporation range of the cathode in the display panel in the related art;

[0013] Figure 2 As shown in Figure 1 an enlarged view of the dashed area in

[0014] Figure 3 It shows a plan view of a display panel provided by an embodiment of the present disclosure;

[0015] Figure 4 As shown in Figure 3 a cross-sectional view along B-B;

[0016] Figure 5 It shows a plan view of a cathode layer provided by an embodiment of the present disclosure;

[0017] Figure 6 It shows a schematic diagram of the structure of a display panel provided by an embodiment of the present disclosure;

[0018] Figure 7The following is a schematic structural diagram of another display panel provided by an embodiment of the present disclosure;

[0019] Figure 8 The following is a schematic diagram of a display device provided by an embodiment of the present disclosure. Detailed implementation manners

[0020] In order to more clearly understand the above objects, features, and advantages of the present disclosure, the solutions of the present disclosure will be further described below. It should be noted that, without conflict, the embodiments of the present disclosure and the features in the embodiments may be combined with each other.

[0021] Many specific details are set forth in the following description in order to fully understand the present disclosure, but the present disclosure may also be implemented in other ways different from those described herein; obviously, the embodiments in the specification are only a part of the embodiments of the present disclosure, rather than all the embodiments.

[0022] Figure 1 The following is a schematic diagram of the evaporation range of the cathode in the display panel in the related art. Figure 2 The following is shown as Figure 1 an enlarged view of the dashed area in Figure 1 and Figure 2 , the display panel 100' includes a display area AA' and a non-display area NA', the non-display area NA' is located on at least one side of the display area AA', and the cathode layer 00' covers the display area AA' and the non-display area NA'. Area 01' is a certain area at the junction of the display area AA' and the non-display area NA'. Please refer to Figure 2 , the display area AA' includes a plurality of anodes 02', the cathode layer 00' covers all the anodes 02' in the display area AA', that is, the sub-pixels in the display area AA' share a cathode, and the same cathode voltage is input to this cathode. However, the light emission efficiencies of different color sub-pixels are not the same. When the cathode voltages input to different color sub-pixels are the same, it will increase the device power consumption and cause color deviation. Currently, AMOLED (Active-matrix organic light-emitting diode) products form the light-emitting element layer in the form of evaporation. The light-emitting element layer includes an anode layer, a light-emitting layer, and a cathode layer 00'. In the manufacturing process, first, the anode layer is evaporated and formed on the driving substrate, and then the light-emitting layer and the cathode layer 00' are evaporated on the anode layer. Please refer to Figure 1 , the cathode layer 00' of AMOLED products is usually formed by full-surface evaporation. The material of the full-surface evaporated cathode layer 00' of conventional AMOLED products is Mg-Ag alloy. The full-surface evaporated cathode layer 00' is located in both the display area AA' and the non-display area NA' at the same time, resulting in the light transmittance of the display area AA' of such products being only about 50%, greatly losing the light transmittance of the non-anode light-emitting area.

[0023] In view of the above problems, the present disclosure provides a display panel 100 for improving the transmittance of the display area AA. Figure 3 The following is a schematic plan view of a display panel provided by an embodiment of the present disclosure. Figure 4 As shown in Figure 3 the cross-sectional view along B-B. Figure 5 The following is a schematic plan view of a cathode layer provided by an embodiment of the present disclosure. Please refer to Figures 3 to 5 The present disclosure provides a display panel 100, including: a display area AA, the display area AA includes pixel rows P1 arranged along a first direction D1 and pixel columns P2 arranged along a second direction D2, and the first direction D1 intersects with the second direction D2. Figure 3 Only for illustration purposes, the first direction D1 is taken as the row direction and the second direction D2 is taken as the column direction. It can be understood that the first direction D1 can be the column direction and the second direction D2 can be the row direction, and the present disclosure does not limit this.

[0024] The pixel rows P1 and the pixel columns P2 include a plurality of sub-pixels P0, and the sub-pixels P0 include a red sub-pixel R, a green sub-pixel G, and a blue sub-pixel B. Please refer to Figure 4 The display panel 100 includes a substrate 10, a driving layer 20, a light-emitting element layer 30, and a packaging layer 40. The driving layer 20 is located on the side of the substrate 10 facing the light-emitting element layer 30. The driving layer 20 includes a plurality of transistors T. The light-emitting element layer 30 includes a plurality of sub-pixels P0. The transistors T are used to drive the sub-pixels P0 to emit light. The light-emitting element layer 30 includes an anode layer 32, a light-emitting layer 33, and a cathode layer 31. The cathode layer 31 is located on the side of the light-emitting layer 33 facing away from the anode layer 32. The anode layer 32 includes a first anode portion 36. The cathode layer 31 includes a cathode block 34. When the power supply supplies an appropriate voltage, the holes of the first anode portion 36 and the electrons of the cathode block 34 will combine in the light-emitting layer 33 to generate light. It should be noted that Figure 5 in RGB only indicates the position of the cathode block 34 corresponding to the sub-pixel P0. Actually, the structure of the sub-pixel P0 needs to refer to Figure 4 . Please refer to Figure 5, the cathode layer 31 further includes cathode lines 35 for connecting the cathode blocks 34. The cathode lines 35 and the cathode blocks 34 can be formed by performing a mask evaporation process on the cathode material. In an alternative embodiment provided by the present disclosure, the shapes or sizes of the cathode blocks 34 corresponding to different color sub-pixels P0 are different. For example, the area of the cathode block 34 corresponding to the red sub-pixel R is smaller than the area of the cathode block 34 corresponding to the blue sub-pixel B, and the area of the cathode block 34 corresponding to the green sub-pixel G is smaller than the area of the cathode block 34 corresponding to the blue sub-pixel B... The present disclosure does not limit the relative size relationship of the cathode blocks 34, as long as the cathode layer 31 is patterned and the cathode blocks 34 corresponding to different color sub-pixels P0 are independent of each other. It can be understood that when the cathode layer 31 is patterned, the cathode blocks 34 are only provided at positions corresponding to the light-emitting regions in the cathode layer 31, and no cathode blocks 34 are provided in the portions outside the light-emitting regions, which can improve the transmittance of the non-light-emitting regions of the display panel 100. Through experimental verification by the inventor, the transmittance can be increased by about 50% on the basis of the existing process.

[0025] Please refer to Figure 5 , the sub-pixel P0 includes a pixel opening; the sub-pixel P0 includes a first color sub-pixel P11 and a second color sub-pixel P12. The cathode block 34 corresponding to the first color sub-pixel P11 is connected to the first signal line 11, and the cathode block 34 corresponding to the second color sub-pixel P12 is connected to the second signal line 12. The voltages of the first signal line 11 and the second signal line 12 are different.

[0026] Specifically, due to different luminous efficiencies of different color sub-pixels P0, the sizes of the corresponding pixel openings are different. For example, the green sub-pixel G has the highest luminous efficiency, so the pixel opening corresponding to the green sub-pixel G is the smallest, and the blue sub-pixel B has the lowest luminous efficiency, so the pixel opening corresponding to the blue sub-pixel B is the largest; correspondingly, the area of the cathode block 34 corresponding to the green sub-pixel G is the smallest, the area of the cathode block 34 corresponding to the red sub-pixel R is larger than the area of the cathode block 34 corresponding to the green sub-pixel G, and the area of the cathode block 34 corresponding to the blue sub-pixel B is the largest. By setting the cathode blocks 34 with corresponding sizes based on the pixel openings of different color sub-pixels P0, while ensuring the normal light emission of the sub-pixels P0, the evaporation area of the cathode layer 31 can be reduced, the light shielding of the non-light-emitting regions can be reduced, and the transmittance of the display panel 100 can be improved.

[0027] In an alternative embodiment provided by the present disclosure, the first color sub-pixel P11 is a red sub-pixel R, and the first cathode block 38 corresponding to the red sub-pixel R is connected to the first signal line 11. The first signal line 11 can be a voltage signal line. The second color sub-pixel P12 is a green sub-pixel G, and the second cathode block 39 corresponding to the green sub-pixel G is connected to the second signal line 12. The second signal line 12 can be a voltage signal line, and the voltage of the second signal line 12 is different from that of the first signal line 11. When the central brightness of the display panel 100 is constant, the current flowing through the display panel 100 is constant, and the anode voltages of different color sub-pixels P0 are the same, for example, 4.6V. According to the formula P = UI, the power consumption of each sub-pixel P0 can be simply calculated by multiplying the current flowing through the sub-pixel P0 by the voltage difference between its anode voltage and cathode voltage. In the related art, different color sub-pixels are controlled by the same cathode voltage, for example, -3.0V. At this time, the voltage difference between the cathode voltage and the anode voltage of the green sub-pixel is 7.6V. In this embodiment, for the luminous efficiency of different color sub-pixels P0, the voltages of the first color sub-pixel P11 and the second color sub-pixel P12 are controlled separately. For example, in order to turn on the blue sub-pixel B, the cathode voltages corresponding to the first color sub-pixel P11 and the third color sub-pixel P13 are set to -3.0V. Since the luminous efficiency of the green sub-pixel G is relatively high, only by setting the cathode voltage of the green sub-pixel G to -2.5V can it be turned on. At this time, the voltage difference between the anode voltage and the cathode voltage of the green sub-pixel G is 7.1V. The power consumption of the green sub-pixel G in the embodiment of the present disclosure is lower than that of the green sub-pixel in the related art. Thus, according to the luminous efficiency of different color sub-pixels P0, the cathode voltages corresponding to different color sub-pixels P0 are controlled separately, which can reduce the power consumption of the display panel 100.

[0028] It should be noted that the above values of the cathode voltages are only examples and do not represent the cathode voltages of each sub-pixel P0 in the actual process. They can be specifically set according to the actual situation.

[0029] Through experimental verification by the inventor, when the distance between the cathode block 34 corresponding to two adjacent first color sub-pixels P11 along the second direction D2 and the cathode block 34 corresponding to the third color sub-pixel is set in the range greater than or equal to 27μm, the following can be achieved Figure 5The arrangement of the cathode blocks 34 shown. Optionally, the cathode blocks 34 corresponding to two adjacent first-color sub-pixels P11 along the second direction D2 and the cathode blocks 34 corresponding to the third-color sub-pixels may be greater than or equal to 28 μm, or may also be greater than or equal to 29 μm, or may also be greater than or equal to 30 μm... and so on, which will not be listed one by one here. Exemplarily, the distance between the cathode blocks 34 corresponding to two adjacent first-color sub-pixels P11 along the second direction D2 and the cathode blocks 34 corresponding to the third-color sub-pixels may be 27 μm, 30 μm, etc. In actual process fabrication, a fine metal mask can be used for evaporation plating twice. For the first evaporation plating, the first cathode blocks 38 corresponding to the first-color sub-pixels P11 (one row or one column) are formed; for the second evaporation plating, the second cathode blocks 39 corresponding to the second-color sub-pixels P12 (one row or one column) are formed. Further, the first cathode blocks 38 corresponding to the first-color sub-pixels P11 are connected to the first signal line 11 on the left side of the display area AA, and the second cathode blocks 39 corresponding to the second-color sub-pixels P12 are connected to the second signal line 12 on the right side of the display area AA. It can be understood that the evaporation plating order of the first cathode blocks 38 corresponding to the first-color sub-pixels P11 and the second cathode blocks 39 corresponding to the second-color sub-pixels P12 can be swapped, and further, the positions of the first signal line 11 and the second signal line 12 can also be swapped.

[0030] In this way, by patterning the cathode layer 31 in the display panel 100, the cathode blocks 34 corresponding to different color sub-pixels P0 can be independently set, and further, the voltages of the first signal line 11 connected to the first-color sub-pixels P11 and the second signal line 12 connected to the second-color sub-pixels P12 can be set differently to reduce power consumption and improve the brightness uniformity of the display panel 100; in addition, cathode blocks 34 may not be provided in the part of the cathode layer 31 other than the light-emitting area to improve the transmittance of the display panel 100 and increase the display brightness.

[0031] Figure 6 The following is a schematic diagram of a display panel structure provided by an embodiment of the present disclosure. Please refer to Figures 3 to 6 The present disclosure provides a display panel 100, which includes a non-display area NA located on at least one side of the display area AA; a first signal line 11 and a second signal line 12 are respectively located in the non-display areas NA on both sides of the display area AA; the non-display area NA includes a gate driving circuit 21, and in the non-display area NA, the first signal line 11 or the second signal line 12 overlaps with the gate driving circuit 21.

[0032] Specifically, the non-display area NA can be located on one or both sides of the display area AA along the first direction D1; alternatively, the non-display area NA can be located on one or both sides of the display area AA along the second direction D2; or, the non-display area NA is located on one or both sides of the display area AA along the first direction D1, and the non-display area NA is located on one or both sides of the display area AA along the second direction D2; the present disclosure does not specifically limit the position of the non-display area NA. Figure 6 It is schematically shown that the non-display area NA is located on both sides of the display area AA along the first direction D1.

[0033] The first signal line 11 and the second signal line 12 are respectively located in the non-display area NA on both sides of the display area AA along the first direction D1, or the first signal line 11 and the second signal line 12 are respectively located in the non-display area NA on both sides of the display area AA along the second direction D2; that is, the first signal line 11 and the second signal line 12 are located in the non-display area NA and are symmetrically arranged with the display area AA as the center. The present disclosure does not specifically limit the specific positions of the first signal line 11 and the second signal line 12, as long as the first signal line 11 and the second signal line 12 are located in the non-display area NA and are symmetrically arranged along a certain direction with the display area AA as the center. Figure 6 It is schematically shown that the first signal line 11 and the second signal line 12 are respectively located in the non-display area NA on both sides of the display area AA along the first direction D1.

[0034] The non-display area NA includes a gate driving circuit 21, and the first signal line 11 and the second signal line 12 are located in the non-display area NA on both sides of the display area AA. In the non-display area NA on the left side of the display area AA, the first signal line 11 and the gate driving circuit 21 overlap in a direction perpendicular to the plane of the display panel 100; in the non-display area NA on the right side of the display area AA, the second signal line 12 and the gate driving circuit 21 overlap in a direction perpendicular to the plane of the display panel 100. Here, "overlap" can mean that the first signal line 11 or the second signal line 12 partially or completely overlaps with the gate driving circuit 21, and the present disclosure does not limit this. Figure 6 It is schematically shown that the first signal line 11 or the second signal line 12 completely overlaps with the gate driving circuit 21. In this way, in a direction perpendicular to the plane of the display panel 100, by arranging the first signal line 11 or the second signal line 12 to overlap with the gate driving circuit 21, the total lateral space width occupied by the gate driving circuit 21 and the first signal line 11 / second signal line 12 in the non-display area NA can be reduced, and further the width of the non-display area NA along the first direction D1 can be reduced, which is beneficial to realizing a narrow border.

[0035] Please continue to refer to Figure 6 The present disclosure provides a display panel 100, in the non-display area NA, the first signal line 11 or the second signal line 12 covers the gate driving circuit 21.

[0036] Specifically, in an optional embodiment provided by the present disclosure, the first signal line 11 and the second signal line 12 are respectively located in the non-display areas NA on both sides of the display area AA along the first direction D1. In the non-display area NA, the first signal line 11 covers the gate driving circuit 21 located on the left side of the display area AA, and the second signal line 12 covers the gate driving circuit 21 located on the right side of the display area AA. Compared with the scheme in which only a part of the first signal line 11 or the second signal line 12 overlaps with the gate driving circuit 21, the first signal line 11 or the second signal line 12 covering the gate driving circuit 21 can further reduce the width of the non-display area NA in the first direction D1, which is beneficial to further realizing a narrow border.

[0037] Please continue to refer to Figures 4 to 6 , the present disclosure provides a display panel 100. The display panel 100 includes a driving layer 20 and a light-emitting element layer 30. The light-emitting element layer 30 includes an anode layer 32, a light-emitting layer 33, and a cathode layer 31; the driving layer 20 is located on the side of the anode layer 32 away from the light-emitting layer 33. The driving layer 20 includes an active layer Poly, a first metal layer M1, a capacitive metal layer MC, a second metal layer M2, and a third metal layer M3. The capacitive metal layer MC is located between the active layer Poly and the first metal layer M1, and the third metal layer M3 is located on the side of the second metal layer M2 away from the first metal layer M1; the display panel 100 further includes a packaging layer 40, and the packaging layer 40 is located on the side of the light-emitting element layer 30 away from the driving layer 20. It can be understood that the display panel 100 may further include other film layer structures, which are not limited in the present disclosure.

[0038] The gate driving circuit 21 and its connected signal lines are located on the active layer Poly, the first metal layer M1, the capacitive metal layer MC, and the second metal layer M2.

[0039] Specifically, the driving layer 20 includes an active layer Poly. The active layer Poly is located on the side of the first metal layer M1 facing away from the second metal layer M2. In some other embodiments, the active layer Poly may also be located on the side of the first metal layer M1 facing the second metal layer M2. The present disclosure does not limit this. The active layer Poly includes a source region and a drain region, and the source region s and the drain region d are formed by doping N-type impurity ions or P-type impurity ions. The driving layer 20 includes a transistor T. The source electrode s and the drain electrode d of the transistor T may be located on the second metal layer M2. The source electrode s and the drain electrode d of the transistor T are electrically connected to the active layer Poly through contact holes respectively. The capacitive metal layer MC is located between the active layer Poly and the first metal layer M1. The second metal layer M2 is located on the side of the first metal layer M1 facing away from the capacitive metal layer MC. The capacitive metal layer MC is used to form a capacitive structure with the first metal layer M1 or the second metal layer M2. Along the thickness direction of the display panel 100, the first metal layer M1 may be, for example, a gate metal layer, and the gate of the transistor T in the display panel 100 may be provided on the first metal layer M1. Exemplarily, the third metal layer M3 is generally used to set PVDD (Pixel VDD, positive power supply line) to provide a positive voltage for the pixel circuit in the display panel 100 to ensure that the sub-pixel P0 emits light normally. Optionally, the data signal line may also be provided on the third metal layer M3.

[0040] In an alternative embodiment provided by the present disclosure, the gate driving circuit 21 and its connected signal lines are located on the active layer Poly, the first metal layer M1, the capacitive metal layer MC, and the second metal layer M2. Compared with the related art, where the active layer Poly, the first metal layer M1, the capacitive metal layer MC, the second metal layer M2, and the third metal layer M3 are usually used for routing the gate driving circuit 21, the routing method in this embodiment can reduce the film layer occupation, facilitate the concentration of routing, and improve the production efficiency.

[0041] Please continue to refer to Figures 4 to 6 The present disclosure provides a display panel 100, where the first signal line 11 and the second signal line 12 are located on the third metal layer M3 and the anode layer 32.

[0042] Specifically, in an alternative embodiment provided by the present disclosure, the gate driving circuit 21 and its connected signal lines are located in the active layer Poly, the first metal layer M1, the capacitor metal layer MC, and the second metal layer M2. The first signal line 11 and the second signal line 12 are located in the third metal layer M3 and the anode layer 32. That is, the first signal line 11 or the second signal line 12 and the signal lines connected to the gate driving circuit 21 are located in different film layers, and the first signal line 11 or the second signal line 12 covers the gate driving circuit 21. By the relative positional relationship between the first signal line 11 or the second signal line 12 and the gate driving circuit 21 and the film layer wiring design, the width of the non-display area NA can be minimized as much as possible to achieve a narrow border. At the same time, the signal interference between the first signal line 11 or the second signal line 12 and the gate driving circuit 21 can also be reduced, improving the display uniformity.

[0043] Please continue to refer to Figures 3 to 6 The present disclosure provides a display panel 100. The sub-pixel P0 includes a third color sub-pixel P13. In the same pixel row P1 or the same pixel column P2, the cathode block 34 corresponding to the third color sub-pixel P13 is connected to the cathode block 34 corresponding to the first color sub-pixel P11. The cathode blocks 34 corresponding to the third color sub-pixel P13 and the first color sub-pixel P11 are both connected to the first signal line 11.

[0044] Specifically, in an optional embodiment provided by the present disclosure, the first color sub-pixel P11 is a red sub-pixel R, the second color sub-pixel P12 is a green sub-pixel G, and the third color sub-pixel P13 is a blue sub-pixel B. In the same pixel row P1, the cathode block 34 corresponding to the blue sub-pixel B is connected to the cathode block 34 corresponding to the red sub-pixel R, and both the blue sub-pixel B and the red sub-pixel R are connected to the first signal line 11. At this time, the first signal line 11 is located on one side of the display area AA along the first direction D1; that is, the cathode voltages input by the blue sub-pixel B and the red sub-pixel R are the same. In another pixel row P1 (referring to a pixel row P1 different from the blue sub-pixel B and the red sub-pixel R), the cathode blocks 34 corresponding to two adjacent green sub-pixels G are connected, and the green sub-pixel G is connected to the second signal line 12. The voltage of the second signal line 12 is different from that of the first signal line 11. At this time, the second signal line 12 is located on the other side of the display area AA along the first direction D1, and the first signal line 11 and the second signal line 12 are respectively located on both sides of the display area AA along the first direction D1. The red sub-pixel R and the blue sub-pixel B are controlled by the same cathode voltage, and the green sub-pixel G is controlled by another cathode voltage. Since the luminous efficiency of the blue sub-pixel B is relatively low, the cathode voltage needs to be more negative. Separately controlling the cathode voltages of different color sub-pixels P0 can reduce the cathode voltage corresponding to the blue sub-pixel B, and at the same time can optimize the cathode voltage corresponding to the green sub-pixel G, thereby improving the power consumption and heating color shift of the display panel 100. In addition, by arranging the first signal line 11 and the second signal line 12 on both sides of the display area AA along the first direction D1, only the left and right side frames of the display panel 100 need to be provided with the first signal line 11 and the second signal line 12, and the lower frame of the display panel 100 does not need to be provided with the first signal line 11 and the second signal line 12. Through experimental verification by the inventor, the lower frame of the display panel 100 can be reduced from the current mass production of 550 μm to 300 μm.

[0045] Figure 7 The following is a schematic structural diagram of another display panel provided by an embodiment of the present disclosure. Please refer to Figure 7, in an alternative embodiment provided by the present disclosure, the first color sub-pixel P11 is a red sub-pixel R, the second color sub-pixel P12 is a green sub-pixel G, and the third color sub-pixel P13 is a blue sub-pixel B. In the same pixel column P2, the cathode block 34 corresponding to the blue sub-pixel B is connected to the cathode block 34 corresponding to the red sub-pixel R, and both the blue sub-pixel B and the red sub-pixel R are connected to the first signal line 11. That is, the cathode voltages input to the blue sub-pixel B and the red sub-pixel R are the same. At this time, the first signal line 11 is located on one side of the display area AA along the second direction D2. In another pixel column P2 (referring to a pixel column P2 different from the blue sub-pixel B and the red sub-pixel R), the cathode blocks 34 corresponding to two adjacent green sub-pixels G are connected, and the green sub-pixel G is connected to the second signal line 12. The voltage of the second signal line 12 is different from that of the first signal line 11. At this time, the second signal line 12 is located on the other side of the display area AA along the second direction D2, and the first signal line 11 and the second signal line 12 are respectively located on both sides of the display area AA along the second direction D2. The red sub-pixel R and the blue sub-pixel B are controlled by the same cathode voltage, and the green sub-pixel G is controlled by another cathode voltage. Since the luminous efficiency of the blue sub-pixel B is relatively low, the cathode voltage needs to be more negative. Separately controlling the cathode voltages of different color sub-pixels P0 can reduce the cathode voltage corresponding to the blue sub-pixel B and optimize the cathode voltage corresponding to the green sub-pixel G, thereby improving the power consumption and heating color deviation of the display panel 100. Optionally, the first signal line 11 is located in the non-display area NA above the display area AA, and the second signal line 12 is located in the non-display area NA below the display area AA, or the first signal line 11 is located in the non-display area NA below the display area AA, and the second signal line 12 is located in the non-display area NA above the display area AA. The present disclosure does not limit this.

[0046] Please refer to Figure 7 , taking the first signal line 11 located in the non-display area NA above the display area AA as an example, the first signal line 11 located above the display area AA can extend downward along the non-display areas NA on the left and right sides of the display area AA to below the display area AA. At this time, at least part of the first signal line 11 is located in the non-display area NA on the left side of the display area AA, and at least part of the first signal line 11 is located in the non-display area NA on the right side of the display area AA. The voltage signals transmitted by the voltage signal lines in the non-display areas NA on the left and right sides of the display area AA are the same. For example, the same voltage signal can be transmitted to the red sub-pixel R and the blue sub-pixel B at the same time. There is no need to set the overlapping part 50 (the overlapping part 50 is used to connect the cathode line 35 to the first signal line 11 or the second signal line 12) in the non-display areas NA on the left and right sides of the display area AA, and only wiring is required. In this way, the wiring width can be halved on the original basis, which is beneficial to realizing a narrow border. The inventor has verified through experiments that the non-display areas NA on the left and right sides of the display area AA can be reduced from the current mass-produced 750 μm border to between 650 μm and 700 μm.

[0047] It should be noted that in another embodiment, the second signal line 12 is located in the non-display area NA above the display area AA. The second signal line 12 above the display area AA can extend downward along the non-display areas NA on the left and right sides of the display area AA to the lower part of the display area AA. At this time, at least part of the second signal line 12 is located in the non-display area NA on the left side of the display area AA, and at least part of the second signal line 12 is located in the non-display area NA on the right side of the display area AA. The voltage signals transmitted by the voltage signal lines in the non-display areas NA on the left and right sides of the display area AA are the same. For example, the same cathode voltage signal can be transmitted to the green sub-pixels G at the same time. When the first signal line 11 and the second signal line 12 are located in the non-display areas NA on both sides of the display area AA along the second direction D2, the cathode voltage signals transmitted by the voltage signal lines in the non-display areas NA on both sides of the display area AA along the first direction D1 are the same. For example, the same voltage signal is provided for the red sub-pixels R and the blue sub-pixels B at the same time, or the same voltage signal is provided for the green sub-pixels G at the same time. At this time, the width of the non-display areas NA on both sides of the display area AA along the first direction D1 can be halved on the original wiring width, which is beneficial to realizing a narrow border.

[0048] In this way, in the same pixel row P1 or the same pixel column P2, the third color sub-pixel P13 and the first color sub-pixel P11 are both connected to the first signal line 11. The cathode voltage of the third color sub-pixel P13 can be reduced only through the first signal line 11 without reducing the cathode voltage of the second color sub-pixel P12, which is beneficial to reducing the power consumption of the display panel 100 and reducing color shift.

[0049] Please continue to refer to Figures 3 to 7 The present disclosure provides a display panel 100. The non-display area NA further includes a lapping portion 50, and the lapping portion 50 is used to connect the cathode line 35 to the first signal line 11 or the second signal line 12. It can be understood that the cathode line 35 and the cathode block 34 are located in the cathode layer 31; the first signal line 11 and the second signal line 12 are arranged on the same layer and are located in the third metal layer M3 and the anode layer 32. The lapping portion 50 and the first signal line 11 and the second signal line 12 are located in the non-display area NA. The lapping portion 50 and the first signal line 11 or the second signal line 12 at least partially overlap. The lapping portion 50 is used to transmit the voltage signal of the first signal line 11 or the second signal line 12 to the cathode line 35, and further transmit it to the cathode block 34 through the cathode line 35.

[0050] Please refer to Figure 4 and Figure 6, the anode layer 32 includes a plurality of first anode portions 36 located in the display area AA and an extension portion 37 located in the non-display area NA. The extension portion 37 is an extension of the first anode portion 36 in the non-display area NA. In the non-display area NA, the extension portion 37 overlaps with the first signal line 11 or the second signal line 12, and the overlapping portion 50 at least partially overlaps with the extension portion 37. It can be understood that the first anode portion 36 and the extension portion 37 are provided on the same layer. The first anode portion 36 is located in the display area AA, and the extension portion 37 is located in the non-display area NA. In the non-display area NA, the extension portion 37 of the anode layer 32 overlaps with the first signal line 11 or the second signal line 12, and the overlapping portion 50 at least partially overlaps with the extension portion 37. That is, in the direction perpendicular to the plane of the display panel 100, the overlapping portion 50, the extension portion 37, the first signal line 11 or the second signal line 12 at least partially overlap with each other. In this way, by maximizing the overlapping area between the extension portion 37, the overlapping portion 50, the first signal line 11 or the second signal line 12 in the direction perpendicular to the plane of the display panel 100, the widths of the extension portion 37, the overlapping portion 50, the first signal line 11 or the second signal line 12 in the first direction D1 can be reduced, which is beneficial to reducing the width of the non-display area NA and facilitating the realization of a narrow border.

[0051] In a specific process, the first signal line 11 and the second signal line 12 are routed in the third metal layer M3 and the anode layer 32. The first signal line 11 or the second signal line 12 respectively covers the entire gate driving circuit 21, and the cathode layer 31 is located above the anode layer 32. Before depositing the cathode layer 31, other possible organic vapor deposition coating layers in the extension portion 37 of the non-display area NA are removed by laser. Optionally, the overlapping portion 50 is on the same layer as the cathode layer 31, and the overlapping portion 50 can be directly overlapped with the underlying extension portion 37 while depositing the cathode layer 31. Further, the overlapping portion 50 is electrically connected to the first signal line 11 or the second signal line 12 through the extension portion 37. The overlapping width of the overlapping portion 50 with the first signal line 11 or the second signal line 12 in the first direction D1 is in the range of greater than or equal to 50 μm and less than or equal to 100 μm, which can simultaneously achieve overlapping and reduce the border. Optionally, the overlapping width of the overlapping portion 50 with the first signal line 11 or the second signal line 12 in the first direction D1 is 55 μm, 60 μm, 65 μm, 70 μm, 75 μm, 80 μm, 85 μm, 90 μm, 95 μm... Here, they are not listed one by one. As long as the overlapping width of the overlapping portion 50 with the first signal line 11 or the second signal line 12 in the first direction D1 is in the range of greater than or equal to 50 μm and less than or equal to 100 μm.

[0052] Thus, by arranging the overlapping portion 50, the extending portion 37, the first signal line 11, or the second signal line 12 to overlap in a direction perpendicular to the plane of the display panel 100, the width of the non-display area NA in the direction parallel to the plane of the display panel 100 can be reduced, the width of the non-display area NA can be decreased, which is conducive to achieving a narrow border.

[0053] Please continue to refer to Figure 6 , the present disclosure provides a display panel 100. The overlapping portion 50 includes a first overlapping portion 51 and a second overlapping portion 52. The first overlapping portion 51 and the second overlapping portion 52 are respectively located in the non-display areas NA on both sides of the display area AA along the first direction D1; the first signal line 11 and the second signal line 12 are respectively located in the non-display areas NA on both sides of the display area AA along the first direction D1.

[0054] Specifically, in an optional embodiment provided by the present disclosure, the first overlapping portion 51 and the second overlapping portion 52 are respectively located in the non-display areas NA on both sides of the display area AA along the first direction D1. The first overlapping portion 51 overlaps with the first signal line 11, and the second overlapping portion 52 overlaps with the second signal line 12. Alternatively, the first overlapping portion 51 overlaps with the second signal line 12, and the second overlapping portion 52 overlaps with the first signal line 11. The present disclosure does not limit this. Figure 6 Taking the first overlapping portion 51 overlapping with the first signal line 11 and the second overlapping portion 52 overlapping with the second signal line 12 as an example for illustration. Since the first signal line 11 is connected to the first color sub-pixel P11 and the third color sub-pixel P13, the first overlapping portion 51 overlapping with the first signal line 11 is used to transmit corresponding voltage signals to the first color sub-pixel P11 and the third color sub-pixel P13. Since the second signal line 12 is connected to the second color sub-pixel P12, the second overlapping portion 52 overlapping with the second signal line 12 is used to transmit corresponding voltage signals to the second color sub-pixel P12, and the voltages of the first signal line 11 and the second signal line 12 are different. That is, the voltages of the first overlapping portion 51 and the second overlapping portion 52 located on both sides of the display area AA along the first direction D1 are different. Since the first overlapping portion 51 and the second overlapping portion 52 are wound around the L / R border of the display panel 100, the overlapping portion 50 may not be provided on the lower border of the display panel 100, and only the cutting and packaging area and the wiring area need to be reserved on the lower border to achieve a narrow border.

[0055] Thus, by arranging the first overlapping portion 51 and the second overlapping portion 52 in the non-display areas NA on both sides of the display area AA along the first direction D1, the overlapping portion 50 may not be provided on both sides of the display area AA along the second direction D2, the width of the lower border of the display panel 100 can be reduced, thereby achieving a narrow border.

[0056] Please continue to refer to Figure 7, the present disclosure provides a display panel 100. The overlapping portion 50 includes a first overlapping portion 51 and a second overlapping portion 52. The first overlapping portion 51 and the second overlapping portion 52 are respectively located in the non-display areas NA on both sides of the display area AA along the second direction D2. The first signal line 11 and the second signal line 12 are respectively located in the non-display areas NA on both sides of the display area AA along the second direction D2. In the non-display area NA, the first signal line 11 extends along the second direction D2 to the same side as the second signal line 12, or the second signal line 12 extends along the second direction D2 to the same side as the first signal line 11.

[0057] Specifically, in an optional embodiment provided by the present disclosure, the first overlapping portion 51 and the second overlapping portion 52 are respectively located in the non-display areas NA on both sides of the display area AA along the second direction D2, and the first signal line 11 and the second signal line 12 are respectively located in the non-display areas NA on both sides of the display area AA along the second direction D2. The first overlapping portion 51 overlaps with the first signal line 11, and the second overlapping portion 52 overlaps with the second signal line 12. Figure 7 Taking the non-display area NA above the display area AA where the first signal line 11 is located as an example for illustration, it can be understood that it can also be the non-display area NA above the display area AA where the second signal line 12 is located, and the present disclosure does not limit this. The first signal line 11 is connected to the first color sub-pixel P11 and the third color sub-pixel P13. The first overlapping portion 51 overlapping with the first signal line 11 is used to transmit corresponding voltage signals to the first color sub-pixel P11 and the third color sub-pixel P13. The first signal line 11 in the non-display area NA above the display area AA needs to wind around from the non-display areas NA on the left and right sides of the display area AA along the second direction D2 to the lower part of the display area AA, and then further connect to the driving chip. At this time, only the first signal line 11 transmitting the same voltage signal exists in the non-display areas NA on the left and right sides of the display area AA. Part of the first signal lines 11 wind around from the non-display area NA on the left side of the display area AA, and part of the first signal lines 11 wind around from the non-display area NA on the right side of the display area AA. Compared with the existing wiring design, the wiring width of the non-display areas NA on the left and right sides of the display area AA in this embodiment can be halved, which is beneficial to achieving a narrow border.

[0058] In this way, by arranging the first overlapping portion 51 and the second overlapping portion 52 in the non-display areas NA on both sides of the display area AA along the second direction D2, the overlapping portion 50 can be not arranged on both sides of the display area AA along the first direction D1, reducing the width of the left and right borders of the display panel 100, thereby achieving a narrow border.

[0059] Figure 8 The following shows a schematic diagram of a display device provided by an embodiment of the present disclosure. Please refer to Figure 8, the present disclosure provides a display device 200, including the display panel as described above. The display device 200 provided by the embodiments of the present disclosure may be any electronic device with a display function, such as a touch display screen, a mobile phone, a tablet computer, a laptop computer, an e-reader, or a television. The display device 200 provided by the embodiments of the present disclosure has the beneficial effects of the display panel provided by the embodiments of the present disclosure. For the specific description of the display panel, reference may be made to the above embodiments, and details are not repeated herein.

[0060] It can be understood that Figure 8 only a right-angled rectangular structure is taken as an example to illustrate a shape of the display device 200. In some other embodiments of the present disclosure, the display device 200 may also be embodied as a circular shape, an oval shape, a rounded rectangular shape, or any other feasible shape, and the present disclosure does not specifically limit this.

[0061] In summary, a display panel and a display device provided by the present disclosure include: a display area, the display area includes pixel rows arranged along a first direction and pixel columns arranged along a second direction, the first direction intersects with the second direction; the pixel rows and pixel columns include a plurality of sub-pixels; the sub-pixels include a light-emitting layer and a cathode layer, the cathode layer is located on one side of the light-emitting layer; the cathode layer includes cathode blocks and cathode lines, and the cathode lines are used to connect the cathode blocks; the sub-pixels include pixel openings, the sub-pixels include a first color sub-pixel and a second color sub-pixel, the cathode block corresponding to the first color sub-pixel is connected to a first signal line, the cathode block corresponding to the second color sub-pixel is connected to a second signal line, and the voltages of the first signal line and the second signal line are different.

[0062] By patterning the cathode layer in the display panel, the cathode blocks corresponding to different color sub-pixels can be made different, and then the voltages corresponding to different color sub-pixels can be set differently to reduce power consumption and improve the brightness uniformity of the display panel.

[0063] By setting the first signal line or the second signal line to overlap with the gate driving circuit, the width of the non-display area in the direction parallel to the plane of the display panel can be reduced, which is beneficial to realizing a narrow border. The gate driving circuit and the signal lines connected thereto are located in the active layer, the first metal layer, the capacitive metal layer, and the second metal layer, which can reduce the occupation of the film layer, facilitate the concentration of wiring, and improve production efficiency. The first signal line or the second signal line and the signal lines of the gate driving circuit and the connections thereof are located in different film layers, and the first signal line or the second signal line covers the gate driving circuit, which can reduce the signal interference between the first signal line or the second signal line and the gate driving circuit while minimizing the width of the non-display area as much as possible and realizing a narrow border, and improve the display uniformity.

[0064] In the same pixel row or the same pixel column, connecting the third color sub-pixel and the first color sub-pixel to the first signal line can reduce the cathode voltage of the second color sub-pixel only through the second signal line, without having to reduce the cathode voltages of the first color sub-pixel and the third color sub-pixel, which is beneficial to reducing the power consumption of the display panel and reducing color shift.

[0065] By arranging the overlapping portion, the extending portion, the first signal line or the second signal line to overlap in a direction perpendicular to the plane of the display panel, the width of the non-display area in the direction parallel to the plane of the display panel can be reduced, and the width of the non-display area can be reduced, which is beneficial to realizing a narrow border.

[0066] By arranging the first overlapping portion and the second overlapping portion in the non-display areas on both sides of the display area along the first direction, the overlapping portions can not be arranged on both sides of the display area along the second direction, thereby reducing the width of the lower border of the display panel and realizing a narrow border. By arranging the first overlapping portion and the second overlapping portion in the non-display areas on both sides of the display area along the second direction, the overlapping portions can not be arranged on both sides of the display area along the first direction, thereby reducing the widths of the left and right borders of the display panel and realizing a narrow border.

[0067] The above are only specific embodiments of the present disclosure, enabling those skilled in the art to understand or implement the present disclosure. Various modifications to these embodiments will be obvious to those skilled in the art. The general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present disclosure. Therefore, the present disclosure will not be limited to these embodiments described herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A display panel, characterized in that, include: a display area, the display area comprising pixel rows arranged along a first direction and pixel columns arranged along a second direction, the first direction intersecting the second direction; the pixel rows and the pixel columns comprising a plurality of sub-pixels; The sub-pixel includes a light-emitting layer and a cathode layer, wherein the cathode layer is located on one side of the light-emitting layer; the cathode layer includes cathode blocks and cathode lines, wherein the cathode lines are used to connect the cathode blocks; The sub-pixel includes a pixel opening, and the sub-pixel includes a first color sub-pixel and a second color sub-pixel. The cathode block corresponding to the first color sub-pixel is connected to a first signal line, and the cathode block corresponding to the second color sub-pixel is connected to a second signal line. The voltages of the first signal line and the second signal line are different.

2. The display panel according to claim 1, wherein The display panel includes a non-display area, and the non-display area is located on at least one side of the display area; the first signal line and the second signal line are respectively located in the non-display area on both sides of the display area; The non-display area includes a gate driving circuit, and in the non-display area, the first signal line or the second signal line overlaps with the gate driving circuit.

3. The display panel according to claim 2, wherein In the non-display area, the first signal line or the second signal line covers the gate driving circuit.

4. The display panel according to claim 3, wherein The display panel includes a driving layer and an anode layer, wherein the driving layer is located on a side of the anode layer away from the light-emitting layer, the driving layer includes an active layer, a first metal layer, a capacitor metal layer, a second metal layer, and a third metal layer, wherein the capacitor metal layer is located between the active layer and the first metal layer, and the third metal layer is located on a side of the second metal layer away from the first metal layer; The gate driving circuit and the signal lines connected thereto are located in the active layer, the first metal layer, the capacitor metal layer, and the second metal layer.

5. The display panel according to claim 4, characterized in that, The first signal line and the second signal line are located in the third metal layer and the anode layer.

6. The display panel according to claim 1, wherein The sub-pixels include a third color sub-pixel, and in the same pixel row or the same pixel column, the cathode block corresponding to the third color sub-pixel is connected to the cathode block corresponding to the first color sub-pixel; The third color sub-pixel and the first color sub-pixel are both connected to the first signal line.

7. The display panel according to claim 4, wherein The non-display area further includes a bridging portion, wherein the bridging portion is used to connect the cathode line and the first signal line or the second signal line; The anode layer includes a plurality of first anode portions located in the display area and an extension portion located in the non-display area. In the non-display area, the extension portion overlaps with the first signal line or the second signal line, and the overlap portion at least partially overlaps with the extension portion.

8. The display panel according to claim 7, wherein The overlapping portion includes a first overlapping portion and a second overlapping portion, wherein the first overlapping portion and the second overlapping portion are respectively located in the non-display area on both sides of the display area along the first direction; The first signal line and the second signal line are respectively located in the non-display area at two sides of the display area along the first direction.

9. The display panel according to claim 7, characterized in that, The overlapping portion includes a first overlapping portion and a second overlapping portion, wherein the first overlapping portion and the second overlapping portion are respectively located in the non-display area on both sides of the display area along the second direction; The first signal line and the second signal line are respectively located in the non-display areas on both sides of the display area along the second direction; In the non-display area, the first signal line extends along the second direction to the same side as the second signal line, or the second signal line extends along the second direction to the same side as the first signal line.

10. A display device, characterized in that, It includes a display panel according to any one of claims 1-9.

Images