Liquid crystal display apparatus and method for controlling the same

Abstract

To provide a liquid crystal display device capable of suppressing color shift, and a control method of the liquid crystal display device.SOLUTION: The liquid crystal display device includes: a plurality of gate bus lines, a plurality of source bus lines, and a plurality of pixels arranged in a display region; a source drive circuit; and a timing controller. The display region extends in a column direction and includes a plurality of first polarity regions P1 and a plurality of second polarity regions P2 arranged alternately in a row direction. The timing controller controls the source drive circuit 53a so that data signals output to a pair of adjacent source bus lines SL1R, SL2L, which are included in one of the plurality of first polarity regions and one of the plurality of second polarity regions, have the same polarity.SELECTED DRAWING: Figure 9

Description

[Technical Field]

[0001] The present disclosure relates to a liquid crystal display device and a method for controlling a liquid crystal display device. [Background technology]

[0002] The liquid crystal layer used in liquid crystal display devices has the characteristic of being easily deteriorated when a voltage of the same polarity is continuously applied to it, so liquid crystal display devices are generally configured to operate using AC drive.

[0003] AC driving methods include frame inversion driving, row line inversion driving, column line inversion driving, and dot inversion driving, and an appropriate driving method is selected taking into consideration the characteristics of the liquid crystal layer used in the liquid crystal display device, the application of the liquid crystal display device, and the like.

[0004] However, depending on the AC driving method used, when a specific image pattern is displayed on an LCD device, the color on the display screen may not be the correct color but may take on a different color. This type of display is called color shift. When the color shift is particularly greenish, it is called the greenish phenomenon. Image patterns that are prone to color shift are called killer patterns.

[0005] For example, Patent Documents 1 and 2 disclose liquid crystal display devices that can suppress such color shifts. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Japanese Patent Application Laid-Open No. 2005-258447 [Patent Document 2] International Publication No. 2018 / 128142 Summary of the Invention [Problem to be solved by the invention]

[0007] An object of the present disclosure is to provide a liquid crystal display device and a method for controlling a liquid crystal display device that can suppress such color shifts. [Means for solving the problem]

[0008] a plurality of pixels arranged two-dimensionally in the row and column directions in the display region, each pixel connected to one of the plurality of gate bus lines and one of the plurality of source bus lines; a source drive circuit connected to the plurality of source bus lines and outputting a plurality of data signals to the plurality of source bus lines by a column line inversion drive method or a dot inversion drive method; and a timing controller for controlling the source drive circuit, wherein the display region extends in the column direction and includes a plurality of first polarity regions and a plurality of second polarity regions arranged alternately in the row direction, and the timing controller controls the source drive circuit so that the polarities of the data signals output to each pair of adjacent source bus lines are the same. [Effects of the Invention]

[0009] According to an embodiment of the present disclosure, a liquid crystal display device and a method for controlling a liquid crystal display device are provided that are capable of suppressing color shift when a killer pattern is displayed. [Brief explanation of the drawings]

[0010] [Figure 1] FIG. 1 is a schematic cross-sectional view showing an example of the configuration of a liquid crystal display device according to an embodiment. [Figure 2]FIG. 2 is a schematic diagram showing the configuration of the TFT substrate in the liquid crystal display device shown in FIG. [Figure 3] FIG. 3 is a circuit diagram showing a pixel PX of a TFT substrate driven by the column line inversion driving method. [Figure 4] FIG. 4 is a circuit diagram showing a pixel PX of a TFT substrate driven by the 1H dot inversion driving method. [Figure 5] FIG. 5 is a circuit diagram showing a pixel PX of a TFT substrate driven by the 2H dot inversion driving method. [Figure 6] FIG. 6 is a schematic diagram showing the arrangement of red, green, and blue pixels in a liquid crystal display device. [Figure 7] FIG. 7 is a block diagram illustrating an example of the configuration of the control device. [Figure 8] FIG. 8 is a schematic diagram showing an example of the distribution of first and second polarity regions in the entire display area. [Figure 9] FIG. 9 shows the relationship between the first and second polarity regions and the polarity of the data signal output to the source bus line. [Figure 10] FIG. 10 is a schematic diagram showing an example of the polarities of data signals output from two source driver chips. [Figure 11] FIG. 11 is a schematic diagram showing an example of the polarities of data signals output from two source driver chips. [Figure 12] FIG. 12 is a schematic diagram showing an example of the polarities of data signals output from two source driver chips. [Figure 13A] FIG. 13A is a schematic diagram showing the polarity of a data signal applied during a certain frame period when a conventional liquid crystal display device is driven by the column line inversion method. [Figure 13B] FIG. 13B is a schematic diagram showing the polarity of a data signal applied during a certain frame period when a conventional liquid crystal display device is driven by the column line inversion method. [Figure 13C] FIG. 13C is a schematic diagram showing an example of a killer pattern in the column line inversion method. [Figure 14] FIG. 14 is a schematic diagram showing fluctuations in the potential of the common electrode. [Figure 15A] FIG. 15A is a schematic diagram showing the polarity of a data signal applied during a certain frame period when a conventional liquid crystal display device is driven by the 1H dot inversion method. [Figure 15B] FIG. 15B is a schematic diagram showing the polarity of a data signal applied during a certain frame period when a conventional liquid crystal display device is driven by the 1H dot inversion method. [Figure 15C] FIG. 15C is a schematic diagram showing an example of a killer pattern in the 1H dot inversion method. [Figure 16A] FIG. 16A is a schematic diagram showing the polarity of a data signal applied during a certain frame period when a conventional liquid crystal display device is driven by the 2H dot inversion method. [Figure 16B] FIG. 16B is a schematic diagram showing the polarity of a data signal applied during a certain frame period when a conventional liquid crystal display device is driven by the 2H dot inversion method. [Figure 16C] FIG. 16C is a schematic diagram showing an example of a killer pattern in the 2H dot inversion method. [Figure 17] FIG. 17 shows a killer pattern and the polarity of a data signal applied during a certain frame period when the liquid crystal display device of this embodiment is driven by the column line inversion method. [Figure 18] FIG. 18 shows the killer pattern and the polarity of the data signal applied during a certain frame period when the liquid crystal display device of this embodiment is driven by the 1H dot inversion method. [Figure 19] FIG. 19 shows the killer pattern and the polarity of the data signal applied in a certain frame period when the liquid crystal display device of this embodiment is driven by the 2H dot inversion method. [Figure 20] FIG. 20 shows an example of the results of measuring the relationship between the width in the row direction of the first and second polarity regions and the chromaticity difference between the first and second polarity regions. DETAILED DESCRIPTION OF THE INVENTION

[0011] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. The present disclosure is not limited to the following embodiments, and appropriate design modifications may be made within the scope of the configuration of the present disclosure. In the following description, the same reference numerals are used in different drawings for identical parts or parts having similar functions, and repeated description thereof may be omitted. Furthermore, the configurations described in the embodiments may be appropriately combined or modified without departing from the spirit of the present disclosure. For ease of understanding, the drawings referred to below may show simplified or schematic configurations, or may omit some components. Furthermore, the dimensional ratios between components shown in each drawing do not necessarily represent actual dimensional ratios.

[0012] 1 is a schematic cross-sectional view showing an example of the configuration of a liquid crystal display device 101 of this embodiment. The liquid crystal display device 101 includes a liquid crystal panel 10 and a control device 50. The liquid crystal panel 10 includes a TFT substrate 20, a counter substrate 30, and a liquid crystal layer 40. As will be described later, the liquid crystal panel 10 includes a plurality of pixels arranged in row and column directions. The liquid crystal layer 40 is located between the TFT substrate 20 and the counter substrate 30, and is sealed between the TFT substrate 20 and the counter substrate 30 by a seal 41.

[0013] The liquid crystal display device 101 may further include a pair of polarizing plates 42 and a backlight 80. The pair of polarizing plates 42 are arranged in a crossed Nicol state with the liquid crystal panel 10 sandwiched between them.

[0014] The backlight 80 is disposed on the rear surface 10b of the liquid crystal panel 10. The backlight 80 may be an edge-type backlight or a direct-type backlight. The backlight 80 may also be capable of being partially driven.

[0015] 2 is a schematic diagram showing a configuration example of the TFT substrate 20. The TFT substrate 20 includes a substrate 21, a plurality of source bus lines (data signal lines) SL, a plurality of gate bus lines (scanning signal lines) GL, and a plurality of pixels PX.

[0016] The substrate 21 has a main surface 21a including a display region 21h and a non-display region 21g other than the display region 21h. A plurality of gate bus lines GL, a plurality of source bus lines SL, and a plurality of pixels PX are arranged in the display region 21h. Specifically, the plurality of gate bus lines GL extend in the row direction (x direction) and are arranged at predetermined intervals in the column direction (y direction) intersecting the row direction. The plurality of source bus lines SL extend in the column direction and are arranged at predetermined intervals in the row direction. A pixel PX is arranged in a region surrounded by a pair of adjacent gate bus lines GL and a pair of adjacent source bus lines SL. The plurality of pixels PX are arranged two-dimensionally in the row and column directions. The source bus lines SL and gate bus lines GL extend into the non-display region 21g.

[0017] 3 is a circuit diagram showing pixels PX of a TFT substrate 20 driven by a column line inversion driving method. Each pixel PX includes a pixel electrode PE, a switching element SW, and a common electrode CE. The switching element SW is, for example, a thin film transistor (TFT), which is a three-terminal element, and its three terminals are connected to a gate bus line GL, a source bus line SL, and a pixel electrode PE. For example, the switching element is a TFT having a gate electrode GE, a source electrode SE, and a drain electrode DE, where the gate electrode GE is connected to the gate bus line GL, the source electrode SE is connected to the source bus line SL, and the drain electrode DE is connected to the pixel electrode PE and the storage capacitor CS. In this way, each pixel PX is connected to one of a plurality of gate bus lines GL and one of a plurality of source bus lines via the switching element SW.

[0018] Each gate bus line GL is connected to the gate electrodes G of the TFTs of the pixels PX arranged in the row direction among the plurality of pixels PX. On the other hand, each source bus line SL is connected to the source electrodes S of the TFTs of the pixels PX arranged in the column direction among the plurality of pixels PX. Therefore, data signals of the same polarity are applied to the plurality of pixels arranged in the column direction by inversion driving.

[0019] The pixel electrodes PE are disposed to face the liquid crystal layer 40. The common electrode CE is, for example, a plate- or sheet-like single element that connects adjacent pixels PX and extends across the entire display area 21h, and is located between the pixel electrodes and the substrate 21. An insulating layer is disposed between the common electrode CE and the pixel electrodes PE. The common electrode CE is provided across the entire display area 21h, and by applying a voltage between the pixel electrodes PE and the common electrode CE, an electric field is generated in the liquid crystal layer 40, driving the liquid crystal panel 10 in a transverse electric field mode such as in-plane switching (IPS) or fringe field switching (FFE). This allows the liquid crystal panel 10 to have a wide viewing angle.

[0020] Figures 4 and 5 are circuit diagrams showing pixels PX of a TFT substrate 20 driven by a dot inversion driving method. Figure 4 is a circuit diagram of a TFT substrate 20 driven by a 1H dot inversion method, in which the pixels in the i-th row and the pixels in the (i+1)-th row are alternately connected to the source bus line SL in the (i+1)-th row. Figure 5 is a circuit diagram of a TFT substrate 20 driven by a 2H dot inversion method, in which the pixels in the i-th row and the pixels in the (i+1)-th row are alternately connected two by two to the source bus line SL in the (i+1)-th row.

[0021] As shown in Fig. 6, the pixels PX include multiple red pixels R, multiple green pixels G, and multiple blue pixels B, with pixels of the same color arranged in the column direction. Additionally, red pixels R, green pixels G, and blue pixels B are arranged repeatedly in this order in the row direction. Three pixels consisting of a red pixel R, a green pixel G, and a blue pixel B adjacent in the row direction constitute a color pixel PXc that can display achromatic colors and any color. The red pixel R, the green pixel G, and the blue pixel B are called sub-pixels, and a group of these three sub-pixels may also be called a pixel.

[0022] 7 is a block diagram showing an example configuration of the control device 50. The control device 50 includes a timing controller 51, a gate drive circuit 52, and a source drive circuit 53. The control device 50 is configured by an electronic circuit using active components such as ICs, LSIs, and FETs, and passive components such as resistors and capacitors.

[0023] The timing controller 51 receives a video signal from an external device. The video signal includes a video data signal and a video synchronization signal. The timing controller 51 generates a gate control signal and a source control signal based on the received video signal.

[0024] The gate control signals include, for example, a gate start pulse signal, a gate clock signal, a gate clear signal, a gate output signal, etc. The source control signals include, for example, a source start pulse signal, a source shift clock signal, a source output signal, a polarity signal, etc.

[0025] 2, the gate drive circuit 52 and the source drive circuit 53 are arranged in the non-display area 21g of the substrate 21. The gate drive circuit 52 is connected to at least one end of the gate bus line GL. The source drive circuit 53 is connected to one end of the source bus line SL. The timing controller 51 is connected by, for example, a flexible printed circuit (FPC) 90.

[0026] The gate drive circuit 52 and the source drive circuit 53 may be components in a package covered with resin or the like, or may be bare chips, and may be mounted in the non-display area 21g of the substrate 21. Alternatively, the gate drive circuit 52 and the source drive circuit 53 may be monolithic drivers constituted by a plurality of TFTs or the like fabricated in the non-display area 21g of the substrate 21.

[0027] In this embodiment, the gate drive circuits 52 are arranged at both ends of the gate bus lines GL, and are monolithic drivers that are integrally formed with the substrate 21 by TFTs and the like formed on the substrate 21, similar to the TFTs that are the switching elements SW of the pixels PX. Meanwhile, in this embodiment, the source drive circuit 53 includes multiple source driver chips 53a. The source driver chips 53a are bare chips that are mounted on the substrate 21.

[0028] The gate drive circuit 52 receives a gate control signal, generates a plurality of scanning signals, and outputs them to the plurality of gate bus lines GL, respectively. The source drive circuit 53 receives a source control signal, and outputs a plurality of data signals to the source bus lines SL, respectively. The plurality of data signals include voltage values ​​corresponding to the gradation display of each pixel. Since the liquid crystal display device 101 is driven by a column line inversion drive system or a dot inversion drive system, the polarities of the data signals output to the plurality of source bus lines SL aligned in the row direction are alternately inverted.

[0029] However, among the plurality of source bus lines SL, there are a plurality of locations where data signals of the same polarity are output between pairs of adjacent source bus lines. As a result of the contiguous source bus lines to which data signals of the same polarity are applied, the display region 21h of the liquid crystal display device 101 has two polarity regions where the polarity of the AC drive is reversed.

[0030] Fig. 8 shows the distribution of the two polarity regions throughout the display area 21h, and Fig. 9 shows the relationship between the polarity regions and the polarities of data signals output to the source bus lines. The display area 21h of the liquid crystal display device 101 includes a plurality of first polarity regions P1 and a plurality of second polarity regions P2. The plurality of first polarity regions P1 and the plurality of second polarity regions P2 each extend in the column direction and are alternately arranged in the row direction.

[0031] The source driving circuit 53 outputs data signals to the source bus lines SL included in the adjacent first polarity region P1 and second polarity region P2 so that the polarities of the data signals output to each of the adjacent pair of source bus lines SL are the same. For example, as shown in Fig. 9, at the boundary B1 between the second polarity region P2 and the first polarity region P1 adjacent to it on the left side during a certain frame period, a negative (-) data signal is output to each of the adjacent pair of source bus lines SL1R and SL2L. Also, at the boundary B2 between the second polarity region P2 and the first polarity region P1 adjacent to it on the right side, a positive (+) data signal is output to each of the adjacent pair of source bus lines SL2R and SL1L.

[0032] Of the source bus lines SL included in the first polarity region P1 and the second polarity region P2, the polarities of the data signals output to the source bus lines located at both ends (SL1L and SL1R, and / or SL2L and SL2R) may be the same or different. In the example shown in FIG. 9, the polarities of the data signals output to the source bus lines SL located at both ends in each of the first polarity region P1 and the second polarity region P2 are different. In the first polarity region P1 and the second polarity region, the polarities of the data signals output to the multiple source bus lines SL aligned in the row direction are alternately inverted. Furthermore, in the next frame period, the polarities of the above-mentioned data signals are inverted.

[0033] The boundary (B1, B2) between the first polarity region P1 and the second polarity region P2 is preferably located between the above-mentioned color pixels PXc and PXc. For example, as shown in Fig. 9, when the color pixels are configured in the row direction in the order of red pixel R, green pixel G, and blue pixel B, the boundary B1, B2 is preferably located between the blue pixel B and red pixel R. In other words, the pair of source bus lines (SL1L and SL1R, and / or SL2L and SL2R) to which data signals of the same polarity are output are preferably located at the red pixel R and the blue pixel B, respectively.

[0034] The display region 21h preferably includes a plurality of first polarity regions P1 and a plurality of second polarity regions P2. As will be described later, including a plurality of first polarity regions P1 and a plurality of second polarity regions P2 in the display region 21h can further suppress the effect of color shift that occurs when a killer pattern is displayed. Furthermore, when the pixel density of the liquid crystal display device 101 is 200 ppi or higher, the widths W1 and W2 in the row direction of the plurality of first polarity regions P1 and the plurality of second polarity regions P2 are preferably 15 mm or less. The width W1 of the first polarity region P1 and the width W2 of the second polarity region P2 may be the same or different. Furthermore, the plurality of first polarity regions P1 may have the same width W1 or may be different from each other. The same applies to the second polarity region P2. To more efficiently suppress color shift, it is preferable that the sum of the widths W1 of the plurality of first polarity regions P1 is equal to the sum of the widths W2 of the plurality of second polarity regions P2.

[0035] In this embodiment, the source driver chip 53a outputs data signals to the source bus lines SL located in the first polarity region P1 and the second polarity region P2. For this reason, the timing controller 51 is programmed using, for example, an EPROM so that data signals of the same polarity are output to the source bus lines SL1R and SL2L, and / or SL2R and SL1L, and the polarities of the data signals output to the other source bus lines SL arranged in the row direction are alternately inverted. The polarities of the data signals output to a pair of adjacent source bus lines between the source driver chips 53a may be the same or inverted.

[0036] 10 to 12 show output examples of two source driver chips 53a. As shown in FIG. 10, the source driver chip 1 and the source driver chip 2 may be controlled by the timing controller 51 so that the polarities of data signals output to a pair of adjacent source bus lines SL are the same. In the example shown in FIG. 10, data signals of the same polarity are output to the source bus lines SL connected to terminals 1_i and 1_(i+1) of the source driver chip 1, and data signals of the same polarity are output to the source bus lines SL connected to terminals 2_j and 2_(j+1) of the source driver chip 2. Terminals 1_n and 2_1 of the source driver chip 2 output data signals of the same polarity to a pair of adjacent source bus lines SL. Therefore, polarity region boundaries are formed at the three locations described above, and the source driver chip 1 and the source driver chip 2 output data signals to the source bus lines SL located in the first polarity region P1 and the second polarity region P2, respectively.

[0037] 11, one source driver chip may be controlled by a timing controller 51 so that data signals output to two or more pairs of adjacent source bus lines SL have the same polarity. In the example shown in Fig. 11, data signals of the same polarity are output to source bus lines SL connected to terminals numbered 2_j and 2_(j+1) of the source driver chip 2, and data signals of the same polarity are output to source bus lines SL connected to terminals numbered 2_k and 2_(k+1) of the source driver chip 2. Therefore, the source driver chip 2 outputs data signals to source bus lines SL located in two first polarity regions P1 and one second polarity region P2.

[0038] 12, a terminal numbered 1_n of the source driver chip 1 and a terminal numbered 2_1 of the source driver chip 2 may output data signals of different polarities to a pair of adjacent source bus lines SL. In this case, some terminals of the source driver chip 1 and some terminals of the source driver chip 2 output data signals to source bus lines SL located in one continuous first polarity region P1 or second polarity region P2.

[0039] Next, we will explain why a color shift occurs when a killer pattern is displayed in a conventional liquid crystal display device driven by an inversion driving method, and why this color shift is suppressed in the liquid crystal display device of this embodiment.

[0040] Figures 13A and 13B show the polarities of data signals applied during two consecutive frame periods when a conventional liquid crystal display device is driven using the column-line inversion method. Figure 13C shows an example of a killer pattern used in the column-line inversion method. As mentioned above, the color pixel PXc is composed of a red pixel R, a green pixel G, and a blue pixel B, and these pixels are arranged in the row direction. Therefore, when a conventional liquid crystal display device is driven using the column-line inversion method, the polarities of the data signals applied to the red pixel R and the blue pixel B are always opposite to those of the green pixel G.

[0041] In this case, as shown in Figure 13C, the killer pattern is a checkerboard pattern in which white display pixels and shaded black display pixels are alternately arranged in the row and column directions in units of color pixels PXc. In the example shown in Figure 13C, in column j, pixels (i+1), (i+3),..., and in column (j+1), pixels i, (i+2), (i+4),... are black display pixels. When a liquid crystal display device is driven in a normally black mode, no voltage is applied to the liquid crystal layer in the black display pixels.

[0042] As shown in FIG. 13 , in the row direction, there are pixels that display black and pixels that display white in units of color pixels PXc. Therefore, when a liquid crystal display device is driven in a normally black mode, during a certain frame period, for example, in the i-th pixel row, data signals are applied to all white-displaying pixels in the red pixel R and the blue pixel B with positive polarity, causing the pixels to display white. Therefore, in the i-th pixel row, the number of pixel electrodes to which a positive voltage is applied is greater than the number of pixel electrodes to which a negative voltage is applied. Similarly, in the (i+1)-th pixel row, data signals are applied to all white-displaying pixels in the red pixel R and the blue pixel B with negative polarity, causing the number of pixel electrodes to which a negative voltage is applied is greater than the number of pixel electrodes to which a positive voltage is applied. As a result, when the pixels PXc in each row are sequentially scanned, positive and negative voltages are alternately applied to the pixel electrodes collectively.

[0043] In this case, noise occurs in the common electrode CE due to voltage changes in the pixel electrodes, causing the common electrode potential Vcom, which should be constant, to fluctuate. Figure 14 schematically shows the fluctuations in the pixel electrodes and common electrode when a data signal is applied to the i-th pixel row in Figure 13. Although Figure 14 shows the reference potential as 0 V, the reference potential may be a value other than 0 V.

[0044] As shown in Figure 13, the polarity of the data signal voltage applied to the pixel electrode is predominantly positive, so when it is applied, a ripple occurs in the common electrode potential Vcom, which fluctuates to the positive side. The ripple converges over time, and at time t2, the common electrode potential returns to Vcom. At this time, a voltage determined by the difference between the pixel electrode potential Vp+ or Vp- and the common electrode potential Vcom at the time when the TFT of each pixel turns off is applied to the liquid crystal layer of each pixel.

[0045] 14, when the TFTs are turned off at time t1, the voltage ΔV+ applied to the liquid crystal layer in the red pixel R and blue pixel B, to which a positive data signal is applied, also changes to the positive side of the common electrode potential Vcom, reducing the voltage ΔV+ applied to the liquid crystal layer, and the luminance of the red pixel R and blue pixel B decreases compared to the value determined by the data signal. On the other hand, the voltage ΔV- applied to the liquid crystal layer in the green pixel G, to which a negative data signal is applied, changes to the positive side of the common electrode potential Vcom, increasing the voltage ΔV- applied to the liquid crystal layer, and the luminance of the green pixel G increases compared to the value determined by the data signal. As a result, the pixel PXc as a whole shifts from white to green.

[0046] When a data signal is applied to the (i+1)th pixel row, the polarity of the voltage of the data signal applied to the pixel electrode becomes negative, causing a negative ripple in the common electrode potential Vcom. At this time, a negative data signal is applied to the red pixel R and the blue pixel B, and a positive data signal is applied to the green pixel G. Therefore, the luminance of the red pixel R and the blue pixel B decreases compared to the value determined by the data signal, and the luminance of the green pixel G increases compared to the value determined by the data signal. As a result, the pixel PXc as a whole shifts from white to green.

[0047] During the next frame period, the voltage applied to each pixel is reversed, as shown in FIG. 13B. However, noise occurs in the common electrode potential in the direction of the dominant polarity of the pixel electrode in each row of pixel columns, causing pixel PXc as a whole to shift to green. As can be seen from FIG. 14, the earlier the time t1 at which the TFT turns off, the greater the voltage fluctuation due to the ripple, making the pixel PXc's shift to green more pronounced. In other words, the higher the frame frequency, the greener the displayed image will appear when a killer pattern is displayed.

[0048] Figures 15A and 15B show the polarities of data signals applied during two consecutive frame periods when a conventional liquid crystal display device is driven using the 1H dot inversion method. Figure 15C shows an example of a killer pattern used in the 1H dot inversion method. As shown in Figure 15C, when a liquid crystal display device is driven using the 1H dot inversion method, the killer pattern has columns of pixels PXc that display white and columns of pixels PXc that display black alternately arranged in the row direction.

[0049] Figures 16A and 16B show the polarities of data signals applied during two consecutive frame periods when a conventional liquid crystal display device is driven using the 2H dot inversion method. Figure 16C shows an example of a killer pattern when using the 1H dot inversion method. As shown in Figure 16C, when a liquid crystal display device is driven using the 2H dot inversion method, the killer pattern is a checkered pattern in which two consecutive white and two consecutive black pixels are alternately arranged in the column direction.

[0050] In this way, even when a liquid crystal display device is driven by the 1H dot inversion method or the 2H dot inversion method, the image shifts to green when a killer pattern is displayed in a conventional liquid crystal display device.

[0051] Next, we will explain why this color shift is suppressed in the liquid crystal display device of this embodiment. Figure 17 shows the killer pattern and the polarity of the data signal applied during a certain frame period when the liquid crystal display device of this embodiment is driven using the column inversion method. As described above, the polarities of the data signals output to a pair of adjacent source bus lines SL1R and SL2L, which are included in the adjacent first polarity region P1 and second polarity region P2, respectively, are the same. As shown in Figure 17, during a certain frame period, the polarities of the data signals applied to the pixels located on the source bus line SL1R and the source bus line SL2L are both negative.

[0052] In the first polarity region P1 of the i-th pixel row, data signals are applied to all white-displaying pixels, with the red pixels R and blue pixels B being positive polarity, to display white. Meanwhile, in the second polarity region P2, data signals are applied to all white-displaying pixels, with the red pixels R and blue pixels B being negative polarity, to display white. As a result, in the first polarity region P1 of the i-th pixel row, a larger number of pixel electrodes are applied with a positive voltage, and in the second polarity region P2, a larger number of pixel electrodes are applied with a negative voltage, thereby suppressing bias in the polarity of the pixel electrodes throughout the i-th pixel row.

[0053] In the (i+1)th pixel row, the positions of the pixels that display black are shifted, resulting in a polarity inversion. Therefore, in the first polarity region P1, a larger number of pixel electrodes are applied with a negative voltage, and in the second polarity region P2, a larger number of pixel electrodes are applied with a positive voltage. As a result, the polarity bias of the pixel electrodes throughout the (i+1)th pixel row is suppressed.

[0054] The polarity bias of the pixel electrodes in the first polarity region P1 and the polarity bias of the pixel electrodes in the second polarity region P2 may be ideally offset to completely suppress the ripples occurring in the common electrode potential Vcom, and in this case, the color shift caused by the ripples in the common electrode potential Vcom described above can be completely suppressed.

[0055] Even if ripples are not completely suppressed, the polarity bias of the pixel electrodes in the i-th row and the (i+1)-th row of pixels is suppressed, thereby reducing the ripples occurring in the common electrode potential Vcom, as shown in FIG. 14 . For example, when scanning the i-th row of pixels, the suppression of the polarity bias of the pixel electrodes reduces the ripples occurring in the common electrode potential Vcom′. If a small positive ripple remains, the reduction in the potential difference ΔV+′ between the pixel electrode potential Vp+ and the common electrode potential Vcom′ in the red and blue pixels in the first polarity region P1 is suppressed, thereby reducing the reduction in luminance in the red and blue pixels. Furthermore, the increase in the potential difference ΔV−′ between the pixel electrode potential Vp− and the common electrode potential Vcom′ in the green pixels is suppressed, thereby reducing the increase in luminance in the green pixels. Therefore, the amount of shift toward green in pixels displaying white is reduced in the first polarity region P1.

[0056] Meanwhile, in the second polarity region P2, negative data signals are applied to the red and blue pixels, but a small positive ripple remains in the common electrode potential Vcom in the i-th pixel row. As shown by the potential difference ΔV-' between the pixel electrode potential Vp- and the common electrode potential Vcom' in the red and blue pixels and the potential difference ΔV+' between the pixel electrode potential Vp+ and the common electrode potential Vcom' in the green pixels, the brightness of the red and blue pixels increases slightly, while the brightness of the green pixels decreases slightly. Therefore, in the second polarity region P2, pixels displaying white shift slightly toward magenta.

[0057] In this way, fluctuations in the voltage of the common electrode due to ripples are suppressed, so the shift to green in the first polarity region P1 and the shift to magenta in the second polarity region P2 are suppressed compared to the shift to green in conventional liquid crystal display devices.

[0058] Figure 18 shows the killer pattern and the polarity of the data signal applied during a certain frame period when the liquid crystal display device of this embodiment is driven using the 1H dot inversion method. Figure 19 shows the killer pattern and the polarity of the data signal applied during a certain frame period when the liquid crystal display device of this embodiment is driven using the 2H dot inversion method. These driving methods also suppress color shifts when displaying killer patterns, as with driving using the column-line inversion method.

[0059] FIG. 20 shows an example of the results of measuring the chromaticity of the first polarity regions P1 and the second polarity regions P2 using a liquid crystal display device with a pixel density of 200 ppi, varying the row widths of the first polarity regions P1 and the second polarity regions P2, and then calculating the chromaticity difference between the first polarity regions P1 and the second polarity regions P2. As shown in FIG. 20, the chromaticity difference Δxy between the first polarity regions P1 and the second polarity regions P2 varies depending on the row widths of the first polarity regions P1 and the second polarity regions P2. More specifically, as the row widths of the first polarity regions P1 and the second polarity regions P2 decrease, the chromaticity difference Δxy also decreases. Therefore, by providing multiple first polarity regions P1 and multiple second polarity regions P2, the row widths of the first polarity regions P1 and the second polarity regions P2 can be reduced, and the chromaticity difference Δxy can also be reduced.

[0060] Detailed experiments by the inventors of the present application have shown that when the row-direction width W1 of each first polarity region P1 and the row-direction width W2 of each second polarity region P2 are 15 mm or less, the chromaticity difference Δxy is 0.002 or less, and the stripe pattern due to the difference in color between the first polarity region P1 and the second polarity region P2 is barely visible. Since the chromaticity difference changes, it is not simply that the color-changing areas become smaller and less visible as the widths of the first polarity region P1 and the second polarity region P2 become smaller, but rather that the ripple generated in the reference potential of the common electrode becomes smaller as the width W becomes smaller. Furthermore, similar measurements were performed on liquid crystal displays with different pixel densities, and it was found that the chromaticity difference can be similarly reduced when the pixel density is between 150 ppi and 300 ppi.

[0061] As described above, according to the liquid crystal display device of this embodiment, when column line inversion driving or dot inversion driving is performed, color shifts occurring in images can be suppressed even when a killer pattern is displayed.

[0062] The liquid crystal display device and the method for controlling the liquid crystal display device of the present disclosure are not limited to the above-described embodiments and may be modified in various ways. For example, the number of source driver chips constituting the source drive circuit can be determined to any value. Furthermore, in the above-described embodiments, at least one source driver chip is driven so that data signals output to a pair of adjacent source bus lines have the same polarity. However, the source driver chip may also be driven so that data signals of the same polarity are not output to a pair of adjacent source bus lines. By making the polarities of data signals output from two source driver chips to a pair of adjacent source bus lines the same, a boundary between the first polarity region and the second polarity region can be established as described above.

[0063] The liquid crystal display device may also include a separate feedback circuit that suppresses ripples in the potential of the common electrode. In this case, the configuration of the liquid crystal device suppresses ripples, so that the ripples that the feedback circuit must suppress are reduced, thereby reducing the current consumption of the feedback circuit.

[0064] Furthermore, in the liquid crystal display device of this embodiment, if there is a possibility that flickering may be visible during low-frequency driving due to the polarity of data signals applied to adjacent source bus lines being the same, the arrangement of the common electrode, etc. can be adjusted so that the parasitic capacitance between adjacent source bus lines is reduced.

[0065] The liquid crystal display device and the method for controlling the liquid crystal display device according to the present disclosure can also be explained as follows.

[0066] The liquid crystal display device according to the first configuration comprises: a plurality of gate bus lines arranged in a display region, each extending in a row direction and arranged in a column direction; a plurality of source bus lines arranged in the display area, each extending in the column direction and arranged in the row direction; a plurality of pixels arranged two-dimensionally in the row direction and the column direction in the display area, each of the plurality of pixels being connected to one of the plurality of gate bus lines and one of the plurality of source bus lines; a source driver circuit connected to the plurality of source bus lines and outputting a plurality of data signals to the plurality of source bus lines, respectively, by a column line inversion driving method or a dot inversion driving method; a timing controller for controlling the source driving circuit; Equipped with the display area extends in the column direction and includes a plurality of first polarity areas and a plurality of second polarity areas alternately arranged in the row direction; The timing controller is included in each of the plurality of first polarity regions and each of the plurality of second polarity regions adjacent to each other, and controls the source driving circuit so that the polarities of the data signals output to each pair of adjacent source bus lines are the same.

[0067] According to the first configuration, when a killer pattern is displayed, it is possible to suppress fluctuations in potential that may occur in the common electrode, and to suppress color shifts in the displayed image.

[0068] In the liquid crystal display device according to the second configuration, in the first configuration, each of the first polarity regions and each of the second polarity regions may have a width in the row direction of 15 mm or less, thereby more reliably suppressing color shifts in the displayed image.

[0069] A liquid crystal display device according to a third configuration may be configured such that, in the first configuration, the source driving circuit includes at least one source driver chip that outputs the plurality of data signals, and the timing controller controls the at least one source driver chip so that the data signals output to the pair of adjacent source bus lines have the same polarity.

[0070] In a liquid crystal display device according to a fourth configuration, in the first configuration, the plurality of pixels may include a plurality of red pixels, a plurality of green pixels, and a plurality of blue pixels, pixels of the same color being arranged in the column direction, and red pixels, green pixels, and blue pixels being arranged repeatedly in this order in the row direction, and the pair of source bus lines to which the data signals of the same polarity are output may be located at the red pixels and the blue pixels, respectively.

[0071] A method for controlling a liquid crystal display device according to a fifth configuration includes: a plurality of gate bus lines arranged in a display region, each extending in a row direction and arranged in a column direction; a plurality of source bus lines arranged in the display area, each extending in the column direction and arranged in the row direction; a plurality of pixels arranged two-dimensionally in the row direction and the column direction in the display area, each of the plurality of pixels being connected to one of the plurality of gate bus lines and one of the plurality of source bus lines; a source driver circuit connected to the plurality of source bus lines and outputting a plurality of data signals to the plurality of source bus lines, respectively, by a column line inversion driving method or a dot inversion driving method; a timing controller for controlling the source driving circuit; A method for controlling a liquid crystal display device comprising: the display area extends in the column direction and includes a plurality of first polarity areas and a plurality of second polarity areas alternately arranged in the row direction; The timing controller is included in each of the plurality of first polarity regions and each of the plurality of second polarity regions adjacent to each other, and controls the source driving circuit so that the polarities of the data signals output to each pair of adjacent source bus lines are the same.

[0072] According to the fifth configuration, when a killer pattern is displayed, it is possible to suppress fluctuations in potential that may occur in the common electrode, and to suppress color shifts in the displayed image.

[0073] A sixth configuration of the method for controlling a liquid crystal display device in the fifth configuration may be such that each of the first polarity regions and each of the second polarity regions has a width in the row direction of 15 mm or less.

[0074] A seventh configuration of the control method for a liquid crystal display device is the fifth configuration, wherein the source drive circuit includes at least one source driver chip that outputs the plurality of data signals, and the timing controller controls the at least one source driver chip so that the polarities of the data signals output to the pair of adjacent source bus lines are the same.

[0075] In an eighth configuration, in the fifth configuration, the liquid crystal display device may be configured such that the plurality of pixels include a plurality of red pixels, a plurality of green pixels, and a plurality of blue pixels, pixels of the same color are arranged in the column direction, and red pixels, green pixels, and blue pixels are arranged repeatedly in this order in the row direction, and the pair of source bus lines to which the data signals of the same polarity are output may be located at the red pixels and the blue pixels, respectively. [Explanation of symbols]

[0076] 10...liquid crystal panel, 10b...rear face, 20...TFT substrate, 21...substrate, 21a...main surface, 21g...non-display area, 21h...display area, 30...opposite substrate, 40...liquid crystal layer, 41...seal 42...polarizing plate, 50...controller, 51...timing controller, 52...gate drive circuit 53...source driver circuit, 53a...source driver chip, 80...backlight, 101...liquid crystal display device, P1...first polarity region, P2...second polarity region, SL1R, SL1L, SL2L, SL2R

Claims

1. a plurality of gate bus lines arranged in a display region, each extending in a row direction and arranged in a column direction; a plurality of source bus lines arranged in the display area, each extending in the column direction and arranged in the row direction; a plurality of pixels arranged two-dimensionally in the row direction and the column direction in the display region, each of the plurality of pixels being connected to one of the plurality of gate bus lines and one of the plurality of source bus lines; a source driver circuit connected to the plurality of source bus lines and outputting a plurality of data signals to the plurality of source bus lines, respectively, by a column line inversion driving method or a dot inversion driving method; a timing controller for controlling the source driving circuit; Equipped with the display area extends in the column direction and includes a plurality of first polarity areas and a plurality of second polarity areas alternately arranged in the row direction; The timing controller is included in each of the plurality of first polarity regions and each of the plurality of second polarity regions adjacent to each other, and controls the source driving circuit so that the polarities of the data signals output to each pair of adjacent source bus lines are the same.

2. 2. The liquid crystal display device according to claim 1, wherein each of the first polarity regions and each of the second polarity regions has a width in the row direction of 15 mm or less.

3. the source driving circuit includes at least one source driver chip that outputs the plurality of data signals; 2. The liquid crystal display device according to claim 1, wherein the timing controller controls the at least one source driver chip so that the polarities of the data signals output to the pair of adjacent source bus lines are the same.

4. the plurality of pixels includes a plurality of red pixels, a plurality of green pixels, and a plurality of blue pixels; Pixels of the same color are arranged in the column direction, red pixels, green pixels, and blue pixels are arranged repeatedly in this order in the row direction; 2. The liquid crystal display device according to claim 1, wherein the pair of source bus lines to which the data signals of the same polarity are output are located at the red pixel and the blue pixel, respectively.

5. a plurality of gate bus lines arranged in a display region, each extending in a row direction and arranged in a column direction; a plurality of source bus lines arranged in the display area, each extending in the column direction and arranged in the row direction; a plurality of pixels arranged two-dimensionally in the row direction and the column direction in the display region, each of the plurality of pixels being connected to one of the plurality of gate bus lines and one of the plurality of source bus lines; a source driver circuit connected to the plurality of source bus lines and outputting a plurality of data signals to the plurality of source bus lines, respectively, by a column line inversion driving method or a dot inversion driving method; a timing controller for controlling the source driving circuit; A method for controlling a liquid crystal display device comprising: the display area extends in the column direction and includes a plurality of first polarity areas and a plurality of second polarity areas alternately arranged in the row direction; a timing controller included in each of the plurality of first polarity regions and each of the plurality of second polarity regions adjacent to each other, and controlling the source driving circuit so that the polarities of data signals output to each pair of adjacent source bus lines are the same.

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