Display panel and display device

Abstract

A display panel comprises a substrate, a plurality of sub-pixels and a plurality of data lines located in a display area, and a plurality of data fan-out lines and a plurality of control signal lines located in a first frame area. The plurality of data fan-out lines comprise a first group of data fan-out lines and a second group of data fan-out lines, and the plurality of control signal lines comprise a first group of control signal lines and a second group of control signal lines. The number of control signal lines in the first group of control signal lines is greater than the number of control signal lines in the second group of control signal lines. Each data fan-out line in the first group of data fan-out lines is overlapped with the orthographic projection of the first group of control signal lines on the substrate, and each data fan-out line in the second group of data fan-out lines is overlapped with the orthographic projection of the second group of control signal lines on the substrate. And at least one organic insulating layer is arranged between the data fan-out lines and the control signal lines with overlapped orthographic projections on the substrate.

Description

Technical Field

[0001] This application relates to, but is not limited to, the field of display technology, and particularly relates to a display panel and a display device. Background Art

[0002] An organic light emitting diode (OLED) is an active light emitting display device, which has the advantages of self-luminescence, wide viewing angle, high contrast ratio, low power consumption, extremely high response speed, etc. With the continuous development of display technology, a display device using an OLED as a light emitting device and controlled by thin film transistors (TFTs) has become the mainstream product in the current display field. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail in this application. This overview is not intended to limit the scope of protection of the claims.

[0004] Embodiments of the present application provide a display panel and a display device.

[0005] On the one hand, this embodiment provides a display panel, including: a substrate, a plurality of sub-pixels, a plurality of data lines, a plurality of data fan-out lines, and a plurality of control signal lines. The substrate includes: a display area, and a first border area located on one side of the display area. The plurality of sub-pixels and the plurality of data lines are located in the display area, the plurality of data lines are connected to the plurality of sub-pixels, and are configured to provide data signals to the plurality of sub-pixels. The plurality of data fan-out lines and the plurality of control signal lines are located in the first border area. The plurality of data fan-out lines are configured to provide data signals to the plurality of data lines; the plurality of data fan-out lines include: a first group of data fan-out lines and a second group of data fan-out lines, and the plurality of control signal lines include: a first group of control signal lines and a second group of control signal lines. The number of control signal lines in the first group of control signal lines is greater than the number of control signal lines in the second group of control signal lines. Each data fan-out line in the first group of data fan-out lines overlaps with the first group of control signal lines in the orthographic projection on the substrate, and each data fan-out line in the second group of data fan-out lines overlaps with the second group of control signal lines in the orthographic projection on the substrate. At least one organic insulating layer is provided between the data fan-out line and the control signal line that overlaps in the orthographic projection on the substrate.

[0006] In some exemplary embodiments, the control signal line includes: a first control segment, a positive projection of the first control segment on the substrate overlaps with a positive projection of the first set of data fan-out lines or the second set of data fan-out lines on the substrate, the first control segment is located on a side of the first set of data fan-out lines or the second set of data fan-out lines away from the substrate, and the first control segment intersects an extending direction of the plurality of data fan-out lines.

[0007] In some exemplary embodiments, in a direction perpendicular to the display panel, the display panel at least includes: a first gate metal layer, a second gate metal layer, a first source-drain metal layer, and a second source-drain metal layer that are arranged along a direction away from the substrate; at least a first planarization layer is disposed between the first source-drain metal layer and the second source-drain metal layer. The plurality of data fan-out lines are located in at least one of the first gate metal layer and the second gate metal layer, and the first control segment of the plurality of control signal lines is located in the second source-drain metal layer.

[0008] In some exemplary embodiments, in a direction perpendicular to the display panel, the display panel at least includes: a first gate metal layer, a second gate metal layer, a first source-drain metal layer, a second source-drain metal layer, and a third source-drain metal layer that are arranged along a direction away from the substrate; at least a first planarization layer is disposed between the first source-drain metal layer and the second source-drain metal layer, and at least a second planarization layer is disposed between the second source-drain metal layer and the third source-drain metal layer. The plurality of data fan-out lines are located in at least one of the first gate metal layer and the second gate metal layer, and the first control segment of the plurality of control signal lines is located in the third source-drain metal layer.

[0009] In some exemplary embodiments, the plurality of data fan-out lines includes: a plurality of first data fan-out lines located in the first gate metal layer and a plurality of second data fan-out lines located in the second gate metal layer. The plurality of first data fan-out lines and the plurality of second data fan-out lines are arranged at intervals one by one, and a positive projection of the plurality of first data fan-out lines and a positive projection of the plurality of second data fan-out lines on the substrate do not overlap.

[0010] In some exemplary embodiments, the control signal line further includes: a second control segment and a third control segment, the second control segment is connected to one end of the first control segment, the third control segment is connected to the other end of the first control segment, and a positive projection of the second control segment and the third control segment on the substrate does not overlap with a positive projection of the plurality of data fan-out lines on the substrate; the second control segment and the third control segment are of the same layer structure and are located on a side of the first control segment close to the substrate.

[0011] In some exemplary embodiments, each data fan-out line in the first group of data fan-out lines and the first group of control signal lines have a first overlapping area in the orthographic projection on the substrate, each data fan-out line in the second group of data fan-out lines and the second group of control signal lines have a second overlapping area in the orthographic projection on the substrate, and the ratio range of the first overlapping area to the second overlapping area is from 0.9 to 1.1.

[0012] In some exemplary embodiments, each data fan-out line in the first group of data fan-out lines includes: a first sub-segment that overlaps with the orthographic projection of the first group of control signal lines on the substrate. Each data fan-out line in the second group of data fan-out lines includes: a second sub-segment that overlaps with the orthographic projection of the second group of control signal lines on the substrate. The line width of the first sub-segment is less than the line width of the second sub-segment.

[0013] In some exemplary embodiments, the ratio of the line width of the second sub-segment to the line width of the first sub-segment is greater than 1 and less than 2.

[0014] In some exemplary embodiments, each data fan-out line in the first group of data fan-out lines further includes: a third sub-segment connected to one end of the first sub-segment, and a fourth sub-segment connected to the other end of the first sub-segment; the orthographic projections of the third sub-segment and the fourth sub-segment on the substrate do not overlap with the orthographic projection of the first group of control signal lines on the substrate; the first sub-segment, the third sub-segment, and the fourth sub-segment of each data fan-out line in the first group of data fan-out lines are an integrally connected structure. Each data fan-out line in the second group of data fan-out lines further includes: a fifth sub-segment connected to one end of the second sub-segment, and a sixth sub-segment connected to the other end of the second sub-segment; the orthographic projections of the fifth sub-segment and the sixth sub-segment on the substrate do not overlap with the orthographic projection of the second group of control signal lines on the substrate. The second sub-segment, the fifth sub-segment, and the sixth sub-segment of each data fan-out line in the second group of data fan-out lines are an integrally connected structure. The line widths of the first sub-segment, the third sub-segment, the fourth sub-segment, the fifth sub-segment, and the sixth sub-segment are the same.

[0015] In some exemplary embodiments, each data fan-out line in the first group of data fan-out lines includes: a first sub-segment that overlaps with the orthographic projection of the first group of control signal lines on the substrate. Each data fan-out line in the second group of data fan-out lines includes: a second sub-segment that overlaps with the orthographic projection of the second group of control signal lines on the substrate. The orthographic projection of the first sub-segment on the substrate is a straight-line trace, and the orthographic projection of the second sub-segment on the substrate is a serpentine trace.

[0016] In some exemplary embodiments, each data fan-out line in the second group of data fan-out lines further includes: a fifth sub-line segment connected to one end of the second sub-line segment, and a sixth sub-line segment connected to the other end of the second sub-line segment; the orthographic projections of the fifth sub-line segment and the sixth sub-line segment on the substrate do not overlap with the orthographic projection of the second group of control signal lines on the substrate. The second sub-line segment, the fifth sub-line segment, and the sixth sub-line segment of each data fan-out line in the second group of data fan-out lines are an integrally connected structure; the orthographic projection of the fifth sub-line segment or the sixth sub-line segment of at least one data fan-out line in the second group of data fan-out lines on the substrate is a serpentine trace.

[0017] In some exemplary embodiments, each control signal line in the first group of control signal lines includes: a first control line segment that overlaps with the orthographic projection of the first group of data fan-out lines on the substrate; each control signal line in the second group of control signal lines includes: a first control line segment that overlaps with the orthographic projection of the second group of data fan-out lines on the substrate; the line width of the first control line segment of at least one control signal line in the second group of control signal lines is greater than the line width of the first control line segment of the control signal lines in the first group of control signal lines.

[0018] In some exemplary embodiments, the substrate further includes: a second border region and a third border region located on both sides of the display region along a first direction, and both the second border region and the third border region communicate with the first border region. The display panel further includes: a first group of gate driving circuits located in the second border region and a second group of gate driving circuits located in the third border region, and the number of gate driving circuits included in the first group of gate driving circuits is greater than the number of gate driving circuits included in the second group of gate driving circuits. The first group of control signal lines includes: a plurality of first driving control lines configured to provide driving control signals to the first group of gate driving circuits. The second group of control signal lines includes: a plurality of second driving control lines configured to provide driving control signals to the second group of gate driving circuits.

[0019] In some exemplary embodiments, at least one of the plurality of sub-pixels includes: a pixel circuit. The first group of gate driving circuits includes: a light-emitting driving circuit, a first reset driving circuit, and a second reset driving circuit; the light-emitting driving circuit is configured to provide a light-emitting control signal to the pixel circuit, the first reset driving circuit is configured to provide a first reset control signal to the pixel circuit, and the second reset driving circuit is configured to provide a second reset control signal to the pixel circuit. The second group of gate driving circuits includes: a first scanning driving circuit and a second scanning driving circuit; the first scanning driving circuit is configured to provide a first scanning signal to the pixel circuit, and the second scanning driving circuit is configured to provide a second scanning signal to the pixel circuit.

[0020] On the other hand, this embodiment provides a display device, including the display substrate as described above.

[0021] On the other hand, this embodiment provides a display panel, including: a substrate, a plurality of sub-pixels, a plurality of data lines, a plurality of data fan-out lines, and a plurality of control signal lines. The substrate includes: a display area, and a first border area located on one side of the display area. The plurality of sub-pixels and the plurality of data lines are located in the display area, the plurality of data lines are connected to the plurality of sub-pixels and are configured to provide data signals to the plurality of sub-pixels. The plurality of data fan-out lines and the plurality of control signal lines are located in the first border area, and the plurality of data fan-out lines are configured to provide data signals to the plurality of data lines. The plurality of data fan-out lines includes: a first group of data fan-out lines and a second group of data fan-out lines, and the plurality of control signal lines includes: a first group of control signal lines and a second group of control signal lines; the number of control signal lines in the first group of control signal lines is greater than the number of control signal lines in the second group of control signal lines. Each data fan-out line in the first group of data fan-out lines has an overlap with the first group of control signal lines in the orthographic projection on the substrate, and each data fan-out line in the second group of data fan-out lines has an overlap with the second group of control signal lines in the orthographic projection on the substrate. Each data fan-out line in the first group of data fan-out lines has a first overlap area with the first group of control signal lines in the orthographic projection on the substrate, and each data fan-out line in the second group of data fan-out lines has a second overlap area with the second group of control signal lines in the orthographic projection on the substrate, and the ratio range of the first overlap area to the second overlap area is from 0.9 to 1.1.

[0022] In some exemplary embodiments, each data fan-out line in the first group of data fan-out lines includes a first sub-segment that overlaps with the orthographic projection of the first group of control signal lines on the substrate. Each data fan-out line in the second group of data fan-out lines includes a second sub-segment that overlaps with the orthographic projection of the second group of control signal lines on the substrate. The line width of the first sub-segment is smaller than the line width of the second sub-segment.

[0023] In some exemplary embodiments, each data fan-out line in the first group of data fan-out lines includes a first sub-segment that overlaps with the orthographic projection of the first group of control signal lines on the substrate. Each data fan-out line in the second group of data fan-out lines includes a second sub-segment that overlaps with the orthographic projection of the second group of control signal lines on the substrate. The orthographic projection of the first sub-segment on the substrate is a straight trace, and the orthographic projection of the second sub-segment on the substrate is a serpentine trace.

[0024] In some exemplary embodiments, each control signal line in the first group of control signal lines includes a first control segment that overlaps with the orthographic projection of the first group of data fan-out lines on the substrate. Each control signal line in the second group of control signal lines includes a first control segment that overlaps with the orthographic projection of the second group of data fan-out lines on the substrate. The line width of the first control segment of at least one control signal line in the second group of control signal lines is greater than the line width of the first control segment of the control signal lines in the first group of control signal lines.

[0025] Other features and advantages of the present application will be described in the subsequent specification, and in part will become apparent from the specification, or will be understood by implementing the present application. Other advantages of the present application can be realized and obtained by the solutions described in the specification and the drawings. Description of the Drawings

[0026] The drawings are used to provide an understanding of the technical solutions of the present application, and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solutions of the present application, and do not constitute a limitation to the technical solutions of the present application.

[0027] Figure 1 Schematic diagram of a display panel according to at least one embodiment of the present disclosure;

[0028] Figure 2 Equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0029] Figure 3 is Figure 2 Working timing diagram of the provided pixel circuit;

[0030] Figure 4Schematic diagram of a partial cross-section of a display area according to at least one embodiment of the present disclosure;

[0031] Figure 5 Schematic diagram of the arrangement of a gate driving circuit according to at least one embodiment of the present disclosure;

[0032] Figure 6 Partial plan view of a first border area according to at least one embodiment of the present disclosure;

[0033] Figure 7 is Figure 6 Partial enlarged view of area S1 in

[0034] Figure 8A is Figure 7 Partial cross-section example diagram along the Q1-Q1' direction in

[0035] Figure 8B is Figure 7 Partial cross-section example diagram along the Q2-Q2' direction in

[0036] Figure 9 Another partial cross-section schematic diagram of a display panel according to at least one embodiment of the present disclosure;

[0037] Figure 10A is Figure 7 Another partial cross-section example diagram along the Q1-Q1' direction in

[0038] Figure 10B is Figure 7 Another partial cross-section example diagram along the Q2-Q2' direction in

[0039] Figure 11 Another partial plan view of a first border area according to at least one embodiment of the present disclosure;

[0040] Figure 12A is Figure 11 Partial enlarged view of area S2 in

[0041] Figure 12B is Figure 12A Partial schematic diagram of the first set of data fan-out lines in

[0042] Figure 13A is Figure 11 Partial enlarged view of area S3 in

[0043] Figure 13B is Figure 13A Partial schematic diagram of the second set of data fan-out lines in

[0044] Figure 14A is Figure 11 Another partial enlarged view of area S3 in

[0045] Figure 14B is Figure 14A a partial schematic view of the outgoing line of the second group of data sectors in

[0046] Figure 15 is Figure 11 another partial enlarged schematic view of region S3 in

[0047] Figure 16A is Figure 11 another partial enlarged schematic view of region S2 in

[0048] Figure 16B is Figure 16A a partial schematic view of the outgoing line of the first group of data sectors in

[0049] Figure 17A is Figure 11 another partial enlarged schematic view of region S3 in

[0050] Figure 17B is Figure 17A a partial schematic view of the outgoing line of the second group of data sectors in

[0051] Figure 18 is a schematic view of a display device according to at least one embodiment of the present disclosure. Detailed implementation manners

[0052] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. The implementation manners can be implemented in multiple different forms. Those of ordinary skill in the art to which the present disclosure pertains can easily understand the fact that the manners and contents can be transformed into various forms without departing from the gist and scope of the present disclosure. Therefore, the present disclosure should not be construed as being limited only to the contents described in the following implementation manners. Without conflict, the embodiments and features in the embodiments of the present disclosure can be combined with each other arbitrarily.

[0053] In the drawings, sometimes for clarity, the sizes, thicknesses of layers, or regions of one or more constituent elements are exaggerated. Therefore, one aspect of the present disclosure is not necessarily limited to such dimensions, and the shapes and sizes of one or more components in the drawings do not reflect the true proportions. In addition, the drawings schematically show ideal examples, and one aspect of the present disclosure is not limited to the shapes or numerical values shown in the drawings.

[0054] The ordinal numbers such as "first", "second", "third", etc. in this specification are set to avoid confusion of constituent elements, rather than to limit the quantity. "Multiple" in the present disclosure means two or more quantities.

[0055] In this specification, for convenience, terms indicating orientation or positional relationship such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. are used to describe the positional relationship of the components with reference to the accompanying drawings. This is only for the convenience of describing this specification and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation to the present disclosure. The positional relationship of the components is appropriately changed according to the directions describing each component. Therefore, it is not limited to the terms described in the specification and can be appropriately replaced according to the circumstances.

[0056] In this specification, unless otherwise clearly defined and limited, the terms "mounted", "connected", and "coupled" shall be construed broadly. For example, it may be a fixed connection, a detachable connection, or an integral connection; it may be a mechanical connection or an electrical connection; it may be a direct connection, an indirect connection through an intermediate member, or a communication inside two elements. For those of ordinary skill in the art, the meanings of the above terms in the present disclosure can be understood according to the circumstances.

[0057] In this specification, a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In this specification, the channel region refers to the region where current mainly flows.

[0058] In this specification, the first pole can be the drain electrode and the second pole can be the source electrode, or the first pole can be the source electrode and the second pole can be the drain electrode. In the case of using transistors with opposite polarities or when the current direction changes during circuit operation, etc., the functions of the "source electrode" and "drain electrode" are sometimes interchanged. Therefore, in this specification, the "source electrode" and "drain electrode" can be interchanged with each other.

[0059] In this specification, "connection" includes the case where components are connected together through an element having a certain electrical effect. There is no particular limitation on the "element having a certain electrical effect" as long as it can transmit electrical signals between the components to be connected. Examples of the "element having a certain electrical effect" include not only electrodes and wirings, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0060] In this specification, "parallel" means a state where the angle formed by two straight lines is more than -10° and less than 10°, and thus also includes a state where the angle is more than -5° and less than 5°. In addition, "perpendicular" means a state where the angle formed by two straight lines is more than 80° and less than 100°, and thus also includes an angle state of more than 85° and less than 95°.

[0061] In the present disclosure, "about" and "substantially" mean that the boundaries are not strictly defined and situations within the process and measurement error ranges are allowed.

[0062] In this specification, A extending along the B direction means that A may include a main body part and a secondary part connected to the main body part. The main body part is in the shape of a line, a line segment, or a strip. The main body part extends along the B direction, and the length of the main body part extending along the B direction is greater than the length of the secondary part extending along other directions. When it is said in this specification that "A extends along the B direction", it always means that "the main body part of A extends along the B direction".

[0063] When it is said in this specification that "A and B are of the same layer structure", it means that A and B are formed simultaneously through the same patterning process. "The same layer" does not always mean that the thickness or height of the layer is the same in a cross-sectional view. "The orthographic projection of A includes the orthographic projection of B" means that the orthographic projection of B falls within the orthographic projection range of A, or the orthographic projection of A covers the orthographic projection of B.

[0064] With the development of display technology, users' requirements for display image quality have gradually increased. In the lower border area of a display panel, the capacitance generated by the overlapping of traces will affect the signals transmitted by the traces, resulting in load differences (for example, load differences of data signals), thereby causing poor display of the display panel. Taking the application of a display panel in wearable products such as watches as an example, the data fan-out lines for transmitting data signals overlapping with the traces for transmitting AC signals will cause signal load differences, thereby resulting in display defects such as bright and dark stripes or split screens.

[0065] This embodiment provides a display panel, including: a substrate, a plurality of sub-pixels, a plurality of data lines, a plurality of data fan-out lines, and a plurality of control signal lines. The substrate includes: a display area and a first border area located on one side of the display area. The plurality of sub-pixels and the plurality of data lines are located in the display area. The plurality of data lines are connected to the plurality of sub-pixels and are configured to provide data signals to the plurality of sub-pixels. The plurality of data fan-out lines and the plurality of control signal lines are located in the first border area. The plurality of data fan-out lines are configured to provide data signals to the plurality of data lines. The plurality of data fan-out lines include: a first group of data fan-out lines and a second group of data fan-out lines. The plurality of control signal lines include: a first group of control signal lines and a second group of control signal lines; the number of control signal lines in the first group of control signal lines is greater than the number of control signal lines in the second group of control signal lines. Each data fan-out line in the first group of data fan-out lines overlaps with the first group of control signal lines in the orthographic projection on the substrate, and each data fan-out line in the second group of data fan-out lines overlaps with the second group of control signal lines in the orthographic projection on the substrate. At least one organic insulating layer is provided between the data fan-out line and the control signal line that overlaps in the orthographic projection on the substrate.

[0066] For the display panel provided in this embodiment, in the first border area, at least one organic insulating layer is provided between the data fan-out line and the overlapping control signal line, which can increase the distance between the data fan-out line and the overlapping control signal line, thereby reducing the parasitic capacitance between the data fan-out line and the overlapping control signal line, and can improve display defects such as low gray-scale dark stripes caused by uneven overlap between the data fan-out line and the control signal line transmitting an AC signal.

[0067] In some exemplary embodiments, the control signal line may include: a first control signal segment, a positive projection of the first control signal segment on the substrate overlaps with a positive projection of the first group of data fan-out lines or the second group of data fan-out lines on the substrate, the first control signal segment may be located on a side of the first group of data fan-out lines or the second group of data fan-out lines away from the substrate, and the first control signal segment may intersect with an extending direction of a plurality of data fan-out lines. In some examples, in a direction perpendicular to the display panel, the display panel may at least include: a first gate metal layer, a second gate metal layer, a first source-drain metal layer, and a second source-drain metal layer disposed along a direction away from the substrate; at least a first planarization layer is disposed between the first source-drain metal layer and the second source-drain metal layer. A plurality of data fan-out lines may be located in at least one of the first gate metal layer and the second gate metal layer, and the first control signal segment of the plurality of control signal lines may be located in the second source-drain metal layer. In other examples, in a direction perpendicular to the display panel, the display panel may at least include: a first gate metal layer, a second gate metal layer, a first source-drain metal layer, a second source-drain metal layer, and a third source-drain metal layer disposed along a direction away from the substrate; at least a first planarization layer may be disposed between the first source-drain metal layer and the second source-drain metal layer, and at least a second planarization layer may be disposed between the second source-drain metal layer and the third source-drain metal layer. A plurality of data fan-out lines may be located in at least one of the first gate metal layer and the second gate metal layer, and the first control signal segment of the plurality of control signal lines may be located in the third source-drain metal layer. In this example, by setting the film layer where the first control signal segment of the control signal line is located (for example, the first control signal segment is located in the second source-drain metal layer or the third source-drain metal layer), the distance between the data fan-out line and the first control signal segment of the overlapping control signal line can be increased, and the parasitic capacitance between the data fan-out line and the overlapping control signal line can be reduced, thereby effectively improving display defects such as low gray-scale dark stripes caused by uneven overlap between the data fan-out line and the control signal line.

[0068] In some exemplary embodiments, each data fan-out line in the first group of data fan-out lines has a first overlapping area with a positive projection of the first group of control signal lines on the substrate, and each data fan-out line in the second group of data fan-out lines has a second overlapping area with a positive projection of the second group of control signal lines on the substrate. The ratio range of the first overlapping area to the second overlapping area may be from 0.9 to 1.1, for example, it may be 1.0. For example, the first overlapping area and the second overlapping area may be substantially the same. In this example, by adjusting the overlapping area of each data fan-out line with a plurality of control signal lines, the parasitic capacitance between the data fan-out line and the overlapping control signal line is adjusted, so that the parasitic capacitances between the two groups of data fan-out lines and the control signal lines are substantially the same, thereby optimizing display defects such as low gray-scale dark stripes caused by uneven overlap between the data fan-out line and the control signal line transmitting an alternating current signal.

[0069] In some exemplary embodiments, each data fan-out line within the first group of data fan-out lines may include a first sub-segment that overlaps with an orthographic projection of the first group of control signal lines on the substrate; and each data fan-out line within the second group of data fan-out lines may include a second sub-segment that overlaps with an orthographic projection of the second group of control signal lines on the substrate. The line width of the first sub-segment may be smaller than the line width of the second sub-segment. For example, the ratio of the line width of the second sub-segment to the line width of the first sub-segment may be greater than 1 and less than 2. In this example, by increasing the line width of the second sub-segment of the second group of data fan-out lines, the overlapping area between the second group of data fan-out lines and the second group of control signal lines can be increased, so that the second overlapping area corresponding to the data fan-out lines in the second group of data fan-out lines and the first overlapping area corresponding to the data fan-out lines in the first group of data fan-out lines can be roughly the same, and the parasitic capacitance between the second group of data fan-out lines and the overlapping routing lines is increased, so that the parasitic capacitance between the two groups of data fan-out lines and the overlapping routing lines is roughly the same, thereby improving display defects such as low grayscale dark stripes caused by uneven overlap of the data fan-out lines and the control signal lines.

[0070] In some exemplary embodiments, each data fan-out line within the first group of data fan-out lines may include a first sub-segment that overlaps with the orthographic projection of the first group of control signal lines on the substrate; and each data fan-out line within the second group of data fan-out lines may include a second sub-segment that overlaps with the orthographic projection of the second group of control signal lines on the substrate. The orthographic projection of the first sub-segment on the substrate may be a straight line, and the orthographic projection of the second sub-segment on the substrate may be a serpentine line. A serpentine line is a type of meandering curve. For example, one end of the line extends a certain distance in one direction, then bends and twists and extends a certain distance in the opposite direction, then bends and twists again and extends in the same direction, and repeats this process several times to form a serpentine line. In this example, by designing a serpentine line for some segments of the second group of data fan-out lines, the overlap area between the second group of data fan-out lines and the second group of control signal lines can be increased, thereby reducing the difference in parasitic capacitance between the two groups of data fan-out lines and the overlapping control signal lines.

[0071] In some exemplary embodiments, each control signal line in the first group of control signal lines may include: a first control segment that overlaps with the orthographic projection of the first group of data fan-out lines on the substrate; each control signal line in the second group of control signal lines may include: a first control segment that overlaps with the orthographic projection of the second group of data fan-out lines on the substrate. The line width of the first control segment of at least one control signal line in the second group of control signal lines may be greater than the line width of the first control segment of the control signal lines in the first group of control signal lines. In this example, by increasing the line width of the first control segment of the second group of control signal lines, the overlapping area between the second group of data fan-out lines and the second group of control signal lines can be increased, so that the parasitic capacitances between the two groups of data fan-out lines and the overlapping control signal lines are approximately the same, thereby improving display defects such as low gray-scale dark streaks caused by uneven overlapping of data fan-out lines and control signal lines.

[0072] The following are some examples to illustrate the solution of this embodiment.

[0073] Figure 1 Schematic diagram of a display panel according to at least one embodiment of the present disclosure. In some examples, as Figure 1 shown, the display panel may include: a display area AA, a peripheral border area B2 surrounding the display area AA, and a first border area B1 located on one side of the display area AA. The first border area B1 may be located on the side of the peripheral border area B2 away from the display area AA along the second direction Y. The first border area B1 may be in communication with the peripheral border area B2. For example, the first border area B1 may be the lower border of the display panel. The peripheral border area B2 may include: a second border area B21 and a third border area B22 located on both sides of the display area AA along the first direction X. The second border area B21 may be in communication with the first border area B1, and the third border area B22 may be in communication with the first border area B1. For example, the second border area B21 may be the left border of the display panel, and the third border area B22 may be the right border of the display panel.

[0074] In some examples, as Figure 1 shown, the display area AA may be a flat area, including a plurality of sub-pixels PX that make up a pixel array. The plurality of sub-pixels PX may be configured to display dynamic pictures or still images. The display area AA may be referred to as an active area. In some examples, the display area AA may be circular or elliptical. However, this embodiment is not limited thereto. For example, the display area may be other shapes such as rectangular. In some examples, the display panel may be a flexible panel, and thus the display panel may be deformable, such as curling, bending, folding, or rolling up.

[0075] In some examples, as Figure 1As shown, the display area AA may include: a display structure layer disposed on a substrate, or may include a display structure layer and a touch structure layer sequentially disposed on the substrate. For example, the display panel may integrate a touch structure to form a structure with the touch structure on the thin film encapsulation (Touch on Thin Film Encapsulation, abbreviated as Touch on TFE). The Touch on TFE structure mainly includes a flexible multi-layer on-cell (FMLOC, Flexible Multi-Layer On Cell) structure and a flexible single-layer on-cell (FSLOC, Flexible Single-Layer On Cell) structure. The FMLOC structure is based on the working principle of mutual capacitance detection. Generally, two layers of metal are used to form a driving (Tx) electrode and a sensing (Rx) electrode. The driving chip (IC) realizes the touch operation by detecting the mutual capacitance between the driving electrode and the sensing electrode. The FSLOC structure is based on the working principle of self-capacitance (or voltage) detection. Generally, a single layer of metal is used to form a touch electrode. The integrated circuit realizes the touch operation by detecting the self-capacitance (or voltage) of the touch electrode.

[0076] In some examples, the display structure layer may include a plurality of sub-pixels PX, a plurality of gate lines GL, and a plurality of data lines DL. The plurality of gate lines GL may extend in a first direction X, and the plurality of data lines DL may extend in a second direction Y. The orthographic projections of the plurality of gate lines GL and the plurality of data lines DL on the substrate may intersect to form a plurality of sub-pixel regions. One sub-pixel PX may be disposed in one sub-pixel region. The plurality of data lines DL may be electrically connected to the plurality of sub-pixels PX, and the plurality of data lines DL may be configured to provide data signals to the plurality of sub-pixels PX. The plurality of gate lines GL may be electrically connected to the plurality of sub-pixels PX, and the plurality of gate lines GL may be configured to provide gate driving signals to the plurality of sub-pixels PX. For example, the gate driving signal may include a scan signal, or may include a scan signal and a light emission control signal, or may include a scan signal, a reset control signal, and a light emission control signal.

[0077] In some examples, as Figure 1 shown, the first direction X may be the extension direction of the gate line GL in the display area AA (for example, the row direction), and the second direction Y may be the extension direction of the data line DL in the display area AA (for example, the column direction). The first direction X and the second direction Y may intersect with each other, for example, may be perpendicular to each other.

[0078] In some examples, a pixel unit in the display area AA may include three sub-pixels, which may be a first sub-pixel that emits first color light (e.g., red light), a second sub-pixel that emits second color light (e.g., green light), and a third sub-pixel that emits third color light (e.g., blue light). However, this embodiment is not limited thereto. In some examples, a pixel unit may include four sub-pixels, which may be a sub-pixel that emits red light, a sub-pixel that emits green light, a sub-pixel that emits blue light, and a sub-pixel that emits white light. For another example, a pixel unit may include four sub-pixels, which may include a sub-pixel that emits red light, a sub-pixel that emits blue light, and two sub-pixels that emit green light.

[0079] In some examples, the shape of the sub-pixel may be rectangular, rhombic, pentagonal, or hexagonal. When a pixel unit includes three sub-pixels, the three sub-pixels may be arranged in a horizontal side-by-side, vertical side-by-side, or triangular arrangement; when a pixel unit includes four sub-pixels, the four sub-pixels may be arranged in a horizontal side-by-side, vertical side-by-side, or square arrangement. However, this embodiment is not limited thereto.

[0080] In some examples, a sub-pixel may include: a pixel circuit and a light-emitting element electrically connected to the pixel circuit. The pixel circuit may include multiple transistors and at least one capacitor. For example, the pixel circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. Herein, T in the above circuit structures refers to a thin-film transistor, C refers to a capacitor, the number before T represents the number of thin-film transistors in the circuit, and the number before C represents the number of capacitors in the circuit. In some examples, the multiple transistors in the pixel circuit may include P-type transistors and N-type transistors. In some other examples, the multiple transistors in the pixel circuit may be P-type transistors or may be N-type transistors. Using the same type of transistors in the pixel circuit can simplify the process flow, reduce the process difficulty of the display substrate, and improve the yield of the product.

[0081] In some examples, the light-emitting element may be any one of a light-emitting diode (LED), an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED), a micro-LED (including: mini-LED or micro-LED), etc. For example, the light-emitting element may be an OLED, and the light-emitting element can emit red light, green light, blue light, or white light, etc. under the drive of its corresponding pixel circuit. The color of the light emitted by the light-emitting element can be determined as needed. In some examples, the light-emitting element may include: an anode, a cathode, and an organic light-emitting layer located between the anode and the cathode. The anode of the light-emitting element can be electrically connected to the corresponding pixel circuit. However, this embodiment is not limited thereto.

[0082] Figure 2 This is an equivalent circuit diagram of the pixel circuit according to at least one embodiment of the present disclosure. The pixel circuit in this example is described by taking the 8T1C structure as an example. In some examples, as Figure 2 shown, the pixel circuit in this example may include eight transistors (i.e., the first transistor T1 to the eighth transistor T8) and a storage capacitor Cst. The first transistor T1 may also be referred to as the first reset transistor, the second transistor T2 may also be referred to as the threshold compensation transistor, the third transistor T3 may also be referred to as the driving transistor, the fourth transistor T4 may also be referred to as the data writing transistor, the fifth transistor T5 may also be referred to as the first light-emitting control transistor, the sixth transistor T6 may also be referred to as the second light-emitting control transistor, the seventh transistor T7 may also be referred to as the second reset transistor, and the eighth transistor T8 may also be referred to as the third reset transistor. The light-emitting element EL may include an anode, a cathode, and an organic light-emitting layer disposed between the anode and the cathode.

[0083] In some examples, the first transistor T1, the third transistor T3 to the eighth transistor T8 may be first-type transistors, for example, they may be P-type transistors, and the second transistor T2 may be a second-type transistor, for example, it may be an N-type transistor. However, this embodiment is not limited thereto. For example, multiple transistors of the pixel circuit may all be P-type transistors, or they may all be N-type transistors.

[0084] In some examples, the first type of transistors in the pixel circuit (e.g., including the first transistor T1, the third transistor T3 to the eighth transistor T8) can be made of low-temperature poly-silicon thin-film transistors, and the second type of transistors in the pixel circuit (e.g., including the second transistor T2) can be made of oxide thin-film transistors. The active layer of the low-temperature poly-silicon thin-film transistor is made of low-temperature poly-silicon (LTPS, Low Temperature Poly-Silicon), and the active layer of the oxide thin-film transistor is made of oxide semiconductor (Oxide). The low-temperature poly-silicon thin-film transistor has advantages such as high mobility and fast charging, and the oxide thin-film transistor has advantages such as low leakage current. Integrating the low-temperature poly-silicon thin-film transistor and the oxide thin-film transistor on a display substrate to form a low-temperature polycrystalline oxide (LTPS+Oxide) display substrate can utilize the advantages of both, enable low-frequency driving, reduce power consumption, and improve display quality.

[0085] In some examples, as Figure 2 shown, the pixel circuit can be electrically connected to a first scan line GL1, a second scan line GL2, a data line DL, a first power supply line PL1, a second power supply line PL2, a light emission control line EML, a first initial signal line INIT1, a second initial signal line INIT2, a third initial signal line INIT3, a first reset control line RST1, and a second reset control line RST2. The first power supply line PL1 can be configured to provide a constant first voltage signal VDD to the pixel circuit, the second power supply line PL2 can be configured to provide a constant second voltage signal VSS to the pixel circuit, and the first voltage signal VDD is greater than the second voltage signal VSS. The first scan line GL1 can be configured to provide a first scan signal SCAN1 to the pixel circuit. The second scan line GL2 can be configured to provide a second scan signal SCAN2 to the pixel circuit. The data line DL can be configured to provide a data signal to the pixel circuit. The light emission control line EML can be configured to provide a light emission control signal EM to the pixel circuit. The first reset control line RST1 can be configured to provide a first reset control signal RESET1 to the pixel circuit. The second reset control line can be configured to provide a second reset control signal RESET2 to the pixel circuit.

[0086] In some examples, as Figure 2As shown, the gate of the third transistor T3 is electrically connected to the first node N1, the first pole of the third transistor T3 is electrically connected to the second node N2, and the second pole of the third transistor T3 is electrically connected to the third node N3. The gate of the fourth transistor T4 is electrically connected to the first scan line GL1, the first pole of the fourth transistor T4 is electrically connected to the data line DL, and the second pole of the fourth transistor T4 is electrically connected to the second node N2. The gate of the second transistor T2 is electrically connected to the second scan line GL2, the first pole of the second transistor T2 is electrically connected to the third node N3, and the second pole of the second transistor T2 is electrically connected to the first node N1. The gate of the fifth transistor T5 is electrically connected to the emission control line EML, the first pole of the fifth transistor T5 is electrically connected to the first power supply line PL1, and the second pole of the fifth transistor T5 is electrically connected to the second node N2. The gate of the sixth transistor T6 is electrically connected to the emission control line EML, the first pole of the sixth transistor T6 is electrically connected to the third node N3, and the second pole of the sixth transistor T6 is electrically connected to the fourth node N4. The gate of the first transistor T1 is electrically connected to the first reset control line RST1, the first pole of the first transistor T1 is electrically connected to the first initial signal line INIT1, and the second pole of the first transistor T1 is electrically connected to the third node N3. The first transistor T1 can be configured to reset the third node N3. The gate of the seventh transistor T7 is electrically connected to the second reset control line RST2, the first pole of the seventh transistor T7 is electrically connected to the second initial signal line INIT2, and the second pole of the seventh transistor T7 is electrically connected to the fourth node N4. The seventh transistor T7 can be configured to reset the fourth node N4. The gate of the eighth transistor T8 is electrically connected to the second reset control line RST2, the first pole of the eighth transistor T8 is electrically connected to the third initial signal line INIT3, and the second pole of the eighth transistor T8 is electrically connected to the second node N2. The eighth transistor T8 can be configured to reset the second node N2. The first electrode of the storage capacitor Cst is electrically connected to the first node N1, and the second electrode of the storage capacitor Cst is electrically connected to the first power supply line PL1.

[0087] In this example, the first node N1 is the connection point of the storage capacitor Cst, the second transistor T2, and the third transistor T3; the second node N2 is the connection point of the fifth transistor T5, the fourth transistor T4, the eighth transistor T8, and the third transistor T3; the third node N3 is the connection point of the first transistor T1, the third transistor T3, the second transistor T2, and the sixth transistor T6; and the fourth node N4 is the connection point of the sixth transistor T6, the seventh transistor T7, and the light-emitting element EL.

[0088] Figure 3 For Figure 2 the provided timing diagram of the pixel circuit operation. Refer to the following Figure 3 for Figure 2The operation process of the pixel circuit shown will be described. Among them, the first transistor T1, the third transistor T3 to the eighth transistor T8 of the pixel circuit are P-type transistors, and the second transistor T2 is an N-type transistor.

[0089] In some examples, such as Figure 2 and Figure 3 shown, during a frame display period, the operation process of the pixel circuit may at least include: a first stage S11, a second stage S12, a third stage S13, and a fourth stage S14.

[0090] The first stage S11 is called the first reset stage. The second reset control signal RESET2 provided by the second reset control line RST2 is a low-level signal, which turns on the seventh transistor T7 and the eighth transistor T8; the second scan signal SCAN2 provided by the second scan line GL2 is a high-level signal, which turns on the second transistor T2. When the eighth transistor T8 is turned on, the third initial signal provided by the third initial signal line INIT3 is provided to the second node N2. When the seventh transistor T7 is turned on, the second initial signal provided by the second initial signal line INIT2 is provided to the fourth node N4 to initialize the fourth node N4. The first scan signal SCAN1 provided by the first scan line GL1 is a high-level signal, the first reset control signal RESET1 provided by the first reset control line RST1 is a high-level signal, and the emission control signal EM provided by the emission control line EML is a high-level signal, which turns off the fourth transistor T4, the first transistor T1, the fifth transistor T5, and the sixth transistor T6. The light-emitting element EL does not emit light in this stage.

[0091] The second stage S12 is called the second reset stage. The first reset control signal RESET1 provided by the first reset control line RST1 is a low-level signal, which turns on the first transistor T1; the second scan signal SCAN2 provided by the second scan line GL2 is a high-level signal, which turns on the second transistor T2. When the first transistor T1 and the second transistor T2 are turned on, the first initial signal provided by the first initial signal line INIT1 is provided to the first node N1 to initialize the first node N1. The second reset control signal RESET2 provided by the second reset control line RST2 is a high-level signal, the first scan signal SCAN1 provided by the first scan line GL1 is a high-level signal, and the emission control signal EM provided by the emission control line EML is a high-level signal, which turns off the seventh transistor T7, the eighth transistor T8, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6. The light-emitting element EL does not emit light in this stage.

[0092] The third stage S13 is called the data writing stage or the threshold compensation stage. The first scan signal SCAN1 provided by the first scan line GL1 is a low-level signal, and the fourth transistor T4 is turned on; the second scan signal SCAN2 provided by the second scan line GL2 is a high-level signal, and the second transistor T2 is turned on. At this stage, the first electrode of the storage capacitor Cst is at a low level, and the third transistor T3 is turned on. The second transistor T2, the fourth transistor T4, and the third transistor T3 are turned on, so that the data voltage Vdata output by the data line DL is provided to the first node N1 through the second node N2, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2, and the difference between the data voltage Vdata output by the data line DL and the threshold voltage of the third transistor T3 is charged into the storage capacitor Cst. The voltage of the first electrode (i.e., the first node N1) of the storage capacitor Cst is Vdata - |Vth|, where Vdata is the data voltage output by the data line DL, and Vth is the threshold voltage of the third transistor T3. The first reset control signal RESET1 provided by the first reset control line RST1 is a high-level signal, the second reset control signal RESET2 provided by the second reset control line RST2 is a high-level signal, and the emission control signal EM provided by the emission control line EML is a high-level signal, so that the first transistor T1, the seventh transistor T7, the eighth transistor T8, the fifth transistor T5, and the sixth transistor T6 are turned off.

[0093] In the fourth stage S14, the emission control signal EM provided by the emission control line EML can be switched from a high-level signal to a low-level signal, so that the fifth transistor T5 and the sixth transistor T6 are turned on. The second scan signal SCAN2 provided by the second scan line GL2 is a low-level signal, so that the second transistor T2 is turned off. The first scan signal SCAN1 provided by the first scan line GL1, the first reset control signal RESET1 provided by the first reset control line RST1, and the second reset control signal RESET2 provided by the second reset control line RST2 are high-level signals, so that the fourth transistor T4, the first transistor T1, the seventh transistor T7, and the eighth transistor T8 are turned off. The first voltage signal VDD output by the first power supply line PL1 can provide a driving voltage to the anode of the light-emitting element EL through the turned-on fifth transistor T5, the third transistor T3, and the sixth transistor T6, driving the light-emitting element EL to emit light.

[0094] During the driving process of the pixel circuit, the driving current flowing through the third transistor T3 is determined by the voltage difference between its gate and the first pole. Since the voltage of the first node N1 is Vdata - |Vth|, the driving current of the third transistor T3 is:

[0095] I = K × (Vgs - Vth) 2 = K × [(VDD - Vdata + |Vth|) - Vth]2 = K × [VDD - Vdata] 2 ;

[0096] Wherein, I is the driving current flowing through the third transistor T3, which is also the driving current for driving the light-emitting element, K is a constant, Vgs is the voltage difference between the gate and the first pole of the third transistor T3, Vth is the threshold voltage of the third transistor T3, Vdata is the data voltage output by the data line DL, and VDD is the first voltage signal output by the first power supply line PL1.

[0097] It can be seen from the above formula that the current flowing through the light-emitting element is independent of the threshold voltage of the third transistor T3. Therefore, the pixel circuit of this embodiment can better compensate for the threshold voltage of the third transistor T3. Moreover, the pixel circuit provided in this embodiment can improve the display defect caused by low frequency and improve the display effect of the light-emitting element.

[0098] Figure 4 It is a partial cross-sectional schematic diagram of the display area of at least one embodiment of the present disclosure. Figure 4 The structure of a sub-pixel in the display area is taken as an example for illustration. In this example, Figure 2 the pixel circuit shown is taken as an example including low-temperature polycrystalline silicon thin-film transistors and oxide thin-film transistors for illustration.

[0099] In some examples, as Figure 4 shown, in the direction perpendicular to the display panel, the display area of the display panel may at least include: a substrate 10, and a circuit structure layer 12, a light-emitting structure layer 13, a packaging structure layer 14, and a touch control structure layer 15 sequentially disposed on the substrate 10. Among them, the display structure layer may at least include the circuit structure layer 12 and the light-emitting structure layer 13. The circuit structure layer 12 may at least include: pixel circuits of multiple sub-pixels, and the pixel circuit of each sub-pixel may include multiple transistors and at least one capacitor. The light-emitting structure layer 13 may at least include: light-emitting elements of multiple sub-pixels.

[0100] In some examples, Figure 4 the structure of each sub-pixel including a first-type transistor 21, a second-type transistor 22, and a capacitor C is taken as an example for illustration. Among them, the first-type transistor 21 may be a low-temperature polycrystalline silicon thin-film transistor, and the second-type transistor 22 may be an oxide thin-film transistor.

[0101] In some examples, the circuit structure layer 12 of the display region may include: a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, a third gate metal layer, a first source / drain metal layer, and a second source / drain metal layer disposed on the substrate 10. A first gate insulating (GI) layer 101 may be disposed between the first semiconductor layer and the first gate metal layer, and a second gate insulating layer 102 may be disposed between the first gate metal layer and the second gate metal layer; a third gate insulating layer 103 may be disposed between the second gate metal layer and the second semiconductor layer; a fourth gate insulating layer 104 may be disposed between the second semiconductor layer and the third gate metal layer; an interlayer insulating layer 105 may be disposed between the third gate metal layer and the first source / drain metal layer; a passivation (PVX) layer 106 and a first planarization (PLN) layer 107 may be disposed between the first source / drain metal layer and the second source / drain metal layer, and the first planarization layer 107 may be located on a side of the passivation layer 106 away from the substrate 10; a second planarization layer 108 may be disposed on a side of the second source / drain metal layer away from the substrate 10. Among them, the first gate insulating layer 101, the second gate insulating layer 102, the third gate insulating layer 103, the fourth gate insulating layer 104, the interlayer insulating layer 105, and the passivation layer 106 may be inorganic insulating layers, and the first planarization layer 107 and the second planarization layer 108 may be organic insulating layers. However, this embodiment is not limited thereto. In some other examples, a buffer layer may further be disposed on a side of the first semiconductor layer close to the substrate, and the buffer layer may prevent harmful substances in the substrate from invading the interior of the display panel and may also increase the adhesion of the film layers in the display panel to the substrate. In some other examples, a bottom shielding metal layer (BSM, Bottom Shielding Metal) may further be disposed on a side of the buffer layer close to the substrate, and the bottom shielding metal layer may be configured to at least partially cover the active layer of the transistors of the pixel circuit to avoid the influence of external light on the performance of the transistors. In some other examples, the passivation layer may be omitted between the first source / drain metal layer and the second source / drain metal layer, and only the first planarization layer may be disposed between the first source / drain metal layer and the second source / drain metal layer.

[0102] In some examples, such as Figure 4As shown, the first semiconductor layer of the display region may at least include: the first active layer 210 of the first type transistor 21. The first active layer 210 of the first type transistor 21 may include: a first region 2101, a second region 2102, and a channel region 2100 located between the first region 2101 and the second region 2102. The first gate metal layer may at least include: the first gate 213 of the first type transistor 21, and the first electrode plate 231 of the capacitor 23. The orthographic projection of the first gate 213 of the first type transistor 21 on the substrate 10 may cover the orthographic projection of the channel region 2100 of the first active layer 210 on the substrate 10. The second gate metal layer may at least include: the second electrode plate 232 of the capacitor 23, and the third gate 224 of the second type transistor 22. The orthographic projections of the second electrode plate 232 and the first electrode plate 231 of the capacitor 23 on the substrate 10 may at least partially overlap, for example, they may coincide. The second semiconductor layer may at least include: the second active layer 220 of the second type transistor 22. The third gate metal layer may at least include: the second gate 223 of the second type transistor 22. The orthographic projection of the second gate 223 of the second type transistor 22 on the substrate 10 and the orthographic projection of the second active layer 220 on the substrate 10 may partially overlap. The orthographic projection of the third gate 224 of the second type transistor 22 on the substrate 10 and the orthographic projection of the second active layer 220 on the substrate 10 may partially overlap. The third gate 224 may be the bottom gate of the second type transistor 22, and the second gate 223 may be the top gate of the second type transistor 22.

[0103] In some examples, such as Figure 4As shown, the first source-drain metal layer in the display area may at least include: the first source 211 and the first drain 212 of the first-type transistor 21, the second source 221 and the second drain 222 of the second-type transistor 22. The interlayer insulating layer 105 may be provided with a plurality of pixel vias in the display area (for example, including a first pixel via, a second pixel via, a third pixel via, and a fourth pixel via). The interlayer insulating layer 105, the fourth gate insulating layer 104, the third gate insulating layer 103, the second gate insulating layer 102, and the first gate insulating layer 101 within the first pixel via may be removed to expose at least a part of the surface of the first region 2101 of the first active layer 210; the interlayer insulating layer 105, the third gate insulating layer 104, the third gate insulating layer 103, the second gate insulating layer 102, and the first gate insulating layer 101 within the second pixel via may be removed to expose at least a part of the surface of the second region 2102 of the first active layer 210. The interlayer insulating layer 105, the fourth gate insulating layer 104, and the third gate insulating layer 103 within the third pixel via and the fourth pixel via may be removed to expose at least a part of the surfaces at both ends of the second active layer 220. The first source 211 of the first-type transistor 21 may be electrically connected to the first region 2101 of the first active layer 210 through the first pixel via, and the first drain 212 may be electrically connected to the second region 2102 of the first active layer 210 through the second pixel via. The second source 221 of the second-type transistor 22 may be electrically connected to one end of the second active layer 220 through the third pixel via, and the second drain 222 of the second-type transistor 22 may be electrically connected to the other end of the second active layer 220 through the fourth pixel via. The second source-drain metal layer may at least include: a first transfer electrode 241. The first transfer electrode 241 may be electrically connected to the first drain 212 of the first-type transistor 21 in the pixel circuit through a fifth pixel via formed in the passivation layer 106 and the first planarization layer 107. In this example, the electrical connection between the pixel circuit and the light-emitting element may be achieved through the first transfer electrode 241.

[0104] In some examples, the gate lines in the display area may be located, for example, in the first gate metal layer, the data lines in the display area may be located, for example, in the second source-drain metal layer, and the high-potential power supply lines in the display area may be located, for example, in the second source-drain metal layer. This embodiment is not limited thereto.

[0105] In some examples, such as Figure 4As shown, the light-emitting structure layer 13 may include: a pixel definition layer 134 and a plurality of light-emitting elements. For example, each light-emitting element may include: a stacked first electrode 131, an organic light-emitting layer 132, and a second electrode 133. The first electrode 131 of the light-emitting element may be an anode, and the first electrode 131 may be disposed on the second flat layer 108 and electrically connected to the first transfer electrode 241 through a sixth pixel via formed in the second flat layer 108. The pixel definition layer 134 is disposed on the first electrode 131 and the second flat layer 108, and the pixel definition layer 134 may be provided with a plurality of pixel openings, and at least a part of the surface of a corresponding first electrode 131 may be exposed through one pixel opening. At least a part of the organic light-emitting layer 132 may be disposed in one pixel opening and connected to the corresponding first electrode 131. The second electrode 133 may be disposed on the organic light-emitting layer 132 and connected to the organic light-emitting layer 132. The organic light-emitting layer 132 can emit light of a corresponding color under the drive of the first electrode 131 and the second electrode 133.

[0106] In some examples, the organic light-emitting layer 132 of the light-emitting element may include a light-emitting layer (EML, Emitting Layer), and at least one of the following film layers: a hole injection layer (HIL, Hole Injection Layer), a hole transport layer (HTL, Hole Transport Layer), a hole block layer (HBL, Hole Block Layer), an electron block layer (EBL, Electron Block Layer), an electron injection layer (EIL, Electron Injection Layer), and an electron transport layer (ETL, Electron Transport Layer). Under the voltage drive of the first electrode 131 and the second electrode 133, light can be emitted according to the required gray level by using the light-emitting characteristics of the organic material.

[0107] In some examples, the light-emitting layers of light-emitting elements of different colors can be different. For example, a red light-emitting element includes a red light-emitting layer, a green light-emitting element includes a green light-emitting layer, and a blue light-emitting element includes a blue light-emitting layer. To reduce the process difficulty and improve the yield, the hole injection layer and the hole transport layer on one side of the light-emitting layer can use a common layer, and the electron injection layer and the electron transport layer on the other side of the light-emitting layer can use a common layer. In some examples, any one or more of the hole injection layer, the hole transport layer, the electron injection layer, and the electron transport layer can be fabricated by one process (one evaporation process or one inkjet printing process), and isolation can be achieved by the surface step difference of the formed film layer or by means such as surface treatment. For example, any one or more of the hole injection layer, the hole transport layer, the electron injection layer, and the electron transport layer corresponding to adjacent sub-pixels can be isolated. In some examples, the organic light-emitting layer can be formed by evaporation using a fine metal mask (FMM) or an open mask, or can be formed by an inkjet process.

[0108] In some examples, as Figure 4 shown, the encapsulation structure layer 14 can include a stacked first encapsulation layer 141, a second encapsulation layer 142, and a third encapsulation layer 143. Among them, the first encapsulation layer 141 and the third encapsulation layer 143 can use inorganic materials, such as silicon nitride, silicon oxide, silicon oxynitride, etc. The inorganic materials have high density and can prevent the intrusion of water, oxygen, etc. The second encapsulation layer 142 can be disposed between the first encapsulation layer 141 and the third encapsulation layer 143 to ensure that external water vapor cannot enter the light-emitting element. The second encapsulation layer 142 can use an organic material. For example, it can be a polymer material containing a desiccant or a polymer material that can block water vapor, or can be a polymer resin, etc. to planarize the surface of the display panel, and can relieve the stress between the first encapsulation layer 141 and the third encapsulation layer 143, and can also include water-absorbing materials such as desiccants to absorb substances such as water and oxygen that invade the interior. However, this embodiment is not limited thereto. For example, the encapsulation structure layer can adopt a five-layer stacked structure of inorganic / organic / inorganic / organic / inorganic.

[0109] In some examples, the touch structure layer in the display area can include: a plurality of first touch electrodes, a plurality of first connection parts, a plurality of second touch electrodes, and a plurality of second connection parts. The plurality of first touch electrodes can be arranged in the same layer, and adjacent first touch electrodes can be connected through the first connection parts. The plurality of second touch electrodes can be arranged in the same layer, and adjacent second touch electrodes can be connected through the second connection parts.

[0110] In some examples, as Figure 4As shown, in a direction perpendicular to the display panel, the touch structure layer 15 of the display area may include: a touch buffer layer (TBL) 150, a first touch conductive layer 151, a touch interlayer insulating layer (TLD) 153, a second touch conductive layer 152, and a protective layer 154, which are sequentially arranged. Among them, the touch buffer layer 150 and the touch interlayer insulating layer 153 may be inorganic insulating layers, and the protective layer 154 may be an organic insulating layer. For example, the first touch conductive layer 151 may include a plurality of first touch electrodes, a plurality of second touch electrodes, and a plurality of first connection parts. The first touch electrodes and the first connection parts may be an integrated structure connected to each other. The second touch conductive layer 152 may include a plurality of second connection parts. The second connection parts may be connected to adjacent second touch electrodes through vias formed in the touch interlayer insulating layer. However, this embodiment is not limited thereto. In some other examples, the first touch conductive layer may include: a plurality of first touch electrodes, a plurality of second touch electrodes, and a plurality of second connection parts, and the second touch electrodes and the second connection parts may be an integrated structure connected to each other; the second touch conductive layer may include a plurality of first connection parts, and the first connection parts may be connected to adjacent first touch electrodes through vias formed in the touch interlayer insulating layer. In some examples, the first touch electrodes may be driving (Tx) electrodes, and the second touch electrodes may be sensing (Rx) electrodes. Or, the first touch electrodes may be sensing (Rx) electrodes, and the second touch electrodes may be driving (Tx) electrodes. This embodiment is not limited thereto.

[0111] In some examples, the first touch electrodes and the second touch electrodes may have a rhombus shape, such as a regular rhombus, or a horizontally long rhombus, or a vertically long rhombus. In some other examples, the first touch electrodes and the second touch electrodes may have any one or more of a triangle, a square, a trapezoid, a parallelogram, a pentagon, a hexagon, and other polygons. The embodiments of the present disclosure do not limit this here.

[0112] In some examples, the first touch electrodes and the second touch electrodes may be in the form of transparent conductive electrodes. In some other examples, the first touch electrodes and the second touch electrodes may be in the form of a metal mesh. The metal mesh may be formed by interweaving multiple metal wires. The metal mesh may include a plurality of mesh patterns, and the mesh patterns may be polygons formed by multiple metal wires. The first touch electrodes and the second touch electrodes in the form of a metal mesh have advantages such as low resistance, small thickness, and fast response speed.

[0113] Figure 5 It is a schematic diagram of the arrangement of the gate driving circuit according to at least one embodiment of the present disclosure. In some examples, such as Figure 5As shown, multiple gate driving circuits can be provided in the peripheral border area. The multiple gate driving circuits can include: a first scan driving circuit 31, a second scan driving circuit 32, a light-emitting driving circuit 33, a first reset driving circuit 34, and a second reset driving circuit 35. The first scan driving circuit 31 can be configured to provide a first scan signal to multiple rows of pixel circuits in the display area AA. The second scan driving circuit 32 can be configured to provide a second scan signal to multiple rows of pixel circuits in the display area AA. The light-emitting driving circuit 33 can be configured to provide a light-emitting control signal to multiple rows of pixel circuits in the display area AA. The first reset driving circuit 34 can be configured to provide a first reset control signal to multiple rows of pixel circuits in the display area AA. The second reset driving circuit 35 can be configured to provide a second reset control signal to multiple rows of pixel circuits in the display area AA.

[0114] In some examples, taking the display area AA including M rows of pixel circuits as an example for illustration, where M is a positive integer. The multiple rows of pixel circuits in the display area can be sequentially labeled as the first row to the Mth row along the direction close to the first border area B1. The multiple gate driving circuits can include: a first group of gate driving circuits located in the second border area and a second group of gate driving circuits located in the third border area. The first group of gate driving circuits can include the following three gate driving circuits: the light-emitting driving circuit 33, the first reset driving circuit 34, and the second reset driving circuit 35. For example, within the second border area, the second reset driving circuit 35, the light-emitting driving circuit 33, and the first reset driving circuit 34 can be sequentially arranged in the first direction X along the direction close to the display area AA. The second group of gate driving circuits can include the following two gate driving circuits: the first scan driving circuit 31 and the second scan driving circuit 32. For example, within the third border area, the first scan driving circuit 31 and the second scan driving circuit 32 can be sequentially arranged in the first direction X along the direction away from the display area AA. In some other examples, three gate driving circuits can be provided in the peripheral border area, one gate driving circuit can be provided in the second border area, and two gate driving circuits can be provided in the third border area. This embodiment does not limit this.

[0115] In some examples, the first scan driving circuit 31 can include multiple cascaded first scan driving units (for example, including GP(1) to GP(M)). Each stage of the first scan driving unit can be configured to provide a first scan signal to one row of pixel circuits in the display area AA. For example, the first-stage first scan driving unit GP(1) can be configured to provide a first scan signal to the first row of pixel circuits in the display area AA; the Mth-stage first scan driving unit GP(M) can be configured to provide a first scan signal to the Mth row of pixel circuits in the display area AA.

[0116] In some examples, the second scan driving circuit 32 may include a plurality of cascaded second scan driving units (such as GN(1) to GN(M / 2)). Each stage of the second scan driving unit may be configured to provide a second scan signal to adjacent two rows of pixel circuits in the display area AA. For example, the first-stage second scan driving unit GN(1) may be configured to provide a second scan signal to the pixel circuits of the first row and the second row in the display area AA; the M / 2-stage second scan driving unit GP(M / 2) may be configured to provide a second scan signal to the pixel circuits of the (M - 1)-th row and the M-th row in the display area AA.

[0117] In some examples, the light-emitting driving circuit 33 may include a plurality of cascaded light-emitting driving units (such as EM(1) to EM(M / 2)). Each stage of the light-emitting driving unit may be configured to provide a light-emitting control signal to adjacent two rows of pixel circuits in the display area AA. For example, the first-stage light-emitting driving unit EM(1) may be configured to provide a light-emitting control signal to the pixel circuits of the first row and the second row in the display area AA; the M / 2-stage light-emitting driving unit EM(M / 2) may be configured to provide a light-emitting control signal to the pixel circuits of the (M - 1)-th row and the M-th row in the display area AA.

[0118] In some examples, the first reset driving circuit 34 may include a plurality of cascaded first reset driving units (such as RP(1) to RP(M / 2)). Each stage of the first reset driving unit may be configured to provide a first reset control signal to adjacent two rows of pixel circuits in the display area AA. For example, the first-stage first reset driving unit RP(1) may be configured to provide a first reset control signal to the pixel circuits of the first row and the second row in the display area AA; the M / 2-stage first reset driving unit RP(M / 2) may be configured to provide a first reset control signal to the pixel circuits of the (M - 1)-th row and the M-th row in the display area AA.

[0119] In some examples, the second reset driving circuit 35 may include a plurality of cascaded second reset driving units (such as RH(1) to RH(M / 2)). Each stage of the second reset driving unit may be configured to provide a second reset control signal to adjacent two rows of pixel circuits in the display area AA. For example, the first-stage second reset driving unit RH(1) may be configured to provide a second reset control signal to the pixel circuits of the first row and the second row in the display area AA; the M / 2-stage second reset driving unit RH(M / 2) may be configured to provide a second reset control signal to the pixel circuits of the (M - 1)-th row and the M-th row in the display area AA.

[0120] In some examples, such as Figure 1As shown, the first border region B1 may include: a bending region B12, a fan-out region B13, a first signal access region B14, and a second signal access region B15 arranged in sequence along the direction away from the display region AA. The bending region B12 may communicate with the peripheral border region B2 and the fan-out region B13, and is located on the side of the peripheral border region B2 away from the display region AA. The fan-out region B13 may be located on the side of the bending region B12 away from the display region AA. The first signal access region B14 may be located on the side of the fan-out region B13 away from the display region AA. The second signal access region B15 may be located on the side of the first signal access region B14 away from the display region AA.

[0121] In some examples, the peripheral border region B2 may be provided with a first peripheral power line, a second peripheral power line, and a plurality of gate driving circuits. The first peripheral power line may be connected to a first power line electrically connected to the pixel circuits of a plurality of sub-pixels PX in the display region AA, and is configured to transmit a first voltage signal. The second peripheral power line may extend from the left side along the edge of the display panel to the second border region, and from the right side along the edge of the display panel to the third border region. The second peripheral power line may be connected to a second power line, and is configured to transmit a second voltage signal to a plurality of sub-pixels in the display region AA. The plurality of gate driving circuits may be arranged in the second border region B21 and the third border region B22.

[0122] In some examples, a plurality of multiplexing circuits may be provided in the peripheral border region B2 between the display region AA and the first border region B1. For example, a multiplexing circuit may be connected to a multiplexed data line and a plurality of data lines, and is configured to provide the data signal transmitted by the multiplexed data line to the plurality of data lines.

[0123] In some examples, the peripheral border region B2 may also be provided with a plurality of peripheral control lines. The plurality of peripheral control lines may include: a first group of peripheral control lines and a second group of peripheral control lines. For example, the first group of peripheral control lines may include: a plurality of peripheral driving control lines that provide driving control signals (such as including start signals, clock signals, power signals, etc.) to the first group of gate driving circuits in the second border region B21; the second group of peripheral control lines may include: a plurality of peripheral driving control lines that provide driving control signals to the second group of gate driving circuits in the third border region B22. In some other examples, each group of peripheral control lines may include: a plurality of peripheral driving control lines and a plurality of peripheral multiplexing control lines, and the plurality of peripheral multiplexing control lines may be connected to a plurality of multiplexing circuits, and are configured to provide multiplexing control signals to the multiplexing circuits, so that the multiplexing circuits, under the control of the multiplexing control signals, provide the data signals transmitted by the multiplexed data lines to the plurality of data lines.

[0124] In some examples, the peripheral border area B2 may also be provided with multiple peripheral touch lines. The multiple peripheral touch lines may be located in the touch structure layer and connected to the first touch electrode or the second touch electrode of the display area AA.

[0125] In some examples, the bending area B12 may be configured to bend the fan-out area B13, the first signal access area B14, and the second signal access area B15 to the back of the display area AA. The bending area B12 may be provided with multiple bending connection lines for connecting the peripheral border area B2 and the traces transmitting the same signal in the fan-out area B13. The multiple bending connection lines in the bending area B12 may be of the same layer structure. For example, they may all be located in the second source-drain metal layer.

[0126] Figure 6 It is a partial plan view of the first border area of at least one embodiment of the present disclosure. Figure 6 It schematically shows the partial structures of the bending area B12, the fan-out area B13, the first signal access area B14, and the second signal access area B15. Figure 6 It schematically shows the data bending connection lines, touch bending connection lines, control bending connection lines, control connection lines, and data fan-out lines in the first border area as a whole. The control signal lines are only schematically shown by several traces as an example, and the number of various traces in the first border area in this example is not limited.

[0127] In some examples, as Figure 6 shown, the multiple bending connection lines in the bending area B12 may include: the first power bending connection lines 53a, 53b, 53c, and 53d, the second power bending connection lines 54a and 54b, the first group of data bending connection lines 51a, the second group of data bending connection lines 51b, a group of control bending connection lines 52, the first group of touch bending connection lines 55a, and the second group of touch bending connection lines 55b. The second power bending connection line 54a, the first group of data bending connection lines 51a, the first power bending connection line 53a, the first group of touch bending connection lines 55a, the first power bending connection line 53b, a group of control bending connection lines 52, the first power bending connection line 53c, the second group of touch bending connection lines 55b, the first power bending connection line 53d, the first group of data bending connection lines 51b, and the second power bending connection line 54b may be arranged in sequence along the first direction X.

[0128] In some examples, as Figure 6As shown, the fan-out region B13 can be provided with at least a first power supply lead-out line 43, second power supply lead-out lines 44a and 44b, multiple data fan-out lines (such as including a first group of data fan-out lines 41a and a second group of data fan-out lines 41b), multiple control connection lines (such as including a first group of control connection lines 56a and a second group of control connection lines 56b), multiple control signal lines (such as including a first group of control signal lines 42a and a second group of control signal lines 42b), and multiple touch lead-out lines (such as including a first group of touch lead-out lines 45a and a second group of touch lead-out lines 45b).

[0129] In some examples, as Figure 6 shown, the first power supply lead-out line 43 can be connected to the first peripheral power supply line in the peripheral border region through the first power connection lines 53a, 53b, 53c, and 53d in the bending region B12. The first power supply lead-out line 43 can be located, for example, in the first source-drain metal layer, or can be located in the second source-drain metal layer, or can adopt a double-layer routing structure provided in the first source-drain metal layer and the second source-drain metal layer. The first power supply lead-out line 43 can at least include: a first main body portion extending along the first direction X, four connection portions extending along the second direction Y toward the side close to the bending region B12, a first power supply extension portion extending along the third direction F3, and a second power supply extension portion extending along the fourth direction F4. The third direction F3 can intersect both the first direction X and the second direction Y, the fourth direction F4 can intersect both the first direction X and the second direction Y, and the third direction F3 can intersect the fourth direction F4. The four connection portions of the first power supply lead-out line 43 can be electrically connected to the four first power connection lines 53a, 53b, 53c, and 53d in the bending region B12 in one-to-one correspondence. The first power supply extension portion can bypass the first signal access region B14 from the left to extend to connect to a contact pad in the second signal access region B15, and the second power supply extension portion can bypass the first signal access region B14 from the right to extend to connect to a contact pad in the second signal access region B15.

[0130] In some examples, as Figure 6As shown, the second power lead 44a can be connected to the second peripheral power line of the peripheral frame area through the second power connection line 54a of the bending area B12, and the second power lead 44b can be connected to the second peripheral power line of the peripheral frame area through the second power connection line 54b of the bending area B12. The second power lead 44a can be located on the side opposite to the first power lead 43 along the first direction X, and the second power lead 44b can be located on the side of the first power lead 43 along the first direction X. The second power leads 44a and 44b can both be located in the first source and drain metal layer, or can both be located in the second source and drain metal layer, or can adopt a double-layer routing structure arranged in the first source and drain metal layer and the second source and drain metal layer. The second power lead 44a can bypass the first signal access area B14 from the left to extend to connect to the contact pad in the second signal access area B15. The second power lead 44b can bypass the first signal access area B14 from the right to extend to connect to the contact pad in the second signal access area B15.

[0131] In some examples, such as Figure 6 As shown, the plurality of data fan-out lines in the fan-out area B13 may extend substantially along the second direction Y toward the first signal access area B14. The plurality of data fan-out lines may include a first group of data fan-out lines 41 a and a second group of data fan-out lines 41 b. The first group of data fan-out lines 41 a may be located between the second power lead line 44 a and the first group of control connection lines 56 a, and the second group of data fan-out lines 41 b may be located between the second power lead line 44 b and the second group of control connection lines 56 b. Multiple data fan-out lines in the first group of data fan-out lines 41a can be connected to multiple multiplexed data lines in the peripheral frame area through multiple data bend connection lines in the first group of data bend connection lines 51a in the bend area B12, so as to provide data signals to the multiple data lines through multiple multiplexing circuits; multiple data fan-out lines in the second group of data fan-out lines 41b can be connected to multiple multiplexed data lines in the peripheral frame area through multiple data bend connection lines in the second group of data bend connection lines 51b in the bend area B12, so as to provide data signals to the multiple data lines through multiple multiplexing circuits. For example, the first group of data fan-out lines 41a can be configured to provide data signals to sub-pixels in the left half area of the display area, and the second group of data fan-out lines 41b can be configured to provide data signals to sub-pixels in the right half area of the display area. The number of data fan-out lines in the first group of data fan-out lines 41a can be the same as the number of data fan-out lines in the second group of data fan-out lines 41b. For example, the plurality of data fan-out lines may be located in the first gate metal layer, or may be located in the second gate metal layer, or may be alternately arranged in the first gate metal layer and the second gate metal layer.

[0132] In some examples, such as Figure 6As shown, the multiple control connection lines may include: a first set of control connection lines 56a and a second set of control connection lines 56b. The first set of control connection lines 56a and the second set of control connection lines 56b may be located between the first set of data fan-out lines 41a and the second set of data fan-out lines 41b. The multiple control connection lines may be connected to multiple peripheral control lines in the peripheral border area through a set of control bending connection lines 52 in the bending area B12. The arranged shapes of the first set of control connection lines 56a and the second set of control connection lines 56b may be generally an inverted Y shape. For example, the multiple control connection lines may be located in the first gate metal layer, or may be located in the second gate metal layer, or may adopt a double-layer routing structure arranged in the first gate metal layer and the second gate metal layer.

[0133] In some examples, as Figure 6 shown, the multiple control signal lines in the fan-out area B13 may include: a first set of control signal lines 42a and a second set of control signal lines 42b. The first set of control signal lines 42a may be connected to the first set of control connection lines 56a, and the second set of control signal lines 42b may be connected to the second set of control connection lines 56b. The orthographic projection of the first set of control signal lines 42a on the substrate overlaps with the orthographic projection of the first set of data fan-out lines 41a on the substrate, and the orthographic projection of the second set of control signal lines 42b on the substrate overlaps with the orthographic projection of the second set of data fan-out lines 41b on the substrate. The first set of control signal lines 42a and the second set of control signal lines 42b may be located on a side of the first main body portion of the first power supply lead-out line 43 away from the bending area B12.

[0134] In some examples, each set of control signal lines may at least include multiple driving control lines, and the driving control lines may be configured to provide driving control signals to the gate driving circuit. The multiple driving control lines included in the first set of control signal lines may be configured to provide driving control signals to the first set of gate driving circuits located in the second border area, and the multiple driving control lines included in the second set of control signal lines may be configured to provide driving control signals to the second set of gate driving circuits located in the third border area. In other examples, each set of control signal lines may at least include: multiple driving control lines and multiple multiplexing control lines, and the multiple multiplexing control lines may be configured to provide multiplexing control signals to multiple multiplexing circuits in the peripheral border area.

[0135] In some examples, the first set of control signal lines 42a may bypass the first signal access area B14 from the left to extend to be connected to a contact pad in the second signal access area B15; the second set of control signal lines 42b may bypass the first signal access area B14 from the right to extend to be connected to a contact pad in the second signal access area B15.

[0136] In some examples, the fan-out region B13 may also be provided with a first electrostatic discharge circuit 46 and a second electrostatic discharge circuit 47. The first set of control signal lines 42a may be connected to the first electrostatic discharge circuit 46, and the second set of control signal lines 42b may be connected to the second electrostatic discharge circuit 47. The first electrostatic discharge circuit 46 may be configured to provide an electrostatic discharge path for the first set of control signal lines 42a, and the second electrostatic discharge circuit 47 may be configured to provide an electrostatic discharge path for the second set of control signal lines 42b. The first electrostatic discharge circuit 46 may be located between the first set of data fan-out lines 41a and the first set of touch lead-out lines 45a, and the second electrostatic discharge circuit 47 may be located between the second set of data fan-out lines 41b and the second set of touch lead-out lines 45b.

[0137] In some examples, as Figure 6 shown, multiple touch lead-out lines in the fan-out region B12 may extend substantially along the second direction Y towards the first signal access region B14. The multiple touch lead-out lines may include a first set of touch lead-out lines 45a and a second set of touch lead-out lines 45b. The first set of touch lead-out lines 45a may be connected to the peripheral touch lines in the peripheral border region through the first set of touch bending connection lines 55a in the bending region B12, and the second set of touch lead-out lines 45b may be connected to the peripheral touch lines in the peripheral border region through the second set of touch bending connection lines 55b in the bending region B12. The arranged shapes of the first set of touch lead-out lines 45a and the second set of touch lead-out lines 45b may be substantially Y-shaped. For example, the multiple touch lead-out lines may be located in the first touch conductive layer or the second touch conductive layer of the touch structure layer. The orthographic projection of the first set of touch lead-out lines 45a on the substrate may overlap with the orthographic projection of the first set of control connection lines 56a on the substrate, and the orthographic projection of the second set of touch lead-out lines 45b on the substrate may overlap with the orthographic projection of the second set of control connection lines 56b on the substrate. The first set of touch lead-out lines 45a and the second set of touch lead-out lines 45b may be located between the first set of control signal lines 42a and the second set of control signal lines 42b.

[0138] In some examples, as Figure 6 shown, the first signal access region B14 may be configured to set a driving chip (IC, Integrated Circuit). For example, the driving chip set in the first signal access region B14 may be a display driving chip or may be a touch and display driver integration chip (TDDI, Touch and Display Driver Integration). The first signal access region B14 may also be referred to as a driving chip setting area. The driving chip may be configured to generate data signals required for driving sub-pixels and provide the data signals to the data lines in the display region.

[0139] In some examples, the first signal access area B14 may be provided with a plurality of first contact pads, and the plurality of first contact pads may include: a first group of first contact pads 61 and a second group of first contact pads 62. The second group of first contact pads 62 may be located on a side of the first group of first contact pads 61 away from the bending area B12. The plurality of first contact pads within the first group of first contact pads 61 may be arranged in at least one row in an array along the first direction X. A plurality of data fan-out lines may be connected to the plurality of first contact pads within the first group of first contact pads 61 in the first signal access area B14 to be configured to receive data signals from the driving chip; a plurality of touch lead-out lines may be connected to the plurality of first contact pads within the first group of first contact pads 61 in the first signal access area B14 to be configured to receive touch signals from the driving chip. The plurality of first contact pads within the second group of first contact pads 62 may be arranged in one row along the first direction X.

[0140] In some examples, the second signal access area B15 may be provided with a plurality of second contact pads 63. The plurality of second contact pads 63 may be configured to bind a flexible printed circuit board (FPC), such that a plurality of signal lines (such as including a plurality of control signal lines, a first power supply lead-out line, a second power supply lead-out line, etc.) are connected to an external control device through the plurality of second contact pads 63. The second signal access area B15 may also be referred to as a circuit binding area. The second group of first contact pads 62 in the first signal access area B14 may be electrically connected to the plurality of second contact pads 63 in the second signal access area B15 through a plurality of pin connection lines 64.

[0141] In some examples, since the number of gate driving circuits provided in the peripheral border area is an odd number (such as five), the number of gate driving circuits provided in the second border area and the third border area cannot be evenly distributed (for example, three gate driving circuits are provided in the second border area, and two gate driving circuits are provided in the third border area), which may cause uneven overlap in the routing of two groups of data fan-out lines and two groups of control signal lines in the first border area. For example, the number of control signal lines in the first group of control signal lines that overlap with the first group of data fan-out lines is greater than the number of control signal lines in the second group of control signal lines that overlap with the second group of data fan-out lines, thereby making the parasitic capacitance generated between the plurality of data fan-out lines and the overlapping routing inconsistent, and easily causing display defects such as low gray-scale dark stripes. In this example, by increasing the distance between the data fan-out lines and the overlapping control signal lines, the parasitic capacitance between the data fan-out lines and the overlapping control signals is reduced, thereby improving display defects such as low gray-scale dark stripes caused by uneven overlap of the data fan-out lines and the control signal lines.

[0142] Figure 7 For Figure 6 a partial enlarged schematic diagram of the area S1 inFigure 8A is Figure 7 An example of a partial cross-sectional view along the Q1 - Q1' direction in Figure 8B is Figure 7 An example of a partial cross-sectional view along the Q2 - Q2' direction in . Here, the positional relationship between the first group of data fan-out lines 41a and the first group of control signal lines 42a will be taken as an example for illustration.

[0143] In some examples, as Figure 7 shown, the first group of data fan-out lines 41a may include: a plurality of first data fan-out lines 411a located in the first gate metal layer and a plurality of second data fan-out lines 412a located in the second gate metal layer. The plurality of first data fan-out lines 411a and the plurality of second data fan-out lines 412a may be arranged at intervals one by one, and the orthographic projections of the first data fan-out lines 411a and the second data fan-out lines 412a on the substrate do not overlap. In other words, the interval distance between the orthographic projection of the first data fan-out line 411a and the adjacent second data fan-out line 412a on the substrate may be greater than 0.

[0144] In some examples, as Figure 6 and Figure 7 shown, each control signal line in the first group of control signal lines 42a may include: a first control segment 421a, a second control segment 422a, and a third control segment 423a. One end of the first control segment 421a is connected to one end of the second control segment 422a, and the other end of the first control segment 421a is connected to one end of the third control segment 423a. The other end of the third control segment 423a may be connected to the control connection line 56. The other end of the second control segment 422a may extend to be connected to the contact pad in the second signal access area. The orthographic projection of the first control segment 421a on the substrate overlaps with the orthographic projection of the first group of data fan-out lines 41a on the substrate, and the orthographic projections of the second control segment 422a and the third control segment 423a on the substrate do not overlap with the orthographic projection of the first group of data fan-out lines 41a on the substrate.

[0145] In some examples, the second control segment 422a and the third control segment 423a may be of the same layer structure, for example, they may be located in the first source-drain metal layer. The first control segment 421a and the second control segment 422a and the third control segment 423a may be of different layer structures. For example, the first control segment 421a may be located on the side away from the substrate of the second control segment 422a and the third control segment 423a. For example, the first control segment 421a may be located in the second source-drain metal layer. However, this embodiment is not limited thereto. In other examples, the first control segment, the second control segment, and the third control segment of the control signal line may be an integrally connected structure, for example, they may be located in the second source-drain metal layer.

[0146] In some examples, asFigure 8A and Figure 8B As shown, the first data fan-out line 411a is located in the first gate metal layer, the second data fan-out line 412a is located in the second gate metal layer, and the first control segment 421a of the control signal lines in the first group of control signal lines 42a is located in the second source / drain metal layer. At least one organic insulating layer (including the first planarization layer 107) and a plurality of inorganic insulating layers (for example, at least including the passivation layer 106, the interlayer insulating layer 105, and the second gate insulating layer 102) are provided between the first control segment 421a of the control signal line and the overlapping first data fan-out line 411a; at least one organic insulating layer (including the first planarization layer 107) and a plurality of inorganic insulating layers (for example, at least including the passivation layer 106 and the interlayer insulating layer 105) are provided between the first control segment 421a of the control signal line and the overlapping second data fan-out line 412a.

[0147] In some examples, as Figure 6 shown, each control signal line in the second group of control signal lines 42b may include: a first control segment 421b, a second control segment 422b, and a third control segment 423b. The orthographic projection of the first control segment 421b on the substrate overlaps with the orthographic projection of the second group of data fan-out lines 41b on the substrate, and the orthographic projections of the second control segment 422b and the third control segment 423b on the substrate do not overlap with the orthographic projection of the second group of data fan-out lines 41b on the substrate. The film layer arrangement of the second group of data fan-out lines 41b is the same as that of the first group of data fan-out lines 41a, and the film layer arrangement of the second group of control signal lines 42b is the same as that of the second group of control signal lines 42a, so it will not be elaborated here.

[0148] In this example, by providing an organic insulating layer between the data fan-out line and the first control segment of the overlapping control signal line, the data fan-out line and the first control segment of the control signal line can be separated by a relatively large distance, so as to reduce the parasitic capacitance between the data fan-out line and the control signal line and improve display defects such as low gray-scale dark stripes caused by uneven overlap between the data fan-out line and the control signal line.

[0149] Figure 9 Another partial cross-sectional schematic diagram of the display panel according to at least one embodiment of the present disclosure. Figure 10A is Figure 7 another partial cross-sectional example diagram in the direction of Q1-Q1' in Figure 10B is Figure 7 another partial cross-sectional example diagram in the direction of Q2-Q2' in

[0150] In some examples, as Figure 9As shown, in the direction perpendicular to the display panel, the circuit structure layer 12 of the display area may include: a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, a third gate metal layer, a first source-drain metal layer, a second source-drain metal layer, and a third source-drain metal layer disposed on the substrate 10. A passivation layer 106 and a first planarization layer 107 may be disposed between the first source-drain metal layer and the second source-drain metal layer, a second planarization layer 108 may be disposed between the second source-drain metal layer and the third source-drain metal layer, and a third planarization layer 109 may be disposed on the side of the third source-drain metal layer away from the substrate 10. The first planarization layer 107, the second planarization layer 108, and the third planarization layer 109 may be organic insulating layers. The third source-drain metal layer may at least include: a second transfer electrode 242. The second transfer electrode 242 may be connected to a first transfer electrode 241 located in the second source-drain metal layer through a via formed in the second planarization layer 108. In this example, the electrical connection between the pixel circuit and the light-emitting element may be achieved through the second transfer electrode 242 and the first transfer electrode 241. For the remaining film layer structures of the display panel in this example, reference may be made to the description of the embodiment shown in Figure 4 and will not be elaborated herein.

[0151] In some examples, as Figure 10A and Figure 10B shown, the first data fan-out line 411a is located in the first gate metal layer, the second data fan-out line 412a is located in the second gate metal layer, and the first control segment 421a of the control signal lines in the first group of control signal lines 42a may be located in the third source-drain metal layer. At least two organic insulating layers (including the first planarization layer 107 and the second planarization layer 108) and multiple inorganic insulating layers (such as at least including the passivation layer 106, the interlayer insulating layer 105, and the second gate insulating layer 102) are provided between the first control segment 421a of the control signal lines and the overlapping first data fan-out line 411a; at least two organic insulating layers (including the first planarization layer 107 and the second planarization layer 108) and multiple inorganic insulating layers (such as at least including the passivation layer 106 and the interlayer insulating layer 105) are provided between the first control segment 421a of the control signal lines and the overlapping second data fan-out line 412a. For the remaining descriptions of the first border region in this example, reference may be made to the description of the foregoing embodiment and will not be elaborated herein.

[0152] In this example, by providing two organic insulating layers between the data fan-out line and the first control segment of the overlapping control signal line, the data fan-out line and the first control segment of the control signal line can be spaced farther apart, which can better isolate the parasitic capacitance between the data fan-out line and the control signal line and improve display defects such as low gray-scale dark stripes caused by uneven overlap between the data fan-out line and the control signal line.

[0153] In this example, by adjusting the film layer where the first control segment of the control signal line is located (for example, the first control segment is located in the second source-drain metal layer or the third source-drain metal layer), the distance between the data fan-out line and the first control segment of the overlapping control signal line can be increased, and the parasitic capacitance between the data fan-out line and the overlapping control signal line can be reduced, thereby effectively improving display defects such as low gray-scale dark stripes caused by uneven overlap between the data fan-out line and the control signal line.

[0154] Figure 11 This is another partial plan view of the first border area of at least one embodiment of the present disclosure. Figure 11 It schematically shows the partial structures of the bending area B12, the fan-out area B13, the first signal access area B14, and the second signal access area B15. Figure 11 The data bending connection line, the touch bending connection line, the control bending connection line, the control connection line, and the data fan-out line in the first border area are schematically shown as a whole. Only several signal traces are taken as examples for the control signal line. The number of various signal traces in the first border area is not limited in this example.

[0155] In some examples, as Figure 11 shown, the number of control signal lines in the first group of control signal lines 42a is greater than the number of control signal lines in the second group of control signal lines 42b. Each control signal line in the first group of control signal lines 42a can be an integral structure located in the same film layer, and each control signal line in the second group of control signal lines 42b can be an integral structure located in the same film layer. For example, multiple control signal lines can be located in the first source-drain metal layer. However, this embodiment is not limited thereto. In other examples, multiple control signal lines can be located in the second source-drain metal layer or the third source-drain metal layer.

[0156] Figure 12A It is Figure 11 a partial enlarged view of the area S2 in Figure 12B It is Figure 12A a partial view of the first group of data fan-out lines in Figure 12A and Figure 12B shown, the first group of data fan-out lines 41a can include: multiple first data fan-out lines 411a located in the first gate metal layer and multiple second data fan-out lines 412a located in the second gate metal layer. The multiple first data fan-out lines 411a and the multiple second data fan-out lines 412a can be arranged at intervals one by one, and the orthographic projections of the first data fan-out lines 411a and the second data fan-out lines 412a on the substrate do not overlap. In other words, the interval distance between the orthographic projections of the first data fan-out line 411a and the adjacent second data fan-out line 412a on the substrate can be greater than 0.

[0157] In some examples, asFigure 12A and Figure 12B As shown in Figure 12B , each data fan-out line in the first group of data fan-out lines 41a may include: a first sub-segment 41-1, a third sub-segment 41-3, and a fourth sub-segment 41-4. One end of the first sub-segment 41-1 is connected to one end of the third sub-segment 41-3, and the other end of the first sub-segment 41-1 is connected to one end of the fourth sub-segment 41-4. The other end of the third sub-segment 41-3 may extend toward the bending region side, and the other end of the fourth sub-segment 41-4 may extend toward the first signal access region side. The orthographic projection of the first sub-segment 41-1 on the substrate overlaps with the orthographic projection of the first group of control signal lines 42a on the substrate, and the orthographic projections of the third sub-segment 41-3 and the fourth sub-segment 41-4 on the substrate may not overlap with the orthographic projection of the first group of control signal lines 42a on the substrate. The first sub-segment 41-1, the third sub-segment 41-3, and the fourth sub-segment 41-4 of the data fan-out lines in the first group of data fan-out lines 41a may be an integrally connected structure. The orthographic projections of the data fan-out lines in the first group of data fan-out lines 41a on the substrate may be straight-line traces, and the orthographic projection of the first sub-segment 41-1 on the substrate may be generally elongated. The line width of the first sub-segment 41-1 of the data fan-out line may be the first line width W1, and the line widths of the third sub-segment 41-3 and the fourth sub-segment 41-4 may be the same as the line width of the first sub-segment 41-1.

[0158] In some examples, as Figure 12A and Figure 12B shown, each control signal line in the first group of control signal lines 42a may include: a first control segment 421a, and the orthographic projection of the first control segment 421a on the substrate overlaps with the orthographic projection of the first sub-segment 41-1 of the data fan-out lines in the first group of data fan-out lines 41a on the substrate. For example, the first control segment 421a of each control signal line may have a third line width K1.

[0159] In some examples, the orthographic projection of each data fan-out line in the first group of data fan-out lines 41a and the first group of control signal lines 42a on the substrate may have a first overlapping area. The first overlapping area may be the sum of the overlapping areas of one data fan-out line in the first group of data fan-out lines 41a and all the control signal lines in the first group of control signal lines 42a. The first overlapping areas corresponding to multiple data fan-out lines in the first group of data fan-out lines 41a may be substantially the same.

[0160] Figure 13A is Figure 11 a partial enlarged schematic diagram of region S3 in Figure 13B is Figure 13A a partial schematic diagram of the second group of data fan-out lines in Figure 13A and Figure 13BAs shown, the second group of data fan-out lines 41b may include: a plurality of first data fan-out lines 411b located in the first gate metal layer and a plurality of second data fan-out lines 412b located in the second gate metal layer. The plurality of first data fan-out lines 411b and the plurality of second data fan-out lines 412b may be arranged at intervals one by one, and the orthographic projections of the first data fan-out lines 411b and the second data fan-out lines 412b on the substrate do not overlap. In other words, the interval distance between the orthographic projection of a first data fan-out line 411b and an adjacent second data fan-out line 412b on the substrate may be greater than 0.

[0161] In some examples, as Figure 13A and Figure 13B shown, each data fan-out line in the second group of data fan-out lines 41b may include: a second sub-segment 41-2, a fifth sub-segment 41-5, and a sixth sub-segment 41-6. One end of the second sub-segment 41-2 is connected to one end of the fifth sub-segment 41-5, and the other end of the second sub-segment 41-2 is connected to one end of the sixth sub-segment 41-6. The other end of the fifth sub-segment 41-5 may extend toward the bending region side, and the other end of the sixth sub-segment 41-6 may extend toward the first signal access region side. The orthographic projection of the second sub-segment 41-2 on the substrate overlaps with the orthographic projection of the second group of control signal lines 42b on the substrate, and the orthographic projections of the fifth sub-segment 41-5 and the sixth sub-segment 41-6 on the substrate may not overlap with the orthographic projection of the second group of control signal lines 42b on the substrate. The second sub-segment 41-2, the fifth sub-segment 41-5, and the sixth sub-segment 41-6 of the data fan-out lines in the second group of data fan-out lines 41b may be an integrally connected structure.

[0162] In some examples, as Figure 13A and Figure 13B shown, each control signal line in the second group of control signal lines 42b may include: a first control segment 421b, and the orthographic projection of the first control segment 421b on the substrate overlaps with the orthographic projection of the second sub-segment 41-2 of the data fan-out lines in the second group of data fan-out lines 41b on the substrate. For example, the first control segment 421b of each control signal line may have a fourth line width K2. For example, the fourth line width K2 may be substantially the same as the third line width K1.

[0163] In some examples, each data fan-out line in the second group of data fan-out lines 41b and the orthographic projection of the second group of control signal lines 42b on the substrate may have a second overlapping area. The second overlapping area may be the sum of the overlapping areas of one data fan-out line in the second group of data fan-out lines 41b and all the control signal lines in the second group of control signal lines 42b. The second overlapping areas corresponding to the plurality of data fan-out lines in the second group of data fan-out lines 41b may be substantially the same.

[0164] In some examples, the second sub-segment 41-2 of the data fan-out line within the second group of data fan-out lines 41b may be a serpentine trace in the orthographic projection on the substrate. Since the number of control signal lines within the second group of control signal lines is less than the number of control signal lines within the first group of control signal lines, the number of control signal lines overlapped by each data fan-out line within the second group of data fan-out lines 41b is less than the number of control signal lines overlapped by each data fan-out line within the first group of data fan-out lines 41a. In this example, by setting the second sub-segment 41-2 of the data fan-out line within the second group of data fan-out lines 41b as a serpentine trace, the second overlapping area corresponding to the data fan-out lines within the second group of data fan-out lines can be increased, so that the second overlapping area can be substantially the same as the first overlapping area corresponding to the data fan-out lines within the first group of data fan-out lines, in order to reduce the parasitic capacitance difference between the two groups of data fan-out lines and the overlapping traces. In some examples, the ratio range of the first overlapping area to the second overlapping area may be from 0.9 to 1.1, for example, it may be approximately 1.0.

[0165] In some examples, the fifth sub-segment 41-5 or the sixth sub-segment 41-6 of at least one data fan-out line within the second group of data fan-out lines 41b may be a serpentine trace in the orthographic projection on the substrate. For example, the fifth sub-segment 41-5 or the sixth sub-segment 41-6 of multiple data fan-out lines close to the touch lead-out line within the second group of data fan-out lines 41b may be a serpentine trace in the orthographic projection on the substrate. In some examples, since the number of pixel circuits electrically connected to each of the multiple data lines in the display area is different, the loads of the multiple data lines are different. For example, the display area is circular or elliptical, and the display area can be divided into a middle area and left and right side areas along the first direction X. The number of pixel circuits connected to the data lines in the middle area is more than the number of pixel circuits connected to the data lines in the left or right side area, so that the load of the data lines in the middle area is different from the load of the data lines in the left and right side areas. In order to ensure the display effect of the display area, it is necessary to perform load compensation on the data lines to ensure that the loads of the multiple data lines in the display area are substantially the same. In this example, by setting the fifth sub-segment 41-5 or the sixth sub-segment 41-6 of at least one data fan-out line as a serpentine trace in the orthographic projection on the substrate, the load compensation for the data lines in the display area is adjusted.

[0166] In some examples, the line widths of the fifth sub-segment 41-5 and the sixth sub-segment 41-6 with a straight-line trace design within the second group of data fan-out lines 41b may be substantially the same as the first line width of the first sub-segment 41-1 of the data fan-out lines within the first group of data fan-out lines 41a.

[0167] This example uses a serpentine routing design for partial line segments of the outgoing lines of the second group of data, which can not only increase the overlapping area between the outgoing lines of the second group of data and the second group of control signal lines, thereby reducing the parasitic capacitance difference between the two groups of outgoing data lines and the overlapping control signal lines, but also perform load compensation on the data lines in the display area to ensure that the loads of multiple data lines in the display area are approximately the same.

[0168] Figure 14A For Figure 11 Another partial enlarged schematic diagram of region S3 in Figure 14B For Figure 14A A partial schematic diagram of the second group of outgoing data lines in Figure 14A And Figure 14B As shown, each outgoing data line in the second group of outgoing data lines 41b may include: a second sub-segment 41-2, a fifth sub-segment 41-5, and a sixth sub-segment 41-6. One end of the second sub-segment 41-2 is connected to one end of the fifth sub-segment 41-5, and the other end of the second sub-segment 41-2 is connected to one end of the sixth sub-segment 41-6. The other end of the fifth sub-segment 41-5 may extend toward the bending region side, and the other end of the sixth sub-segment 41-6 may extend toward the first signal access region side. The orthographic projection of the second sub-segment 41-2 on the substrate overlaps with the orthographic projection of the second group of control signal lines 42b on the substrate, and the orthographic projections of the fifth sub-segment 41-5 and the sixth sub-segment 41-6 on the substrate may not overlap with the orthographic projection of the second group of control signal lines 42b on the substrate. The second sub-segment 41-2, the fifth sub-segment 41-5, and the sixth sub-segment 41-6 of the outgoing data lines in the second group of outgoing data lines 41b may be an integrally connected structure.

[0169] In some examples, such as Figure 14A And Figure 14B As shown, the orthographic projection of the second sub-segment 41-2 of the outgoing data lines of the second group of outgoing data lines 41b on the substrate may be a straight-line routing. The second sub-segment 41-2 may have a second line width W2. The second line width W2 may be the maximum line width of the second sub-segment 41-2. The second line width W2 of the second sub-segment 41-2 may be greater than the first line width W1 of the first sub-segment 41-1 of the outgoing data lines of the first group of outgoing data lines 41a.

[0170] In some examples, the fifth sub-segment 41-5 and the sixth sub-segment 41-6 of the data fan-out lines 41b of the second group of data fan-out lines may both be straight-line traces in the orthographic projection on the substrate. The line widths of the fifth sub-segment 41-5 and the sixth sub-segment 41-6 may be substantially the same, for example, both the same as the first line width W1. For example, the ratio between the second line width W2 and the first line width W1 may be greater than 1 and less than 2, such as about 1.7. In some examples, the first line width W1 may be about 5.1 micrometers (um), and the second line width W2 may be about 8.7 um.

[0171] In this example, by increasing the line width of the second sub-segment of the second group of data fan-out lines, the overlapping area between the second group of data fan-out lines and the second group of control signal lines can be increased, so that the second overlapping area corresponding to the data fan-out lines in the second group of data fan-out lines and the first overlapping area corresponding to the data fan-out lines in the first group of data fan-out lines can be substantially the same, increasing the parasitic capacitance between the second group of data fan-out lines and the overlapping traces, making the parasitic capacitances between the two groups of data fan-out lines and the overlapping traces substantially the same, thereby improving display defects such as low gray-scale dark stripes caused by uneven overlapping of data fan-out lines and control signal lines.

[0172] Figure 15 For Figure 11 Another partial enlarged schematic diagram of region S3. In some examples, as Figure 15 shown, the line shapes and line widths of the data fan-out lines in the second group of data fan-out lines 41b can be the same as those of the data fan-out lines in the first group of data fan-out lines 41a. The fourth line width K2 of the first control segment 421b of at least one control signal line in the second group of control signal lines can be greater than the third line width K1 of the first control segment 421a of the control signal lines in the first group of control signal lines. For example, the fourth line width K2 of the first control segment 421b of each control signal line in the second group of control signal lines can be the same and greater than the third line width K1.

[0173] In this example, by increasing the line width of the first control segment of the second group of control signal lines, the overlapping area between the second group of data fan-out lines and the second group of control signal lines can be increased, so that the second overlapping area corresponding to the data fan-out lines in the second group of data fan-out lines and the first overlapping area corresponding to the data fan-out lines in the first group of data fan-out lines can be substantially the same, thereby increasing the parasitic capacitance between the second group of data fan-out lines and the overlapping control signal lines, making the parasitic capacitances between the two groups of data fan-out lines and the overlapping control signal lines substantially the same, and further improving display defects such as low gray-scale dark stripes caused by uneven overlapping of data fan-out lines and control signal lines.

[0174] In some examples, Figures 13A to 15In the illustrated embodiment, in order to ensure that the parasitic capacitance between the data fan-out lines in the first group of data fan-out lines and the first group of control signal lines can be substantially the same as the parasitic capacitance between the data fan-out lines in the second group of data fan-out lines and the second group of control signal lines, the overlapping area between the data fan-out lines in the second group of data fan-out lines and the second group of control signal lines can be increased to increase the parasitic capacitance between the data fan-out lines in the second group of data fan-out lines and the second group of control signal lines.

[0175] In some other examples, the overlapping area between the data fan-out lines in the first group of data fan-out lines and the first group of control signal lines can be reduced to reduce the parasitic capacitance between the data fan-out lines in the first group of data fan-out lines and the first group of control signal lines, so as to ensure that the parasitic capacitance between the data fan-out lines in the first group of data fan-out lines and the first group of control signal lines can be substantially the same as the parasitic capacitance between the data fan-out lines in the second group of data fan-out lines and the second group of control signal lines.

[0176] Figure 16A For Figure 11 Another partial enlarged schematic diagram of region S2 in Figure 16B For Figure 16A A partial schematic diagram of the first group of data fan-out lines in Figure 17A For Figure 11 Another partial enlarged schematic diagram of region S3 in Figure 17B For Figure 17A A partial schematic diagram of the second group of data fan-out lines in

[0177] In some examples, as Figure 16A and Figure 16B shown, each data fan-out line in the first group of data fan-out lines 41a may include a third sub-segment 41-3, a first sub-segment 41-1, and a fourth sub-segment 41-4 connected in sequence. The orthographic projection of the first sub-segment 41-1 on the substrate may overlap with the orthographic projection of the first group of control signal lines 42a on the substrate. The orthographic projection of the data fan-out lines in the first group of data fan-out lines 41a on the substrate may be a straight-line trace. The minimum line width of the first sub-segment 41-1 may be less than the line widths of the third sub-segment 41-3 and the fourth sub-segment 41-4. The line widths of the third sub-segment 41-3 and the fourth sub-segment 41-4 may be substantially the same.

[0178] In some examples, as Figure 17A and Figure 17BAs shown, each data fan-out line in the second group of data fan-out lines 41b may include a fifth sub-segment 41-5, a second sub-segment 41-2, and a sixth sub-segment 41-6 connected in sequence. The orthographic projection of the second sub-segment 41-2 on the substrate and the orthographic projection of the second group of control signal lines 42b on the substrate may overlap. The orthographic projection of the data fan-out lines in the second group of data fan-out lines 41b on the substrate may be a straight-line trace. The line widths of the second sub-segment 41-2, the fifth sub-segment 41-5, and the sixth sub-segment 41-6 may be substantially the same. The line width of the second sub-segment 41-2 may be greater than the line width of the first sub-segment 41-1.

[0179] In this example, by reducing the line width of the first sub-segment of the first group of data fan-out lines, the overlapping area between the first group of data fan-out lines and the first group of control signal lines can be reduced, so that the first overlapping area corresponding to the data fan-out lines in the first group of data fan-out lines and the second overlapping area corresponding to the data fan-out lines in the second group of data fan-out lines can be substantially the same, reducing the parasitic capacitance between the first group of data fan-out lines and the overlapping trace, making the parasitic capacitances between the two groups of data fan-out lines and the overlapping trace substantially the same, thereby improving display defects such as low-gray-scale dark stripes caused by uneven overlapping of data fan-out lines and control signal lines.

[0180] In some other examples, by reducing the line width of the first control segment of the first group of control signal lines, the overlapping area between the first group of data fan-out lines and the first group of control signal lines can be reduced, so that the first overlapping area corresponding to the data fan-out lines in the first group of data fan-out lines and the second overlapping area corresponding to the data fan-out lines in the second group of data fan-out lines can be substantially the same, thereby reducing the parasitic capacitance between the first group of data fan-out lines and the overlapping control signal lines, making the parasitic capacitances between the two groups of data fan-out lines and the overlapping control signal lines substantially the same, and further improving display defects such as low-gray-scale dark stripes caused by uneven overlapping of data fan-out lines and control signal lines.

[0181] In some other examples, the first overlapping area corresponding to the data fan-out lines within the first group of data fan-out lines and the second overlapping area corresponding to the data fan-out lines within the second group of data fan-out lines can be made substantially the same by reducing the line width of the first sub-segment of the first group of data fan-out lines and increasing the line width of the second sub-segment of the second group of data fan-out lines. Or, in some other examples, the first overlapping area corresponding to the data fan-out lines within the first group of data fan-out lines and the second overlapping area corresponding to the data fan-out lines within the second group of data fan-out lines can be made substantially the same by reducing the line width of the first control segment of the first group of control signal lines and increasing the line width of the first control segment of the second group of control signal lines. Or, in some other examples, the first overlapping area corresponding to the data fan-out lines within the first group of data fan-out lines and the second overlapping area corresponding to the data fan-out lines within the second group of data fan-out lines can be made substantially the same by reducing the line width of the first sub-segment of the first group of data fan-out lines and increasing the line width of the second sub-segment of the second group of data fan-out lines, and reducing the line width of the first control segment of the first group of control signal lines and increasing the line width of the first control segment of the second group of control signal lines.

[0182] Figures 11 to 17B In the illustrated embodiment, by adjusting the overlapping area between the data fan-out lines and the overlapping control signal lines, the parasitic capacitance between the data fan-out lines and the overlapping control signal lines is adjusted, so that the parasitic capacitances between the first group of data fan-out lines and the second group of data fan-out lines and the overlapping control signal lines are substantially the same, thereby effectively improving display defects such as low gray-scale dark stripes caused by uneven overlapping of the data fan-out lines and the control signal lines.

[0183] In some other examples, the parasitic capacitance between the data fan-out lines and the overlapping control signal lines can be adjusted by adjusting the film layer where the first control segment of the control signal lines is located and adjusting the overlapping area between the data fan-out lines and the overlapping control signal lines, so that the parasitic capacitances between the first group of data fan-out lines and the second group of data fan-out lines and the overlapping control signal lines are substantially the same, thereby effectively improving display defects such as low gray-scale dark stripes caused by uneven overlapping of the data fan-out lines and the control signal lines. For example, the first control segments of multiple control signal lines can be located in the second source-drain metal layer or the third source-drain metal layer; the line width of the second sub-segment of the second group of data fan-out lines can be greater than the line width of the first sub-segment of the first group of data fan-out lines; or, the line width of the first control segment of the second group of control signal lines can be greater than the line width of the first control segment of the first group of control signal lines.

[0184] This embodiment also provides a display panel, including: a substrate, a plurality of sub-pixels, a plurality of data lines, a plurality of data fan-out lines, and a plurality of control signal lines. The substrate includes: a display area, and a first border area located on one side of the display area. The plurality of sub-pixels and the plurality of data lines are located in the display area. The plurality of data lines are connected to the plurality of sub-pixels and are configured to provide data signals to the plurality of sub-pixels. The plurality of data fan-out lines and the plurality of control signal lines are located in the first border area. The plurality of data fan-out lines are configured to provide data signals to the plurality of data lines. The plurality of data fan-out lines include: a first group of data fan-out lines and a second group of data fan-out lines. The plurality of control signal lines include: a first group of control signal lines and a second group of control signal lines. The number of control signal lines in the first group of control signal lines is greater than the number of control signal lines in the second group of control signal lines. Each data fan-out line in the first group of data fan-out lines has an overlap with the first group of control signal lines in the orthographic projection on the substrate. Each data fan-out line in the second group of data fan-out lines has an overlap with the second group of control signal lines in the orthographic projection on the substrate. Each data fan-out line in the first group of data fan-out lines has a first overlap area with the first group of control signal lines in the orthographic projection on the substrate. Each data fan-out line in the second group of data fan-out lines has a second overlap area with the second group of control signal lines in the orthographic projection on the substrate. The ratio range of the first overlap area to the second overlap area is from 0.9 to 1.1.

[0185] In this embodiment, by adjusting the overlap area between each data fan-out line and the plurality of control signal lines, the parasitic capacitance between the data fan-out line and the control signal line with which there is an overlap is adjusted, so that the parasitic capacitances between the two groups of data fan-out lines and the control signal lines are substantially the same, thereby optimizing display defects such as low gray-scale dark stripes caused by uneven overlap between the data fan-out lines and the control signal lines for transmitting AC signals.

[0186] In some exemplary embodiments, each data fan-out line in the first group of data fan-out lines includes: a first sub-segment that overlaps with the first group of control signal lines in the orthographic projection on the substrate. Each data fan-out line in the second group of data fan-out lines includes: a second sub-segment that overlaps with the second group of control signal lines in the orthographic projection on the substrate. The line width of the first sub-segment can be less than the line width of the second sub-segment. In this example, by increasing the line width of the second sub-segment of the second group of data fan-out lines, the overlap area between the second group of data fan-out lines and the second group of control signal lines can be increased, so that the second overlap area corresponding to the data fan-out lines in the second group of data fan-out lines can be substantially the same as the first overlap area corresponding to the data fan-out lines in the first group of data fan-out lines, increasing the parasitic capacitance between the second group of data fan-out lines and the overlapping traces, so that the parasitic capacitances between the two groups of data fan-out lines and the overlapping traces are substantially the same, thereby improving display defects such as low gray-scale dark stripes caused by uneven overlap between the data fan-out lines and the control signal lines.

[0187] In some exemplary embodiments, each data fan-out line in the first group of data fan-out lines includes: a first sub-segment that overlaps with the orthographic projection of the first group of control signal lines on the substrate; each data fan-out line in the second group of data fan-out lines includes: a second sub-segment that overlaps with the orthographic projection of the second group of control signal lines on the substrate; the orthographic projection of the first sub-segment on the substrate can be a straight-line trace, and the orthographic projection of the second sub-segment on the substrate can be a serpentine trace. In this example, by designing the serpentine trace for part of the line segments of the second group of data fan-out lines, the overlapping area between the second group of data fan-out lines and the second group of control signal lines can be increased, thereby reducing the parasitic capacitance difference between the two groups of data fan-out lines and the overlapping control signal lines.

[0188] In some exemplary embodiments, each control signal line in the first group of control signal lines includes: a first control segment that overlaps with the orthographic projection of the first group of data fan-out lines on the substrate; each control signal line in the second group of control signal lines includes: a first control segment that overlaps with the orthographic projection of the second group of data fan-out lines on the substrate. The line width of the first control segment of at least one control signal line in the second group of control signal lines can be greater than the line width of the first control segment of the control signal lines in the first group of control signal lines. In this example, by increasing the line width of the first control segment of the second group of control signal lines, the overlapping area between the second group of data fan-out lines and the second group of control signal lines can be increased, making the parasitic capacitance between the two groups of data fan-out lines and the overlapping control signal lines roughly the same, thereby improving display defects such as low-gray-scale dark stripes caused by uneven overlapping of data fan-out lines and control signal lines.

[0189] For the remaining descriptions of the display panel in this example, reference can be made to the descriptions of the foregoing embodiments, so they will not be elaborated here.

[0190] Figure 18 It is a schematic diagram of a display device according to at least one embodiment of the present disclosure. As Figure 18 shown, this embodiment provides a display device 91, including the display panel 910 of the foregoing embodiment. In some examples, the display panel 910 can be an OLED display panel, such as an OLED display panel integrated with a touch structure. The display device 91 can be: any product or component with a display function such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, or a navigator, or can be a product or component with touch and display functions.

[0191] In some examples, the display device 91 can be a wearable display device, for example, it can be worn on the human body in certain ways. For example, the display device 91 can be a smart watch, a smart bracelet, etc. However, this embodiment is not limited thereto.

[0192] The accompanying drawings in this disclosure only relate to the structures involved in this disclosure. For other structures, reference may be made to the general design. Without conflict, the embodiments in this disclosure, that is, the features in the embodiments, can be combined with each other to obtain new embodiments. Those of ordinary skill in the art should understand that the technical solutions of this disclosure can be modified or equivalently replaced without departing from the spirit and scope of the technical solutions of this disclosure, and should all be covered within the scope of the claims of this disclosure.

[0193] In the description of this specification, the description with reference to terms such as "one embodiment", "some embodiments", "example", or "some examples" means that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of this application. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples. In addition, without contradiction, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples.

[0194] Although the embodiments of this application have been shown and described above, it can be understood that the above embodiments are exemplary and should not be construed as limiting this application. Those of ordinary skill in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of this application.

Claims

1. A display panel, characterized in that, Comprising: A substrate, comprising: a display area, and a first border area located on one side of the display area; A plurality of sub-pixels and a plurality of data lines, located in the display area, the plurality of data lines being connected to the plurality of sub-pixels and configured to provide data signals to the plurality of sub-pixels; A plurality of data fan-out lines and a plurality of control signal lines, located in the first border area, the plurality of data fan-out lines being configured to provide data signals to the plurality of data lines; the plurality of data fan-out lines comprising: a first group of data fan-out lines and a second group of data fan-out lines, the plurality of control signal lines comprising: a first group of control signal lines and a second group of control signal lines; the number of control signal lines in the first group of control signal lines being greater than the number of control signal lines in the second group of control signal lines; Each data fan-out line in the first group of data fan-out lines has an overlap with the first group of control signal lines in the orthographic projection on the substrate, and each data fan-out line in the second group of data fan-out lines has an overlap with the second group of control signal lines in the orthographic projection on the substrate; At least one organic insulating layer is provided between the data fan-out line and the control signal line with which there is an overlap in the orthographic projection on the substrate.

2. The display panel according to claim 1, wherein The control signal line comprises: a first control line segment, the orthographic projection of the first control line segment on the substrate has an overlap with the orthographic projection of the first group of data fan-out lines or the second group of data fan-out lines on the substrate, the first control line segment is located on the side of the first group of data fan-out lines or the second group of data fan-out lines away from the substrate, and the first control line segment intersects with the extending direction of the plurality of data fan-out lines.

3. The display panel according to claim 2, wherein In a direction perpendicular to the display panel, the display panel at least comprises: a first gate metal layer, a second gate metal layer, a first source-drain metal layer and a second source-drain metal layer arranged along the direction away from the substrate; at least a first planarization layer is provided between the first source-drain metal layer and the second source-drain metal layer; The plurality of data fan-out lines are located in at least one of the first gate metal layer and the second gate metal layer, and the first control line segment of the plurality of control signal lines is located in the second source-drain metal layer.

4. The display panel according to claim 2, characterized in that, In a direction perpendicular to the display panel, the display panel at least comprises: a first gate metal layer, a second gate metal layer, a first source-drain metal layer, a second source-drain metal layer and a third source-drain metal layer arranged along the direction away from the substrate; at least a first planarization layer is provided between the first source-drain metal layer and the second source-drain metal layer, and at least a second planarization layer is provided between the second source-drain metal layer and the third source-drain metal layer; The plurality of data fan-out lines are located in at least one of the first gate metal layer and the second gate metal layer, and the first control line segment of the plurality of control signal lines is located in the third source-drain metal layer.

5. The display panel according to claim 3 or 4, characterized in that, The plurality of data fan-out lines comprise: a plurality of first data fan-out lines located in the first gate metal layer and a plurality of second data fan-out lines located in the second gate metal layer; The multiple first data fan-out lines and the multiple second data fan-out lines are arranged at intervals one by one, and the orthographic projections of the multiple first data fan-out lines and the multiple second data fan-out lines on the substrate do not overlap.

6. The display panel according to claim 2, wherein The control signal line further includes: a second control line segment and a third control line segment. The second control line segment is connected to one end of the first control line segment, and the third control line segment is connected to the other end of the first control line segment. The orthographic projections of the second control line segment and the third control line segment on the substrate do not overlap with the orthographic projections of the multiple data fan-out lines on the substrate; the second control line segment and the third control line segment are of the same layer structure and are located on the side of the first control line segment close to the substrate.

7. The display panel according to claim 1, characterized in that, Each data fan-out line in the first group of data fan-out lines has a first overlapping area with the orthographic projection of the first group of control signal lines on the substrate, and each data fan-out line in the second group of data fan-out lines has a second overlapping area with the orthographic projection of the second group of control signal lines on the substrate. The ratio range of the first overlapping area to the second overlapping area is 0.9 to 1.

1.

8. The display panel according to claim 7, characterized in that Each data fan-out line in the first group of data fan-out lines includes: a first sub-segment that overlaps with the orthographic projection of the first group of control signal lines on the substrate; Each data fan-out line in the second group of data fan-out lines includes: a second sub-segment that overlaps with the orthographic projection of the second group of control signal lines on the substrate; The line width of the first sub-segment is smaller than the line width of the second sub-segment.

9. The display panel according to claim 8, wherein, The ratio of the line width of the second sub-segment to the line width of the first sub-segment is greater than 1 and less than 2.

10. The display panel according to claim 8, characterized in that, Each data fan-out line in the first group of data fan-out lines further includes: a third sub-segment connected to one end of the first sub-segment and a fourth sub-segment connected to the other end of the first sub-segment; the orthographic projections of the third sub-segment and the fourth sub-segment on the substrate do not overlap with the orthographic projection of the first group of control signal lines on the substrate; the first sub-segment, the third sub-segment, and the fourth sub-segment of each data fan-out line in the first group of data fan-out lines are an integrally connected structure; Each data fan-out line in the second group of data fan-out lines further includes: a fifth sub-segment connected to one end of the second sub-segment and a sixth sub-segment connected to the other end of the second sub-segment; the orthographic projections of the fifth sub-segment and the sixth sub-segment on the substrate do not overlap with the orthographic projection of the second group of control signal lines on the substrate; The second sub-segment, the fifth sub-segment, and the sixth sub-segment of each data fan-out line in the second group of data fan-out lines are an integrally connected structure; The line widths of the first sub-segment, the third sub-segment, the fourth sub-segment, the fifth sub-segment, and the sixth sub-segment are the same.

11. The display panel according to claim 7, characterized in that, Each data fan-out line in the first group of data fan-out lines includes: a first sub-segment that overlaps with the orthographic projection of the first group of control signal lines on the substrate; Each data fan-out line in the second group of data fan-out lines includes: a second sub-segment that overlaps with the orthographic projection of the second group of control signal lines on the substrate; The positive projection of the first sub-segment on the substrate is a straight trace, and the positive projection of the second sub-segment on the substrate is a serpentine trace.

12. The display panel according to claim 11, wherein Each data fan-out line in the second group of data fan-out lines further includes: a fifth sub-segment connected to one end of the second sub-segment, and a sixth sub-segment connected to the other end of the second sub-segment; the positive projections of the fifth sub-segment and the sixth sub-segment on the substrate do not overlap with the positive projection of the second group of control signal lines on the substrate; The second sub-segment, the fifth sub-segment, and the sixth sub-segment of each data fan-out line in the second group of data fan-out lines are an integrally connected structure; The positive projection of the fifth sub-segment or the sixth sub-segment of at least one data fan-out line in the second group of data fan-out lines on the substrate is a serpentine trace.

13. The display panel according to claim 7, wherein, Each control signal line in the first group of control signal lines includes: a first control segment that overlaps with the positive projection of the first group of data fan-out lines on the substrate; Each control signal line in the second group of control signal lines includes: a first control segment that overlaps with the positive projection of the second group of data fan-out lines on the substrate; The line width of the first control segment of at least one control signal line in the second group of control signal lines is greater than the line width of the first control segment of the control signal lines in the first group of control signal lines.

14. The display panel according to claim 1, wherein The substrate further includes: a second border region and a third border region located on both sides of the display region along a first direction, and both the second border region and the third border region communicate with the first border region; The display panel further includes: a first group of gate driving circuits located in the second border region and a second group of gate driving circuits located in the third border region, and the number of gate driving circuits included in the first group of gate driving circuits is greater than the number of gate driving circuits included in the second group of gate driving circuits; The first group of control signal lines includes: a plurality of first driving control lines configured to provide driving control signals to the first group of gate driving circuits; The second group of control signal lines includes: a plurality of second driving control lines configured to provide driving control signals to the second group of gate driving circuits.

15. The display panel according to claim 14, wherein At least one of the plurality of sub-pixels includes: a pixel circuit; The first group of gate driving circuits includes: a light-emitting driving circuit, a first reset driving circuit, and a second reset driving circuit; the light-emitting driving circuit is configured to provide a light-emitting control signal to the pixel circuit, the first reset driving circuit is configured to provide a first reset control signal to the pixel circuit, and the second reset driving circuit is configured to provide a second reset control signal to the pixel circuit; The second group of gate driving circuits includes: a first scanning driving circuit and a second scanning driving circuit; the first scanning driving circuit is configured to provide a first scanning signal to the pixel circuit, and the second scanning driving circuit is configured to provide a second scanning signal to the pixel circuit.

16. A display device, characterized in that, A display panel including any one of claims 1 to 15.

17. A display panel, characterized in that, Including: A substrate, comprising: a display area, and a first border area located on one side of the display area; A plurality of sub-pixels and a plurality of data lines, located in the display area, the plurality of data lines being connected to the plurality of sub-pixels and configured to provide data signals to the plurality of sub-pixels; A plurality of data fan-out lines and a plurality of control signal lines, located in the first border area, the plurality of data fan-out lines being configured to provide data signals to the plurality of data lines; the plurality of data fan-out lines includes: a first group of data fan-out lines and a second group of data fan-out lines, the plurality of control signal lines includes: a first group of control signal lines and a second group of control signal lines; the number of control signal lines in the first group of control signal lines is greater than the number of control signal lines in the second group of control signal lines; Each data fan-out line in the first group of data fan-out lines has an overlap with the first group of control signal lines in the orthographic projection on the substrate, and each data fan-out line in the second group of data fan-out lines has an overlap with the second group of control signal lines in the orthographic projection on the substrate; Each data fan-out line in the first group of data fan-out lines has a first overlap area with the first group of control signal lines in the orthographic projection on the substrate, and each data fan-out line in the second group of data fan-out lines has a second overlap area with the second group of control signal lines in the orthographic projection on the substrate, and the ratio range of the first overlap area to the second overlap area is from 0.9 to 1.

1.

18. The display panel according to claim 17, wherein, Each data fan-out line in the first group of data fan-out lines includes: a first sub-segment that overlaps with the first group of control signal lines in the orthographic projection on the substrate; Each data fan-out line in the second group of data fan-out lines includes: a second sub-segment that overlaps with the second group of control signal lines in the orthographic projection on the substrate; The line width of the first sub-segment is less than the line width of the second sub-segment.

19. The display panel according to claim 17, wherein Each data fan-out line in the first group of data fan-out lines includes: a first sub-segment that overlaps with the first group of control signal lines in the orthographic projection on the substrate; Each data fan-out line in the second group of data fan-out lines includes: a second sub-segment that overlaps with the second group of control signal lines in the orthographic projection on the substrate; The orthographic projection of the first sub-segment on the substrate is a straight-line trace, and the orthographic projection of the second sub-segment on the substrate is a serpentine trace.

20. The display panel according to claim 17, wherein, Each control signal line in the first group of control signal lines includes: a first control segment that overlaps with the first group of data fan-out lines in the orthographic projection on the substrate; Each control signal line in the second group of control signal lines includes: a first control segment that overlaps with the second group of data fan-out lines in the orthographic projection on the substrate; The line width of the first control segment of at least one control signal line in the second group of control signal lines is greater than the line width of the first control segment of the control signal lines in the first group of control signal lines.

Images