Display device

Abstract

A display device may include a substrate including a display area and a non-display area surrounding the display area; a gate driving portion disposed on the substrate in the non-display area; the driving chip is arranged on the substrate in the non-display area; a first line disposed on the substrate, the first line electrically connected to the driving chip; and a second line disposed between the substrate and the first line. Accordingly, it is possible to prevent screen defects by minimizing cracks that may occur when the driver chip is attached to the display panel.

Description

[0001] Cross - reference to related applications

[0002] This application claims the priority of Korean Patent Application No. 10 - 2024 - 0013101, filed on January 29, 2024, the entire contents of which are incorporated herein by reference. Technical field

[0003] The present disclosure relates to a display device, and more particularly, provides a display device capable of preventing or at least reducing screen defects. Background art

[0004] With technological advancements, display devices for displaying images have become thinner and lighter. In addition to a display panel, a display device may further include a driving circuit for driving the display panel. To make the display device lightweight and thin, a driving circuit and driving chips for driving the display panel may be provided in the display panel. Summary of the invention

[0005] To place a driving chip configured to drive a display panel in the display panel, a technique for physically attaching the driving chip to the display panel is used.

[0006] However, when physically attaching the driving chip to the display panel, a physical force is applied to the display panel for the bonding between the driving chip and the display panel, such that defects, for example, cracks, may be generated in the display panel. This may cause an interruption in the signal supply to the display panel, resulting in defects such as screen abnormalities. Therefore, the inventors of the present disclosure have invented a novel structure for a display device, which is capable of preventing or at least reducing screen defects by minimizing defects such as cracks in the display panel.

[0007] Embodiments of the present disclosure provide a display device capable of preventing or at least reducing screen defects by minimizing cracks that may be generated when attaching a driving chip to a display panel.

[0008] A display device according to an embodiment of the present disclosure includes: a substrate including a display area and a non - display area surrounding the display area; a gate driving unit disposed on the substrate in the non - display area; a driving chip disposed on the substrate in the non - display area; a first line disposed on the substrate, the first line being electrically connected to the driving chip; and a second line disposed between the substrate and the first line.

[0009] A display device according to an embodiment of the present disclosure includes: a substrate including a display area and a non-display area surrounding the display area; a gate driving unit disposed on the substrate in the non-display area; a driving chip disposed on the substrate in the non-display area; a first line disposed on the substrate and electrically connected to the driving chip; and a plurality of virtual electrodes, at least some of the plurality of virtual electrodes being disposed on the same layer as the first line.

[0010] According to an embodiment of the present disclosure, since a double line is disposed between the substrate and the protective layer, cracks that may be generated when attaching the driving chip to the display panel can be minimized or at least reduced, thereby preventing or at least reducing screen defects.

[0011] According to an embodiment of the present disclosure, since a double line is disposed between the substrate and the protective layer, delamination of the layer disposed around the driving chip can be minimized or at least reduced, thereby preventing or at least reducing disconnection of the gate line.

[0012] According to an embodiment of the present disclosure, since virtual electrodes are disposed around the driving chip, delamination and cracks of the layer disposed around the driving chip can be minimized or at least reduced, and disconnection and corrosion of the gate line can be prevented or at least reduced.

[0013] According to an embodiment of the present disclosure, a display device capable of reducing power consumption by preventing or at least reducing screen defects and thus increasing the lifespan of the display device can be provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The accompanying drawings, which are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this specification, illustrate aspects of the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0015] Figure 1 Illustrates a display device according to an embodiment of the present disclosure.

[0016] Figure 2 Illustrates the circuit structure of a display device according to an embodiment of the present disclosure.

[0017] Figure 3 Is a circuit diagram of a sub-pixel of a display device according to an embodiment of the present disclosure.

[0018] Figure 4 Is according to an embodiment of the present disclosure, Figure 2 An enlarged view of region A.

[0019] Figure 5 Illustrates according to an embodiment of the present disclosure, along Figure 4An example taken along line II-II'.

[0020] Figure 6 Illustrates an example taken along line III-III' according to an embodiment of the present disclosure. Figure 4 An example taken along line III-III'.

[0021] Figure 7 Illustrates another example of the structure shown in Figure 4 according to an embodiment of the present disclosure.

[0022] Figure 8 Illustrates an example taken along line IV-IV' according to an embodiment of the present disclosure. Figure 7 An example taken along line IV-IV'.

[0023] Figure 9 Illustrates an example taken along line V-V' according to an embodiment of the present disclosure. Figure 7 An example taken along line V-V'. Detailed Embodiments

[0024] Aspects of the present disclosure will now be described in detail, and examples of the present disclosure may be shown in the accompanying drawings. In the following description, when a detailed description of a well-known method, function, structure, or configuration may unnecessarily obscure aspects of the present disclosure, the detailed description of such known functions or configurations may be omitted for the sake of brevity. In addition, for the sake of brevity, repeated descriptions may be omitted. The progress of the described process steps and / or operations is a non-limiting example.

[0025] Unless steps and / or operations must occur in a specific order, the order of steps and / or operations is not limited to the order set forth herein and may be changed to occur in an order different from the order described herein. In one or more examples, two consecutive operations may be performed substantially simultaneously, or the two operations may be performed in a reverse order or a different order depending on the functions or operations involved.

[0026] Unless otherwise indicated, the same reference numerals may always refer to the same elements, even if they are shown in different drawings. Unless otherwise indicated, the same reference numerals may be used throughout the specification and drawings to represent the same or substantially the same elements. In one or more aspects, unless otherwise indicated, the same elements (or elements with the same name) in different drawings may have the same or substantially the same functions and characteristics. The names of the various elements used in the following description are chosen for convenience only and may therefore be different from those used in actual products.

[0027] The advantages and features of the present disclosure and the methods for realizing them will be clarified by various aspects described with reference to the accompanying drawings. However, the present disclosure can be implemented in different forms and should not be construed as limited to the example aspects set forth herein. Rather, these example aspects are examples and are provided so that the present disclosure can be thorough and complete, to assist those skilled in the art in understanding the inventive concept without limiting the scope of the present disclosure.

[0028] The shapes, dimensions (such as size, length, width, height, thickness, position, radius, diameter, and area), ratios, rates, angles, numbers, the number of elements, etc., disclosed herein, including those shown in the accompanying drawings, are only examples, and thus the present disclosure is not limited to the illustrated details. However, it should be noted that the relative dimensions of the components shown in the drawings are part of the present disclosure.

[0029] When terms such as "comprising", "including", "having", "containing", "constituting", "made of", "formed by", "composed of", etc. are used with respect to one or more elements (such as layers, films, regions, components, sections, elements, parts, areas, portions, steps, operations, etc.), one or more other elements can be added unless a term such as "only" is used. The terms used in the present disclosure are only for describing example aspects and are not intended to limit the scope of the present disclosure. Unless the context clearly indicates otherwise, terms in the singular form can include the plural form.

[0030] Unless otherwise specified, the word "exemplary" is used to mean serving as an example or illustration. Each embodiment is an example embodiment. Each aspect is an example aspect. In one or more implementations, "embodiment", "aspect", "example", etc. should not be construed as being preferred or advantageous over other implementations. Unless otherwise stated, an aspect, an example, an example aspect, etc. can refer to one or more aspects, one or more examples, one or more example aspects, etc. In addition, the term "may" includes all meanings of the term "can".

[0031] In one or more aspects, unless otherwise explicitly stated, an element, a feature, or the corresponding information (such as level, range, dimension, size, etc.) is construed to include an error or tolerance range, even in the case where no explicit description of such an error or tolerance range is provided. The error or tolerance range can be caused by various factors (such as process factors, internal or external influences, noise, etc.). When interpreting a numerical value, the value is construed to include the error range unless otherwise explicitly stated.

[0032] When describing positional relationships, for example, when using terms such as "above", "over", "on top of", "upper", "below", "beneath", "under", "near", "close to", "adjacent", "next to", "beside", "alongside", "on one side or on" to describe the positional relationship between two parts (such as layers, films, regions, components, parts, etc.), unless more restrictive terms such as "immediately", "directly", or "closely" are used, one or more other parts can be provided between these two parts. For example, when a structure is described as being "above", "over", "on top of", "upper", "below", "beneath", "under", "near", "close to", "adjacent", "next to", "beside", "alongside", "on one side or on" another structure, this description should be interpreted as including cases where the structures are in contact with each other and cases where one or more additional structures are provided or interposed between them. In addition, terms such as "front", "rear", "back", "left", "right", "top", "bottom", "downward", "upward", "upper part", "lower part", "above", "below", "column", "row", "vertical", "horizontal", etc. refer to an arbitrary reference system.

[0033] Spatial relative terms such as "below", "beneath", "lower", "above", "over", "upper" can be used to describe the correlation between various elements (such as layers, films, regions, components, parts, etc.) shown in the drawings. The spatial relative terms should be understood to include terms for different orientations of the elements in use or in operation, in addition to the orientation depicted in the drawings. For example, if the elements shown in the drawings are inverted, the element described as being "below" or "beneath" other elements will be oriented "above" the other elements. Thus, the term "below" as an example term can include all directions of "above" and "below". Similarly, the exemplary terms "above" or "over" can include both directions of "above" and "below".

[0034] When describing temporal relationships, for example, when the time sequence is described as "after", "subsequent to", "next", "before", "prior to", etc., discontinuous or non-sequential cases can be included, so one or more other events can occur between them unless more restrictive terms such as "exactly", "immediately", or "directly" are used.

[0035] Terms such as "below", "lower", "above", "upper" can be used herein to describe the relationship between the elements shown in the drawings. It will be understood that these terms are spatially relative and based on the orientation depicted in the drawings.

[0036] When describing a signal flow, for example, "a signal is transmitted from node A to node B", unless the terms "immediately" or "directly" are used, it may include the case where the signal is transmitted from node A to node B through one or more intermediate nodes.

[0037] It should be understood that although terms such as "first", "second", etc. may be used herein to describe various elements (e.g., layers, films, regions, components, sections, elements, parts, areas, portions, steps, operations, etc.), these elements should not be limited by these terms, e.g., limited to any specific order, priority, or quantity of the elements. These terms are only used to distinguish one element from another. For example, without departing from the scope of the present disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. In addition, without departing from the scope of the present disclosure, according to the convenience of those skilled in the art, the first element, the second element, etc. may be arbitrarily named. For clarity, the function or structure of these elements (e.g., the first element, the second element, etc.) is not limited by the ordinal number or name in front of the element. In addition, the first element may include one or more first elements. Similarly, the second element, etc. may include one or more second elements, etc.

[0038] When describing the elements of the present disclosure, terms such as "first", "second", "A", "B", "(a)", or "(b)", etc. may be used. These terms are intended to identify the corresponding elements from other elements, and these terms are not used to define the nature, basis, order, or quantity of the elements.

[0039] For an expression where an element (e.g., a layer, a film, a region, a component, a portion, etc.) is described as "connected", "bonded", "attached", "adhered", etc. to another element, unless otherwise specified, the element may not only be directly connected, bonded, attached, adhered, etc. to the other element, but also be indirectly connected, bonded, attached, adhered, etc. to the other element when one or more intermediate elements are provided or interposed between these elements.

[0040] For an expression where an element (e.g., a layer, a film, a region, a component, a portion, etc.) "contacts", "overlaps", etc. with another element, unless otherwise specified, the element may not only directly contact, overlap, etc. with the other element, but also indirectly contact, overlap, etc. with the other element when one or more intermediate elements are provided or interposed between these elements.

[0041] A phrase such as an element (e.g., a layer, film, region, component, part, etc.) "provided", "arranged", "connected", "coupled", etc. in, on, or to another element may be understood to mean, for example, that at least a portion of the element is provided, arranged, etc. in the other element, or that the entire element is provided, arranged, connected, coupled, etc. in the other element. A phrase such as an element (e.g., a layer, film, region, component, part, etc.) "contacting", "overlapping", etc. another element may be understood to mean that at least a portion of the element contacts, overlaps, etc. at least a portion of the other element, that the entire element contacts, overlaps, etc. at least a portion of the other element, or that at least a portion of the element contacts, overlaps, etc. the entire other element.

[0042] Terms such as "line" or "direction" should not be interpreted based solely on the geometric relationship in which the corresponding lines or directions are parallel or perpendicular to each other. These terms may refer to a broader range of lines or directions in which the components of the present disclosure can operate functionally. For example, terms such as "first direction", "second direction", etc., which are parallel or perpendicular to a direction such as the "x-axis", "y-axis", or "z-axis", should not be interpreted based solely on the geometric relationship in which the respective directions are parallel or perpendicular to each other, and may refer to directions having a broader directivity within the range in which the components of the present disclosure can operate functionally.

[0043] The term "at least one" should be understood to include any and all combinations of one or more of the associated listed items. For example, the phrases "at least one of the first item, the second item, or the third item", and "at least one of the first item, the second item, and the third item" may each represent (i) a combination of items provided by one or more of the first item, the second item, and the third item, and (ii) only one of the first item, the second item, and the third item.

[0044] The expression of the first element, the second element "and / or" the third element should be understood to cover one of the first element, the second element, or the third element; one of the first element, the second element, and the third element; and any and all combinations of the first element, the second element, and the third element. For example, A, B, and / or C covers only A; only B; only C; any one of A, B, and C (e.g., A, B, or C); some combinations of A, B, and C (e.g., A and B; A and C; or B and C); and all of A, B, and C. In addition, the expression "A / B" may be understood to mean A and / or B. For example, the expression "A / B" may refer to only A; only B; A or B; or A and B.

[0045] In one or more aspects, unless otherwise specified, for convenience, the terms "between" and "among" may be used interchangeably. For example, the expression "between a plurality of elements" may be understood as among a plurality of elements. In another example, the expression "among a plurality of elements" may be understood as between a plurality of elements. In one or more examples, the number of elements may be two. In one or more examples, the number of elements may be more than two. Further, when an element (e.g., a layer, film, region, component, part, etc.) is said to be "between" at least two elements, the element may be the only element between the at least two elements, or there may also be one or more intermediate elements.

[0046] In one or more aspects, unless otherwise specified, for convenience, the phrases "each other" and "one another" may be used interchangeably. For example, the expression "different from each other" may be understood as different from one another. In another example, the expression "different from one another" may be understood as different from each other. In one or more examples, the number of elements involved in the foregoing expressions may be two. In one or more examples, the number of elements involved in the foregoing expressions may be more than two.

[0047] In one or more aspects, unless otherwise specified, for convenience, the phrases "one or more of among" and "one or more of in" may be used interchangeably.

[0048] The term "or" means "inclusive or" rather than "exclusive or". For example, unless otherwise stated or apparent from the context, the expression "x uses a or b" refers to any of the naturally inclusive arrangements. For example, "a or b" may mean "a", "b", or "a and b". For example, "a, b, or c" may mean "a", "b", "c", "a and b", "b and c", "a and c", or "a, b, and c".

[0049] The features of the various aspects of the present disclosure may be combined or combined in part or in whole with each other, may be technically related to each other, and may be operated, linked, or driven together in various ways. The aspects of the present disclosure may be implemented or carried out independently of each other, or may be implemented or carried out together in a co-dependent or related relationship. In one or more aspects, the components of each device according to the various aspects of the present disclosure are operatively combined and configured.

[0050] Unless otherwise defined, the terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which the example aspects belong. It should be further understood that, unless explicitly defined otherwise herein, terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and should not be interpreted in an idealized or overly formal sense.

[0051] The terms used herein have been chosen to be common in the relevant technical field; however, depending on technological developments and / or changes, conventions, preferences of those skilled in the art, etc., there may be other terms. Therefore, the terms used herein should not be construed as limiting the technical concept, but should be understood as examples of terms used to describe the example aspects.

[0052] In addition, in specific cases, the applicant may arbitrarily choose terms, in which case their detailed meanings are described herein. Therefore, the terms used herein should be understood not only based on the term names, but also based on the meanings and contents of the terms.

[0053] The "X-axis direction", "Y-axis direction", and "Z-axis direction" should not be interpreted only by the geometric relationship of perpendicularity to each other, and may have a wider directivity within the range where the elements of the present disclosure can function functionally.

[0054] In the following description, various example aspects of the present disclosure are described in detail with reference to the accompanying drawings. Regarding the reference numerals of the elements in each of the accompanying drawings, the same elements may be shown in other drawings, and the same reference numerals may represent the same elements, unless otherwise stated. Even if the same or similar elements are shown in different drawings, they may be represented by the same reference numerals. In addition, for ease of description, the proportions, dimensions, sizes, and thicknesses of each element shown in the drawings may be different from the actual proportions, dimensions, sizes, and thicknesses. Therefore, the aspects of the present disclosure are not limited to the proportions, dimensions, sizes, and thicknesses shown in the drawings.

[0055] Hereinafter, various embodiments will be described in detail with reference to the accompanying drawings.

[0056] Figure 1 A display device according to an embodiment of the present disclosure is illustrated.

[0057] The display panel 110 may include signal lines, such as a plurality of data lines DL and a plurality of gate lines GL. The display panel 110 may include a plurality of sub-pixels SP connected to the plurality of data lines DL and gate lines GL.

[0058] The display panel 110 may include a display area AA for displaying an image and a non-display area NA for not displaying an image.

[0059] In the display area AA, signal lines such as a plurality of data lines DL and a plurality of gate lines GL can be provided, and a plurality of sub-pixels SP configured to display an image can be provided. In the non-display area NA, the signal lines provided in the display area AA can be provided to extend, the data driving unit 120 or the gate driving unit 130 can be mounted, or a pad unit connecting the data driving unit 120, the gate driving unit 130, or a printed circuit can be provided.

[0060] The timing controller 140 can supply a data control signal DCS to the data driving unit 120 to control the operation timing of the data driving unit 120. The timing controller 140 can supply a gate control signal GCS configured to control the operation timing of the gate driving unit 130 to the gate driving unit 130.

[0061] The timing controller 140 can start gate driving (scanning) according to the timing achieved in each frame, convert input image data (or image signals) input from the external host module 150 into image data according to the data signal form used in the data driving unit 120, supply the image data to the data driving unit 120, and control the data driving at an appropriate time according to the gate driving.

[0062] The timing controller 140 can receive various timing signals including a vertical synchronization signal VSYNC, a horizontal synchronization signal HSYNC, an input data enable signal DE, and a clock signal, as well as input image data (image signals) from the outside (e.g., a host system). However, the timing signals are not limited thereto.

[0063] To control the data driving unit 120 and the gate driving unit 130, the timing controller 140 can receive timing signals such as a vertical synchronization signal VSYNC, a horizontal synchronization signal HSYNC, an input data enable signal DE, and a clock signal CLK, generate various control signals DCS and GCS, and output the control signals to the data driving unit 120 and the gate driving unit 130.

[0064] For example, to control the gate driving unit 130, the timing controller 140 can output various gate control signals GCS including a gate start pulse GSP, a gate shift clock GSC, and a gate output enable signal GOE.

[0065] The gate start pulse GSP can control the operation start timing of one or more gate driver integrated circuits constituting each gate driving unit 130. The gate shift clock GSC is a clock signal commonly input to one or more gate driver integrated circuits and can control the shift timing of a scan signal (gate pulse). The gate output enable signal GOE can specify timing information regarding one or more gate driver integrated circuits.

[0066] To control the data driving unit 120, the timing controller 140 may output various data control signals DCS including, for example, a source start pulse SSP, a source sampling clock SSC, and a source output enable signal SOE, but is not limited thereto.

[0067] The source start pulse SSP may control the start timing of data sampling of one or more source driver integrated circuits constituting the data driving unit 120. The source sampling clock SSC may be a clock signal configured to control the sampling timing of data in each source driver integrated circuit. The source output enable signal SOE may control the output timing of the data driving unit 120.

[0068] The timing controller 140 may be implemented as a component separate from the data driving unit 120, or the timing controller 140 may be implemented as an integrated circuit together with the data driving unit 120, but embodiments of the present disclosure are not limited thereto.

[0069] The data driving unit 120 may receive image data from the timing controller 140 and supply data voltages to a plurality of data lines DL, thereby driving the plurality of data lines DL. The data driving unit 120 may be a source driving circuit, but is not limited thereto.

[0070] The data driving unit 120 may include one or more source driver integrated circuits (SDICs). Each source driver integrated circuit (SDIC) may include a shift register, a latch circuit, a digital-to-analog converter (AAC), and an output buffer. In some cases, each source driver integrated circuit (SDIC) may further include an analog-to-digital converter ADC, but is not limited thereto.

[0071] For example, each source driver integrated circuit (SDIC) may be connected to the display panel 110 by a tape automated bonding (TAB) type, or may be connected to a bonding pad of the display panel 110 by a chip-on-glass (COG) or chip-on-panel (COP) type, or may be implemented by a chip-on-film (COF) type and connected to the display panel 110.

[0072] Figure 1 It is shown that the data driving unit 120 is disposed outside the display panel 110, but is not limited thereto. For example, the data driving unit 120 may be disposed inside the display panel 110.

[0073] Under the control of the timing controller 140, the gate driving unit 130 may output a gate signal of a conductive level voltage or a gate signal of a cut-off level voltage. The gate driving unit 130 may drive a plurality of gate lines GL by sequentially supplying gate signals of a conductive level voltage to the plurality of gate lines GL.

[0074] The gate driving unit 130 may be connected to the display panel 110 by the TAB method, or connected to the bonding pads of the display panel 110 by the COG or COP method, or may be connected to the display panel 110 according to the COF method. Alternatively, the gate driving unit 130 may be formed as an in-panel gate (GIP) type in the non-display area NA of the display panel 110. According to an embodiment of the present disclosure, an example in which the gate driving unit 130 is connected to the bonding pads of the display panel 110 in the chip-on-panel (COP) type is described, but the embodiments of the present disclosure are not limited thereto.

[0075] Figure 1 It is shown that the gate driving unit 130 is provided outside the display panel 110, but it is not limited thereto. For example, the gate driving unit 130 may be provided inside the display panel 110.

[0076] When a specific gate line GL is turned on through the gate driving unit 130, the data driving unit 120 may convert the image data received from the timing controller 140 into an analog data voltage and supply it to a plurality of data lines DL.

[0077] The data driving unit 120 may be connected to one side (e.g., the upper side or the lower side, or a part, or the upper part or the lower part) of the display panel 110. According to the driving scheme or the panel design scheme, the data driving unit 120 may be connected to both sides (e.g., the upper side and the lower side, or two parts, or the upper part and the lower part) of the self-emitting display panel 110, or connected to two or more sides (or parts) among the four sides (or four parts) of the self-emitting display panel 110.

[0078] The gate driving unit 130 may be connected to one side (e.g., the left side or the right side, or a part, or the left part or the right part) of the display panel 110. According to the driving scheme or the panel design scheme, the gate driving unit 130 may be connected to both sides (e.g., the left side and the right side, or two parts, or the upper part and the lower part) of the display panel 110, or connected to two or more sides (or parts) among the four sides (or four parts) of the display panel 110.

[0079] The timing controller 140 may be a timing controller used in display technology, or a control device that can execute other control functions as well as the functions of the timing controller, but it is not limited thereto.

[0080] The timing controller 140 may be implemented as various circuits or electronic components, such as an integrated circuit (IC), a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), or a processor, but it is not limited thereto.

[0081] Figure 2 The circuit structure of a display device according to an embodiment of the present disclosure is illustrated.

[0082] Reference Figure 2 , a plurality of sub-pixels SP can be set in the display area AA.

[0083] A plurality of gate driving units 130a1 to 130an and a driving chip 200 can be set in the non-display area NA of the display panel 110.

[0084] As Figure 2 As shown in, the plurality of gate driving units 130a1 to 130an can be set in the non-display area NA on both sides (or two parts) of the display area AA, or can be set only in a part of the two non-display areas NA, but is not limited thereto.

[0085] Each of the plurality of gate driving units 130a1 to 130an can be connected to a gate line GL in the display area AA, or one gate driving unit can be connected to all the gate lines GL in the display area AA, but the present disclosure is not limited thereto.

[0086] Hereinafter, for the sake of convenience of description, an example in which the plurality of gate driving units 130a1 to 130an are set in the non-display area NA on opposite sides (or parts) of the display area AA and each gate driving unit is connected to a gate line in the display area AA is described, but the embodiments of the present disclosure are not limited thereto.

[0087] The plurality of gate driving units 130a1 to 130an can be respectively connected to the gate lines GL provided in the display area AA.

[0088] The plurality of gate driving units 130a1 to 130an can include a plurality of first gate driving units 130a1 to 130a(n - 1) connected to the gate lines GL in the display area AA on one side (or a part) adjacent to the display area AA, and a plurality of second gate driving units 130a2 to 130an connected to the gate lines GL in the display area AA on the other side (or another part) adjacent to the display area AA.

[0089] The plurality of second gate driving units 130a2 to 130an can be gate driving units that output gate signals, but are not limited thereto, and can be light-emitting driving units that output light-emitting control signals. When the plurality of second gate driving units 130a2 to 130an are light-emitting driving units, the plurality of second gate driving units 130a2 to 130an can be connected to signal lines configured to transmit light-emitting control signals.

[0090] Figure 2Illustrated is a structure in which a plurality of first gate driving units 130a1 to 130a(n - 1) and a plurality of second gate driving units 130a2 to 130an are connected to different gate lines GL. However, embodiments of the present disclosure are not limited thereto, and the plurality of first gate driving units 130a1 to 130a(n - 1) and the plurality of second gate driving units 130a2 to 130an may be connected to the same gate line GL. In this case, the total number of gate driving units may be greater than the total number of gate driving units in the case where the plurality of first gate driving units 130a1 to 130a(n - 1) and the plurality of second gate driving units 130a2 to 130a are connected to different gate lines GL.

[0091] A plurality of gate lines 210a1 to 210a may be respectively connected to a plurality of gate driving units 130a1 to 130an.

[0092] The plurality of gate lines 210a1 to 210an may be lines for transmitting signals configured to control the plurality of gate driving units 130a1 to 130an.

[0093] For example, the first gate line 210a1 and the third gate line 210a3 may be lines for respectively transmitting a gate clock signal to the first gate driving unit 130a1 and the third gate driving unit 130a3.

[0094] The plurality of gate lines 210a1 to 210an may be connected to the driving chip 200 at a portion different from the portion connected to the plurality of gate driving units 130a1 to 130an.

[0095] The driving chip 200 may be disposed in the non - display area NA in the display panel 110. However, embodiments of the present disclosure are not limited thereto.

[0096] The driving chip 200 may be connected to the plurality of gate lines 210a1 to 210a, the plurality of connection lines 230, and the external line 220 in the non - display area NA.

[0097] The driving chip 200 may include a data driving unit and a timing controller. The timing controller may be disposed outside the display panel 110. However, embodiments of the present disclosure are not limited thereto. When the timing controller is disposed outside the display panel 110, the timing controller may be connected to the display panel 110 through (or via) the external line 220.

[0098] The driving chip 200 may transmit a data voltage to the data line DL through (or via) the plurality of connection lines 230. The plurality of connection lines 230 may be connected to the data line DL.

[0099] The driving chip 200 may receive power through the external line 220. For example, an integrated circuit configured to supply power may supply power to the driving chip 200 through (or via) the external line 220.

[0100] Figure 3 is a circuit diagram of a sub-pixel of a display device according to an embodiment of the present disclosure.

[0101] Referring to Figure 3 , each of a plurality of sub-pixels SP provided in a display panel 110 of a display device 100 according to an embodiment of the present disclosure may include a light-emitting element ED, a driving transistor DRT, a scanning transistor SCT, and a storage capacitor Cst. If the sub-pixel SP includes two transistors DRT and SCT, and one capacitor Cst, the sub-pixel SP may be referred to as having a 2T (transistor) 1C (capacitor) structure.

[0102] The light-emitting element ED may include a pixel electrode PE and a common electrode CE, and may further include a light-emitting layer EL between the pixel electrode PE and the common electrode CE. The pixel electrode PE may be an anode electrode or a cathode electrode, but is not limited thereto. The common electrode CE may be a cathode electrode or an anode electrode, but is not limited thereto. For example, the light-emitting element ED may be an organic light-emitting diode OLED, a light-emitting diode (LED), a mini-LED, a micro LED, or a quantum dot light-emitting element, but is not limited thereto.

[0103] The driving transistor DRT may be a transistor configured to drive the light-emitting element ED. The driving transistor DRT may include a first node N1, a second node N2, and a third node N3.

[0104] The first node N1 of the driving transistor DRT may be a gate node of the driving transistor DRT, and may be electrically connected to a source node or a drain node of the scanning transistor SCT. The second node N2 of the driving transistor DRT may be a source node or a drain node of the driving transistor DRT, and may be electrically connected to the pixel electrode PE of the light-emitting element ED. The third node N3 of the driving transistor DRT may be electrically connected to a driving voltage line DVL that supplies a driving voltage EVDD.

[0105] The scanning transistor SCT may be controlled by a gate signal (or a scanning signal) SCAN and may be connected between the first node N1 of the driving transistor DRT and a data line DL. For example, the scanning transistor SCT may be turned on or off according to the gate signal SCAN supplied from a scanning signal line SCL, controlling the connection between the data line DL and the first node N1 of the driving transistor DRT.

[0106] The scanning transistor SCT may be turned on by the gate signal SCAN having a conductive level voltage and transmit a data voltage Vdata supplied from the data line DL to the first node N1 of the driving transistor DRT.

[0107] Each of the driving transistor DRT and the scanning transistor SCT may be an n-type transistor or a p-type transistor.

[0108] The storage capacitor Cst may be electrically connected between a first node N1 and a second node N2 of the driving transistor DRT. The storage capacitor Cst may be charged with an electric charge corresponding to a voltage difference between its both ends, and may maintain the voltage difference between the both ends for a predetermined frame time. Accordingly, during the predetermined frame time, the corresponding sub-pixel SP may emit light.

[0109] The storage capacitor Cst is not a parasitic capacitor (e.g., Cgs or Cgd) of an internal capacitor existing between a gate node and a source node (or a drain node) of the driving transistor DRT, but may be an external capacitor intentionally designed outside the driving transistor DRT, but is not limited thereto.

[0110] The sub-pixel SP provided in the display panel 110 may include one or more transistors for providing a compensation function for reducing eigenvalue deviation between the driving transistors DRT or eigenvalue deviation between the light-emitting elements ED. In some cases, the sub-pixel may further include one or more capacitors. For example, the sub-pixel SP may have a circuit structure of 3T1C, 4T1C, 6T1C, 7T1C, 8T1C, or 8T2C, but is not limited to any one circuit structure.

[0111] Figure 4 is according to an embodiment of the present disclosure, Figure 2 an enlarged view of region A. Figure 5 illustrates an example taken along line II-II’ according to an embodiment of the present disclosure, Figure 4 of. Figure 6 illustrates an example taken along line III-III’ according to an embodiment of the present disclosure, Figure 4 of.

[0112] Referring to Figure 5 , the display panel 110 may include a substrate 500, a first buffer layer 510, a first insulating layer 520, a first line 530, a second insulating layer 540, a third insulating layer 550, and a second buffer layer 560.

[0113] The substrate 500 may support various components of the display device. The substrate 500 may be formed of a plastic material such as polyimide, but is not limited thereto.

[0114] An inorganic film may be further formed on the substrate 500 to prevent or at least reduce moisture penetration. The inorganic film may be formed of a single layer or multiple layers of silicon nitride (SiNx) or silicon oxide (SiOx), but is not limited thereto.

[0115] The first buffer layer 510 may be provided on the substrate 500.

[0116] The first buffer layer 510 can block alkali components and the like released from the substrate 500.

[0117] The first buffer layer 510 can be formed of a single layer or multiple layers of silicon nitride (SiNx) or silicon oxide (SiOx), but is not limited thereto. When the first buffer layer 510 is formed of multiple layers, silicon oxide (SiOx) and silicon nitride (SiNx) can be alternately formed, but is not limited thereto.

[0118] A first insulating layer 520 can be provided on the first buffer layer 510.

[0119] The first insulating layer 520 can insulate the gate electrode in the transistor from the semiconductor pattern. The first insulating layer 520 can be formed of a single layer or multiple layers of silicon nitride (SiNx) or silicon oxide (SiOx), but the embodiments of the present disclosure are not limited thereto.

[0120] A first line 530 can be provided on the first insulating layer 520.

[0121] The first line 530 can be formed of a single layer or multiple layers of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), nickel (Ni), neodymium (Nd), tungsten (W), and gold (Au) or an alloy thereof, but is not limited thereto.

[0122] The first line 530 can be a gate line electrically connected to the driving chip to transmit a signal configured to control the gate driving unit from the driving chip. For example, the first line 530 can be a line that transmits a gate clock signal to the gate driving unit.

[0123] The first line 530 can be the third gate line 210a3. Hereinafter, for convenience of description, the third gate line 210a3 is described as the first line 530.

[0124] A second insulating layer 540 can be provided on the first line 530. The second insulating layer 540 can be formed of a single layer or multiple layers of silicon nitride (SiNx) or silicon oxide (SiOx), but the embodiments of the present disclosure are not limited thereto.

[0125] A third insulating layer 550 can be provided on the second insulating layer 540.

[0126] The third insulating layer 550 can protect the thin film transistor and can relieve or planarize steps caused by various patterns.

[0127] The third insulating layer 550 may be formed of at least one or more materials such as benzocyclobutene (BCB), acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin, but is not limited thereto. The third insulating layer 550 may be provided as a single layer, but may be provided as two or more layers in consideration of the arrangement of the electrodes.

[0128] A second buffer layer 560 may be provided on the third insulating layer 550.

[0129] The second buffer layer 560 may be formed of a single layer or multiple layers of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto.

[0130] A driving chip may be provided on the second buffer layer 560.

[0131] Referring together Figure 2 , the driving chip 200 may be provided on multiple gate lines 210a1 to 210a in the non-display area NA of the display panel 110. For example, the driving chip 200 may be provided on the first gate line 210a1 and the third gate line 210a3.

[0132] The driving chip 200 may be attached to the display panel 110 through a plurality of bonding pads. In addition, the driving chip 200 may be electrically connected to multiple gate lines 210a1 to 210a through some of the plurality of bonding pads.

[0133] Multiple gate lines 210a1 to 210a1 may partially overlap with the driving chip 200 in the area where the driving chip 200 is connected to the plurality of bonding pads of the display panel 110.

[0134] The thickness of the display panel 110 in the area where the driving chip 200 overlaps with multiple gate lines 210a1 to 210a may be greater than the thickness of the display panel 110 in the area where the driving chip 200 does not overlap with multiple gate lines 210a1 to 210a.

[0135] For example, compared with the area where the driving chip 200 does not overlap with multiple gate lines 210a1 to 210a, the display panel 110 may further include at least one line layer in the area where the driving chip 200 overlaps with multiple gate lines 210a1 to 210a. Therefore, in the area where the driving chip 200 overlaps with multiple gate lines 210a1 to 210a, the thickness of the display panel 110 may be thicker.

[0136] Therefore, the external force applied when attaching the driving chip 200 to the display panel 110 may be more concentrated in the area where the driving chip 200 overlaps with multiple gate lines 210a1 to 210a. Therefore, cracks may be generated in the area where multiple gate lines 210a1 to 210a are provided.

[0137] The region where cracks are generated may be the region adjacent to the driving chip 200 in the region where a plurality of gate lines 210a1 to 210a are provided, and / or the region near the region where the first gate line 210a1 or the third gate line 210a3 is bent.

[0138] When the driving chip 200 is attached to the second buffer layer 560, an external force is applied from the top (or upper part) to the bottom (or lower part) of the second buffer layer 560, so cracks can be generated from the upper part of the display panel 110.

[0139] The cracks generated from the upper part of the display panel 110 can pass through the second buffer layer 560, the third insulating layer 550, and the second insulating layer 540, and can reach the first line 530.

[0140] When the cracks reach the first line 530 and the first line 530 is damaged, signals such as gate clock signals transmitted through the first line 530 can be interrupted.

[0141] When the signals transmitted through the first line 530 are interrupted, the gate driving unit and the gate lines may not operate properly, and the sub-pixels SP provided in the display panel 110 may not operate normally, so defects can be generated in the display screen.

[0142] Referring to Figure 4 and Figure 5 , a second line 700 can be further provided on the first buffer layer 510.

[0143] The second line 700 can be formed of a single layer or multiple layers of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), nickel (Ni), neodymium (Nd), tungsten (W), and gold (Au), or their alloys, but is not limited thereto.

[0144] The second line 700 can be provided between the first buffer layer 510 and the first insulating layer 520.

[0145] The second line 700 can be provided lower than the first line 530.

[0146] Since the driving chip is attached to the second buffer layer 560, the vertical distance from the driving chip to the second line 700 can be greater than the vertical distance from the driving chip to the first line 530.

[0147] The second line 700 can be electrically connected to the first line 530. This will be described in detail below.

[0148] Since the second line 700 is electrically connected to the first line 530, the second line 700 can be an electrode that receives a signal configured to control the gate driving unit from the driving chip and transmits the signal to the gate driving unit.

[0149] The second line 700 can transmit the same signal as the first line 530.

[0150] For example, when the first line 530 transmits a gate clock signal, the second line 700 can transmit the gate clock signal in the same manner.

[0151] The second line 700 can be disposed along the path where the first line 530 is disposed.

[0152] The second line 700 can at least partially overlap with the first line 530.

[0153] The width of the second line 700 on the plane can be the same as the width of the first line 530, but is not limited thereto, and can be greater than the width of the first line 530 or less than the width of the first line 530.

[0154] Although Figure 4 and Figure 5 illustrate a structure in which the second line 700 is only disposed below the first line 530, the second line 700 can be disposed below all of the plurality of gate lines 210a1 to 210a, and can be disposed along each of the paths where the plurality of gate lines 210a1 to 210a are disposed.

[0155] The first line electrode 710 can be disposed on the second insulating layer 540.

[0156] The first line electrode 710 can be formed of three layers of titanium (Ti), aluminum (Al), and titanium (Ti), but is not limited thereto.

[0157] The first line electrode 710 can be disposed between the second insulating layer 540 and the third insulating layer 550.

[0158] The first line electrode 710 can be disposed higher than the first line 530.

[0159] Since the driving chip is attached to the second buffer layer 560, the vertical distance from the driving chip to the first line electrode 710 can be less than the vertical distance from the driving chip to the first line 530. As used herein, the vertical distance can refer to the distance in a direction perpendicular or substantially perpendicular to the substrate 500 or its plane.

[0160] The first line electrode 710 can be electrically connected to the first line 530 and the second line 700. This will be described in detail below.

[0161] The first line electrode 710 can be disposed along the path where the first line 530 is disposed.

[0162] The first line electrode 710 can at least partially overlap with the first line 530.

[0163] The width of the first line electrode 710 on the plane may be the same as the width of the first line 530, but is not limited thereto. For example, the width of the first line 530 may be greater than or less than the width of the first line 530.

[0164] Although Figure 4 and Figure 5 a structure in which the first line electrode 710 is only provided on the first line 530 is shown, the first line electrode 710 may be provided on all of the plurality of gate lines 210a1 to 210a along each of the paths in which the plurality of gate lines 210a1 to 210a are provided.

[0165] Referring to Figure 4 and Figure 6 , at least one contact hole 600 may be formed in the path in which the first line 530 is provided.

[0166] The contact hole 600 may pass through the second insulating layer 540, the first line 530, and a part of the first insulating layer 520.

[0167] The first line electrode 710 may be provided to cover the bottom surface and the side surface of the contact hole 600. For example, the first line electrode 710 may be provided to cover both the bottom surface and the side surface of the contact hole 600.

[0168] The first line electrode 710 provided on the bottom surface of the contact hole 600 may contact the second line 700. The first line electrode 710 may be electrically connected to the second line 700 through or via the contact hole 600.

[0169] The first line electrode 710 provided on the side surface of the contact hole 600 may contact the first line 530. The first line electrode 710 may be electrically connected to the first line 530 through or via the contact hole 600.

[0170] Since the first line electrode 710 is electrically connected to each of the first line 530 and the second line 700 through the contact hole 600, the first line 530 may be electrically connected to the second line 700. Therefore, the first line 530 and the second line 700 may transmit the same signal. The present disclosure is not limited thereto. For example, the first line electrode 710 may be connected to the first line 530 through one contact hole, and the second line 700 may be connected to the first line 530 through another contact hole. That is, the first line electrode 710 and the second line 700 may be electrically connected to each other through the first line 530. For example, the first line 530 and the second line 700 may be connected to each other through the first line electrode 710 at the portions connected to the first line and the second line, and the portions of the first line electrode 710 connected to the first line 530 and the second line 700 may be a part of the first line electrode provided at or on the contact hole 600. Here, this part of the first line electrode 710 may be a part provided at the bottom surface and / or the side surface of the contact hole 600.

[0171] The display device according to an embodiment of the present disclosure may include a first wire electrode 710 provided along a path along which the first wire 530 is provided. Since the first wire electrode 710 is provided higher than the first wire 530, cracks that may be generated in an upper portion of the display panel when a driving chip is attached to the display panel 110 can be prevented from reaching the first wire 530.

[0172] In addition, the display device according to the present disclosure may include a second line 700 provided along the path provided by the first line 530. Since the second line 700 is provided lower than the first line 530 and is electrically connected to the first line 530, even when the first line 530 is partially damaged due to a crack when the driver chip is attached to the display panel, the gate control signal can still be transmitted through the second line 700. Thus, defects of the display screen can be prevented or at least reduced.

[0173] According to an embodiment of the present disclosure, since a double line is configured between the substrate and the protective layer, it is possible to prevent screen defects by minimizing or at least reducing cracks that may be generated when attaching the driving chip to the display panel 110 .

[0174] According to the embodiment of the present disclosure, since a double line is disposed between a substrate and a protective layer, disconnection of a gate line can be prevented by minimizing delamination of layers disposed around a driving chip.

[0175] Figure 7 Illustrated is an embodiment according to the present disclosure, Figure 4 Another example of the structure shown in . Figure 8 According to an embodiment of the present disclosure, Figure 7 An example of interception of line IV-IV'. Figure 9 According to an embodiment of the present disclosure, Figure 7 An example of an interception of line V-V'.

[0176] In describing these embodiments, descriptions of elements that are substantially the same as or correspond to elements of the previous embodiments will be omitted.

[0177] Reference Figure 7 and Figure 8 A first buffer layer 510 may be provided on the substrate 500. A first insulating layer 520 may be provided on the first buffer layer 510. A second insulating layer 540 may be provided on the first insulating layer 520. A second buffer layer 560 may be provided on the second insulating layer 540.

[0178] The driving chip 200 may be disposed in a partial region on the second buffer layer 560 .

[0179] The driving chip 200 can be disposed on or attached to the second buffer layer 560 through a plurality of bonding pads.

[0180] As Figure 7 and Figure 8 shown, in the region overlapping with the line IV-IV' in the region where the driving chip 200 is disposed, the driving chip 200 may not overlap with a plurality of gate lines 210a1 to 210a.

[0181] The region where the driving chip 200 does not overlap with a plurality of gate lines 210a1 to 210a, for example, the region overlapping with the line IV-IV' in the region where the driving chip 200 is disposed does not include a line layer. Therefore, the thickness of the display panel 110 in the region overlapping with the line IV-IV' in the region where the driving chip 200 is disposed may be smaller than that in the region where the driving chip 200 overlaps with a plurality of gate lines 210a1 to 210a.

[0182] Referring to Figure 7 and Figure 9 , the display device may include a plurality of virtual electrodes 900 and 1100.

[0183] The plurality of virtual electrodes 900 and 1100 may include a plurality of first virtual electrodes 900 and a plurality of second virtual electrodes 1100.

[0184] The plurality of first virtual electrodes 900 and the plurality of second virtual electrodes 1100 may be disposed in a region that at least partially overlaps with the region where the driving chip 200 is disposed.

[0185] The plurality of first virtual electrodes 900 and the plurality of second virtual electrodes 1100 may overlap with the driving chip 200 on a side surface different from the side surface where the driving chip 200 is connected to the plurality of gate lines 210a1 to 210a.

[0186] The horizontal width of the plurality of first virtual electrodes 900 and the plurality of second virtual electrodes 1100 may be W. The horizontal distance is perpendicular to the vertical distance described herein and may be parallel or substantially parallel to the substrate 500 or its plane.

[0187] The plurality of second virtual electrodes 1100 may be disposed between the first buffer layer 510 and the first insulating layer 520.

[0188] The plurality of second virtual electrodes 1100 may be formed of the same material as the second line, but are not limited thereto.

[0189] The plurality of first virtual electrodes 900 may be disposed between the first insulating layer 520 and the second insulating layer 540.

[0190] The vertical distance from the driving chip 200 to the plurality of second virtual electrodes 1100 may be greater than the vertical distance from the driving chip 200 to the plurality of first virtual electrodes 900.

[0191] The plurality of first virtual electrodes 900 may be formed of the same material as the first line, but are not limited thereto.

[0192] According to an embodiment of the present disclosure, since the plurality of virtual electrodes 900 and 1100 are arranged to at least partially overlap with the region where the driving chip 200 is disposed, the region overlapping with the line V-V' in the region where the driving chip 200 is disposed may include at least one line layer. Therefore, the thickness of the display panel 110 in the region where the driving chip 200 overlaps with the line V-V' may be greater than the thickness of the display panel 110 in the region where the driving chip 200 overlaps with the line IV-IV'.

[0193] For example, since the plurality of virtual electrodes 900 and 1100 are provided, the thickness of the display panel 110 may be increased in the region where the driving chip 200 in the region where the driving chip 200 is disposed does not overlap with the plurality of gate lines 210a1 to 210a.

[0194] Therefore, the concentration of external force applied to the region where the driving chip 200 overlaps with the plurality of gate lines 210a1 to 210a when the driving chip 200 is attached to the display panel 110 can be alleviated. Therefore, cracks can be prevented from occurring around the region where the driving chip 200 is disposed.

[0195] According to an embodiment of the present disclosure, since virtual electrodes are arranged around the driving chip, delamination and cracks of the layers disposed around the driving chip can be minimized, and disconnection and corrosion of the gate lines can be prevented.

[0196] The display device according to an embodiment of the present disclosure can be applied to mobile devices, video phones, smart watches, watch phones, wearable devices, foldable devices, rollable devices, bendable devices, flexible devices, curved devices, slidable devices, variable devices, electronic notebooks, e-books, portable multimedia players (PMPs), personal digital assistants (PDAs), MP3 players, mobile medical devices, desktop PCs, laptop PCs, netbook computers, workstations, navigation devices, vehicle navigation, vehicle displays, vehicle devices, theater devices, theater displays, televisions, wallpaper devices, sign devices, game devices, laptop computers, monitors, cameras, portable video cameras, and household appliances.

[0197] The display device according to various embodiments of the present disclosure can be described as follows.

[0198] A display device according to various embodiments of the present disclosure may include: a substrate including a display area and a non-display area surrounding the display area; a gate driving unit disposed at the non-display area on the substrate; a driving chip disposed at the non-display area on the substrate; a first line on the substrate, the first line being electrically connected to the driving chip; and a second line between the substrate and the first line.

[0199] A display device according to various embodiments of the present disclosure may further include a first line electrode on the first line, the first line electrode being connected to the first line and the second line.

[0200] According to various embodiments of the present disclosure, the first line and the second line may be electrically connected to each other through the first line electrode.

[0201] According to various embodiments of the present disclosure, a vertical distance from the driving chip to a layer where the first line electrode is disposed may be less than a vertical distance from the driving chip to a layer where the first line is disposed.

[0202] According to various embodiments of the present disclosure, at least a portion of the first line and the second line may overlap with an area where the driving chip is disposed. <00>

[0203] According to various embodiments of the present disclosure, a vertical distance from the driving chip to a layer where the second line is disposed may be greater than a vertical distance from the driving chip to a layer where the first line is disposed.

[0204] A display device according to various embodiments of the present disclosure may further include: a plurality of first virtual electrodes, at least some of the plurality of first virtual electrodes overlapping with an area where the driving chip is disposed in the non-display area; and a plurality of second virtual electrodes, each of the plurality of second virtual electrodes overlapping with each of the plurality of first virtual electrodes, the plurality of second virtual electrodes being between the substrate and the plurality of first virtual electrodes.

[0205] According to various embodiments of the present disclosure, the plurality of first virtual electrodes may be in the same layer as the first line, and the plurality of second virtual electrodes may be in the same layer as the second line.

[0206] According to various embodiments of the present disclosure, a vertical distance from the driving chip to the substrate in an area where the plurality of first virtual electrodes overlap with the driving chip may be equal to a vertical distance from the driving chip to the substrate in an area where the first line overlaps with the driving chip.

[0207] According to various embodiments of the present disclosure, the plurality of first virtual electrodes may include the same material as the first line. The plurality of second virtual electrodes may include the same material as the second line.

[0208] According to various embodiments of the present disclosure, the same signal may be applied to the first line and the second line such that the second line may transmit the same signal as the first line.

[0209] According to various embodiments of the present disclosure, the first line electrode and the second line may be electrically connected to each other through the first line.

[0210] According to various embodiments of the present disclosure, the first line may contact a portion of the first line electrode on a side surface of the contact hole, and the second line may contact a portion of the first line electrode on a bottom surface of the contact hole.

[0211] A display device according to an embodiment of the present disclosure may include: a substrate including a display area and a non-display area surrounding the display area; a gate driving unit at the non-display area on the substrate; a driving chip at the non-display area on the substrate; a first line on the substrate and electrically connected to the driving chip; and a plurality of virtual electrodes, at least some of the plurality of virtual electrodes being in the same layer as the first line.

[0212] According to various embodiments of the present disclosure, the plurality of virtual electrodes may overlap with an area where the driving chip is disposed.

[0213] According to various embodiments of the present disclosure, the plurality of virtual electrodes may include a first virtual electrode and a second virtual electrode. According to various embodiments of the present disclosure, the first virtual electrode may be in the same layer as the first line. According to various embodiments of the present disclosure, the second virtual electrode may overlap with the first virtual electrode and may be below the first virtual electrode.

[0214] According to various embodiments of the present disclosure, a vertical distance from the driving chip to the second virtual electrode may be greater than a vertical distance from the driving chip to the first virtual electrode.

[0215] According to various embodiments of the present disclosure, the display device may further include a second line between the substrate and the first line and disposed along the first line. According to various embodiments of the present disclosure, the second virtual electrode may be in the same layer as the second line.

[0216] According to various embodiments of the present disclosure, the first virtual electrode may include the same material as the first line. According to various embodiments of the present disclosure, the second virtual electrode may include the same material as the second line.

[0217] According to various embodiments of the present disclosure, a vertical distance from the driving chip to the substrate in a region where the first virtual electrode overlaps with the driving chip may be equal to a vertical distance from the driving chip to the substrate in a region where the first line overlaps with the driving chip.

[0218] It will be apparent to those skilled in the art that various modifications and variations can be made in the present disclosure without departing from the scope of the present disclosure. Accordingly, the present disclosure is intended to cover modifications and variations of the present disclosure provided that such modifications and variations come within the scope of the appended claims and their equivalents.

Claims

1. A display device, comprising: a substrate, the substrate including a display area and a non-display area surrounding the display area; a gate driving unit at the non-display area on the substrate; a driving chip at the non-display area on the substrate; a first line on the substrate, and the first line being electrically connected to the driving chip; and a second line between the substrate and the first line.

2. The display device according to claim 1, further comprising a first line electrode on the first line, the first line electrode being connected to the first line and the second line.

3. The display device according to claim 2, wherein the first line and the second line are electrically connected to each other through the first line electrode.

4. The display device according to claim 2 or claim 3, wherein a vertical distance from the driving chip to the layer where the first line electrode is disposed is less than a vertical distance from the driving chip to the layer where the first line is disposed.

5. The display device according to claim 1, wherein at least a part of the first line and the second line overlaps with the area where the driving chip is disposed.

6. The display device according to claim 1, wherein a vertical distance from the driving chip to the layer where the second line is disposed is greater than a vertical distance from the driving chip to the layer where the first line is disposed.

7. The display device according to claim 1, further comprising: a plurality of first virtual electrodes, at least some of the plurality of first virtual electrodes overlapping with the area where the driving chip is disposed in the non-display area; and a plurality of second virtual electrodes, each of the plurality of second virtual electrodes overlapping with each of the plurality of first virtual electrodes, the plurality of second virtual electrodes being between the substrate and the plurality of first virtual electrodes.

8. The display device according to claim 7, wherein the plurality of first virtual electrodes are in the same layer as the first line, and wherein the plurality of second virtual electrodes are in the same layer as the second line.

9. The display device according to claim 7 or claim 8, wherein a vertical distance from the driving chip to the substrate in the area where the plurality of first virtual electrodes overlap with the driving chip is equal to a vertical distance from the driving chip to the substrate in the area where the first line overlaps with the driving chip.

10. A display device, comprising: a substrate, the substrate including a display area and a non-display area surrounding the display area; a gate driving unit at the non-display area on the substrate; a driving chip at the non-display area on the substrate; a first line on the substrate, the first line being electrically connected to the driving chip; and a plurality of virtual electrodes, at least some of the plurality of virtual electrodes being in the same layer as the first line.

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