Display panel and display device

Abstract

The invention relates to a display panel and a display device. The display panel comprises a plurality of pixel driving circuits arranged along a first direction and a second direction, the first direction and the second direction are crossed, and each pixel driving circuit comprises a switch transistor and a first capacitor which are connected to a first node, and a node connecting line connected between the switch transistor and the first capacitor; the display panel further comprises a data signal line extending in the second direction and a first reset signal auxiliary line extending in the second direction. Wherein the first reset signal auxiliary line and the node connecting line are partially overlapped in the thickness direction of the display panel, and the minimum distance from the node connecting line to the data signal line in the first direction is larger than or equal to the minimum distance from the first reset signal auxiliary line to the data signal line in the first direction; according to the pixel driving circuit, signal crosstalk between the first node in the pixel driving circuit and the data signal line can be reduced, and the display effect of the display panel is improved.

Description

Technical Field

[0001] This application relates to the field of display technologies, and particularly to a display panel and a display device. Background Art

[0002] As a new type of self-luminous display panel, an Organic Light-Emitting Diode (OLED) display panel is ultra-clear, thin, flexible, and highly designable. At the same time, it uses organic semiconductors for light emission, has a wide range of material selection, and is easy to achieve full-color display within the visible light range. In particular, the top-emitting OLED display panel has advantages such as a large aperture ratio and is increasingly widely used in various fields.

[0003] Specifically, the OLED display panel includes a plurality of pixel driving circuits distributed in an array and a light-emitting period connected to the pixel driving circuits, and realizes the light emission of the light-emitting device through the control of the pixel driving circuits; among them, the OLED display panel further includes a data line connected to the pixel driving circuit to transmit a data signal to the pixel driving circuit.

[0004] However, due to the large capacitance formed between the data line and some nodes in the pixel driving circuit, a large signal crosstalk will be generated, affecting the display effect of the OLED display panel. Summary of the Invention

[0005] Embodiments of this application provide a display panel and a display device, which can reduce the signal crosstalk between the first node in the pixel driving circuit and the data signal line.

[0006] Embodiments of this application provide a display panel, the display panel includes a plurality of pixel driving circuits arranged along a first direction and a second direction, the first direction and the second direction intersect, and the pixel driving circuit includes a switching transistor connected to a first node, a first capacitor, and a node connection line connected between the switching transistor and the first capacitor;

[0007] The display panel further includes a data signal line extending along the second direction and a first reset signal auxiliary line extending along the second direction;

[0008] Wherein, the first reset signal auxiliary line partially overlaps with the node connection line in the thickness direction of the display panel, and the minimum distance from the node connection line to the data signal line along the first direction is greater than or equal to the minimum distance from the second line segment to the data signal line along the first direction.

[0009] In one embodiment of the present application, the first reset signal auxiliary line includes a first line segment and a second line segment connected to each other. The minimum distance from the first line segment to the data signal line along the first direction is greater than the minimum distance from the second line segment to the data signal line along the first direction.

[0010] In one embodiment of the present application, the display panel further includes:

[0011] A substrate;

[0012] A semiconductor layer disposed on one side of the substrate. The semiconductor layer includes a switching active portion of the switching transistor. The data signal line is located on one side of a plurality of pixel driving circuits arranged along the second direction and is connected to the switching active portion in the pixel driving circuit;

[0013] A first conductive layer disposed on the side of the semiconductor layer away from the substrate. The first conductive layer includes the node connection line;

[0014] A second conductive layer disposed on the side of the first conductive layer away from the semiconductor layer. The second conductive layer includes the data signal line and the first reset signal auxiliary line. The node connection line and the second line segment have an overlapping portion in the thickness direction of the display panel. The minimum distance from the overlapping portion to the data signal line along the first direction is greater than or equal to the minimum distance from the second line segment to the data signal line along the first direction.

[0015] In one embodiment of the present application, the display panel further includes:

[0016] A first gate layer disposed between the semiconductor layer and the first conductive layer. The first gate layer includes a first electrode plate of the first capacitor;

[0017] A second gate layer disposed between the first gate layer and the first conductive layer. The second gate layer includes a second electrode plate of the first capacitor. The first electrode plate and the second electrode plate are disposed opposite to each other;

[0018] Wherein, the node connection line is connected to the second electrode plate. The minimum distance from the second electrode plate to the data signal line along the first direction is greater than or equal to the minimum distance from the second line segment to the data signal line along the first direction.

[0019] In one embodiment of the present application, the first conductive layer further includes a first power supply signal line extending along the first direction. The first power supply signal line includes a plurality of first sub - portions arranged along the first direction. The first sub - portion extends along the second direction;

[0020] For the same pixel driving circuit, the positive projection of the first sub - part on the substrate is located between the positive projection of the node connection line on the substrate and the positive projection of the data signal line on the substrate, and the first sub - part and the node connection line overlap at least partially in the first direction.

[0021] In an embodiment of the present application, a plurality of the first sub - parts arranged in the first direction are correspondingly arranged with a plurality of pixel driving circuits arranged in the first direction, and a plurality of the data signal lines are correspondingly connected to the plurality of pixel driving circuits arranged in the first direction;

[0022] For the same pixel driving circuit, the minimum distance between the second electrode plate and the data signal line in the first direction is greater than or equal to the minimum distance between the first sub - part and the data signal line in the first direction.

[0023] In an embodiment of the present application, the pixel driving circuit further includes a second capacitor connected to the first node, and the node connection line is further connected between the switching transistor and the second capacitor;

[0024] For the same pixel driving circuit, the first power supply signal line is located on the side of the second capacitor away from the switching transistor, the first sub - part and the first capacitor overlap partially in the thickness direction of the display panel, and the first sub - part and the second capacitor overlap partially in the thickness direction of the display panel.

[0025] In an embodiment of the present application, the first power supply signal line further includes a second sub - part connected between two adjacent first sub - parts, the second sub - part is located on the side of the node connection line away from the switching transistor, the second sub - part and the first capacitor overlap partially in the thickness direction of the display panel, and the second sub - part and the second capacitor do not overlap in the thickness direction of the display panel.

[0026] In an embodiment of the present application, the first gate layer includes a third electrode plate of the second capacitor, the second gate layer includes a fourth electrode plate of the second capacitor, the third electrode plate and the fourth electrode plate are arranged oppositely, and the node connection line is connected to the third electrode plate;

[0027] The second gate layer further includes a plate connection line connected to the fourth electrode plate, at least part of the plate connection line extends in the second direction and is located between two second electrode plates in two adjacent pixel driving circuits arranged in the first direction, and the plate connection line and the data signal line do not overlap at least partially in the thickness direction of the display panel.

[0028] In an embodiment of the present application, for the same pixel driving circuit, the center of the plate connection line extending along the second direction is located on one side of the center of the data signal line, and the center of the first sub - part is located on the opposite side of the center of the data signal line.

[0029] In an embodiment of the present application, the pixel driving circuit further includes a switch reset transistor connected to the first node. The semiconductor layer includes a switch reset active part of the switch reset transistor. The switch reset active part is electrically connected to the first reset signal auxiliary line. The switch reset active part and the switch active part are arranged adjacent to each other along the first direction and are connected to the first node.

[0030] The first reset signal auxiliary line is located on one side of a plurality of pixel driving circuits arranged along the second direction and is electrically connected to the switch reset active part in the pixel driving circuit.

[0031] In an embodiment of the present application, the switch active part includes a first connection sub - part and a second connection sub - part arranged along the first direction, and a third connection sub - part extending along the first direction and connecting between the first connection sub - part and the second connection sub - part. Both the first connection sub - part and the second connection sub - part extend along the second direction.

[0032] The switch reset active part includes a fourth connection sub - part and a fifth connection sub - part arranged along the first direction, and a sixth connection sub - part extending along the first direction and connecting between the fourth connection sub - part and the fifth connection sub - part. Both the fourth connection sub - part and the fifth connection sub - part extend along the second direction.

[0033] Wherein, there is a first distance along the first direction between the first connection sub - part and the second connection sub - part, and a second distance along the first direction between the fourth connection sub - part and the fifth connection sub - part. The first distance is greater than or equal to the second distance.

[0034] In an embodiment of the present application, the display panel further includes a plurality of light - emitting parts arranged along the first direction and the second direction. The first conductive layer further includes a second power supply signal line extending along the second direction. A plurality of light - emitting parts arranged along the second direction are located on one side of the corresponding second power supply signal line.

[0035] Wherein, the second power signal line includes overlapping line segments, the light-emitting portion includes a bottom surface on a side close to the second power signal line, the overlapping line segments overlap with the bottom surface of the light-emitting portion in the thickness direction of the display panel, and the ratio of the area of the orthogonal projection of the overlapping line segments on the substrate to the area of the orthogonal projection of the bottom surface of the light-emitting portion on the substrate is greater than or equal to 0.5.

[0036] In an embodiment of the present application, the first line segment is parallel to the data signal line, the second line segment includes an intermediate sub-portion and a connecting sub-portion connecting the intermediate sub-portion and the first line segment, the intermediate sub-portion is parallel to the data signal line, and the extending direction of the connecting sub-portion intersects with the data signal line.

[0037] According to the above object of the present application, an embodiment of the present application further provides a display device, and the display device includes the display panel.

[0038] The present application provides a display panel and a display device. By making the minimum distance from the node connection line to the data signal line in the first direction greater than or equal to the minimum distance from the first reset signal auxiliary line to the data signal line in the first direction, the first reset signal auxiliary line can cover the edge of the node connection line close to the data signal line, so that the first reset signal auxiliary line can be used as a shielding structure to be spaced between the node connection line and the data signal line, reducing the signal crosstalk between the first node in the pixel driving circuit and the data signal line, and improving the display effect of the display panel.

[0039] Other features and advantages of the present application will be described in detail in the subsequent specific implementation section. Description of the Drawings

[0040] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for the description of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application, and those skilled in the art can obtain other drawings based on these drawings without creative efforts.

[0041] In order to more completely understand the present application and its beneficial effects, the following description will be made in conjunction with the drawings, where the same reference numerals represent the same parts in the following description.

[0042] Figure 1 It is a film stack diagram of a sub-pixel in the display panel provided by the embodiment of the present application;

[0043] Figure 2 It is a structural diagram of a pixel driving circuit of the display panel provided by the embodiment of the present application;

[0044] Figure 3 Schematic diagram of a planar structure of a display panel provided by an embodiment of the present application;

[0045] Figure 4 Schematic diagram of a cross-sectional structure of a display panel provided by an embodiment of the present application;

[0046] Figure 5 Provided by an embodiment of the present application Figure 1 Structural diagram of the semiconductor layer in

[0047] Figure 6 Provided by an embodiment of the present application Figure 1 Structural diagram of the first gate layer in

[0048] Figure 7 Provided by an embodiment of the present application Figure 1 Stacked diagram of the semiconductor layer and the first gate layer in

[0049] Figure 8 Provided by an embodiment of the present application Figure 1 Structural diagram of the second gate layer in

[0050] Figure 9 Provided by an embodiment of the present application Figure 1 Stacked diagram of the semiconductor, the first gate layer, and the second gate layer in

[0051] Figure 10 Provided by an embodiment of the present application Figure 1 Structural diagram of the first conductive layer in

[0052] Figure 11 Provided by an embodiment of the present application Figure 1 Stacked diagram of the semiconductor, the first gate layer, the second gate layer, and the first conductive layer in

[0053] Figure 12 Provided by an embodiment of the present application Figure 1 Structural diagram of the second conductive layer in

[0054] Figure 13 Provided by an embodiment of the present application Figure 1 Stacked diagram of the semiconductor, the first gate layer, the second gate layer, the first conductive layer, and the second conductive layer in

[0055] Figure 14 Provided by an embodiment of the present application Figure 1 Structural diagram of the anode layer in

[0056] Figure 15 Provided by an embodiment of the present application Figure 1 Stacked diagram of the semiconductor, the first gate layer, the second gate layer, the first conductive layer, the second conductive layer, and the anode layer in

[0057] Figure 16 For the embodiments of the present application Figure 4 Schematic plan view of the first pixel definition layer and the second pixel definition layer in

[0058] Explanation of reference numerals:

[0059] AA, display area; NA, non-display area; PX, sub-pixel; PD, pixel driving circuit; EL, light-emitting device;

[0060] 10, substrate; 11, gate driving circuit; 12, bonding terminal; 13, light-emitting layer; 100, light-emitting part; 1001, bottom surface; 20, semiconductor layer; 21, second reset signal auxiliary line; 211, first protruding part; 22, first connecting sub-part; 23, second connecting sub-part; 24, third connecting sub-part; 25, fourth connecting sub-part; 26, fifth connecting sub-part; 27, sixth connecting sub-part; 30, first gate layer; 40, second gate layer; 41, first jumper line; 42, plate connection line; 421, third line segment; 422, fourth line segment; 423, fifth line segment; 43, second protruding part; 50, first conductive layer; 51, second jumper line; 52, third jumper line; 53, node connection line; 54, fourth jumper line; 55, fifth jumper line; 56, sixth jumper line; 57, seventh jumper line; 58, eighth jumper line; 59, ninth jumper line; 510, tenth jumper line; 511, eleventh jumper line; 512, twelfth jumper line; 60, second conductive layer; 61, second power supply signal line; 611, overlapping line segment; 62, first reset signal auxiliary line; 621, first line segment; 622, second line segment; 6221, intermediate sub-part; 6222, connecting sub-part; 63, functional trace; 64, anode connection part; 70, anode layer; 71, anode; 81, first gate insulating layer; 82, second gate insulating layer; 83, interlayer dielectric layer; 84, first planarization layer; 85, second planarization layer; 86, pixel definition layer; 861, first pixel definition layer; 862, second pixel definition layer; 860, pixel opening;

[0061] T1, switching transistor; T2, driving transistor; T3, compensating transistor; T4, first reset transistor; T5, second reset transistor; T6, third reset transistor; T7, switching reset transistor; T8, first light-emitting control transistor; T9, second light-emitting control transistor; C1, first capacitor; C2, second capacitor; C3, third capacitor; C4, fourth capacitor; C5, fifth capacitor; C6, sixth capacitor; SCAN1, first control signal line; SCAN2, second control signal line; SCAN3, third control signal line; SCAN4, fourth control signal line; EM1, first light-emitting control signal line; EM2, second light-emitting control signal line; DATA, data signal line; DATA1, first data signal line; DATA2, second data signal line; DATA3, third data signal line; VI1, first reset signal line; VI2, second reset signal line; VI3, third reset signal line; VI4, fourth reset signal line; VDD, first power supply signal line; VDD1, first sub-section; VDD2, second sub-section; VSS, third power supply signal line; N1, first node; N2, second node; N3, third node; N4, fourth node; N5, fifth node;

[0062] C11, first electrode plate; C12, second electrode plate; C21, third electrode plate; C22, fourth electrode plate; C31, fifth electrode plate; C41, sixth electrode plate;

[0063] T1A, switching active part; T2A, driving active part; T3A, compensating active part; T4A, first reset active part; T5A, second reset active part; T6A, third reset active part; T7A, switching reset active part; T8A, first light-emitting control active part; T9A, second light-emitting control active part;

[0064] T1G, switching gate; T2G, driving gate; T3G, compensating gate; T4G, first reset gate; T5G, second reset gate; T6G, third reset gate; T7G, switching reset gate; T8G, first light-emitting control gate; T9G, second light-emitting control gate;

[0065] T1D, switching drain; T2D, driving drain; T3D, compensating drain; T4D, first reset drain; T5D, second reset drain; T6D, third reset drain; T7D, switching reset drain; T8D, first light-emitting control drain; T9D, second light-emitting control drain;

[0066] T1S, switching source; T2S, driving source; T3S, compensating source; T4S, first reset source; T5S, second reset source; T6S, third reset source; T7S, switching reset source; T8S, first light-emitting control source; T9S, second light-emitting control source. Detailed implementation manners

[0067] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative efforts belong to the protection scope of the present application.

[0068] Please refer to Figure 1 and Figure 2 , an embodiment of the present application provides a display panel, the display panel includes a plurality of pixel driving circuits PD arranged along a first direction X and a second direction Y, the first direction X and the second direction Y intersect, and the pixel driving circuit PD includes a switching transistor T1 and a first capacitor C1 connected to a first node N1, and a node connection line 53 connected between the switching transistor T1 and the first capacitor C1.

[0069] The display panel further includes a data signal line DATA extending along the second direction Y and a first reset signal auxiliary line 62 extending along the second direction Y.

[0070] Wherein, the first reset signal auxiliary line 62 and the node connection line 53 partially overlap in the thickness direction of the display panel, and the minimum distance L1 from the node connection line 53 to the data signal line DATA along the first direction X is greater than or equal to the minimum distance L2 from the first reset signal auxiliary line 53 to the data signal line DATA along the first direction X.

[0071] In the implementation and application process, by making the minimum distance L1 from the node connection line 53 to the data signal line DATA along the first direction X greater than or equal to the minimum distance L2 from the first reset signal auxiliary line 62 to the data signal line DATA along the first direction X, the first reset signal auxiliary line 62 can cover the edge of the node connection line 53 close to the data signal line DATA, so that the first reset signal auxiliary line 62 can be used as a shielding structure to be spaced between the node connection line 53 and the data signal line DATA, reducing the signal crosstalk between the first node N1 in the pixel driving circuit PD and the data signal line DATA, and improving the display effect of the display panel.

[0072] Specifically, please refer to Figure 2 and Figure 3, the display panel may include a display area AA and a non-display area NA adjacent to the display area AA. The non-display area NA may be disposed around the display area AA, and the non-display area NA may be a border area of the display panel.

[0073] In some embodiments, the display panel further includes a plurality of sub-pixels PX disposed in the display area AA and configured to implement the display function of the display panel, and a gate driving circuit 11 disposed in the non-display area NA. The gate driving circuit 11 is configured to input a control signal into the sub-pixels PX in the display area AA.

[0074] In some embodiments, a pixel driving circuit PD is provided in each sub-pixel PX, and the gate driving circuit 11 is configured to input a gate control signal into a transistor in the pixel driving circuit PD.

[0075] In some embodiments, a bonding terminal 12 is disposed on the lower side of the display area AA. The display panel further includes a data signal line DATA extending into the display area AA and connected to the pixel driving circuit PD. The bonding terminal 12 may be connected to an external circuit, and the bonding terminal 12 transmits a signal input by the external circuit to the data signal line DATA, thereby driving the display panel to display an image. For example, the bonding terminal 12 may be bonded to a chip or a chip-on-film to provide power and driving signals for the display panel.

[0076] In some embodiments, the gate driving circuit 11 is disposed in the non-display area NA, and the gate driving circuit 11 may be disposed on both sides of the display area AA. The gate driving circuit 11 may include a plurality of cascaded gate driving units, and the structure of the gate driving unit is not specifically limited in this application.

[0077] In some embodiments, a plurality of the pixel driving circuits PD may be arranged in an array in the display area AA. The pixel driving circuit PD may be a 7T1C, 7T2C, 8T1C, 8T2C, 8T3C, 8T4C, 9T2C, 9T6C or other pixel driving circuit PD. In the following embodiments, the 9T6C pixel driving circuit PD is taken as an example for illustration.

[0078] Please refer to Figure 2, the pixel driving circuit PD includes a switching transistor T1, a driving transistor T2, a compensating transistor T3, a first reset transistor T4, a second reset transistor T5, a third reset transistor T6, a switching reset transistor T7, a first light-emitting control transistor T8, a second light-emitting control transistor T9, a first capacitor C1, a second capacitor C2, a third capacitor C3, and a fourth capacitor C4. The display panel further includes a light-emitting device EL connected to the pixel driving circuit PD.

[0079] Further, the display panel further includes a plurality of signal lines, and the plurality of signal lines are used to connect to the pixel driving circuit PD and transmit signals to the pixel driving circuit PD; in some embodiments, the signal lines include a first control signal line SCAN1, a second control signal line SCAN2, a third control signal line SCAN3, a fourth control signal line SCAN4, a first light-emitting control signal line EM1, a second light-emitting control signal line EM2, a data signal line DATA, a first reset signal line VI1, a second reset signal line VI2, a third reset signal line VI3, a fourth reset signal line VI4, a second power supply signal line 61, a first power supply signal line VDD, and a third power supply signal line VSS.

[0080] Wherein, the drain of the switching transistor T1 is connected to the data signal line DATA to receive a data signal Data, the source of the switching transistor T1 is connected to a first node N1, and the gate of the switching transistor T1 is connected to the first control signal line SCAN1 to receive a first control signal Scan1.

[0081] The drain of the driving transistor T2 is connected to a fifth node N5, the source of the driving transistor T2 is connected to a third node N3, and the gate of the driving transistor T2 is connected to a second node N2.

[0082] The drain of the compensating transistor T3 is connected to the second node N2, the source of the compensating transistor T3 is connected to the third node N3, and the gate of the compensating transistor T3 is connected to the second control signal line SCAN2 to receive a second control signal Scan2.

[0083] The drain of the first reset transistor T4 is connected to the first reset signal line VI1 to receive a first reset signal Vi1, the source of the first reset transistor T4 is connected to the second node N2, and the gate of the first reset transistor T4 is connected to the third control signal line SCAN3 to receive a third control signal Scan3.

[0084] The drain of the second reset transistor T5 is connected to the second reset signal line VI2 to receive the second reset signal Vi2. The source of the second reset transistor T5 is connected to the fourth node N4. The gate of the second reset transistor T5 is connected to the fourth control signal line SCAN4 to receive the fourth control signal Scan4.

[0085] The drain of the third reset transistor T6 is connected to the third reset signal line VI3 to receive the third reset signal Vi3. The source of the third reset transistor T6 is connected to the fifth node N5. The gate of the third reset transistor T6 is connected to the fourth control signal line SCAN4 to receive the fourth control signal Scan4.

[0086] The drain of the switch reset transistor T7 is connected to the fourth reset signal line VI4 to receive the fourth reset signal Vi4. The source of the switch reset transistor T7 is connected to the first node N1. The gate of the switch reset transistor T7 is connected to the second control signal line SCAN2 to receive the second control signal Scan2.

[0087] The drain of the first light-emitting control transistor T8 is connected to the third node N3. The source of the first light-emitting control transistor T8 is connected to the fourth node N4. The gate of the first light-emitting control transistor T8 is connected to the first light-emitting control signal line EM1 to receive the first light-emitting control signal Em1.

[0088] The drain of the second light-emitting control transistor T9 is connected to the second power supply signal line 61 to receive the first power supply signal Vdd. The drain of the second light-emitting control transistor T9 is connected to the fifth node N5. The gate of the second light-emitting control transistor T9 is connected to the second light-emitting control signal to receive the second light-emitting control signal Em2.

[0089] The display panel further includes a light-emitting device EL connected to the pixel driving circuit PD. One end of the light-emitting device EL is connected to the fourth node N4. The other end of the light-emitting device EL is connected to the third power supply signal line VSS to receive the third power supply signal Vss.

[0090] One plate of the first capacitor C1 is connected to the first node N1, and the other plate of the first capacitor C1 is connected to the second node N2; one plate of the second capacitor C2 is connected to the first node N1, and the other plate of the second capacitor C2 is connected to the first power supply signal line VDD; the third capacitor C3 and the fourth capacitor C4 are connected in series between the active part of the switching transistor T1 and the active part of the switching reset transistor T7; one plate of the fifth capacitor C5 is connected to the active part of the first reset transistor T4, and the other plate of the fifth capacitor C5 is connected to the first power supply signal line VDD; one plate of the sixth capacitor C6 is connected to the active part of the compensation transistor T3, and the other plate of the sixth capacitor C6 is connected to the first power supply signal line VDD.

[0091] It should be noted that in the embodiment of the present application, the signal can be coupled to the second node N2, that is, to the gate of the driving transistor T2, through the first capacitor C1; and the first capacitor C1 and the second capacitor C2 can stabilize the potentials of the first node N1 and the second node N2, reducing the probability of signal instability and signal flicker; the third capacitor C3, the fourth capacitor C4, the fifth capacitor C5, and the sixth capacitor C6 are respectively used to prevent the switching transistor T1, the switching reset transistor T7, the first reset transistor T4, and the compensation transistor T3 from leaking electricity, and can also reduce the probability of signal flicker.

[0092] For the switching transistors T1 in different sub-pixels PX, the data signal lines DATA they are connected to are different. In the present application, only one of them is taken as an example for illustration.

[0093] In this embodiment, the second power supply signal line 61 and the first power supply signal line VDD are used to provide a constant voltage high level to the pixel driving circuit PD, and the second power supply signal line 61 and the first power supply signal line VDD can be connected, and the third power supply signal line VSS is used to provide a constant voltage low level to the pixel driving circuit PD.

[0094] In this embodiment, the switching transistor T1, the driving transistor T2, the compensating transistor T3, the first reset transistor T4, the second reset transistor T5, the third reset transistor T6, the switching reset transistor T7, the first light-emitting control transistor T8, and the second light-emitting control transistor T9 are each independently selected from one of a P-type transistor and an N-type transistor; in this application, the switching transistor T1, the driving transistor T2, the compensating transistor T3, the first reset transistor T4, the second reset transistor T5, the third reset transistor T6, the switching reset transistor T7, the first light-emitting control transistor T8, and the second light-emitting control transistor T9 are all P-type transistors as an example for illustration.

[0095] In this embodiment, the source electrode is only the output end of this application, and the drain electrode is only the input end of this application, and they only have a difference in naming.

[0096] Next, for the Figure 4 [[ID=⑧]]structure, the film layer structure of the pixel circuit of this application will be described.

[0097] The display area AA and the non-display area NA of the display panel may be provided with a substrate 10 and an array driving layer provided on the substrate 10; within the display area AA, the display panel may further include a pixel definition layer 86 provided on the array driving layer, and a light-emitting portion 100 provided on the pixel definition layer 86. Next, the film layer structure within the display area AA will be mainly described.

[0098] In some embodiments, the substrate 10 supports the various layers provided on the substrate 10. When the display panel is a bottom-emitting light-emitting display device or a double-sided emitting light-emitting display device, a transparent substrate may be used. When the display panel is a top-emitting light-emitting display device, a semi-transparent or opaque substrate and a transparent substrate may be used.

[0099] In this embodiment, the substrate 10 is used to support the various film layers provided on the substrate ①, and the substrate 10 may be made of an insulating material such as glass, quartz, or polymer resin. The substrate 10 may be a rigid substrate or a flexible substrate that can be bent, folded, curled, etc. Examples of flexible materials for the flexible substrate include polyimide (PI), but are not limited to polyimide (PI).

[0100] In this embodiment, the substrate 10 may include a first flexible substrate, a first barrier layer, a second flexible substrate, and a second barrier layer that are stacked. The first flexible substrate and the second flexible substrate may be formed of the same material such as polyimide, and the first barrier layer and the second barrier layer may be formed of an inorganic material including at least one of SiOx and SiNx, for example. It should be noted that there is an error in the original text where "the substrate 10 supports the various layers provided on the substrate ①", and it should be "the substrate 10 supports the various layers provided on the substrate 10" in the translation.

[0101] Please refer to Figure 4 , the array driving layer may include a plurality of thin film transistors, and the thin film transistors may be etching blocking type, back channel etching type, or may be divided into bottom gate thin film transistors, top gate thin film transistors, etc. according to the positions of the gate and the active part, or may be divided into N-type thin film transistors, P-type thin film transistors according to the performance of the thin film transistors; wherein, Figure 4 the thin film transistors in Figure 2 do not represent the structure diagrams of any of the transistors in

[0102] Please refer to Figure 4 , the array driving layer may include a semiconductor layer 20 disposed on the substrate 10, a first gate insulating layer 81 disposed on the semiconductor layer 20, a first gate layer 30 disposed on the first gate insulating layer 81, a second gate insulating layer 82 disposed on the first gate layer 30, a second gate layer 40 disposed on the second gate insulating layer 82, an interlayer dielectric layer 83 disposed on the second gate layer 40, a first conductive layer 50 disposed on the interlayer dielectric layer 83, a first planarization layer 84 disposed on the first conductive layer 50, a second conductive layer 60 disposed on the first planarization layer 84, a second planarization layer 85 disposed on the second conductive layer 60, a light emitting device EL and a pixel defining layer 86 disposed on the second planarization layer 85.

[0103] In some embodiments, the material of the semiconductor layer 20 may be a silicon semiconductor. For example, the material of the semiconductor layer 20 in the present application may be low temperature polycrystalline silicon.

[0104] In some embodiments, the first gate insulating layer 81, the second gate insulating layer 82, and the interlayer dielectric layer 83 are respectively disposed on the corresponding metal layer or semiconductor layer 20 and are separated by different layers of the metal layer or semiconductor layer 20; and the materials of the first gate insulating layer 81, the second gate insulating layer 82, and the interlayer dielectric layer 83 may be inorganic substances combined with silicon oxynitride or organic materials with flatness.

[0105] In some embodiments, the first gate layer 30 and the second gate layer 40 are respectively disposed on the corresponding insulating layer, and the materials of the first gate layer 30 and the second gate layer 40 may be copper, molybdenum, or molybdenum-titanium alloy, etc.

[0106] In some embodiments, the materials of the first conductive layer 50 and the second conductive layer 60 may be copper, molybdenum, molybdenum-titanium alloy, or a three-layer metal of titanium-aluminum-titanium, etc.

[0107] In some embodiments, the first flat layer 84 and the second flat layer 85 are laid in whole layers to ensure the flatness of the film layers of the array driving layer. The materials of the first flat layer 84 and the second flat layer 85 can be inorganic substances combined with silicon oxynitride or organic materials with flatness.

[0108] It should be noted that the pixel definition layer 86 is disposed on the flat layer and is provided with a plurality of pixel openings 860. The light-emitting device EL may include an anode 71, a light-emitting portion 100, and a cathode which are stacked. The anode 71 is located within the pixel opening 860. The light-emitting portion 100 is disposed within the pixel opening 860 and on the anode 71. The cathode is located on the light-emitting portion 100.

[0109] It can be understood that each thin-film transistor and signal line in the pixel driving circuit PD can be located in the array driving layer. For example, the active portions of the thin-film transistors can be located in the semiconductor layer 20, and other electrodes of the thin-film transistors or the connected signal lines can be located in the first gate layer 30, the second gate layer 40, the first conductive layer 50, or the second conductive layer 60.

[0110] Please refer to Figure 1 and Figure 2 , because the capacitance formed between the data signal line DATA and some nodes in the pixel driving circuit PD is relatively large, which will further generate a large signal crosstalk and affect the display effect of the display panel. Thus, in the embodiments of the present application, the display panel further includes a data signal line DATA extending along the second direction Y and a first reset signal auxiliary line 62 extending along the second direction Y. Among them, the first reset signal auxiliary line 62 partially overlaps with the node connection line 53 in the thickness direction of the display panel, and the minimum distance L1 from the node connection line 53 to the data signal line DATA along the first direction X is greater than or equal to the minimum distance L2 from the first reset signal auxiliary line 62 to the data signal line DATA along the first direction X. Therefore, in the embodiments of the present application, by making the minimum distance L1 from the node connection line 53 to the data signal line DATA along the first direction X greater than or equal to the minimum distance L2 from the first reset signal auxiliary line 62 to the data signal line DATA along the first direction X, the first reset signal auxiliary line 62 can cover the edge of the node connection line 53 close to the data signal line DATA, so that the first reset signal auxiliary line 62 can be used as a shielding structure to be spaced between the node connection line 53 and the data signal line DATA, reducing the signal crosstalk between the first node N1 in the pixel driving circuit PD and the data signal line DATA, and improving the display effect of the display panel.

[0111] In some embodiments, each of the second power signal lines 61 is correspondingly located on one side of a plurality of the pixel driving circuits PD arranged along the second direction Y, and is connected to the second light-emitting control transistor T9.

[0112] Each of the data signal lines DATA is correspondingly located on one side of a plurality of the pixel driving circuits PD arranged along the second direction Y, and is connected to the switching transistor T1 in the pixel driving circuit PD.

[0113] Each of the first reset signal auxiliary lines 62 is correspondingly located on one side of a plurality of the pixel driving circuits PD arranged along the second direction Y, and the first reset signal auxiliary line 62 and the data signal line DATA may be located on opposite sides of the same pixel driving circuit PD. The first reset signal auxiliary line 62 is electrically connected to the switching reset transistor T7 in the pixel driving circuit PD, and the first reset signal auxiliary line 62 is connected to the fourth reset signal line VI4.

[0114] In the embodiments of the present application, the first reset signal auxiliary line 62 includes a connected first line segment 621 and a second line segment 622, and the minimum distance L3 between the first line segment 621 and the data signal line DATA is greater than the minimum distance L2 between the second line segment 622 and the data signal line DATA.

[0115] Since the line width of the second power signal line 61 increases, the wiring space in the film layer decreases, the distance between adjacent signal lines decreases, and the signal crosstalk increases. However, in the embodiments of the present application, by increasing the distance between the first line segment 621 in the first reset signal auxiliary line 62 and the data signal line DATA, the signal crosstalk between the first reset signal auxiliary line 62 and the data signal line DATA can be effectively reduced, and the signal transmission stability between the first reset signal auxiliary line 62 and the data signal line DATA can be improved.

[0116] Please refer to Figure 1 , the display panel may include a plurality of pixel driving circuits PD arranged along the first direction X and the second direction Y, and the first direction and the second direction intersect; in some embodiments, the first direction X and the second direction Y are perpendicular to each other.

[0117] Among them, the display panel includes a plurality of repeating units, and Figure 1 as shown is one of the repeating units. Each repeating unit includes three pixel driving circuits PD arranged along the first direction X and three data signal lines DATA connected to the three pixel driving circuits PD in the repeating unit.

[0118] It can be understood that one first reset signal auxiliary line 62 can be correspondingly arranged for each of the repeating units, or one first reset signal auxiliary line 62 can be correspondingly arranged for multiple repeating units; each second power supply signal line 61 extends along the second direction Y, and each second power supply signal line 61 is located on one side of a plurality of pixel driving circuits PD arranged along the second direction Y and is electrically connected to the pixel driving circuit PD.

[0119] It should be noted that for one pixel driving circuit PD, the second power supply signal line 61 is arranged close to the middle area of the pixel driving circuit PD, the first reset signal auxiliary line 62 and the data signal line DATA are respectively located on the opposite first side and second side of the pixel driving circuit PD, and thus the first reset signal auxiliary line 62 is closer to the data signal line DATA connected to one pixel driving circuit PD adjacent to the first side; therefore, the minimum distance L3 between the first line segment 621 and the data signal line DATA can be regarded as the minimum distance between the first line segment 621 and the data signal line DATA connected to one pixel driving circuit PD adjacent to the first side. Similarly, the minimum distance L2 between the second line segment 622 and the data signal line DATA can be regarded as the minimum distance between the second line segment 622 and the data signal line DATA connected to one pixel driving circuit PD adjacent to the second side.

[0120] In the following embodiments, the technical solution of the present application will be described by taking the structure of each film layer in the pixel driving circuit PD in one repeating unit as an example.

[0121] Please refer to Figure 5 , the semiconductor layer 20 includes a switching active part T1A of the switching transistor T1, a driving active part T2A of the driving transistor T2, a compensating active part T3A of the compensating transistor T3, a first reset active part T4A of the first reset transistor T4, a second reset active part T5A of the second reset transistor T5, a third reset active part T6A of the third reset transistor T6, a switching reset active part T7A of the switching reset transistor T7, a first light emission control active part T8A of the first light emission control transistor T8, a second light emission control active part T9A of the second light emission control transistor T9, and a second reset signal auxiliary line 21.

[0122] Among them, the switching active part T1A is connected to the switching reset active part T7A and is arranged at intervals from other active parts; the second reset signal auxiliary line 21 extends along the first direction X and connects the switching reset active parts T7A in a plurality of pixel driving circuits PD arranged along the first direction X together.

[0123] Among them, the switching active part T1A is in an n shape, and one end of the switching active part T1A is used to be connected to the data signal line DATA, and the other end of the switching active part T1A is connected to the switching reset active part T7A; the switching reset active part T7A is in an n shape, one end of the switching reset active part T7A is connected to the switching active part T1A, and the other end of the switching reset active part T7A is connected to the second reset signal auxiliary line 21; the switching active part T1A and the switching reset active part T7A are connected to each other at the first node N1.

[0124] In some embodiments, the switching active part T1A includes a first connection sub-part 22 and a second connection sub-part 23 arranged along the first direction X, and a third connection sub-part 24 extending along the first direction X and connected between the first connection sub-part 22 and the second connection sub-part 23. Both the first connection sub-part 22 and the second connection sub-part 23 extend along the second direction Y.

[0125] The switching reset active part T7A includes a fourth connection sub-part 25 and a fifth connection sub-part 26 arranged along the first direction X, and a sixth connection sub-part 27 extending along the first direction X and connected between the fourth connection sub-part 25 and the fifth connection sub-part 26. Both the fourth connection sub-part 25 and the fifth connection sub-part 26 extend along the second direction Y.

[0126] The first connection sub-part 22 is used to be connected to the data signal line DATA. The second connection sub-part 23 and the fourth connection sub-part 25 are connected to each other at the first node N1. The fifth connection sub-part 26 is used to be connected to the fourth reset signal line VI4.

[0127] Among them, there is a first distance between the first connection sub-part 22 and the second connection sub-part 23 along the first direction X, and there is a second distance between the fourth connection sub-part 25 and the fifth connection sub-part 26 along the first direction X. The first distance is greater than or equal to the second distance. By increasing the distance between the first connection sub-part 22 and the second connection sub-part 23 in the embodiments of the present application, the distance between the data signal line DATA and the first node N1 can be increased, and the signal crosstalk between the data signal line DATA and the first node N1 can be reduced.

[0128] The driving active part T2A, the compensating active part T3A, the first reset active part T4A, the second reset active part T5A, the third reset active part T6A, the first light-emitting control active part T8A, and the second light-emitting control active part T9A are connected, and the third reset active parts T6A in the plurality of pixel driving circuits PD arranged along the first direction X are connected together.

[0129] Among them, the driving active part T2A is in an n shape. One end of the driving active part T2A is connected to the third node N3, and the other end of the driving active part T2A is connected to the fifth node N5; one end of the compensating active part T3A is connected to the second node N2, and the other end of the compensating active part T3A is connected to the third node N3; one end of the first reset active part T4A is connected to the second node N2, and the other end of the first reset active part T4A is for signal input; one end of the first light-emitting control active part T8A is connected to the third node N3, and the other end of the first light-emitting control active part T8A is connected to the fourth node N4; one end of the second reset active part T5A is connected to the fourth node N4, and the other end of the second reset active part T5A is for signal input; one end of the second light-emitting control active part T9A is connected to the fifth node N5, and the other end of the second light-emitting control active part T9A is for signal input; one end of the third reset active part T6A is connected to the fifth node N5, and the other end of the third reset active part T6A is for signal input.

[0130] Further, the compensating active part T3A, the first reset active part T4A, the second reset active part T5A, the third reset active part T6A, the first light-emitting control active part T8A, and the second light-emitting control active part T9A are all located on a side of the driving active part T2A away from the switching active part T1A; furthermore, the first light-emitting control active part T8A is located on a side of the compensating active part T3A away from the driving active part T2A, and the second light-emitting control active part T9A is located on a side of the first reset active part T4A away from the driving active part T2A.

[0131] In some embodiments, the switching active part T1A and the switching reset active part T7A are adjacent and connected along the first direction X, and the first reset active part T4A and the compensating active part T3A are adjacent and connected along the first direction X.

[0132] In some embodiments, in the same pixel driving circuit PD, the first light-emitting control active part T8A is located on a side of the driving active part T2A away from the switching active part T1A and extends along the second direction Y.

[0133] Please refer to Figure 6 and Figure 7 , the first gate layer 30 is disposed on a side of the semiconductor layer 20 away from the substrate 10, and the first gate layer 30 includes gates of transistors in the pixel driving circuit PD.

[0134] Specifically, the first gate layer 30 includes a switching gate T1G of the switching transistor T1, a driving gate T2G of the driving transistor T2, a compensation gate T3G of the compensation transistor T3, a first reset gate T4G of the first reset transistor T4, a second reset gate T5G of the second reset transistor T5, a third reset gate T6G of the third reset transistor T6, a switching reset gate T7G of the switching reset transistor T7, a first light-emitting control gate T8G of the first light-emitting control transistor T8, a second light-emitting control gate T9G of the second light-emitting control transistor T9, a first electrode plate C11 of the first capacitor C1, and a third electrode plate C21 of the second capacitor C2.

[0135] Among them, the first electrode plate C11 of the first capacitor C1 is multiplexed as the driving gate T2G.

[0136] Please combine Figure 5 , Figure 6 and Figure 7 , there are two overlapping positions between the switching gate T1G and the switching active part T1A, so that the switching transistor T1 can form a double-gate structure; there are two overlapping positions between the switching reset gate T7G and the switching reset active part T7A, so that the switching reset transistor T7 can form a double-gate structure; there are two overlapping positions between the compensation gate T3G and the compensation active part T3A, which can make the compensation transistor T3 form a double-gate structure; there are two overlapping positions between the first reset transistor T4 and the first reset active part T4A, so that the first reset transistor T4 can form a double-gate structure; it can be understood that the thin-film transistor with the above double-gate structure can effectively reduce the leakage current and improve the electrical properties of the thin-film transistor.

[0137] In addition, the driving gate T2G is disposed on a side of the driving active part T2A away from the substrate 10, the driving gate T2G overlaps with the driving active part T2A, the second reset gate T5G overlaps with the second reset active part T5A, the third reset gate T6G overlaps with the third reset active part T6A, the first light-emitting control gate T8G overlaps with the first light-emitting control active part T8A, and the second light-emitting control gate T9G overlaps with the second light-emitting control active part T9A.

[0138] It should be noted that the fourth control signal line SCAN4 extends along the first direction X and overlaps with the second reset active part T5A and the third reset active part T6A at the same time, so as to be multiplexed as the second reset gate T5G and the third reset gate T6G.

[0139] In some embodiments, the widths of the overlapping parts of the second reset active part T5A and the second reset gate T5G, the overlapping parts of the third reset active part T6A and the third reset gate T6A, the overlapping parts of the first light-emitting control active part T8A and the first light-emitting control gate T8G, and the overlapping parts of the second light-emitting control active part T9A and the second light-emitting control active part T9A are all increased, and are all greater than the widths of the active parts of other thin-film transistors in the pixel driving circuit PD. For example, the overlapping parts of the switching active part T1A and the switching gate T1G, the overlapping parts of the driving active part T2A and the driving gate T2G, the overlapping parts of the compensation active part T3A and the compensation gate T3G, the overlapping parts of the first reset active part T4A and the first reset gate T4G, and the overlapping parts of the switching reset active part T7A and the switching reset gate T7G.

[0140] Furthermore, the relatively other end of the switching active part T1A away from the first node N1 can be multiplexed as the switching drain T1D, and the end of the switching active part T1A close to the first node N1 can be multiplexed as the switching source T1S; the relatively other end of the switching reset active part T7A away from the first node N1 can be multiplexed as the switching reset drain T7D, and the end of the switching reset active part T7A close to the first node N1 can be multiplexed as the switching reset source T7S.

[0141] One end of the driving active part T2A close to the fifth node N5 can be reused as the driving drain T2D, and one end of the driving active part T2A close to the third node N3 can be reused as the driving source T2S; one end of the compensating active part T3A close to the second node N2 can be reused as the compensating drain T3D, and one end of the compensating active part T3A close to the third node N3 can be reused as the compensating source T3S; one end of the first reset active part T4A close to the second node N2 can be reused as the first reset source T4S, and the end of the first reset active part T4A far from the second node N2 can be reused as the first reset drain T4D; one end of the first light-emitting control active part T8A close to the third node N3 can be reused as the first light-emitting control drain T8D, and one end of the first light-emitting control active part T8A close to the fourth node N4 can be reused as the first light-emitting control source T8S; one end of the second reset active part T5A close to the fourth node N4 can be reused as the second reset drain T5D, and the opposite end of the second reset active part T5A far from the fourth node N4 can be reused as the second reset source T5S; one end of the second light-emitting control active part T9A close to the fifth node N5 can be reused as the second light-emitting control source T9S, and the opposite end of the second light-emitting control active part T9A far from the fifth node N5 can be reused as the second light-emitting control drain T9D; one end of the third reset active part T6A close to the fifth node N5 can be reused as the third reset source T6S, and the opposite end of the third reset active part T6A far from the fifth node N5 can be reused as the third reset drain T6D.

[0142] Please refer to Figure 8 and Figure 9 , the second gate layer 40 is disposed on a side of the first gate layer 30 away from the semiconductor layer 20, and the second gate layer 40 includes a plurality of signal lines and capacitor plates.

[0143] Specifically, the second gate layer 40 includes a second plate C12 of the first capacitor C1, a fourth plate C22 of the second capacitor C2, a fifth plate C31, a sixth plate C41, a first reset signal line VI1, a third reset signal line VI3, a first light-emitting control signal line EM1, a second light-emitting control signal line EM2, a first jumper wire 41, and a plate connection wire 42; and the fifth plate C31 and the sixth plate C41 are both connected to the third reset signal line VI3, and the seventh plate C51 and the eighth plate C61 are both connected to the fourth plate C22 and can be electrically connected to the second power supply signal line 61 and the first power supply signal line VDD.

[0144] Wherein, the first electrode plate C11 and the second electrode plate C12 are arranged opposite to each other to form the first capacitor C1, the fourth electrode plate C22 and the third electrode plate C21 are arranged opposite to each other to form the second capacitor C2, the fifth electrode plate C31 and the switch active part T1A are arranged opposite to each other to form the third capacitor C3, and the sixth electrode plate C41 and the switch reset active part T7A are arranged opposite to each other to form the fourth capacitor C4.

[0145] In addition, the electrode plate connection line 42 is connected to the fourth electrode plate C22; at least a part of the electrode plate connection line 42 extends along the second direction Y and is located between two of the second electrode plates C12 in two adjacent pixel driving circuits PD arranged along the first direction X.

[0146] Wherein, the electrode plate connection line 42 and the data signal line DATA do not overlap at least partially in the thickness direction of the display panel; thus, the capacitance between the second power supply signal line 61 and the data signal line DATA can be effectively reduced, and signal interference can be reduced.

[0147] In some embodiments, the electrode plate connection line 42 includes a third line segment 421 extending along the second direction Y, a fourth line segment 422 extending along the first direction X, and a fifth line segment 423 extending along the first direction X. The fourth line segment 422 is connected between the third line segment 421 and the fifth line segment 423, and the third line segment 421 is connected between the fourth line segment 423 and the fourth electrode plate C22.

[0148] The width of the fourth line segment 422 along the second direction Y is smaller than the width of the fifth line segment 423 along the second direction Y. The data signal line DATA partially overlaps with the fourth line segment 423 in the thickness direction of the display panel, and the data signal line DATA does not overlap with the fifth line segment 423 in the thickness direction of the display panel; that is, in the embodiments of the present application, by reducing the line width of the electrode plate connection line 42 and making the part with the reduced line width overlap with the data signal line DATA, the capacitance between the data signal line DATA and the second power supply signal line 61 can be further reduced, and signal interference can be reduced.

[0149] The first reset active part T4A and the fifth line segment 423 are aligned in the thickness direction of the display panel to form the fifth capacitor C5; the compensation active part T3A and the fifth line segment 423 are aligned in the thickness direction of the display panel to form the sixth capacitor C6; and in the embodiment of the present application, the fifth line segment 423 is maintained at a relatively large line width without line width reduction, thereby increasing the overlapping area between the first reset active part T4A and the fifth line segment 423 and between the compensation active part T3A and the fifth line segment 423, and further increasing the capacitance value between the fifth capacitor C5 and the sixth capacitor C6, and improving the electrical stability of the first reset transistor T4 and the compensation transistor T3.

[0150] The first light emission control signal line EM1 is used to electrically connect to the first light emission control gate T8G to transmit signals, the second light emission control signal line EM2 is used to electrically connect to the second light emission control gate T9G to transmit signals, the first reset signal line VI1 is used to electrically connect to the first reset drain T4D, and the third reset signal line VI3 is used to electrically connect to the third reset drain T6D; the specific connection relationship can be seen in the subsequent embodiments.

[0151] In some embodiments, the semiconductor layer 20 further includes a second reset signal auxiliary line 21 extending along the first direction X. In a top view, the second reset signal auxiliary line 21 is located on a side of the second capacitor C2 away from the first capacitor C1; the second reset signal auxiliary line 21 is connected to the first reset signal auxiliary line 62, and a first protrusion 211 extending along the second direction Y is connected to the second reset signal auxiliary line 21.

[0152] A second protruding portion 43 extending in the second direction Y is connected to the fourth electrode plate C22, and the first protruding portion 211 and the second protruding portion 43 at least partially overlap in the thickness direction of the display panel; thereby, the capacitance between the second power supply signal line 61 and the first reset signal auxiliary line 62 can be increased, and the total capacitance that the second power supply signal line 61 can form in the pixel driving circuit PD can be increased. Furthermore, the proportion of the capacitance formed between the second power supply signal line 61 and the data signal line DATA in the total capacitance is reduced, and the signal crosstalk generated by the capacitance formed between the second power supply signal line 61 and the data signal line DATA can be effectively reduced; at the same time, the total capacitance that the first reset signal auxiliary line 62 can form in the pixel driving circuit PD can also be increased, and further, the capacitance proportion between the first reset signal auxiliary line 62 and the data signal line DATA can be reduced, and the signal crosstalk generated by the capacitance formed between the first reset signal auxiliary line 62 and the data signal line DATA can be effectively reduced.

[0153] In some embodiments, the first protruding portion 211 is located on a side of the second reset signal auxiliary line 21 away from the first capacitor C1, and the second protruding portion 43 is located on a side of the fourth substrate C22 away from the first capacitor C1.

[0154] Please refer to Figure 10 and Figure 11 , the first conductive layer 50 is disposed on a side of the second gate layer 40 away from the first gate layer 30. The first conductive layer 50 includes the first control signal line SCAN1, the second control signal line SCAN2, the third control signal line SCAN3, the second reset signal line VI2, the fourth reset signal line VI4, the first power supply signal line VDD, the second jumper wire 51, the third jumper wire 52, the node connection wire 53, the fourth jumper wire 54, the fifth jumper wire 55, the sixth jumper wire 56, the seventh jumper wire 57, the eighth jumper wire 58, the ninth jumper wire 59, the tenth jumper wire 510, the eleventh jumper wire 511, and the twelfth jumper wire 512.

[0155] Among them, please combine Figure 6 , ​ and ​ , the first power supply signal line VDD extends along the first direction X and is connected to the fourth electrode plate C22.

[0156] The switching gate T1G is connected to the first control signal line SCAN1, and the switching active part T1A is connected to the second jumper wire 51.

[0157] The switch reset gate T7G is connected to the second control signal line SCAN2, and the switch reset active part T7A is connected to the second reset signal auxiliary line 21.

[0158] The third jumper wire 52 is connected to the switch reset active part T7A and the second reset signal auxiliary line 21;

[0159] One end of the node connection wire 53 is connected to the first node N1, and the other end of the node connection wire 53 is connected to the third electrode plate C21 and the second electrode plate C12; the fourth jumper wire 54 is connected between the second node N2 and the first electrode plate C11; the fifth jumper wire 55 is connected between the second light emission control signal line EM2 and the second light emission control gate T9G; the sixth jumper wire 56 is connected between the first reset signal line VI1 and the first reset active part T4A; the seventh jumper wire 57 is connected to the second light emission control active part T9A; the eighth jumper wire 58 is connected between the first light emission control signal line EM1 and the first light emission control gate T8G; the ninth jumper wire 59 is connected to the fourth node N4; the eleventh jumper wire 510 is connected to the third reset active part T6A and the first jumper wire 41, and the third jumper wire 52 is ​ connected to the third reset signal line VI3 in another repeating unit in the lower middle; both the eleventh jumper wire 511 and the twelfth jumper wire 512 are connected between the second reset active part T5A and the second reset signal line VI2. For example, one repeating unit contains three pixel driving circuits PD, and in some of the pixel driving circuits PD, the eleventh jumper wire 511 is connected between the second reset active part T5A and the second reset signal line VI2, and in another part of the pixel driving circuits PD, the twelfth jumper wire 512 is connected between the second reset active part T5A and the second reset signal line VI2.

[0160] Please refer to ​ and ​ As shown in FIGS.

[0161] The data signal line DATA is connected to the second jumper wire 51, and further, the data signal line DATA is connected to the switch active part T1A through the second jumper wire 51.

[0162] In some embodiments, the fourth control signal line SCAN4 is reduced in width near the fifth jumper wire 64 to avoid the connection control arrangement of the subsequent jumper wire 64 and the anode 71, and the width of the fourth control signal line SCAN4 near the fifth jumper wire 64 is less than the width of the second reset gate T5G and also less than the width of the third reset gate T6G.

[0163] In some embodiments, the second conductive layer 60 includes a plurality of the data signal lines DATA arranged along the first direction X and a plurality of the second power signal lines 61 arranged along the first direction, and one of the second power signal lines 61 is located between two adjacent data signal lines DATA.

[0164] In some embodiments, in a repeating unit, the data signal lines DATA may include a first data signal line DATA1, a second data signal line DATA2, and a third data signal line DATA3, and the first data signal line DATA1, the second data signal line DATA2, and the third data signal line DATA3 are respectively connected to a pixel driving circuit PD. For example, the light emitting device EL corresponding to the pixel driving circuit PD connected to the first data signal line DATA1 emits red light, the light emitting device EL corresponding to the pixel driving circuit PD connected to the second data signal line DATA2 emits green light, and the light emitting device EL corresponding to the pixel driving circuit PD connected to the third data signal line DATA3 emits blue light.

[0165] The first reset signal auxiliary line 62 is connected to the third jumper wire 52. Further, the first reset signal auxiliary line 62 is connected to the switch reset active part T7A and the second reset signal auxiliary line 21 through the third jumper wire 52. The second reset signal auxiliary lines 21 extending along the first direction X and the first reset signal auxiliary lines 62 extending along the second direction Y in a plurality of pixel driving circuits PD are connected to form a mesh, which can reduce the impedance while realizing signal transmission.

[0166] The second power signal line 61 is connected to the first power signal line VDD and can also be used to transmit a high-level potential. The first power signal lines VDD extending along the first direction X and the second power signal lines 61 extending along the second direction Y in a plurality of pixel driving circuits PD are connected to form a mesh, which can reduce the impedance while realizing signal transmission.

[0167] In some embodiments, the second power signal line 61 is further connected to the seventh patch cord 57 and is connected to the second light-emitting control active part T9A through the seventh patch cord 57.

[0168] Among them, the second power signal line 61 is used to transmit a constant voltage high level, and has a large thickness and width, and the second power signal line 61 is located below the light-emitting part 100. Therefore, the second power signal line 61 has a great influence on the film layer flatness of the position where the light-emitting part 100 is located. Therefore, in the embodiments of the present application, the second power signal line 61 includes an overlapping line segment 611, the light-emitting part 100 includes a bottom surface 1001 on one side close to the second power signal line 61, and the orthographic projection of the overlapping line segment 611 on the substrate 10 is located within the orthographic projection of the bottom surface 1001 on the substrate 10. The ratio of the orthographic projection area of the overlapping line segment 611 on the substrate 10 to the orthographic projection area of the bottom surface 1001 of the light-emitting part 100 on the substrate 10 is greater than or equal to 0.5. Furthermore, in the embodiments of the present application, by increasing the area and coverage range of the overlapping line segment 611, the film layer flatness of the position where the light-emitting part 100 is located can be improved, the film thickness uniformity and yield of the light-emitting part 100 can be improved, and thus the light-emitting effect and light-emitting efficiency of the display panel can be improved.

[0169] In some embodiments, the ratio of the orthographic projection area of the overlapping line segment 611 on the substrate 10 to the orthographic projection area of the bottom surface 1001 of the light-emitting part 100 on the substrate 10 is less than or equal to 1, or the ratio of the orthographic projection area of the overlapping line segment 611 on the substrate 10 to the orthographic projection area of the bottom surface 1001 of the light-emitting part 100 on the substrate 10 is less than or equal to 0.8. For example, the ratio of the orthographic projection area of the overlapping line segment 611 on the substrate 10 to the orthographic projection area of the bottom surface 1001 of the light-emitting part 100 on the substrate 10 can be 0.5, 0.6, 0.7, 0.8, 0.9 or 1.

[0170] In some embodiments, the ratio of the width of the overlapping line segment 611 in the first direction X to the width of the bottom surface 1001 in the first direction X is greater than or equal to 0.5 and less than or equal to 1. It should be noted that in the related art, the line width of the power signal line usually accounts for less than 0.2 of the width of the light-emitting pixel, and the thickness of the power signal is usually large, which will have a great influence on the film layer flatness of the position where the light-emitting pixel is located. Furthermore, in the embodiments of the present application, by increasing the width and coverage range of the overlapping line segment 611, the film layer flatness of the position where the light-emitting part 100 is located can be improved, the film thickness uniformity and yield of the light-emitting part 100 can be improved, and thus the light-emitting effect and light-emitting efficiency of the display panel can be improved.

[0171] In some embodiments, the ratio of the width of the overlapping line segment 611 in the first direction X to the width of the bottom surface 1001 in the first direction X is 0.5, 0.6, 0.7, 0.8, 0.9 or 1; further preferably, the ratio of the width of the overlapping line segment 611 in the first direction X to the width of the bottom surface 1001 in the first direction X is greater than or equal to 0.5 and less than or equal to 0.8.

[0172] In some embodiments, the ratio of the width of the overlapping line segment 611 in the first direction X to the width of the bottom surface 1001 in the first direction X is greater than or equal to 0.5 and less than or equal to 1.

[0173] It can be understood that since the width of the second power supply signal line 61 increases, the wiring space in the film layer will be reduced, resulting in a decrease in the distance between adjacent traces, and signal crosstalk is likely to occur.

[0174] In the embodiment of the present application, the first reset signal auxiliary line 62 is located between the second power supply signal line 61 and the data signal line DATA. Wherein, the first reset signal auxiliary line 62 includes a connected first line segment 621 and a second line segment 622, and the distance between the first line segment 621 and the data signal line DATA is greater than the distance between the second line segment 622 and the data signal line DATA.

[0175] Therefore, in the embodiment of the present application, by increasing the distance between the first line segment 621 in the first reset signal auxiliary line 62 and the data signal line DATA, the signal crosstalk between the first reset signal auxiliary line 62 and the data signal line DATA can be effectively reduced, and the signal transmission stability between the first reset signal auxiliary line 62 and the data signal line DATA can be improved.

[0176] In some embodiments, the minimum distance L1 from the node connection line 53 to the data signal line DATA in the first direction X is greater than or equal to the minimum distance L2 from the second line segment 622 to the data signal line DATA in the first direction X; and then the side of the node connection line 53 closest to the data signal line DATA will be covered by the second line segment 622, so that the second line segment 622 is spaced between the node connection line 53 and the side of the node connection line 53 closest to the data signal line DATA, so as to play a shielding role and reduce the signal crosstalk between the node connection point 53 (i.e., the first node N1) and the data signal line DATA.

[0177] Further, the first line segment 621 is parallel to the data signal line DATA. The second line segment 622 includes an intermediate sub - portion 6221 and a connecting sub - portion 6222 connecting the intermediate sub - portion 6221 and the first line segment 621. The intermediate sub - portion 6221 is parallel to the data signal line DATA, and the extending direction of the connecting sub - portion 6222 intersects with the data signal line DATA. It should be noted that in the embodiment of the present application, the first reset signal auxiliary line 62 is designed with a broken line at the second line segment 622 in the direction of the data signal line DATA, increasing the distance between the first line segment 621 and the data signal line DATA to reduce the signal crosstalk between the data signal line DATA and the first reset signal auxiliary line 62. And the second line segment 621 is spaced between the node connection line 53 and the data signal line DATA closest to the node connection line 53 to play a shielding role and reduce the signal crosstalk between the node connection point 53 (i.e., the first node N1) and the data signal line DATA.

[0178] Further, in some embodiments, the node connection line 53 and the second line segment 622 have an overlapping portion in the thickness direction of the display panel. The minimum distance from the overlapping portion along the first direction X to the data signal line DATA is greater than or equal to the minimum distance from the second line segment 622 along the first direction X to the data signal line DATA, so as to ensure that the side of the node connection line 53 closest to the data signal line DATA is covered by the second line segment 622.

[0179] In some embodiments, the node connection line 53 is connected to the second electrode plate C12. The minimum distance from the second electrode plate C12 along the first direction X to the data signal line DATA is greater than or equal to the minimum distance from the second line segment 622 along the first direction X to the data signal line DATA. Since the second electrode plate C12 is also electrically connected to the first node N1, in the embodiment of the present application, the second line segment 622 can cover the side of the second substrate C12 closest to the data signal line DATA, and further, the second line segment 621 can be spaced between the second capacitor C12 and the data signal line DATA closest to the second capacitor C12 to play a shielding role and reduce the signal crosstalk between the first node N1 and the data signal line DATA.

[0180] In some embodiments, the first power supply signal line VDD extends along the first direction X. The first power supply signal line VDD includes a plurality of first sub-parts VDD1 arranged along the first direction X. The first sub-parts VDD1 extend along the second direction Y. The first sub-parts VDD1 are located between the node connection line 53 and the data signal line DATA. The first sub-parts VDD1 and the node connection line 52 overlap at least partially along the first direction X.

[0181] Further, the center of the plate connection line 42 extending along the second direction Y is located on one side of the center of the data signal line DATA, and the center of the first sub-part VDD1 is located on the opposite side of the center of the data signal line DATA; thus, the first sub-part VDD1 and the plate connection line 42 extending along the second direction Y are respectively located on opposite sides of the data signal line DATA, and can be used to shield the signal crosstalk between the data signal line DATA and the first node N1 (i.e., the node connection line 53).

[0182] In some embodiments, a plurality of the first sub-parts VDD1 arranged along the first direction X are correspondingly arranged with a plurality of pixel driving circuits PD arranged along the first direction X. A plurality of the data signal lines DATA are correspondingly connected to a plurality of the pixel driving circuits PD arranged along the first direction X; for the same pixel driving circuit PD, the minimum distance L4 between the second electrode plate C12 and the data signal line DATA along the first direction X is greater than or equal to the minimum distance L5 between the first sub-part VDD1 and the data signal line DATA along the first direction X.

[0183] In some embodiments, the first power supply signal line VDD further includes a second sub-part VDD2 connected between adjacent first sub-parts VDD1, and the extending direction of the second sub-part VDD2 intersects both the first direction X and the second direction Y. The acute angle between the extending direction of the second sub-part VDD2 and the first direction X is less than the acute angle between the extending direction of the second sub-part VDD2 and the second direction Y.

[0184] In some embodiments, one end of the anode connection part 64 is connected to the ninth jumper wire 59, and the other end of the anode connection part 64 is used to connect to the anode 71.

[0185] The functional trace 63 extends along the second direction Y, and one functional trace 63 can be provided in each repeating unit.

[0186] In some embodiments, the functional trace 63 may extend into the non-display area NA and be connected to a constant low voltage signal located in the non-display area NA to form an auxiliary cathode line, reducing the resistance of the cathode in the display panel.

[0187] In some embodiments, the functional trace 63 may be used to connect at least one of the first reset signal line VI1, the second reset signal line VI2, and the third reset signal line VI3 extending along the first direction X to form a mesh trace structure, reducing the trace resistance.

[0188] Please refer to ​ and ​ , the anode layer 70 is disposed on a side of the second flat layer 85 away from the first flat layer 84. The anode layer 70 includes a plurality of anodes 71, and the anodes 71 are connected to the anode connection portion 64, that is, the anodes 71 are connected to the first light-emitting control active portion T8A through the anode connection portion 64.

[0189] Please refer to ​ , the pixel definition layer 86 is disposed on a side of the anode layer 70 away from the second conductive layer 60. A plurality of pixel openings 860 are formed in the pixel definition layer 86, and a partial surface of the corresponding anode 71 is exposed through each pixel opening 860.

[0190] In some embodiments, the pixel definition layer 86 may include a first pixel definition layer 861 and a second pixel definition layer 862. Among them, the first pixel definition layer 861 may extend along the first direction X, the second pixel definition layer 862 may extend along the second direction Y, and the first pixel definition layer 861 and the second pixel definition layer 862 intersect to enclose the pixel openings 860.

[0191] The light-emitting layer 13 is disposed on the pixel definition layer 86. The light-emitting layer 13 includes a plurality of light-emitting portions 100. The plurality of light-emitting portions 100 are disposed corresponding to the plurality of pixel openings 860. One light-emitting portion 100 is disposed in the corresponding pixel opening 860 and is located on a side of the anode 71 away from the substrate 10.

[0192] In some embodiments, the cathode covers the pixel definition layer 86 and the plurality of light-emitting portions 100, and the stacked anodes 71, light-emitting portions 100, and cathode may form the light-emitting device EL.

[0193] In some embodiments, the display panel further includes a packaging layer disposed on a side of the cathode away from the pixel defining layer 86, and the packaging layer covers the cathode to block moisture from entering the light-emitting device EL, thereby improving the stability and service life of the display panel.

[0194] In some embodiments, in the same pixel driving circuit PD, the first capacitor C1 and the driving transistor T2 partially overlap in the thickness direction of the display panel, the second capacitor C2 is located between the first capacitor C1 and the switching transistor T1, and the second capacitor is located between the driving transistor T2 and the switching transistor T1.

[0195] Continuing from the above, for the pixel driving circuit PD described in the above embodiments, at least a part of the thin film transistors partially overlap with the overlapping line segment 611 in the first direction X to further increase the coverage of the overlapping line segment 611.

[0196] In some embodiments, the switching transistor T1 partially overlaps with the overlapping line segment 611 in the thickness direction of the display panel, the driving transistor T2 partially overlaps with the overlapping line segment 611 in the thickness direction of the display panel, and the first capacitor C1 partially overlaps with the overlapping line segment 611 in the thickness direction of the display panel.

[0197] Among them, in the switching transistor T1, the switching active part T1A partially overlaps with the overlapping line segment 611 in the thickness direction of the display panel, the switching gate T1G partially overlaps with the overlapping line segment 611 in the thickness direction of the display panel, the driving active part T2A partially overlaps with the overlapping line segment 611 in the thickness direction of the display panel, the driving gate T1G partially overlaps with the overlapping line segment 611 in the thickness direction of the display panel, and both the first electrode plate C11 and the second electrode plate C12 in the first capacitor C1 partially overlap with the overlapping line segment 611 in the thickness direction of the display panel.

[0198] In some embodiments, the second capacitor C2 is electrically connected to the second power signal line 61, and the second capacitor C2 partially overlaps with the overlapping line segment 611 in the thickness direction of the display panel.

[0199] Among them, both the third electrode plate C21 and the fourth electrode plate C22 in the second capacitor C2 partially overlap with the overlapping line segment 611 in the thickness direction of the display panel.

[0200] In some embodiments, the first reset transistor T4 is located on a side of the driving transistor T2 away from the switching transistor T1, and the first reset transistor T4 and the overlapping line segment 611 are partially overlapped in the thickness direction of the display panel.

[0201] Wherein, in the first reset transistor T4, the first reset active part T4A and the overlapping line segment 611 are partially overlapped in the thickness direction of the display panel, and the first reset gate T4G and the overlapping line segment 611 are partially overlapped in the thickness direction of the display panel.

[0202] In some embodiments, the compensation transistor T3 is located on a side of the driving transistor T2 away from the switching transistor T1, the compensation transistor T3 and the first reset transistor T4 are arranged adjacent to each other along the first direction X, and the compensation transistor T3 and the overlapping line segment 611 are partially overlapped in the thickness direction of the display panel.

[0203] Wherein, in the compensation transistor T3, the compensation active part T3A and the overlapping line segment 611 are partially overlapped in the thickness direction of the display panel, and the compensation gate T3G and the overlapping line segment 611 are partially overlapped in the thickness direction of the display panel.

[0204] It should be noted that the compensation gate T3G and the compensation active part T3A are arranged close to the edge of the bottom surface 1001 of the light-emitting part 100. In the embodiments of the present application, the overlapping line segment 611 is arranged to be partially overlapped with the compensation gate T3G and the compensation active part T3A, so as to effectively increase the coverage range of the overlapping line segment 611 and improve the flatness of the film layer where the light-emitting part 100 is located.

[0205] In some embodiments, the first light-emitting control transistor T8 is located on a side of the compensation transistor T3 away from the driving transistor T2, and the first light-emitting control transistor T8 and the overlapping line segment 611 are partially overlapped in the thickness direction of the display panel.

[0206] Wherein, in the first light-emitting control transistor T8, the first light-emitting control active part T8A and the overlapping line segment 611 are partially non-overlapped in the thickness direction of the display panel, and the first light-emitting control gate T8G and the overlapping line segment 611 are partially overlapped in the thickness direction of the display panel.

[0207] In some embodiments, the second light-emitting control transistor T9 is located on a side of the first reset transistor T4 away from the driving transistor T2, and the second light-emitting control transistor T9 and the overlapping line segment 611 are partially overlapped in the thickness direction of the display panel.

[0208] Among them, in the second light-emitting control transistor T9, the second light-emitting control active part T9A partially overlaps with the overlapping line segment 611 in the thickness direction of the display panel, and the second light-emitting control gate T9G partially overlaps with the overlapping line segment 611 in the thickness direction of the display panel.

[0209] In some embodiments, the second reset transistor T5 does not partially overlap with the overlapping line segment 611 in the thickness direction of the display panel, and the third reset transistor T6 does not partially overlap with the overlapping line segment 611 in the thickness direction of the display panel.

[0210] Among them, in the second reset transistor T5, both the second reset active part T5A and the second reset gate T5G do not overlap with the overlapping line segment 611 in the thickness direction of the display panel; in the third reset transistor T6, both the third reset active part T6A and the third reset gate T6G do not overlap with the overlapping line segment 611 in the thickness direction of the display panel.

[0211] In some embodiments, the switch reset transistor T7 is disposed adjacent to the switch transistor T1 along the first direction X, and the switch reset transistor T7 partially overlaps with the overlapping line segment 611 in the thickness direction of the display panel.

[0212] Among them, in the switch reset transistor T7, the switch reset active part T7A partially overlaps with the overlapping line segment 611 in the thickness direction of the display panel, and the switch reset gate T7G partially overlaps with the overlapping line segment 611 in the thickness direction of the display panel.

[0213] Further, in some embodiments, please refer to ​, the overlapping line segment 611 includes a first side 6111 and a second side 6112 that are oppositely arranged along the first direction X. In at least a part of the overlapping line segment 611 of the second power supply signal line 61, both the first side 6111 and the second side 6112 are parallel to the second direction Y. For example, in the second power supply signal line 61 adjacent to the first data signal line DATA1, the first side 6111 of the overlapping line segment 611 is parallel to the second direction Y, and a part of the second side 6112 is parallel to the second direction Y; in the second power supply signal line 61 adjacent to the second data signal line DATA2, the first side 6111 of the overlapping line segment 611 is parallel to the second direction Y, and the second side 6112 is parallel to the second direction Y; in the second power supply signal line 61 adjacent to the third data signal line DATA3, the first side 6111 of the overlapping line segment 611 is parallel to the second direction Y, and the second side 6112 is parallel to the second direction Y.

[0214] In summary, in the embodiment of the present application, by increasing the width of the overlapping line segment 611 in the second power supply signal line 61, the coverage range of the overlapping line segment 611 in the area corresponding to the bottom surface 1001 of the light emitting part 100 can be increased, the film layer flatness at the position where the light emitting part 100 is located can be improved, and further the film thickness uniformity of the light emitting part 100 can be effectively improved, and the light emitting effect and light emitting efficiency of the display panel are improved.

[0215] For the above object of the present application, an embodiment of the present application further provides a display device, and the display device includes the display panel in the above embodiment.

[0216] It can be understood that since the display device has the same display panel as in the above embodiment, therefore, the display device has the same beneficial effects as the display panel, and will not be described in detail herein.

[0217] In the description of the present application, the terms "first" and "second" are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more features. In the description of the present application, "a plurality" means two or more, unless otherwise specifically defined.

[0218] In the above embodiments, the descriptions of the respective embodiments have their own emphases. For the parts not detailed in a certain embodiment, reference may be made to the relevant descriptions of other embodiments.

[0219] The embodiments, implementation manners and related technical features of the present application can be combined and replaced with each other without conflict.

[0220] The above are only the preferred embodiments of the present application, and do not impose any form of limitation on the present application. However, any simple modification, equivalent change and modification made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application still fall within the scope of the technical solution of the present application.

Claims

1. A display panel, characterized in that, The display panel includes a plurality of pixel driving circuits arranged in a first direction and a second direction, the first direction and the second direction intersecting, and the pixel driving circuit includes a switching transistor and a first capacitor connected to a first node, and a node connection line connected between the switching transistor and the first capacitor; The display panel further includes a data signal line extending in the second direction and a first reset signal auxiliary line extending in the second direction; Wherein, the first reset signal auxiliary line partially overlaps with the node connection line in the thickness direction of the display panel, and the minimum distance from the node connection line to the data signal line in the first direction is greater than or equal to the minimum distance from the first reset signal auxiliary line to the data signal line in the first direction.

2. The display panel according to claim 1, wherein The first reset signal auxiliary line includes a first line segment and a second line segment connected to each other, and the minimum distance from the first line segment to the data signal line in the first direction is greater than the minimum distance from the second line segment to the data signal line in the first direction.

3. The display panel according to claim 2, wherein The display panel further includes: A substrate; A semiconductor layer disposed on one side of the substrate, the semiconductor layer including a switching active portion of the switching transistor, the data signal line being located on one side of a plurality of the pixel driving circuits arranged in the second direction and connected to the switching active portion in the pixel driving circuit; A first conductive layer disposed on a side of the semiconductor layer away from the substrate, the first conductive layer including the node connection line; A second conductive layer disposed on a side of the first conductive layer away from the semiconductor layer, the second conductive layer including the data signal line and the first reset signal auxiliary line, the node connection line and the second line segment having an overlapping portion in the thickness direction of the display panel, and the minimum distance from the overlapping portion to the data signal line in the first direction being greater than or equal to the minimum distance from the second line segment to the data signal line in the first direction.

4. The display panel according to claim 3, characterized in that, The display panel further includes: A first gate layer disposed between the semiconductor layer and the first conductive layer, the first gate layer including a first electrode plate of the first capacitor; A second gate layer disposed between the first gate layer and the first conductive layer, the second gate layer including a second electrode plate of the first capacitor, the first electrode plate and the second electrode plate being disposed opposite to each other; Wherein, the node connection line is connected to the second electrode plate, and the minimum distance from the second electrode plate to the data signal line in the first direction is greater than or equal to the minimum distance from the second line segment to the data signal line in the first direction.

5. The display panel according to claim 4, characterized in that, The first conductive layer further includes a first power supply signal line extending in the first direction, the first power supply signal line including a plurality of first sub - portions arranged in the first direction, and the first sub - portions extending in the second direction; For the same pixel driving circuit, the orthographic projection of the first sub - part on the substrate is located between the orthographic projection of the node connection line on the substrate and the orthographic projection of the data signal line on the substrate, and the first sub - part and the node connection line overlap at least partially in the first direction.

6. The display panel according to claim 5, wherein A plurality of the first sub - parts arranged in the first direction are correspondingly arranged with a plurality of pixel driving circuits arranged in the first direction, and a plurality of the data signal lines are correspondingly connected to the plurality of pixel driving circuits arranged in the first direction; For the same pixel driving circuit, the minimum distance between the second electrode plate and the data signal line in the first direction is greater than or equal to the minimum distance between the first sub - part and the data signal line in the first direction.

7. The display panel according to claim 5, wherein The pixel driving circuit further includes a second capacitor connected to the first node, and the node connection line is further connected between the switching transistor and the second capacitor; For the same pixel driving circuit, the first power signal line is located on the side of the second capacitor away from the switching transistor, the first sub - part and the first capacitor overlap partially in the thickness direction of the display panel, and the first sub - part and the second capacitor overlap partially in the thickness direction of the display panel.

8. The display panel according to claim 7, wherein, The first power signal line further includes a second sub - part connected between two adjacent first sub - parts, the second sub - part is located on the side of the node connection line away from the switching transistor, the second sub - part and the first capacitor overlap partially in the thickness direction of the display panel, and the second sub - part and the second capacitor do not overlap in the thickness direction of the display panel.

9. The display panel according to claim 7, wherein, The first gate layer includes the third electrode plate of the second capacitor, the second gate layer includes the fourth electrode plate of the second capacitor, the third electrode plate and the fourth electrode plate are arranged opposite to each other, and the node connection line is connected to the third electrode plate; The second gate layer further includes a plate connection line connected to the fourth electrode plate, at least part of the plate connection line extends in the second direction and is located between two second electrode plates in two adjacent pixel driving circuits arranged in the first direction, and the plate connection line and the data signal line do not overlap at least partially in the thickness direction of the display panel.

10. The display panel according to claim 9, wherein For the same pixel driving circuit, the center of the plate connection line extending in the second direction is located on one side of the center of the data signal line, and the center of the first sub - part is located on the opposite side of the center of the data signal line.

11. The display panel according to any one of claims 3 to 10, characterized in that, The pixel driving circuit further includes a switch reset transistor connected to the first node, the semiconductor layer includes the switch reset active part of the switch reset transistor, the switch reset active part is electrically connected to the first reset signal auxiliary line, and the switch reset active part and the switch active part are arranged adjacent to each other in the first direction and connected to the first node; The first reset signal auxiliary line is located on one side of a plurality of pixel driving circuits arranged in the second direction and is electrically connected to the switch reset active part in the pixel driving circuit.

12. The display panel according to claim 11, wherein, The switch active part includes a first connection sub - part and a second connection sub - part arranged along the first direction, and a third connection sub - part extending along the first direction and connecting between the first connection sub - part and the second connection sub - part. Both the first connection sub - part and the second connection sub - part extend along the second direction; The switch reset active part includes a fourth connection sub - part and a fifth connection sub - part arranged along the first direction, and a sixth connection sub - part extending along the first direction and connecting between the fourth connection sub - part and the fifth connection sub - part. Both the fourth connection sub - part and the fifth connection sub - part extend along the second direction; Wherein, there is a first distance along the first direction between the first connection sub - part and the second connection sub - part, and a second distance along the first direction between the fourth connection sub - part and the fifth connection sub - part, and the first distance is greater than or equal to the second distance.

13. The display panel according to any one of claims 3 to 10, characterized in that, The display panel further includes a plurality of light - emitting parts arranged along the first direction and the second direction. The first conductive layer further includes a second power signal line extending along the second direction, and a plurality of the light - emitting parts arranged along the second direction are located on one side of the corresponding second power signal line; Wherein, the second power signal line includes overlapping line segments, the light - emitting part includes a bottom surface on the side close to the second power signal line, the overlapping line segments overlap with the bottom surface of the light - emitting part along the thickness direction of the display panel, and the ratio of the orthographic projection area of the overlapping line segments on the substrate to the orthographic projection area of the bottom surface of the light - emitting part on the substrate is greater than or equal to 0.

5.

14. The display panel according to claim 2, characterized in that, The first line segment is parallel to the data signal line. The second line segment includes an intermediate sub - part and a connection sub - part connecting between the intermediate sub - part and the first line segment. The intermediate sub - part is parallel to the data signal line, and the extending direction of the connection sub - part intersects with the data signal line.

15. A display device, characterized in that, The display device includes the display panel according to any one of claims 1 to 14.

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