Method and electronic device with parallel single-stage switching

Abstract

An electronic apparatus includes a plurality of processor device-memory device groups, and each of the plurality of processor device-memory device groups includes a plurality of memory devices, each of the plurality of memory devices including one or more memories, a plurality of processor devices, and a plurality of switches, the plurality of processor devices each include one or more processors. Each of the plurality of switches includes a plurality of ports. Each of a plurality of first memory devices included in a first processor device-memory device group of the plurality of processor device-memory device groups is connected to a first subset of ports of one of a plurality of first switches included in the first processor device-memory device group, and to a first subset of ports of one switch of a plurality of second switches of the plurality of switches included in a second processor device-memory device group of the plurality of processor device-memory device groups.

Description

Technical Field

[0001] The following description relates to methods and electronic devices with parallel single-stage switching. Background Art

[0002] As the complexity of operations implemented by large-scale computer systems increases, information exchange is frequently performed between processor devices and / or memory devices. In a data center or supercomputer, for example, approximately 100 to 400 processor devices may be installed in a typical rack. Summary of the Invention

[0003] Solution to the Problem

[0004] The present Summary of the Invention is provided to introduce, in a simplified form, a selection of concepts that will be further described in the Detailed Description below. The present Summary of the Invention is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to assist in determining the scope of the claimed subject matter.

[0005] In one or more general aspects, an electronic device includes: a plurality of processor device-memory device groups, and each of the plurality of processor device-memory device groups includes a plurality of memory devices, a plurality of processor devices, and a plurality of switches, the plurality of memory devices each include one or more memories, and the plurality of processor devices each include one or more processors. Each of the plurality of switches includes a plurality of ports. Each of the plurality of first memory devices included in the first processor device-memory device group among the plurality of processor device-memory device groups is connected to a first subset of ports of one switch among the plurality of first switches included in the first processor device-memory device group, and is connected to a first subset of ports of one switch among the plurality of second switches included in the second processor device-memory device group among the plurality of processor device-memory device groups.

[0006] The plurality of first memory devices may be connected to the first switch among the plurality of first switches and the first switch among the plurality of second switches.

[0007] The first processor device-memory device group and the second processor device-memory device group may be arranged to be physically closest to each other.

[0008] The first processor device-memory device group and the second processor device-memory device group may not be physically closest to each other, but may be logically closest to each other.

[0009] The first processor device-memory device group and the second processor device-memory device group may be arranged to send electrical signals to each other.

[0010] In each of the plurality of processor device - memory device groups, an equal number of connections may exist between the corresponding plurality of memory devices and the corresponding plurality of switches.

[0011] Any one of the plurality of switches may not be connected to another one of the plurality of switches.

[0012] The number of the plurality of memory devices in any one of the plurality of processor device - memory device groups may be determined based on the following condition: the product between the number of the plurality of processor device - memory device groups, the number of switches in the corresponding processor device - memory device group in the plurality of processor device - memory device groups, and the number of the plurality of ports of the plurality of switches in the corresponding processor device - memory device group does not exceed the product between the number of the plurality of switches in the corresponding processor device - memory device group and the number of a subset of ports connected to the corresponding plurality of memory devices in the corresponding processor device - memory device group.

[0013] The number of the plurality of memory devices in each of the plurality of processor device - memory device groups may be equal.

[0014] The number of the plurality of switches in each of the plurality of processor device - memory device groups is equal.

[0015] A second subset of ports of one switch among the plurality of first switches may be connected to the corresponding processor device among the plurality of processor devices.

[0016] The number of the plurality of processor devices may be less than or equal to a value obtained by dividing the difference between the total number of ports of the plurality of switches and the total number of ports of the plurality of memory devices by the number of ports of a processor device among the plurality of processor devices.

[0017] The number of the plurality of processor devices may be a multiple of a predetermined integer.

[0018] Each of the plurality of switches may be a Compute Express Link (CXL) switch.

[0019] Each of the plurality of switches may be a single - stage switch.

[0020] Each of the plurality of processor devices may include a plurality of ports, and each of the plurality of first processor devices among the plurality of processor devices in the first processor device-memory device group may be connected to a second subset of the ports of one of the plurality of first switches and a second subset of the ports of one of the plurality of second switches included in the second processor device-memory device group.

[0021] The electronic device may be a storage device.

[0022] In another one or more general aspects, an electronic device includes: a plurality of processor device-memory device groups, and each of the plurality of processor device-memory device groups includes a plurality of memory devices, a plurality of processor devices, and a plurality of switches. The plurality of memory devices each include one or more memories, and the plurality of processor devices each include one or more processors. Each of the plurality of processor devices includes a plurality of ports, and each of the plurality of first processor devices in the first processor device-memory device group included in the plurality of processor device-memory device groups is connected to a first subset of a plurality of first switches included in the first processor device-memory device group and a first subset of the ports of one of the plurality of second switches included in the second processor device-memory device group among the plurality of processor device-memory device groups.

[0023] In another one or more general aspects, an electronic device includes: a plurality of memory device groups, and each of the plurality of memory device groups includes a plurality of memory devices and a plurality of switches. The plurality of memory devices each include one or more memories. Each of the plurality of memory devices includes a plurality of ports. Each of the first ones in the first memory device group included in the plurality of memory device groups is connected to a first subset of the ports of one of the plurality of first switches included in the first memory device group and a first subset of the ports of one of the plurality of second switches included in the second processor device-memory device group among the plurality of processor device-memory device groups.

[0024] The plurality of first memory devices may be connected to the first switch among the plurality of first switches and the first switch among the plurality of second switches.

[0025] In another or more general aspects, an electronic device includes: a plurality of groups of processor devices, and each of the plurality of groups of processor devices includes a plurality of processor devices and a plurality of switches, and each of the plurality of processor devices includes one or more processors. Each of the plurality of processor devices includes a plurality of ports, and each of the plurality of first processor devices included in a first group of processor devices among the plurality of groups of processor devices is connected to a first subset of a plurality of first switches among the plurality of switches included in the first group of processor devices, and is connected to a first subset of a switch among a plurality of second switches included in the plurality of second processor devices among the plurality of groups of processor devices.

[0026] In another or more general aspects, an electronic device includes: a plurality of groups of processor - memory devices, and each of the plurality of groups of processor - memory devices includes a plurality of memory devices, a plurality of processor devices, and a plurality of switches, each of the plurality of memory devices includes one or more memories, and each of the plurality of processor devices includes one or more processors. Each of the plurality of switches includes a plurality of ports. The plurality of memory devices in one of the plurality of groups of processor - memory devices are connected to a first subset of the ports of each of the plurality of switches in the one of the plurality of groups of processor - memory devices and another group of processor - memory devices.

[0027] The plurality of memory devices in the other group of processor - memory devices may be connected to a second subset of the ports of each of the plurality of switches in the other group of processor - memory devices and a third group of processor - memory devices.

[0028] The plurality of processor devices in the one group of processor - memory devices may be connected to a third subset of the ports of each of the plurality of switches in the one group of processor - memory devices and the other group of processor - memory devices.

[0029] Each of the plurality of groups of processor - memory devices may further include a plurality of network devices, and the plurality of network devices are connected to a fourth subset of the ports of each of the plurality of switches in the one group of processor - memory devices.

[0030] The electronic device may be a storage device.

[0031] Other features and aspects will be apparent from the following detailed description, the drawings, and the claims. Description of the Drawings

[0032] Figures 1 to 3 Shows an example of a concatenation structure between a switch and a device according to one or more embodiments.

[0033] Figures 4 to 7 Shows an example of a connection structure between multi-port devices according to one or more embodiments.

[0034] Figures 8 to 16 Shows an example of a connection structure of an electronic device according to one or more embodiments.

[0035] Figure 17 and Figure 20 Shows an example of implementing an electronic device according to one or more embodiments.

[0036] Figures 21 to 27 Shows an example of implementing an electronic device according to one or more embodiments.

[0037] Throughout the drawings and the detailed description, unless otherwise described or provided, the same reference numerals can be understood to represent the same or similar elements, features, and structures. The drawings may not be to scale, and for clarity, illustration, and convenience, the relative sizes, proportions, and depictions of elements in the drawings may be exaggerated. Detailed Description

[0038] The following detailed description is provided to assist the reader in obtaining a comprehensive understanding of the methods, devices, and / or systems described herein. However, various changes, modifications, and equivalents of the methods, devices, and / or systems described herein will be apparent after understanding the disclosure of this application. For example, the order of operations within and / or the order of operations described herein are merely examples and are not limited to the order set forth herein, but may be changed as will be apparent after understanding the disclosure of this application, except for the order of operations within and / or the order of operations where at least a portion must occur in a particular order (e.g., a specific order). As another example, the order of operations and / or the order of operations within may be performed in parallel, except where at least a portion of the order of operations and / or the order of operations within must occur in sequence (e.g., a specific sequence). Additionally, for increased clarity and conciseness, descriptions of features known after understanding the disclosure of this application may be omitted.

[0039] The features described herein can be implemented in different forms and should not be construed as limited to the examples described herein. Instead, the examples described herein are provided only to illustrate some of the many possible ways of implementing the methods, apparatuses, and / or systems described herein, which will be apparent after understanding the disclosure of the present application. The use of the term "may" with respect to an example or embodiment herein (e.g., what may be included or implemented with respect to the example or embodiment) means that there is at least one example or embodiment that includes or implements such a feature, while all examples are not so limited.

[0040] Throughout the specification, when a component or element is described as "on", "connected to", "coupled to", or "joined to" another component, element, or layer, it can be directly "on", "connected to", "coupled to", or "joined to" another component, element, or layer (e.g., in contact with another component or element), or one or more other components, elements, layers can reasonably exist therebetween. When a component or element is described as "directly on", "directly connected to", "directly coupled to", or "directly joined to" another component or element, no other element can exist therebetween. Similarly, expressions such as "between" and "immediately between" and "adjacent to" and "immediately adjacent to" can also be interpreted as described above.

[0041] Although terms such as "first", "second", and "third" or A, B, (a), (b), etc. may be used herein to describe various members, components, regions, layers, or parts, these members, components, regions, layers, or parts are not limited by these terms. Each of these terms is not used to define, for example, the nature, order, or sequence of the corresponding member, component, region, layer, or part, but is only used to distinguish the corresponding member, component, region, layer, or part from other members, components, regions, layers, or parts. Thus, the first member, first component, first region, first layer, or first part referred to in the examples described herein may also be referred to as the second member, second component, second region, second layer, or second part without departing from the teachings of the examples.

[0042] The terms used herein are for describing various examples only and are not intended to limit the disclosure. Unless the context clearly indicates otherwise, the singular forms are also intended to include the plural forms. As a non-limiting example, the terms "comprising", "including", and "having" specify the presence of stated features, quantities, operations, components, elements, and / or combinations thereof, but do not preclude the presence or addition of one or more other features, quantities, operations, components, elements, and / or combinations thereof, or the alternative presence of alternative stated features, quantities, operations, components, elements, and / or combinations thereof. Further, while one embodiment may state that the terms "comprising", "including", and "having" specify the presence of stated features, quantities, operations, components, elements, and / or combinations thereof, there may be other embodiments in which one or more of the stated features, quantities, operations, components, elements, and / or combinations thereof do not exist.

[0043] As used herein, the term "and / or" includes any one of the associated listed items and any combination of any two or more thereof. Phrases such as "at least one of A, B, and C", "at least one of A, B, or C", etc. are intended to have a disjunctive meaning, and unless the corresponding description and examples require such a list (e.g., "at least one of A, B, and C") to be interpreted as having a disjunctive meaning, these phrases "at least one of A, B, and C", "at least one of A, B, or C", etc. also include examples where there may be one or more of each of A, B, and / or C (e.g., any combination of one or more of each of A, B, and C).

[0044] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains in the context of understanding the disclosure of this application. Unless explicitly defined as such herein, terms (such as those defined in a common dictionary) will be interpreted as having a meaning consistent with their meaning in the context of the relevant art and specifically in the context of the disclosure of this application, and should not be interpreted in an idealized or overly formal sense.

[0045] Figures 1 to 3 An example of a connection structure between a switch and another device according to one or more embodiments is shown.

[0046] Accordingly, it is found that an efficient management technique for high-density computing resources is expected to improve the rack-scale computing infrastructure. A disaggregated memory pool can be configured on a rack-by-rack basis using Compute Express Link (CXL). The disaggregated memory pool can be implemented as a memory box using a CXL switch. When a CXL switch is used, the connections between the devices (such as switches, memory devices, processor devices, network devices, etc.) included in the electronic device 100 can be re-established. In the examples disclosed herein, the memory box can also be referred to as a storage device. In addition, each of the switch, the memory device, the processor device, and the network device can also be considered an electronic device individually or as any combination of them.

[0047] Referring to Figure 1 , the electronic device 100 can include a switch 110, a memory device 120, a processor device 130, and a network device 140. In one example, the memory device 120, the processor device 130, and the network device 140 can be connected to each other through the switch 110. Regarding Figure 1 , the illustrated memory device 120 represents a plurality of memory devices 120 having corresponding connections as discussed herein, the processor device 130 represents a plurality of processor devices 130 having corresponding connections as discussed herein, and the network device 140 represents a plurality of processor devices 130 having corresponding connections as discussed herein. Therefore, the respective references to the memory device 120, the processor device 130, and the network device 140 are for convenience of description only, and the examples are not limited thereto. Each of the processor devices 130 can be an xPU device (such as a central processing unit (CPU), a graphics processing unit (GPU), and a neural processing unit (NPU) that performs operations dedicated to artificial intelligence (AI), etc.), where each of the xPU devices can itself include a plurality of processors or processor cores.

[0048] The switch 110 can be configured to connect the devices (such as the memory device 120, the processor device 130, the network device 140, etc.) included in the electronic device 100 to each other. The switch 110 can include K ports corresponding to a link composed of L lanes. The total number M of the channels of the switch 110 can be determined as L×K. In a non-limiting example, in the examples of M = 144 and M = 256, a 144-channel switch can include 18 ports based on an 8-channel link, and a 256-channel switch can include 32 ports based on an 8-channel link. The specific values of M, K, and L are not limited to the above examples, and for convenience of description, the operation of the electronic device 100 will be described based on the example of M = 144, L = 8, and K = 16.

[0049] The memory device 120 is a device capable of storing data and / or signals, and may include a non-volatile memory device (e.g., a solid-state drive (SSD), etc.) and / or a volatile memory (e.g., a dynamic random access memory (DRAM), etc.). For example, the memory device 120 may be a CXL memory device that inputs data and / or outputs data according to CXL, but is not limited to the above examples.

[0050] The processor device 130 is a device capable of performing operations, and may include various computing resources (e.g., a central processing unit (CPU) that performs general operations, a graphics processing unit (GPU) that performs operations dedicated to image processing, and a neural processing unit (NPU) that performs operations dedicated to artificial intelligence (AI), etc.).

[0051] The network device 140 is a device for communicating between electronic devices on a computer network to mediate data transmission (e.g., an external device of the electronic device 100). The network device 140 may include, for example, a network interface controller (NIC). For example, the network device 140 may be connected to a global network that is an external scalable network, a storage network that can be scaled as a storage device, and a management network that can be scaled for management purposes.

[0052] In Figure 1 the example, the switch 110 may be connected to two memory devices 120, fifteen processor devices 130, and the network device 140 through 18 ports. In a non-limiting example, the switch 110 may have 1 uplink and 17 downlinks. In an example of the CXL protocol where the maximum capacity of the multi-logical device (MLD) proposed in the CXL protocol is 16, connecting one memory device to 16 processor devices can maximize the number of processor devices that can be connected to one memory device. However, when the processor devices are configured in multiples of 3 based on the structure of Open Rack v3 of the opencompute project (OCP), fifteen processor devices 130 and two memory devices 120 can be connected to the switch 110. In one example, fifteen processor devices 130 and two memory devices 120 may be grouped into a processor device - memory device group.

[0053] Figure 2Depicts an example of an electronic device 200 in which a processor device - memory device group includes 15 processor devices and 2 memory devices extended to a rack size. The electronic device 200 may have a 1U 3 - node structure 230, and the 1U 3 - node structure 230 includes a memory box 210 with a size of 2U and a processor box 220 with 45 nodes. The memory box 210 with a size of 2U includes 12 memory devices, and the processor box 220 with 45 nodes has a size of 15U and includes a total of 90 processing devices. In Figure 2 's example, the electronic device 200 can connect a total of 90 processor devices at a 17U scale (i.e., through the 15U processor box 220), but the number of connectable memory devices for each processor device is fixed at 2 and the number of connectable processor devices for each memory device is fixed at 15. The 1U 3 - node structure 230 shows a 1U configuration for each of the 15U of the processor box 220, including two shaded boxes in each of the three nodes representing a total of 6 processor devices (i.e., two processor devices are installed in each node). In other words, the electronic device 200 may include a total of 6 switches and 90 processor devices. In this example, the processor box may also be referred to as an operating device or be included in an operating device.

[0054] In Figure 3 's example, the memory box 310 may include a total of 6 switches 310a to 310f and 12 memory devices 311a to 311l, and can connect up to 90 processor devices 320. However, in this example, the number of connectable memory devices for each processor device may still be fixed at 2, and the number of connectable processor devices for each memory box may still be fixed at 15. Hereinafter, a structure that can effectively increase the number of connectable memory devices for each processor device and the number of connectable processor devices for each memory device will be described in further detail.

[0055] Figures 4 to 7 Shows an example of a connection structure between multi - port devices according to one or more embodiments.

[0056] In Figure 4 's example, the processor device - memory device group 440 may include a plurality of processor devices 410, a plurality of switches 420, and a plurality of memory devices 430.

[0057] Each of the plurality of processor devices 410 may have P X ports. When the number of ports P X is 2 or more, each of the plurality of processor devices 410 includes a multi - port. The number of the plurality of processor devices 410 may be represented as N X, where N is a positive integer. As discussed above, Figure 4 the xPU shown in Figure 4 can represent one or more processors or processor cores.

[0058] Each of the multiple switches 420 may have K ports, where K = K X + K M , where K X represents the switch ports connected to the processor device, and K M represents the switch ports connected to the memory device. Each of the multiple switches 420 may be a CXL switch or may be included in a CXL switch. Each of the multiple switches 420 may be a single-stage switch or may be included in a single-stage switch. The number of the multiple switches 420 may be represented as N S .

[0059] Each of the multiple memory devices 430 may have P M ports. When the number of P M ports is 2 or more, each of the multiple memory devices 430 may include multi-ports. Thus, the number of the multiple memory devices 430 may be represented as N M .

[0060] The memory box structure for maximizing the performance of rack-scale high-density computing resources will be further described in detail in examples based on a single-port processor device - multi-port memory device, multi-port processor device - single-port memory device, or multi-port processor device - multi-port memory device.

[0061] Due to the limitation that the number of devices that can be connected to a switch with K ports is K, an increase in the memory device expansion gain of the processor device may lead to a decrease in the multi-user gain of the memory device, and an increase in the multi-user gain of the memory device may lead to a decrease in the memory device expansion gain of the processor device. The memory device expansion gain of the processor device and the multi-user gain of the memory device can be effectively improved by using multi-port devices (e.g., multi-port memory devices and / or multi-port processor devices). Here, the memory device expansion gain may indicate the number of devices that a processor device can be connected to, and the multi-user gain may be a multiple access gain or a multiplexing gain, and may indicate the number of devices that a memory device can accommodate.

[0062] When a processor device-memory device group (e.g., processor device-memory device group 440) including a multi-port device (e.g., a multi-port memory device and / or a multi-port processor device) is formed, the connection is physically feasible only when sufficient ports are available for processor device-switch-memory device connections.

[0063] For example, the minimum requirements for a physical connection of a processor device-switch-memory device can be as follows: where N X represents the number of processor devices, N S represents the number of switches, N M represents the number of memory devices, P X represents the number of ports of the processor device, K represents the number of ports of the switch, and K X represents the number of ports among the switch ports allocated to the processor device, K M represents the number of ports among the switch ports allocated to the memory device, and P M represents the number of ports of the memory device.

[0064] The total number of ports of the multiple processor devices 410 in the processor device-memory device group 440 can satisfy N X ×P X <N S ×K X .

[0065] The total number of ports of the multiple switches 420 in the processor device-memory device group 440 can satisfy K X +K M <K.

[0066] The total number of ports of the multiple memory devices 430 in the processor device-memory device group 440 can satisfy N M ×P M <N S ×K M .

[0067] In Figure 5 , the electronic device 500 may include a total of 6 switches 514a, 514b, 524a, 524b, 534a, 534b, 12 memory devices 512a to 512d, 522a to 522d, 532a to 532d, 48 processor devices, and 12 network devices 516a to 516d, 526a to 526d, 536a to 536d. In Figure 5In a non - limiting example, each of the twelve memory devices 512a to 512d, 522a to 522d, 532a to 532d may include four ports, each of the six switches 514a, 514b, 524a, 524b, 534a, 534b may include eighteen ports, and each processor device and network device may include a single port. For ease of reference Figure 5 The description of the connections between the processor devices and the memory devices and the switches may be partially or completely omitted. Figure 5 The number of switches 514a, 514b, 524a, 524b, 534a, 534b, memory devices 512a to 512d, 522a to 522d, 532a to 532d, processor devices and network devices 516a to 516d, 526a to 526d, 536a to 536d shown in is for ease of description and is not limited to the above examples.

[0068] The electronic device 500 may be grouped into different processor - memory device groups (e.g., processor - memory device group 1 510, processor - memory device group 2 520, and processor - memory device group 3 530), and each of the processor - memory device groups 510 to 530 may include two of the switches 514a, 514b, 524a, 524b, 534a, 534b, four of the memory devices 512a to 512d, 522a to 522d, 532a to 532d, and sixteen of the forty - eight processor devices.

[0069] For example, the size of a processor - memory device group configured with N S K - port switches can be determined using Expression 1.

[0070] Expression 1:

[0071] N S ×(K X +K M )≤N S ×K

[0072] Using the above Expression 1, Expression 2 can be used to determine the number N X .

[0073] Expression 2:

[0074] N X ×P X +N M ×P M ≤N S ×(K X +KM ) ≤ N S × K

[0075] N X ≤ (N S × K - N M × P M ) / P X

[0076] When P M = 1 and P X = 1 (for example, in the case of "single - port memory device - single - port processor device"), N X becomes maximum, and the following Expression 3 can be obtained. In this case, the number N of processor devices X can be a multiple of a predetermined number. For example, according to the Open Rack v3 structure, the condition that the number N of processor devices X is a multiple of 3 can be applied to Expression 2 to obtain Expression 3.

[0077] Expression 3:

[0078] N X ≤ (N S × K - N M )

[0079] When P M > 1, P X = 1 (for example, in the case of "multi - port memory device - single - port processor device"), N X is simplified to the form of subtraction in the following Expression 4.

[0080] Expression 4:

[0081] N X ≤ (N S × K - N M × P M )

[0082] Conversely, when P M = 1, P X > 1 (for example, in the case of "single - port memory device - multi - port processor device"), N X is simplified to the form of division in the following Expression 5.

[0083] Expression 5:

[0084] N X ≤ (N S × K - N M ) / P X

[0085] In summary, when compared with a "single-port memory device - multi-port processor device", a "multi-port memory device - single-port processor device" may be advantageous in maintaining a large-scale computing resource that each memory device can be shared. Therefore, the electronic device 500 can be configured to maximize the rack-scale high-density computing resource performance when it is feasible to provide both the memory device expansion gain of the processor device and the multi-user gain of the memory device.

[0086] When the numbers of switches, memory devices, processor devices, and network devices included in the electronic device 500 are known or determined, a routing method for processor device - switch - memory device connection can be easily determined. This routing method can be reflected in the memory device cartridge structure based on the resource granularity that affects routing complexity and the path diversity that affects the memory device expansion gain and multi-user gain.

[0087] To effectively connect a predetermined number of multi-port devices (e.g., multi-port memory devices and / or multi-port processor devices) to a predetermined number of K-port switches, there may be routing paths with partial overlap between processor device - memory device groups and routing paths that surround the edge of the memory cartridge. The routing paths in the processor device - memory device groups can be determined such that the memory devices and processor devices in the processor device - memory device groups are effectively load-balanced for the switches.

[0088] In Figure 5 the example, partial overlap may occur between adjacent processor device - memory device groups (such as between processor device - memory device group 1 (510) and processor device - memory device group 2 (520), and between processor device - memory device group 2 (520) and processor device - memory device group 3 (530)). For example, based on processor device - memory device group 1 (530), partial overlap 540 may occur in processor device - memory device group 2 (520) that is physically closest to processor device - memory device group 1 (530).

[0089] Processor device - memory device group 1 (510) and processor device - memory device group 3 (530) may be logically adjacent to each other even if not physically closest to each other, and a wraparound routing path may occur between the two processor device - memory device groups. For example, based on processor device - memory device group 3 (530), a wraparound routing path 550 may occur in processor device - memory device group 1 (510) that is not physically closest to but logically adjacent to processor device - memory device group 3 (530). Processor device - memory device group 1 (510) and processor device - memory device group 3 (530) may be processor device - memory device groups disposed at the outer edge of the electronic device 500. In one example, there may be a condition that processor device - memory device groups connected by a wraparound routing path need to be set within a physical distance to transmit an electrical signal.

[0090] In addition to the connections within the same processor device - memory device group based on the above - mentioned routing path, both the memory device expansion gain of the processor device and the multi - user gain of the memory device can be obtained through the connections between other processor device - memory device groups. The traffic distribution efficiency between switches can also be obtained through multiple replicated routing paths.

[0091] Assuming there is no limit on the physical reach distance of the electrical wiring within the electronic device 500, a total of 6 switches can be used to connect a total of 12 memory devices in one memory box, and the switches and memory devices can be grouped into a total of 3 processor device - memory device groups.

[0092] According to another embodiment, in addition to the above - mentioned routing method, any one of ordered group routing, stochastic routing, and round - robin routing can be applied. Ordered group routing is a routing technique that performs regular ordered routing connections to adjust resource granularity and make resource partitioning easier, which can lead to low implementation complexity. Stochastic routing is a routing technique that performs irregular routing connections for easier load balancing to effectively allocate system performance limitations by maximizing path diversity, which can lead to relatively high implementation complexity. Round - robin routing is a routing technique that performs sequential routing connections to limit routing complexity and ensure load balancing like stochastic routing, which can lead to relatively low implementation complexity and balanced allocation effects.

[0093] In Figure 6In [the figure], the electronic device 600 may include a total of six switches 614a, 614b, 624a, 624b, 634a, 634b, twelve memory devices 612a to 612d, 622a to 622d, 632a to 632d, forty-eight processor devices 618a to 618r, 628a to 628r, 636a to 636r, and twelve network devices 616a to 616d, 626a to 626d, 636a to 636d. In Figure 6 the example of [the figure], each of the memory devices 612a to 612d, 622a to 622d, 632a to 632d may include four ports, each of the switches 614a, 614b, 624a, 624b, 634a, 634b may include eighteen ports, and each of the processor devices 618a to 618r, 628a to 628r, 636a to 636r and the network devices 616a to 616d, 626a to 626d, 636a to 636d may include a single port. Figure 6 The routing paths among the switches 614a, 614b, 624a, 624b, 634a, 634b, the memory devices 612a to 612d, 622a to 622d, 632a to 632d, and the network devices 616a to 616d, 626a to 626d, 636a to 636d depicted in [the figure] may be determined based on the routing method described above with reference to Figure 5 The switches 614a, 614b, 624a, 624b, 634a, 634b, the memory devices 612a to 612d, 622a to 622d, 632a to 632d, the processor devices 618a to 618r, 628a to 628r, 636a to 636r, and the network devices 616a to 616d, 626a to 626d, 636a to 636d included in the electronic device 600 may be grouped into three processor device - memory device groups 610 to 630. For ease of reference in Figure 6 the description, some of the processor devices may be omitted, and Figure 6 the number of the switches 614a, 614b, 624a, 624b, 634a, 634b, the memory devices 612a to 612d, 622a to 622d, 632a to 632d, the processor devices 618a to 618r, 628a to 628r, 636a to 636r, and the network devices 616a to 616d, 626a to 626d, 636a to 636d shown in [the figure] is only for ease of description and is not limited to the above example.

[0094] The electronic device 600 has a 1U 3-node structure and can be a 10U-scale rack including a 2U memory box and an 8U processor box. The 2U memory box can include 12 memory devices (e.g., memory devices 612a to 612d, 622a to 622d, 632a to 632d), and the 8U processor box can include 48 processor devices (e.g., processor devices 618a to 618r, 628a to 628r, 636a to 636r).

[0095] Memory devices in the same processor device-memory device group (e.g., memory devices 612a to 612d) can be similarly connected to switches (e.g., switches 614a, 614b) in the same processor device-memory device group (e.g., processor device-memory device group 610). For example, each of the first memory devices (e.g., memory devices 612a to 612d) included in the processor device-memory device group 1 (610) can be connected to all the first switches (e.g., switches 614a, 614b) included in the processor device-memory device group 1 (610). Two of the four ports 614a1, 614a2, 614b1, 614b2 of each of the first memory devices (e.g., memory devices 612a to 612d) (e.g., ports 614a1, 614a2) can be connected to the first switches (e.g., switches 614a, 614b) included in the processor device-memory device group 1 (610), and the remaining two ports (e.g., ports 614b1, 614b2) can be used for a partially overlapping routing path. In other words, the remaining two ports (e.g., ports 614b1, 614b2) can be similarly connected to the second switches 624a, 624b of the adjacent processor device-memory device group 2 (620). For partially overlapping routing, the first memory devices 612a to 612d can be connected to some of the remaining switches 624a, 624b, 634a, 634b other than the first switches 614a, 614b. Two of the four ports 634a1, 634a2, 634b1, 634b2 of each of the third memory devices (e.g., memory devices 632a to 632d) in the processor device-memory device group 3 (630) (e.g., ports 634a1, 634b1) can be connected to the third switches 634a, 634b included in the processor device-memory device group 3 (630), and the remaining two ports (e.g., ports 634a2, 634b2) can be used for a loop routing path. In other words, the remaining two ports (e.g., ports 634a2, 634b2) can be similarly connected to the first switches 614a, 614b of the processor device-memory device group 1 (610) that are logically adjacent rather than physically adjacent.

[0096] Switches (e.g., switches 614a, 614b) in the same processor device - memory device group (e.g., processor device - memory device group 610) can similarly be connected to memory devices (e.g., memory devices 612a to 612d) in the same processor device - memory device group. For example, each of the first switches 614a, 614b included in the processor device - memory device group 1 (610) can be connected to all of the first memory devices 612a to 612d included in the processor device - memory device group 1 (610).

[0097] In an example where the processor device and the network device have a single port, the processor device and the network device can be connected to a switch in the same processor device - memory device group. At least some of the remaining ports among the multiple ports included in each of the multiple switches that are not connected to the memory device can be connected to a processor device included in the same processor device - memory device group.

[0098] Switches can be used to connect memory devices and processor devices. The switches may not be connected to each other, but can be used for management purposes when connecting the switches. In other words, signals for management purposes can be sent and received through the connection between the switches. For example, the switch can be a CXL switch.

[0099] The number of memory devices (e.g., memory devices 612a to 612d, 622a to 622d, or 632a to 632d) included in each of the processor device - memory device groups 610 to 630 can be the same. The number of switches (e.g., switches 614a, 614b, 624a, 624b, 634a or 634b) included in each of the processor device - memory device groups 610 to 630 can be the same. The number of processor devices (e.g., processor devices 618a to 618r, 628a to 628r, or 636a to 636r) included in each of the processor device - memory device groups 610 to 630 can be the same.

[0100] In Figure 6In the example, the electronic device 600 may include 12 four-port CXL memory devices (e.g., memory devices 612a to 612d, 622a to 622d, 632a to 632d), 48 processor devices (e.g., processor devices 618a to 618r, 628a to 628r, 636a to 636r), and 12 network devices (e.g., network devices 616a to 616d, 626a to 626d, 636a to 636d). Assuming that the CXL memory device has a storage capacity of 512 gigabytes (GB), a total of 6 terabytes (TB) of available 2U memory cartridges are provided, and as a high-density computing resource scale, connections to a total of 48 processor devices with a size of 10U may be feasible. The memory device expansion gain may allow each processor device to access 8 memory devices, and the multi-access gain may allow each memory device to access 32 processor devices.

[0101] In Figure 6 the example, the routing paths using multiple ports between the memory devices 612a to 612d, 622a to 622d, 632a to 632d and the switches 614a, 614b, 624a, 624b, 634a, 634b may be slightly complex. However, the routing paths using single ports between the processor devices 618a to 618r, 628a to 628r, 636a to 636r and the switches 614a, 614b, 624a, 624b, 634a, 634b may be relatively simple. Based on such connection structure characteristics, multiple processor devices 618a to 618r, 628a to 628r, 636a to 636r can be simply connected to a memory cartridge including multiple memory devices 612a to 612d, 622a to 622d, 632a to 632d and multiple switches 614a, 614b, 624a, 624b, 634a, 634b as shown in Figure 6 to easily provide the rack-scale electronic device 600.

[0102] Figure 7 shows an example of a routing path for describing a partial overlap between a processor device - memory device group. A memory device group n including N M memory devices with P M ports can be connected to P M switches. If P ov switches overlapping with the adjacent memory device group n + 1 on the path are allowed, then considering the partial overlap and the loop routing path, based on the condition N M,group × N M × P M < N S × K Mto minimize the number of switches for a total of N desired connections M，group among memory device groups.

[0103] Figures 8 to 16 FIG. 6 shows an example of a connection structure of an electronic device according to one or more embodiments.

[0104] Figure 8 FIG. 810 and rack 820 showing the connection structure of the electronic device in the case of "dual-port processor device, single-port memory device" are shown. For ease of reference Figure 8 in the description, some of the 42 processor devices may be omitted, and Figure 8 the number of switches, memory devices, processor devices, and network devices shown in FIG. 8 is only for ease of description and is not limited to the above example.

[0105] The electronic device may be configured as a 9U-scale rack including a 2U memory box and a 7U processor box. The electronic device can connect 42 processor devices on a 9U scale and can allow each processor device to access 4 memory devices, thereby increasing the expandable memory device capacity of each processor device.

[0106] In Figure 9 FIG. 8, in the case of "dual-port processor device, single-port memory device" described above with reference to Figure 8 FIG. 8, 14 processor devices, 2 memory devices, and 2 network devices can be connected to switch 910. The switch may include 18 ports composed of 8 channels and may have a total of 144 channels.

[0107] Figure 10 FIG. 1010 and rack 1020 showing the connection structure of the electronic device in the case of "quad-port processor device, single-port memory device" are shown. For ease of reference Figure 10 in the description, some of the 18 processor devices may be omitted, and Figure 10 the number of switches, memory devices, processor devices, and network devices shown in FIG. 10 is only for ease of description and is not limited to the above example.

[0108] The electronic device may be configured as a 5U-scale rack including a 2U memory box and a 3U processor box. The electronic device can connect 18 processor devices on a 5U scale and can allow each processor device to access 8 memory devices, thereby increasing the expandable memory device capacity of each processor device. However, the rack-scale high-density computing resources may be reduced due to the trade-off.

[0109] Referring to Figure 11 FIG. 10, in the above reference to Figure 10In the case of the described "four-port processor device, single-port memory device", 12 processor devices, 2 memory devices, and 2 network devices can be connected to switch 1110. The switch may include 18 ports consisting of 8 channels and may have a total of 144 channels.

[0110] When an electronic device is configured with a single-port processor device, a dual-port processor device, or a four-port processor device based on a single-port memory device, the rack scale and access coverage can be as shown in Table 1 below.

[0111] [Table 1]

[0112]

[0113] As the number of ports of the processor device increases, the number of accessible memory devices per processor device increases. Although one memory device can be shared and used by many processor devices, the rack-scale high-density computing resources can rapidly decrease. As the number of ports of the processor device increases, the number of accessible processor devices per memory device can decrease.

[0114] The relationship in which the computing resource scale decreases as the number of ports of the processor device increases can be the same as Expression 5.

[0115] Figure 12 Shows the connection structure 1210 and rack 1220 of the electronic device in the case of "single-port processor device, dual-port memory device". For ease of reference Figure 12 For description, some of the 72 processor devices can be omitted, and Figure 12 The numbers of switches, memory devices, processor devices, and network devices shown in are only for ease of description and are not limited to the above examples.

[0116] The electronic device can be configured as a 14U-scale rack including a 2U memory box and a 12U processor device box. The electronic device can connect 72 processor devices at a scale of 14U and can allow each processor device to access 4 memory devices, thereby increasing the expandable memory device capacity per processor device. In addition, the electronic device can allow each memory device to access 24 processor devices, and thus the multi-user gain of the memory device can increase.

[0117] Refer to Figure 13 In the above reference Figure 12In the case of the described "single-port processor device, dual-port memory device", 12 processor devices, 4 memory devices, and 2 network devices can be connected to switch 1310. The switch can include 18 ports consisting of 8 channels and a total of 144 channels.

[0118] Figure 14 Shows the connection structure 1410 and rack 1420 of an electronic device in the case of a "single-port processor device, four-port memory device". For ease of reference Figure 14 In the description, some of the 48 processor devices can be omitted, and Figure 14 The numbers of switches, memory devices, processor devices, and network devices shown are only for ease of description and are not limited to the above examples.

[0119] The electronic device can be configured as a 10U-scale rack including a 2U memory box and an 8U processor box. The electronic device can connect 48 processor devices on a 10U scale and allow each processor device to access 8 memory devices, thereby increasing the expandable memory device capacity of each processor device. In addition, the electronic device can allow each memory device to access 32 processor devices, and thus the multi-user gain of the memory device can be increased.

[0120] Refer to Figure 15 In the above reference Figure 13 In the case of the "single-port processor device, four-port memory device" described above, 8 processor devices, 8 memory devices, and 2 network devices can be connected to switch 1510. The switch can include 18 ports consisting of 8 channels and a total of 144 channels.

[0121] When the electronic device is configured with a single-port memory device, a dual-port memory device, or a four-port memory device based on a single-port processor device, the rack scale and access coverage can be as shown in Table 2 below.

[0122] [Table 2]

[0123]

[0124] As the number of ports of the memory device increases, the number of accessible memory devices per processor device increases. One memory device can be shared and used by many processor devices, but the rack-scale high-density computing resources can quickly decrease. As the number of ports of the memory device increases, the number of accessible processor devices per memory device can decrease.

[0125] The relationship in which the computing resource scale decreases as the number of ports of the memory device increases can be the same as Expression 4.

[0126] Figure 16 Shows the connection structure 1610 of the electronic device and the rack 1620 in the case of "four-port processor device, four-port memory device". For ease of reference Figure 16 For description, some of the 12 processor devices may be omitted, and Figure 16 The numbers of switches, memory devices, processor devices, and network devices shown in are only for ease of description and are not limited to the above examples.

[0127] The electronic device can be configured as a 4U-scale rack including a 2U memory box and a 2U processor box. The electronic device can connect 12 processor devices on a 4U scale, and the number of connectable memory devices for each processor device and the number of connectable processor devices for each memory device can be increased, but the overall operation scale per rack can be significantly reduced to the 4U level.

[0128] Figure 17 and Figure 20 Shows an example of implementing an electronic device according to one or more embodiments.

[0129] The drawings show an example of a product with a simple memory bundle (just bunch of memory, JBOM, or memory cluster, memory combination) structure of a memory box based on a CXL switch. Figure 17 Shows an example of a memory enclosure 1700 that can accommodate multiple memory devices according to one or more embodiments. Figure 18 Shows an example of a single-stage CXL switch 1800 according to one or more embodiments. Figure 19 Shows an example of a CXL memory device 1900 that displays multiple memories according to one or more embodiments. Figure 20 Shows an example of a CXL memory box 2000 including multiple memory devices and a switch according to one or more embodiments.

[0130] Figures 21 to 27 Shows an example of implementing an electronic device according to one or more embodiments.

[0131] The drawings show an example of a composable infrastructure product with a single CXL switch-based memory box structure. Figure 21 Shows an example of a 256-channel CXL switch 2100 according to one or more embodiments. Figure 22 Shows an example of a CXL memory box 2200 according to one or more embodiments. The devices other than the switch in the CXL memory box 2200 may have single ports and may all be connected to the switch.Figure 23 An example of a CXL memory 2300 with computing nodes according to one or more embodiments is shown. Figure 24 An example of a 2U 4-node server architecture 2400 according to one or more embodiments is shown. Figure 25 An example of a 1U 3-node server architecture 2500 according to one or more embodiments is shown. Figure 26 An example of a memory cartridge utilizing a composable architecture system 2600 according to one or more embodiments is shown. Figure 27 Another example of a memory cartridge utilizing a composable architecture system 2700 according to one or more embodiments is shown.

[0132] Included herein is with respect to Figures 1 to 27The described switches, processing devices, processors, processor cores, memory devices, memories, and network devices are implemented by or represent hardware components. As described above, or in addition to the above description, examples of hardware components that can be used to perform the operations described in this application include, where appropriate: controllers, sensors, generators, drivers, memories, comparators, arithmetic logic units, adders, subtractors, multipliers, dividers, integrators, and any other electronic components configured to perform the operations described in this application. In other examples, one or more of the hardware components that perform the operations described in this application are implemented by computing hardware (e.g., by one or more processors or computers). A processor or computer can be implemented by one or more processing elements (such as a logic gate array, a controller and an arithmetic logic unit, a digital signal processor, a microcomputer, a programmable logic controller, a field programmable gate array, a programmable logic array, a microprocessor, or any other device or combination of devices configured to respond and execute instructions in a defined manner to achieve a desired result). In one example, a processor or computer includes or is connected to one or more memories that store instructions or software executed by the processor or computer. The hardware components implemented by the processor or computer can execute instructions or software (such as an operating system (OS) and one or more software applications running on the OS) to perform the operations described in this application. The hardware components can also access, manipulate, process, create, and store data in response to the execution of the instructions or software. For the sake of brevity, the singular terms "processor" or "computer" may be used in the description of the examples described in this application, but in other examples, multiple processors or computers may be used, or a processor or computer may include multiple processing elements, or multiple types of processing elements, or both. For example, a single hardware component, or two or more hardware components, can be implemented by a single processor, or two or more processors, or a processor and a controller. One or more hardware components can be implemented by one or more processors, or a processor and a controller, and one or more other hardware components can be implemented by one or more other processors, or additional processors and additional controllers. One or more processors, or a processor and a controller, can implement a single hardware component, or two or more hardware components. As described above, or in addition to the above description, example hardware components can have any one or more of different processing configurations. Examples of different processing configurations include: a single processor, independent processors, parallel processors, single instruction single data (SISD) multiprocessing, single instruction multiple data (SIMD) multiprocessing, multiple instruction single data (MISD) multiprocessing, and multiple instruction multiple data (MIMD) multiprocessing.

[0133] As shown in Figures 1 to 27 and with respect to Figures 1 to 27The method of performing the operations described in this application is performed by computing hardware (e.g., a processor or computer of any one of the switches, memory devices, processor devices, network devices implemented as described above), and the computing hardware implements instructions or software to perform the operations to be performed by the method described in this application. For example, a single operation, or two or more operations, may be performed by a single processor, or two or more processors, or a processor and a controller. One or more operations may be performed by one or more processors, or a processor and a controller, and one or more other operations may be performed by one or more other processors, or additional processors and additional controllers. One or more processors, or a processor and a controller, may perform a single operation, or two or more operations.

[0134] Instructions or software for controlling computing hardware (e.g., one or more processors or computers) to implement the hardware components and execute the methods described above, as well as any associated data, data files, and data structures, can be recorded, stored, or fixed in one or more non-transitory computer-readable storage media or on one or more non-transitory computer-readable storage media, and thus are not signals per se. As described above, or in addition to the above description, examples of non-transitory computer-readable storage media (and one or more memories in any of the memory devices herein) include: any read-only memory (ROM), random access programmable read-only memory (PROM), electrically erasable programmable read-only memory (EEPROM), random access memory (RAM), dynamic random access memory (DRAM), static random access memory (SRAM), flash memory, non-volatile memory, CD-ROM, CD-R, CD+R, CD-RW, CD+RW, DVD-ROM, DVD-R, DVD+R, DVD-RW, DVD+RW, DVD-RAM, BD-ROM, BD-R, BD-R LTH, BD-RE, Blu-ray or optical disc storage devices, hard disk drives (HDD), solid state drives (SSD), flash memory, card-type memories (such as, multimedia card micro or cards such as Secure Digital (SD) or Extreme Digital (XD)), magnetic tapes, floppy disks, magneto-optical data storage devices, optical data storage devices, hard disks, solid state disks, and / or one or more of any other devices configured to store instructions or software, as well as any associated data, data files, and data structures, in a non-transitory manner and to provide the instructions or software, as well as any associated data, data files, and data structures, to one or more processors or computers such that the one or more processors or computers can execute the instructions. In one example, the instructions or software, as well as any associated data, data files, and data structures, are distributed across a networked computer system such that the instructions and software, as well as any associated data, data files, and data structures, are stored, accessed, and executed by one or more processors or computers in a distributed manner.

[0135] Although the present disclosure includes specific examples, it will be apparent after understanding the disclosure of this application that various changes in form and detail can be made in these examples without departing from the spirit and scope of the claims and their equivalents. The examples described herein are considered to be illustrative only and not for purposes of limitation. The description of a feature or aspect in each example is considered to be applicable to similar features or aspects in other examples. Suitable results can be achieved if the described techniques are performed in a different order, and / or if the components in the described systems, architectures, devices, or circuits are combined in a different manner, and / or replaced or supplemented by other components or their equivalents.

[0136] Accordingly, in addition to what is described above and what is disclosed in all of the accompanying drawings, the scope of the disclosure also includes the claims and their equivalents, that is, all variations within the scope of the claims and their equivalents will be construed as being included in the disclosure.

Claims

1. An electronic device, comprising: a plurality of processor device - memory device groups, and each of the plurality of processor device - memory device groups includes a plurality of memory devices, a plurality of processor devices, and a plurality of switches, the plurality of memory devices respectively include one or more memories, the plurality of processor devices respectively include one or more processors, wherein each of the plurality of switches includes a plurality of ports, and each of the plurality of first memory devices included in the first processor device - memory device group among the plurality of processor device - memory device groups is connected to a first subset of ports of one switch among the plurality of first switches included in the first processor device - memory device group, and is connected to a first subset of ports of one switch among the plurality of second switches included in the second processor device - memory device group among the plurality of processor device - memory device groups.

2. The electronic device according to claim 1, wherein, The plurality of first memory devices are connected to the first switch among the plurality of first switches and the first switch among the plurality of second switches.

3. The electronic device according to claim 1, wherein, The first processor device - memory device group and the second processor device - memory device group are arranged to be physically closest to each other.

4. The electronic device according to claim 1, wherein The first processor device - memory device group and the second processor device - memory device group are not physically closest to each other, but are logically close to each other.

5. The electronic device according to claim 4, wherein, The first processor device - memory device group and the second processor device - memory device group are arranged to send electrical signals to each other.

6. The electronic device according to claim 1, Among them, in each of the plurality of processor device - memory device groups, there is an equal number of connections between the corresponding plurality of memory devices and the corresponding plurality of switches.

7. The electronic device according to claim 1, wherein, Any one of the plurality of switches is not connected to another one of the plurality of switches.

8. The electronic device according to claim 1, wherein, The number of the plurality of memory devices in any one of the plurality of processor device - memory device groups is determined based on the following condition: the product of the number of the plurality of processor device - memory device groups, the number of switches in the corresponding processor device - memory device group among the plurality of processor device - memory device groups, and the number of the plurality of ports of the plurality of switches in the corresponding processor device - memory device group does not exceed the product of the number of the plurality of switches in the corresponding processor device - memory device group and the number of the subset of ports connected to the corresponding plurality of memory devices in the corresponding processor device - memory device group.

9. The electronic device according to claim 1, wherein, The number of the plurality of memory devices in each of the plurality of processor device - memory device groups is equal.

10. The electronic device according to claim 1, wherein, The number of the plurality of switches in each of the plurality of processor device - memory device groups is equal.

11. The electronic device according to claim 1, wherein, A second subset of ports of the one switch among the plurality of first switches is connected to the corresponding processor device among the plurality of processor devices.

12. The electronic device according to claim 1, wherein, The number of the plurality of processor devices is less than or equal to a value obtained by dividing a difference between a total number of ports of the plurality of switches and a total number of ports of the plurality of memory devices by a number of ports of a processor device in the plurality of processor devices.

13. The electronic device according to claim 1, wherein, The number of the plurality of processor devices is a multiple of a predetermined integer.

14. The electronic device according to claim 1, wherein, Each of the plurality of switches is a Compute Express Link (CXL) switch.

15. The electronic device according to claim 1, wherein, Each of the plurality of switches is a single-stage switch.

16. The electronic device according to claim 1, Among them, Each of the plurality of processor devices includes a plurality of ports, and Each of the plurality of first processor devices among the plurality of processor devices in the first processor device-memory device group is connected to a second subset of ports of one of the plurality of first switches and a second subset of ports of one of the plurality of second switches included in the second processor device-memory device group.

17. The electronic device according to claim 1, wherein, The electronic device is a storage device.

18. An electronic device, comprising: A plurality of processor device-memory device groups, and each of the plurality of processor device-memory device groups includes a plurality of memory devices, a plurality of processor devices, and a plurality of switches, the plurality of memory devices each include one or more memories, the plurality of processor devices each include one or more processors, wherein each of the plurality of processor devices includes a plurality of ports, and Each of the plurality of first processor devices in the first processor device-memory device group included in the plurality of processor device-memory device groups is connected to a first subset of a plurality of first switches included in the first processor device-memory device group and a first subset of ports of one of the plurality of second switches included in the second processor device-memory device group included in the plurality of processor device-memory device groups.

19. An electronic device, comprising: A plurality of memory device groups, and each of the plurality of memory device groups includes a plurality of memory devices and a plurality of switches, the plurality of memory devices each include one or more memories, wherein each of the plurality of memory devices includes a plurality of ports, and Each of the plurality of first memory devices in the first memory device group included in the plurality of memory device groups is connected to a first subset of ports of one of the plurality of first switches included in the first memory device group and a first subset of ports of one of the plurality of second switches included in the second processor device-memory device group included in the plurality of processor device-memory device groups.

20. The electronic device according to claim 19, wherein, The plurality of first memory devices are connected to the first switch among the plurality of first switches and the first switch among the plurality of second switches.

21. An electronic device, comprising: A plurality of groups of processor devices, and each of the plurality of groups of processor devices includes a plurality of processor devices and a plurality of switches, and the plurality of processor devices each include one or more processors, wherein each of the plurality of processor devices includes a plurality of ports, and each of the plurality of first processor devices included in the first group of processor devices included in the plurality of groups of processor devices is connected to a first subset of a plurality of first switches among the plurality of switches included in the first group of processor devices, and is connected to a first subset of switches among the plurality of second switches included in the plurality of second processor devices included in the plurality of groups of processor devices.

22. An electronic device, comprising: A plurality of groups of processor device-memory device, and each of the plurality of groups of processor device-memory device includes a plurality of memory devices, a plurality of processor devices and a plurality of switches, the plurality of memory devices each include one or more memories, the plurality of processor devices each include one or more processors, wherein each of the plurality of switches includes a plurality of ports, and the plurality of memory devices in one of the plurality of groups of processor device-memory device are connected to a first subset of the ports of each of the plurality of switches in the one of the plurality of groups of processor device-memory device and a first subset of the ports of each of the plurality of switches in another group of processor device-memory device.

23. The electronic device according to claim 22, wherein, The plurality of memory devices in the another group of processor device-memory device are connected to a second subset of the ports of each of the plurality of switches in the another group of processor device-memory device and a second subset of the ports of each of the plurality of switches in a third group of processor device-memory device.

24. The electronic device according to claim 23, wherein, The plurality of processor devices in the one of the plurality of groups of processor device-memory device are connected to a third subset of the ports of each of the plurality of switches in the one of the plurality of groups of processor device-memory device and a third subset of the ports of each of the plurality of switches in the another group of processor device-memory device.

25. The electronic device according to claim 24, wherein, Each of the plurality of groups of processor device-memory device further includes a plurality of network devices, and the plurality of network devices are connected to a fourth subset of the ports of each of the plurality of switches in the one of the plurality of groups of processor device-memory device.

26. The electronic device according to claim 22, wherein, The electronic device is a storage device.

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