3D array structure and process

Abstract

Various 3D array structures and processes are disclosed. In one embodiment, there is provided a word line step structure comprising: a plurality of word line layers alternately deposited with a plurality of insulating layers to form a stack; and a first word line step including all layers in the stack. The wordline step structure further includes one or more additional wordline steps such that each successive additional wordline step is formed to include fewer layers than in the stack of previous wordline steps to form the wordline step structure. The step structure also includes a plurality of contact holes formed in each word line step to contact the plurality of word line layers within the word line step.

Description

[0001] Cross - reference to Related Applications

[0002] This application claims priority under 35 U.S.C.§119(e) to the following: U.S. Provisional Patent Application No. 63 / 418,534, filed on October 22, 2022, titled "3D Array Structures and Processes"; U.S. Provisional Patent Application No. 63 / 421,522, filed on November 1, 2022, titled "3D Cells and Array Structures"; U.S. Provisional Patent Application No. 63 / 458,634, filed on April 11, 2023, titled "3D Cells and Array Structures"; U.S. Provisional Patent Application No. 63 / 459,406, filed on April 14, 2023, titled "3D Cells and Array Structures and Processes"; U.S. Provisional Patent Application No. 63 / 460,406, filed on April 19, 2023, titled "3D Memory Cells and Array Structures"; U.S. Provisional Patent Application No. 63 / 463,040, filed on April 30, 2023, titled "3D Memory Cells and Array Structures"; U.S. Provisional Patent Application No. 63 / 465,526, filed on May 10, 2023, titled "3D Cells and Array Structures"; U.S. Provisional Patent Application No. 63 / 466,155, filed on May 12, 2023, titled "3D Cells and Array Structures"; U.S. Provisional Patent Application No. 63 / 467,004, filed on May 16, 2023, titled "3D Cells and Array Structures"; and U.S. Provisional Patent Application No. 63 / 542,526, filed on October 5, 2023, titled "3D Array Structures and Processes". The entire contents of all of the above applications are incorporated herein by reference. Technical Field

[0003] Exemplary embodiments of the present invention generally relate to the field of memory, and more particularly to memory cells and array structures and related processes. Background Art

[0004] As the complexity and density of electronic circuits continue to increase, the size, complexity, and cost of memory become important considerations. One way to increase memory capacity is to use three - dimensional (3D) array structures. However, a high - performance - to - cost 3D array structure has not been fully realized. Summary of the Invention

[0005] In various exemplary embodiments, 3D array structures and processes are disclosed. In one embodiment, a 3D stepped array structure is formed and multiple new processes are performed to form multiple vertical contacts to each step of the steps. Embodiments of the present invention can be applied to various 3D array structures, such as 3D NAND flash memory. For example, in addition to 3D NAND flash memory, embodiments of the present invention can also be applied to other suitable 3D array structures, such as 3D NOR flash memory, 3D resistive random access memory (RRAM), 3D ferroelectric random access memory (FRAM), 3D phase change memory (PCM), 3D artificial neural network array (ANN), and many other 3D array structures.

[0006] In an exemplary embodiment, a word line stepped structure is provided, which includes: multiple word line layers, which are alternately deposited with multiple insulating layers to form a stack; a first word line step, which includes all the layers in the stack. The word line stepped structure further includes one or more additional word line steps, such that each successive additional word line step is formed to include fewer layers in the stack than the previous word line step to form the word line stepped structure. The word line stepped structure further includes multiple contact holes, which are formed in each word line step to contact the multiple word line layers within the word line step.

[0007] In an exemplary embodiment, an array structure formed by a process, the process includes: alternately depositing word line layers and insulating layers to form a stack; removing selected portions of the word line layers and insulating layers to form a word line stepped structure having multiple word line steps; depositing a thick insulating layer over the word line stepped structure; forming holes from the top surface of the thick insulating layer to the top surface of the word line steps such that multiple holes are formed to each word line step; and etching the word line stepped structure through the holes such that the depth of selected holes is increased to reach selected word line layers of the stack.

[0008] Additional features and benefits of the exemplary embodiments of the present invention will become apparent from the detailed description, drawings, and claims set forth below. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Exemplary embodiments of the present invention will be more fully understood from the following detailed description and the accompanying drawings, which illustrate various embodiments of the present invention but should not be construed as limiting the present invention to these specific embodiments. The drawings are for illustrative and understanding purposes only.

[0010] Figure 1A An embodiment of a word line stepped structure of a 3D array according to the present invention is shown.

[0011] Figure 1B An embodiment of an upper structure of a word line step is shown.

[0012] Figure 2 Exemplary cross-sectional view showing an embodiment of a character line ladder.

[0013] Figures 3A to 3B Shows Figure 2 A detailed embodiment of the ladder structure shown.

[0014] Figures 4A to 4K Shows an embodiment of a process step configured to form a character line contact according to the present invention.

[0015] Figure 4L Shows a process step configured to etch a contact hole in the ladder structure in the Y direction.

[0016] Figure 5A Shows how multiple sacrificial layers are inserted and deposited on top of the character line layer.

[0017] Figures 5B to 5D Shows how to etch a hard mask using an isotropic etching process.

[0018] Figure 6 Top view showing an embodiment of a contact hole formed by the above process.

[0019] Figures 7A to 7B Shows aspects of a "multi-step etch" etching operation.

[0020] Figures 8A to 8C Shows an embodiment illustrating a "triple-step etch" etching operation. Detailed Description

[0021] Those of ordinary skill in the art will recognize that the following detailed description is exemplary only and not limiting. Other embodiments of the present invention will be apparent to those skilled in the art who benefit from this disclosure. The embodiments of the exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. Throughout the drawings and the following detailed description, the same reference numerals or numbers are used to refer to the same or similar components.

[0022] Conventional 3D NAND flash memories include multiple character line (WL) layers. For example, advanced 3D NAND flash memories can have more than 200 character line layers. These character line layers need to be connected to a character line decoder circuit through long contacts. Conventional processes require very long processing times and misalignment of contact holes may occur. In various exemplary embodiments, novel processes are provided for forming character line layer connections while eliminating misalignment problems.

[0023] Figure 1AAn embodiment of a character line stepped structure of a 3D array according to the present invention is shown. Assume that the 3D array includes a plurality of character line layers 101a to 101n. In one embodiment, the character line layers 101a to 101n are separated by insulating layers. The character line layers are divided into a plurality of character line groups 102a to 102d. Each character line group is etched to form steps, such as steps 103a to 103d. For each character line group, a plurality of contact holes or openings, such as holes 104a to 104m, are formed to make contact with the character line layers in the group. For example, the contact holes 104a to 104m can be used to make contact with the character line layers in the character line group 102a.

[0024] Figure 1B An upper structure formed on the character line stepped array is shown. In one embodiment, the steps are covered by a thick insulating layer 105 including a material such as an oxide material. A plurality of vertical contact holes 106a to 106n are formed in the insulating layer 105 by using a deep trench or dry etching process to connect to the contact holes in the steps (such as Figure 1A the contact holes 104a to 104m shown). The contact holes 106a to 106n are filled with a conductor material such as a metal material to form contacts that connect each character line layer 101a to 101n to a conductive layer (not shown) formed on the top of the insulating layer 105.

[0025] In various embodiments, compared with the prior art, Figure 1A the stepped structure shown has several advantages. First, the contact holes in the plurality of character line groups 102a to 102d (such as those of holes 104a to 104m) can be formed together. This greatly reduces the process steps and process time for forming these contact holes. For example, if the character line layers are divided into 16 groups of character line layers, the process steps and process time can be reduced to 1 / 16 of the time required for a conventional structure.

[0026] Second, the contact holes in the character lines (such as Figure 1A the holes 104a to 104n in the stepped array shown) are self-aligned with the vertical contact holes in the insulating layer (such as Figure 1B the holes 106a to 106n shown). Since the holes in the stepped array and the vertical contacts in the insulator 105 are formed together simultaneously, self-alignment is produced. Therefore, the misalignment problem between the vertical contacts and the steps experienced by the conventional structure is eliminated. This greatly reduces the layout size of the steps and also improves the process yield. Detailed process steps are provided in the Figures 4A to 4K description.

[0027] Figure 2An exemplary cross-sectional view of an embodiment of a character line stepped array and an insulating layer 105 with vertical character line contact holes 106 formed in accordance with the present invention is shown. A first group 102a of character lines 101a to 101d is connected to contact holes 106a to 106d. A second group 102b of character lines 101e to 101h is connected to contact holes 106e to 106h. A third group 102c of character lines 101i to 101l is connected to contact holes 106i to 106l. A fourth group 102d of character lines 101m to 101p is connected to contact holes 106m to 106p. Insulating layers 107a to 107p including an oxide material, for example, are also shown between the character line layers 101a to 101p.

[0028] Figures 3A to 3B A detailed embodiment is shown which shows the formation of character line contacts, such as contacts 106a to 106d, in the stepped structure 102a and the insulating layer 105 shown. Figure 2 A detailed side view of the first group 102a of character lines of the stepped structure shown is shown. An insulating layer 108 including a material such as an oxide material is formed on the sidewalls of the vertical contact holes 106a to 106d by using a thin film deposition process. Next, an anisotropic etching process (e.g., reactive ion etching (RIE) or dry etching) is performed to remove the insulating layer 108 deposited on the bottoms of the contact holes 106a to 106d. Next, the contact holes 106a to 106d are filled with a contact material such as a metal material using a deposition process to form character line contacts.

[0029] Figure 3A A view showing Figure 2 Another embodiment of the first group 102a of character lines of the stepped structure shown is shown. In this embodiment, after the contact holes 106a to 106d are formed, an isotropic etching process (e.g., wet etching) is performed to selectively etch the character line layers 101a to 101d through the contact holes 106a to 106d to form recesses in the regions that will later be occupied by the residual insulator 109. Next, the contact holes and the recesses are filled with an insulating material such as an oxide material. Next, an anisotropic etching process (e.g., dry etching) is performed to remove the insulator in the vertical contact holes, leaving a residual insulator material 109 in the recessed regions. Next, the contact holes 106a to 106d are filled with a contact material such as a metal material using a deposition process to form character line contacts.

[0030] Figure 3B A view showing Figure 2 Another embodiment of the first group 102a of character lines of the stepped structure shown is shown. In this embodiment, after the contact holes 106a to 106d are formed, an isotropic etching process (e.g., wet etching) is performed to selectively etch the character line layers 101a to 101d through the contact holes 106a to 106d to form recesses in the regions that will later be occupied by the residual insulator 109. Next, the contact holes and the recesses are filled with an insulating material such as an oxide material. Next, an anisotropic etching process (e.g., dry etching) is performed to remove the insulator in the vertical contact holes, leaving a residual insulator material 109 in the recessed regions. Next, the contact holes 106a to 106d are filled with a contact material such as a metal material using a deposition process to form character line contacts.

[0031] Figures 4A to 4K An embodiment of process steps configured to form character line contacts according to the present invention is shown.

[0032] Figure 4A Shows how multiple word line layers 101a to 101p such as metal layers and multiple insulating layers 107a to 107p such as oxide layers are alternately deposited to form a stack. Next, a hard mask 110 for a pullback operation is formed on top of the stack. In one embodiment, the hard mask 110 is very thick to allow an isotropic etching process (e.g., wet etching) to "pull back" the edge of the mask without using a lithography step. Since the etching is isotropic, the top of the etching mask will also be etched. Therefore, a very thick hard mask 110 is used to allow several iterations of the pullback process. For illustrative purposes, the drawings only show that the pullback occurs at the edge of the hard mask 110. The reduction in the thickness of the hard mask 110 due to the etching process is not shown.

[0033] Figure 4B Shows how the hard mask 110 is etched by using an isotropic etching process (e.g., wet etching) to pull back the edge of the hard mask 110 in the direction shown by arrow 111. Next, an anisotropic etching process (e.g., dry etching) is performed to etch the areas not protected by the hard mask 110 to etch four word line layers 101a to 101d and four insulating layers 107a to 107d, thereby forming a word line step 103d.

[0034] Figure 4C Shows how the hard mask 110 is pulled back again in the direction shown by arrow 111. Next, an anisotropic etching process (e.g., dry etching) is performed using the hard mask 110 to etch another four word line layers 101e to 101h and another four insulating layers 107e to 107h in the area of the word line step 103d. The etching process will also etch the word line layers 101a to 101d and the four insulating layers 107a to 107d to form a word line step 103c.

[0035] Figure 4D Shows how the hard mask 110 is pulled back again in the direction shown by arrow 111. Next, an anisotropic etching process (e.g., dry etching) is performed using the hard mask 110 to etch another four word line layers and another four insulating layers. This will form a word line step 103b. The etching process will also lower the word line steps 103d and 103c. Next, the hard mask 110 is removed and steps 103a to 103d are formed.

[0036] Figure 4E Shows how a thick insulating layer 105 including a material such as an oxide material is deposited on top of the step array. A planarization process (e.g., chemical mechanical polishing (CMP)) is performed to planarize the top surface 401 of the insulating layer 105.

[0037] Figure 4FShows how to pattern the vertical contact holes 106a to 106p by using photolithography and then etch through the shown insulating layer 105 by using an anisotropic etching process (such as deep trench etching) to form the vertical contact holes.

[0038] Figure 4G Shows how to deposit a hard mask layer and pattern-etch it to form hard masks 112a and 112b for a etch-back operation on top of the insulating layer 112.

[0039] Figure 4H Shows how to etch the hard masks 112a and 112b by using an isotropic etching process (such as wet etching) to etch-back the edges of the hard masks to expose a part of the contact holes (such as contact holes 106d, 106h, 106l, and 106p). Next, an anisotropic etching process (such as dry etching) is performed using the hard masks 112a and 112b to cover a part of the insulating layer to etch a word line layer and an insulating layer under the contact holes 106d, 106h, 106l, and 106p.

[0040] Figure 4I Shows how to etch-back the hard masks 112a and 112b again to expose another four contact holes 106c, 106g, 106k, and 106o. Next, an anisotropic etching process (such as dry etching) is performed using the hard masks 112a and 112b to cover a part of the insulating layer to etch a word line layer and an insulating layer under the contact holes 106c, 106d, 106g, 106h, 106k, 106l, 106o, and 106p.

[0041] Figure 4J Shows how to etch-back the hard masks 112a and 112b again to expose another four contact holes 106b, 106f, 106j, and 106n. Next, an anisotropic etching process (such as dry etching) is performed using the hard masks 112a and 112b to cover a part of the insulating layer to etch a word line layer and an insulating layer under the contact holes 106b, 106c, 106d, 106f, 106g, 106h, 106j, 106k, 106l, 106m, 106o, and 106p.

[0042] Figure 4K Shows the structure formed when the remaining parts of the hard masks 112a and 112b are removed by using an isotropic etching process. The contact holes 106a to 106p are in contact with the word line layers 101a to 101p.

[0043] Figures 4A to 4KThe process steps shown are configured to etch contact holes in a stepped structure in the X direction, such as etching the contact holes 106 a to 106 m described above, so that the contact holes are in contact with different word line layers.

[0044] Figure 4L A process step is shown for etching contact holes in a stepped structure in the Y direction, for example, to form contact holes 106a to 106n, so that these contact holes contact different word line layers. For Y-direction etching, a hard mask 120 is formed on top of the insulating layer 105. An etch-back operation as described above is performed to etch back the hard mask 120 in the Y direction indicated by arrow 121. Each etch-back operation exposes a row of contact holes, such as holes 106a to 106m. Next, an etching process as described above is performed to etch through the contact holes 106a to 106m to etch one or more word line layers and insulating layers below the contact holes. As a result, the contact holes 106a to 106m are configured to contact the selected lower word line layer. By repeating the previously described etch-back process in the Y direction, contact holes (e.g., holes 106a to 106n) are etched to contact different word line layers as needed.

[0045] By Figures 4A to 4K and Figure 4L By combining the process steps shown, the contact holes in the X and Y directions can be configured to contact any word line layer. Figure 1A , assuming that the contact holes 104a to 104m are arranged in a 4×6 matrix in the X direction and the Y direction. In one embodiment, Figures 4A to 4K The steps shown in FIG. 1 are for performing 4 etch-backs in the X direction. Figure 4L The steps shown in FIG are for performing 6 etch-backs in the Y direction. As a result, 24 contact holes will be formed to contact the 24 word line layers. In one embodiment, Figure 4L The process steps shown in Figure 4A In another embodiment, Figure 4L The process steps shown in Figures 4A to 4K The process steps shown are performed afterwards.

[0046] exist Figures 4A to 4D In the illustrated embodiment of the process steps, four wordline layers and four insulating layers are etched after each etch back of the hard mask 110. This requires eight iterations of the etching step. If a wordline group includes 50 layers, it would require 100 iterations of the etching step. If the array includes four wordline groups, it would require 400 iterations of the etching step.

[0047] Figures 5A to 5D An embodiment of process steps configured to reduce the number of etching steps used to form wordline stairs in accordance with the present invention is shown.

[0048] Figure 5A It shows that during the process of depositing the character line layers 101a to 101p and the insulating layers 107a to 107p, multiple sacrificial layers 114a to 114c are inserted and deposited on top of the character line layers 101e, 101i, and 101m. As a result, the character line layers 101e, 101i, and 101m form the top layers of the bottom three groups.

[0049] In one embodiment, the sacrificial layers 114a to 114c have a higher etch selectivity than the character line layers 101a to 101p and the insulating layers 107a to 107p. For example, in one embodiment, the character line layers 101a to 101p are metal layers, the insulating layers 107a to 107p are oxide layers, and the sacrificial layers 114a to 114c are nitride layers. After forming the character line stack, a thick hard mask 113 for a re-etch operation is formed on top of the array.

[0050] Figure 5B It shows how to etch the hard mask 113 by using an isotropic etching process (such as wet etching) to re-etch the edge of the hard mask 113 in the direction shown by the arrow 115. Next, an anisotropic etching process (such as deep trench etching) is performed using the hard mask 113 to cover a part of the stack to selectively etch all the character line layers 101a to 101d and the insulating layers 107a to 107d above the sacrificial layer 114a.

[0051] In one embodiment, the selected etchant etches the materials of the character line layers 101a to 101d and the insulating layers 107a to 107d, but cannot etch the sacrificial layer 114a. Therefore, only one etching step is required to etch the four character lines and the insulating layers, and the etching automatically stops at the sacrificial layer 114a. After that, an anisotropic etching process (such as dry etching) is performed to etch the sacrificial layer 114a on top of the step 103d.

[0052] Figure 5C It shows how to re-etch the hard mask 113 again in the direction shown by the arrow 115. The previously described etching process is performed to etch all the character line layers and the insulating layers above both the second sacrificial layer 114b on top of the step 103d and the first sacrificial layer 114a on top of the step 103c. Next, an anisotropic etching process (such as dry etching) is performed to etch the sacrificial layer 114b on top of the step 103d and the sacrificial layer 114a on top of the step 103c.

[0053] Figure 5DShows how to etch the hard mask 113 again in the direction shown by arrow 115. The previously described etching process is performed to etch all the word line layers and insulating layers above the third sacrificial layer 114c on top of the step 103d, the second sacrificial layer 114b on top of the step 103c, and the first sacrificial layer 114a on top of the step 103b. Next, an anisotropic etching process (e.g., dry etching) is performed to etch the sacrificial layer 114c on top of the step 103d, the sacrificial layer 114b on top of the step 103c, and the sacrificial layer 114a on top of the step 103b.

[0054] After performing the above process steps, the hard mask 113 is removed to expose the step 103a. Next, perform Figures 4E to 4K the process steps shown to form the word line layer contact holes 106a to 106p as shown in Figure 4K Figure 4K

[0055] Figure 6 Shows a top view of an embodiment of the contact holes 106a to 106e formed by the above process. During the etch-back operation, the hard mask 112 is etched back in the direction shown by arrow 122. The distance of each etch-back must be precisely controlled such that the edge of the hard mask 112 is located between two rows of contact holes and within the distance 123 between the holes, as shown. This requirement poses a great challenge to the etch-back process and reduces the process yield. As a result, a large distance 123 can be used to increase the process yield, which leads to an increase in die size.

[0056] To address the requirement for precision in the etch-back distance, embodiments of the present invention provide a novel "multiple etch-back" etching operation.

[0057] Figure 7A Shows a top view of an embodiment of the contact holes 106a to 106e formed by the above process to illustrate aspects of the "multiple etch-back" etching operation. First, only the even contact holes 106a, 106c, and 106e are patterned and formed. In the first etch-back operation, the first hard mask 112a is sequentially etched back to etch the even contact holes 106a, 106c, and 106e. As shown, etching only the even contact holes increases the distance between the contact holes and thus increases the process yield as it is easier to meet the etch-back precision requirements.

[0058] Figure 7BShows the operations performed after the first etch operation, where the even contact holes 106a, 106c, and 106e are filled with a sacrificial material. Next, the odd contact holes 106b and 106d are patterned and formed. In one embodiment, a second hard mask 112b is formed and sequentially etched to form the odd contact holes 106b and 106d. This increases the distance between these contact holes, as shown by distance 124b, thereby increasing the process yield.

[0059] After the second etch operation, the sacrificial material in all the contact holes is etched. Next, the following process is performed to form Figures 3A to 3B the contact structure shown.

[0060] Figures 8A to 8C Shows an embodiment of a "triple etch" etch operation.

[0061] Figure 8A Shows how to form and sequentially etch a first set of contact holes (e.g., holes 106a, 106d, and 106g) using the first hard mask 112a. The distance 124a between the contact holes is also shown. After completing the first etch operation, the first set of contact holes, such as holes 106a, 106d, and 106g, are filled with a sacrificial material.

[0062] Figure 8B Shows how to form and sequentially etch a second set of contact holes (e.g., holes 106b, 106e, and 106h) using the second hard mask 112b. The distance 124b between the second set of contact holes is also shown. After completing the second etch operation, the second set of contact holes, such as holes 106b, 106e, and 106h, are filled with a sacrificial material.

[0063] Figure 8C Shows how to form and sequentially etch a third set of contact holes (e.g., holes 106c, 106f, and 106i) using the third hard mask 112c. The distance 124c between the third set of contact holes is also shown. By using this configuration, the etching of selected sets of contact holes can be performed to meet the tight pitch requirements between contact holes for high yield.

[0064] After completing the third etch operation, the sacrificial material in the first and second sets of contact holes is removed by etching. Next, an additional process is performed to form Figures 3A to 3B the contact structure shown.

[0065] Although the embodiments of the present invention described herein use the word line layer as an example, the present invention can be applied to the connection of any other layer (e.g., bit line (BL) layer or source line (SL) layer). In addition, the array geometry, process steps, and process sequence are shown only as examples, and any minor modifications or variations are within the scope of the present invention.

[0066] While the exemplary embodiments of the present invention have been shown and described, it will be apparent to those of ordinary skill in the art that, based on the teachings herein, changes and modifications can be made without departing from the exemplary embodiments and their broader aspects. Accordingly, the appended claims are intended to cover all changes and modifications that are within the true spirit and scope of the exemplary embodiments of the present invention within their scope.

Claims

1. A character line stepped structure, comprising: A plurality of character line layers, which are alternately deposited with a plurality of insulating layers to form a stack; A first character line step, which includes all the layers in the stack; One or more additional character line steps, wherein each successive additional character line step is formed to include fewer layers in the stack than the previous character line step to form the character line stepped structure; And A plurality of contact holes, which are formed in each character line step to contact a plurality of character line layers within the character line step.

2. An array structure formed by the following process, comprising: Alternately depositing character line layers and insulating layers to form a stack; Removing selected portions of the character line layers and the insulating layers to form a character line stepped structure having a plurality of character line steps; Depositing a thick insulating layer over the character line stepped structure; Forming holes from the top surface of the thick insulating layer to the top surface of the character line step, wherein a plurality of holes are formed to each character line step; And Etching the character line stepped structure through the holes such that the depth of selected holes is increased to reach selected character line layers of the stack.

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