Manufacturing method for improving acoustic sensor structure and acoustic sensor structure

Abstract

The invention provides an acoustic sensor improving structure which is characterized in that a first groove body (213) and a second groove body (219) are arranged on a device layer (21) of a first SOI silicon wafer (2), a lower electrode (211) is arranged in the second groove body (219), a silicon wire (212) communicated with the adjacent lower electrode (211) is arranged in the first groove body (213), and a second SOI silicon wafer (1) is bonded on the first SOI silicon wafer (2). The invention has the advantages of simple structure, reasonable arrangement, simple preparation process steps, good temperature coefficient, good transmitting and receiving performance of the transducer and the like.

Description

Technical Field

[0001] The present invention relates to the field of acoustic sensors in MEMS (Micro-electric Mechanical Systems), and in particular to a manufacturing method and structure for improving the structure of an acoustic sensor. Background Art

[0002] A CMUT is an ultrasonic detection device fabricated using micromechanical systems (MEMS) technology based on the capacitive sensing principle. Electric field strength directly impacts two key performance indicators: transmit voltage response and receiver sensitivity. Based on the definition of electric field strength, it can be increased by increasing the voltage or reducing the effective distance between the upper and lower electrodes. The operating voltage of a CMUT is limited by its pull-in voltage, and lower voltages are more readily available. Therefore, reducing the effective distance between the upper and lower electrodes is a practical approach. In a conventional CMUT, the upper electrode is machined onto the surface of a vibrating membrane, with a layer of silicon dioxide acting as an insulating layer between the membrane and the upper electrode. The thickness of the vibrating membrane increases the effective distance between the upper and lower electrodes, reducing the CMUT's electric field strength at a given voltage. The higher the CMUT's operating frequency, and therefore the thicker the vibrating membrane, the greater the impact on the electric field strength.

[0003] In order to overcome the above problems, the inventor designed a technical improvement (application number: 202210064836.2). In this patent, in order to achieve the sealing of the CMUT cavity, a circle of polysilicon is filled around the lower electrode. However, during the production verification, it was found that when filling polysilicon in the isolation groove of the lower electrode, it was necessary to first fill the entire surface of the CMUT wafer with polysilicon, and then perform photolithography and etching to retain only the polysilicon in the isolation groove to achieve the sealing of the CMUT cavity. However, this method of filling polysilicon production, on the one hand, increases the process steps, resulting in a long production cycle and high cost, and on the other hand, during the growth and removal of polysilicon, it will affect the residual stress of the vibrating film, thereby affecting the performance of the CMUT. Summary of the Invention

[0004] The present invention aims to overcome the deficiencies in the prior art and provides an all-silicon electrode capacitive micromachined ultrasonic transducer chip.

[0005] This application provides the following technical solutions: A method for manufacturing an improved acoustic sensor structure, characterized in that it comprises the following steps: 1) obtaining a first SOI silicon wafer, the first SOI silicon wafer comprising a substrate layer, a buried oxide layer, and a device layer sequentially arranged from bottom to top; 2) Patterning is formed on the silicon surface of the device layer, and then etching is performed along the patterning to form a groove on the silicon surface of the device layer; 3) Thermally oxidize the upper surface of the device layer and the bottom surface of the tank to form a silicon dioxide thin film layer on the upper surface; 4) Perform silicon dioxide patterning on the upper surface of the device layer and the bottom surface of the tank to remove a portion of the silicon thin film layer to obtain a silicon material etching window; 5) Continue etching downward until the etching window at the bottom of the groove reaches the buried oxide layer, thereby forming a lower electrode in the groove, and a certain distance is maintained between the lower electrode and the surrounding silicon material; 6) Bonding the second SOI silicon wafer to the upper surface of the device layer of the first SOI silicon wafer, and then removing the substrate layer and buried oxide layer of the second SOI silicon wafer; 7) A set of second through holes and a first through hole are formed downwardly on the second SOI silicon wafer, and the first silicon oxide film layer is removed from the bottom of the second through holes and the first through holes; 8) On the exposed upper surface of the device layer, a metal tube with one end in contact with the upper surface of the device layer is provided in the second through hole, a lower electrode metal pad is provided on the upper surface of the device layer in the first through hole, and an upper electrode metal pad is provided on the second SOI silicon wafer.

[0006] On the basis of the above steps, there are further steps as follows: In step 8), the metal tube, the upper electrode metal pad and the lower electrode metal pad are prepared by sputtering metal Ti / Au.

[0007] After step 6) is completed, the tank body is in an airtight state.

[0008] An improved acoustic sensor structure according to claim 3 is adopted, comprising a first SOI silicon wafer composed of a device layer, a buried oxide layer, and a substrate layer, characterized in that: grooves are provided on the device layer, the grooves comprising first grooves distributed in a grid pattern, and circular second grooves extending outward at the intersections of the first grooves, at least one of the second grooves having a silicon pad having the same height as the device layer, and lower electrodes having a height less than that of the device layer are provided in the other second grooves; The first tank is provided with a silicon wire connecting the adjacent lower electrodes. The device layer, silicon wire and lower electrode are all covered with a silicon dioxide film layer. An annular silicon dioxide film layer is provided on the upper surface of the silicon pad. A device layer having a second SOI silicon wafer bonded thereto is provided. The second SOI silicon wafer is provided with a matrix of through holes, wherein metal tubes communicating with the device layer are provided in the through holes. The second SOI silicon wafer is provided with a first through hole corresponding to a silicon pad, a lower electrode metal pad is provided on the silicon pad in the first through hole, and an upper electrode metal pad is provided on the second SOI silicon wafer.

[0009] On the basis of the above technical solutions, the following further technical solutions can be provided: The thickness of the silicon wire is lower than the height of the first slot.

[0010] The width of the silicon conductive wire is smaller than the width of the first slot body, and the thickness end surfaces on both sides of the silicon conductive wire do not contact the slot wall of the first slot body.

[0011] There is a certain distance between the lower electrode and the second tank body, and the two are not in contact.

[0012] The metal tube and the lower electrode are staggered.

[0013] Advantages of the invention: The present invention features a simple structure, rational layout, simple manufacturing process steps, and a good temperature coefficient. By coating the lower electrode with a silicon dioxide film layer, damage to the CMUT caused by an electrical short circuit when the upper and lower electrodes come into contact is effectively prevented. Furthermore, the lower electrode, through bonding to the first and second grooves and edges, simultaneously ensures a vacuum within the first and second grooves. This eliminates the effect of the thickness of the vibrating film on the electric field strength, thereby improving the transducer's transceiver performance.

[0014] Unlike the traditional CMUT structure in which the lower electrode is the common electrode of the array element and the upper electrode is patterned and interconnected by metal wires, the new structure proposed in this patent has a vibration film / upper electrode as the common electrode of the array element and the lower electrode is patterned and interconnected by silicon wires. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 It is a schematic diagram of the overall structure of the present invention; Figure 2 is a top view of the device layer; Figure 3 yes Figure 2 AA cross-sectional view in FIG; Figure 4 yes Figure 2 BB cross-sectional view in FIG; Figure 5 yes Figure 2 The CC cross-sectional view in FIG. Figure 6 yes Figure 1 Schematic diagram of the structure of the metal tube; Figure 7 is a schematic diagram after step 2) of the preparation method is completed; Figure 8 is a schematic diagram after step 3) of the preparation method is completed; Figure 9 is a schematic diagram after step 4) of the preparation method is completed; Figure 10 is a schematic diagram after step 5) of the preparation method is completed; Figure 11is a schematic diagram after step 6) of the preparation method is completed; Figure 12 is a schematic diagram after step 7) of the preparation method is completed; Figure 13 Schematic diagram after step 8) of the preparation method is completed. DETAILED DESCRIPTION

[0016] like Figure 7-13 The method for manufacturing an improved acoustic sensor structure is characterized in that it includes the following steps: 1) taking a first SOI silicon wafer 2, the first SOI silicon wafer 2 including a substrate layer 23, a buried oxide layer 22 and a device layer 21 distributed in sequence from bottom to top.

[0017] 2) A pattern is formed on the silicon surface of the device layer, and then the device is etched along the pattern to form a groove on the silicon surface of the device layer.

[0018] 3) Thermal oxidation is performed on the upper surface of the device layer 21 , the bottom surface of the groove body, and the surface of the substrate layer 23 to form a silicon dioxide thin film layer on the upper surfaces thereof.

[0019] 4) Silicon dioxide patterning is performed on the upper surface of the device layer and the bottom surface of the groove body to remove a portion of the silicon thin film layer to obtain a silicon material etching window a.

[0020] 5) Continue etching downward along the etching window a until the etching window a at the bottom of the groove reaches the buried oxide layer 22, thereby forming a lower electrode 211 in the groove, and a certain distance is maintained between the lower electrode 211 and the surrounding silicon material.

[0021] 6) Take a second SOI silicon wafer 1 without a buried oxide layer and a substrate layer, and bond the second SOI silicon wafer 1 to the upper surface of the device layer 21 of the first SOI silicon wafer 2. Make the inside of the tank airtight, and achieve vacuum-tight isolation of the lower electrode 211.

[0022] 7) A set of second through holes 11 and a first through hole 11a are formed downwardly on the second SOI silicon wafer, and the silicon dioxide film layer 218 at the bottom of the second through holes 11 and the first through holes 11a is removed. The diameters of the second through holes 11 and the first through hole 11a are smaller than those of the second through holes 11.

[0023] 8) On the exposed upper surface of the device layer, a metal tube 112 is provided in the second through hole 11, one end of which is connected to the upper surface of the device layer 21 by sputtering metal Ti / Au. A lower electrode metal pad 111 is provided on the upper surface of the device layer in the first through hole, and an upper electrode metal pad 114 is provided on the second SOI silicon wafer.

[0024] like Figure 1-6As shown, an improved acoustic sensor structure includes a first SOI silicon wafer 2. The first SOI silicon wafer 2 consists of a device layer 21, a buried oxide layer 22 and a substrate layer 23 distributed in sequence from top to bottom.

[0025] A patterned groove body is provided on the device layer 21, and the groove body includes a first groove body 213 distributed in a grid shape, and a circular second groove body 219 extending outward at the intersection of the first groove body 213. A coaxially distributed lower electrode 211 is distributed in each second groove body 219, and the first groove body 213 and the second groove body 219 have the same height.

[0026] The region of the device layer 21 inside the first groove body 213 serves as a support column 214 , and a circle of the device layer 21 outside the first groove body 213 serves as an annular bonding area 215 .

[0027] Among all the lower electrodes 211 , one has the same height as the silicon pad 216 and the device layer 21 , and serves as the silicon pad 216 , while the heights of the other lower electrodes 211 are lower than the first trough body 213 and the second trough body 219 .

[0028] Silicon wires 212 are distributed within the first trough 213, connecting adjacent lower electrodes 211. The height of the silicon wires 212 is less than the height of the first trough 213, and the width of the silicon wires 212 is less than the width of the first trough 213. The thickness end surfaces of the silicon wires 212 do not contact the walls of the first trough 213. The diameter of the lower electrodes 211 is also less than the diameter of the second trough 219. Because the silicon wires 212 and lower electrodes 211 are each spaced a certain distance from the corresponding walls of the second trough 219 and first trough 213, an airtight isolation space b is formed between the silicon wires 212 and lower electrodes 211 and other silicon materials in the device layer 21.

[0029] The silicon wire 212 and the lower electrode 211 are both covered with a silicon dioxide film layer 218, and the upper surface of the device layer 21 is also covered with a silicon dioxide film layer 218. The second SOI silicon wafer 1 is bonded to the bonding area 215. The buried oxide layer and substrate layer of the second SOI silicon wafer 1 are removed, leaving only the device layer.

[0030] A set of second through-holes 11 are evenly distributed across the second SOI silicon wafer 1. These second through-holes 11 are offset from the bottom electrode 211. Within each second through-hole 11 lies a metal tube 112, connected to a support pillar 214. A flange 113 extends from the upper end of each metal tube 112. The bottom of each metal tube 112 is sealed, and a metal base 115 at the bottom of each metal tube 112 electrically interconnects the support pillar 214 with the device layer of the second SOI silicon wafer 1.

[0031] A first through hole 11a is provided on the second SOI silicon wafer 1, corresponding to the silicon pad 216. A lower electrode metal pad 111 is provided on top of the silicon pad 216 within the first through hole 11a, for forming an electrical signal connection therewith. An upper electrode metal pad 114 is provided on the second SOI silicon wafer 1, for forming an electrical signal connection therewith.

[0032] A silicon dioxide thin film layer 218 is also provided between the upper surface of the silicon pad 216 outside the first through hole 11 a and the second SOI silicon wafer 1 .

[0033] Since the lower electrode 211 is isolated from other silicon materials in the device layer 21 by vacuum airtight isolation, this overcomes the existing method of multiple fillings of polysilicon production, simplifies the production process, shortens the production cycle, and reduces costs. On the other hand, it also avoids the residual stress of the vibrating film during the growth and removal of polysilicon, which in turn affects the CMUT performance.

Claims

1. A method for improving the structure of an acoustic sensor, characterized in that: It includes the following steps: 1) Take a first SOI silicon wafer, which includes a substrate layer, a buried oxide layer, and a device layer arranged in order from bottom to top; 2) Patterning is formed on the silicon surface of the device layer, and then etching is performed along the patterning to form a groove on the silicon surface of the device layer; 3) Thermal oxidation is performed on the upper surface of the device layer and the bottom surface of the tank body to form a silicon dioxide thin film layer on the upper surface; 4) Perform silicon dioxide patterning on the upper surface of the device layer and the bottom surface of the tank to remove a portion of the silicon thin film layer to obtain a silicon material etching window; 5) Continue etching downward until the etching window at the bottom of the groove reaches the buried oxide layer, thereby forming a lower electrode in the groove, and a certain distance is maintained between the lower electrode and the surrounding silicon material; 6) Bonding the second SOI silicon wafer to the upper surface of the device layer of the first SOI silicon wafer, and then removing the substrate layer and buried oxide layer of the second SOI silicon wafer; 7) A set of second through holes and a first through hole are formed downwardly on the second SOI silicon wafer, and the first silicon oxide film layer is removed from the bottom of the second through holes and the first through holes; 8) On the exposed upper surface of the device layer, a metal tube with one end in contact with the upper surface of the device layer is provided in the second through hole, a lower electrode metal pad is provided on the upper surface of the device layer in the first through hole, and an upper electrode metal pad is provided on the second SOI silicon wafer.

2. The method for improving the acoustic sensor structure according to claim 1, characterized in that: In step 8), the metal tube, the upper electrode metal pad and the lower electrode metal pad are prepared by sputtering metal Ti / Au.

3. The method for improving the acoustic sensor structure according to claim 1, characterized in that: After step 6) is completed, the tank body is in an airtight state.

4. An improved acoustic sensor structure according to claim 3, comprising a first SOI silicon wafer (2) consisting of a device layer (21), a buried oxide layer (22) and a substrate layer (23), characterized in that: A trough body is provided on the device layer (21), the trough body comprising first trough bodies (213) distributed in a grid shape, and circular second trough bodies (219) extending outward at the intersection of the first trough bodies (213), a silicon pad (216) being provided in at least one of the second trough bodies (219), the height of the silicon pad (216) being the same as that of the device layer (21), and a lower electrode (211) having a height less than that of the device layer (21) being provided in the other second trough bodies (219); A silicon wire (212) connecting adjacent lower electrodes (211) is provided in the first trough (213); the device layer (21), the silicon wire (212) and the lower electrode (211) are all covered with a silicon dioxide film layer (218); and a ring-shaped silicon dioxide film layer (218) is provided on the upper surface of the silicon pad (216). A device layer having a second SOI silicon wafer (1) bonded to the device layer (21) is provided. A through hole is provided on the second SOI silicon wafer (1) in a matrix pattern. A metal tube (112) connected to the device layer (21) is provided in the through hole. A first through hole corresponding to a silicon pad (216) is provided on the second SOI silicon wafer (1). A lower electrode metal pad (111) is provided on the silicon pad (216) in the first through hole. An upper electrode metal pad (114) is provided on the second SOI silicon wafer (1).

5. The all-silicon electrode capacitive micromachined ultrasonic transducer chip according to claim 4, characterized in that: The thickness of the silicon wire (212) is lower than the height of the first slot (213).

6. The all-silicon electrode capacitive micromachined ultrasonic transducer chip according to claim 4, characterized in that: The width of the silicon wire (212) is smaller than the width of the first slot body (213), and the thickness end surfaces on both sides of the silicon wire (212) do not contact the slot wall of the first slot body (213).

7. The all-silicon electrode capacitive micromachined ultrasonic transducer chip according to claim 4, characterized in that: There is a certain distance between the lower electrode (211) and the second trough body (219), and the two are not in contact.

8. The all-silicon electrode capacitive micromachined ultrasonic transducer chip according to claim 4, characterized in that: The metal tube (112) and the lower electrode (211) are staggered.

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