Resistance simulation module and resistance temperature detector RTD simulator

Abstract

The embodiment of the invention provides a resistance simulation module and a resistance temperature detector RTD simulator, and relates to the technical field of nuclear power. The resistor simulation module comprises a field programmable gate array (FPGA) and a resistor simulation channel, wherein the resistor simulation channel comprises a serial-parallel conversion circuit and a switch resistor array; the FPGA is used for receiving a resistance simulation instruction sent by an upper computer, and the resistance simulation instruction indicates a to-be-simulated resistance value; the serial-to-parallel conversion circuit is used for determining a to-be-simulated coded value by performing parallel BCD coding on the to-be-simulated resistance value; and the switch resistor array is used for controlling the first switch combination corresponding to the to-be-simulated coded value to be in a conduction state and accessing the first resistor combination corresponding to the first switch combination so as to simulate a to-be-simulated resistance value. Therefore, the resistance simulation module provided by the embodiment of the invention can simulate the required resistance value with high efficiency and high accuracy, and then T2 response time test with high efficiency and high accuracy is carried out.

Description

Technical Field

[0001] The present application relates to the field of nuclear power technology, and in particular to a resistance simulation module and a resistance temperature detector (RTD) simulator. Background Art

[0002] T2 response time is a key indicator of the reliability of nuclear reactor protection systems. It reflects the total time required from the moment a sensor (such as a temperature sensor or pressure sensor) detects data exceeding a safety threshold to the moment the nuclear reactor protection system triggers a protective action (such as an emergency shutdown). Therefore, to ensure that the nuclear reactor protection system can execute protective actions promptly and accurately in the event of an accident and avoid serious consequences, T2 response time must be regularly tested.

[0003] Currently, nuclear power plants typically use fixed resistance boxes to test the T2 response time of nuclear reactor protection systems. However, these boxes only provide preset fixed resistance values and cannot dynamically adjust resistance values according to test requirements. While technicians can simulate varying resistance values by manually switching between different resistance box combinations, this manual operation is not only time-consuming and labor-intensive, but also prone to errors due to operator errors, making it difficult to meet the requirements for high-efficiency and high-accuracy testing.

[0004] Therefore, how to efficiently and accurately simulate the required resistance value and then conduct efficient and accurate T2 response time testing has become a technical problem that needs to be solved urgently. Summary of the Invention

[0005] Based on the above problems, the present application provides a resistance simulation module and a resistance temperature detector (RTD) simulator, which can simulate the required resistance value with high efficiency and high accuracy, and then perform high-efficiency and high-accuracy T2 response time testing.

[0006] The embodiments of this application disclose the following technical solutions:

[0007] In a first aspect, the present application discloses a resistance simulation module, comprising: a field programmable gate array (FPGA) and a resistance simulation channel, wherein the resistance simulation channel comprises a serial-to-parallel conversion circuit and a switch resistor array, wherein the switch resistor array comprises a plurality of resistors and a plurality of switch transistors, and each resistor has a unique corresponding switch transistor, wherein the FPGA, the serial-to-parallel conversion circuit, and the switch resistor array are sequentially connected;

[0008] The FPGA is used to receive a resistance simulation instruction sent by a host computer, wherein the resistance simulation instruction indicates a resistance value to be simulated;

[0009] The serial-to-parallel conversion circuit is used to determine the code value to be simulated by performing parallel BCD encoding on the resistance value to be simulated;

[0010] The switch resistor array is used to control a first switch combination corresponding to the code value to be simulated to be in an on state, and connect a first resistor combination corresponding to the first switch combination to simulate the resistance value to be simulated.

[0011] Optionally, the FPGA is further configured to determine a difference between an actual resistance value and a theoretical resistance value of the target resistor combination as a deviation resistance value;

[0012] The serial-to-parallel conversion circuit is further configured to determine a deviation coding value by performing parallel BCD coding on the deviation resistance value;

[0013] The switch resistor array is further configured to, if the deviation coding value is a negative number, control the second switch combination to be in an on state, and connect the second resistor combination corresponding to the second switch combination to simulate the resistance value to be simulated.

[0014] Optionally, the switch resistor array is further used for:

[0015] If the deviation code value is a positive number, the third switch combination corresponding to the deviation code value in the first switch combination is controlled to be in an off state, and the third resistor combination corresponding to the third switch combination is disconnected to simulate the resistance value to be simulated.

[0016] Optionally, the serial-to-parallel conversion circuit is specifically used to:

[0017] The code value to be simulated is determined by converting each decimal digit of the resistance value to be simulated into a BCD code of a binary number and splicing the converted BCD codes.

[0018] Optionally, the FPGA is specifically used for:

[0019] When receiving a real-time resistance simulation instruction sent by a host computer, determining a historical resistance simulation instruction, wherein the historical resistance simulation instruction is a resistance simulation instruction received on the FPGA;

[0020] If the real-time resistance value to be simulated indicated by the real-time resistance simulation instruction is not equal to the historical resistance value to be simulated indicated by the historical resistance simulation instruction, the resistance value to be simulated is sent to the serial-parallel conversion circuit.

[0021] Optionally, the resistance simulation channel further includes an isolation circuit, and the FPGA, the isolation circuit, the serial-to-parallel conversion circuit and the switch resistor array are connected in sequence; the isolation circuit is used to isolate the electrical connection between the FPGA and the resistance simulation channel.

[0022] Optionally, the resistance simulation module includes multiple resistance simulation channels, and there is electrical isolation between the multiple resistance simulation channels.

[0023] In a second aspect, the present application discloses a resistance temperature detector (RTD) simulator, wherein the RTD simulator includes the resistance simulation module as described in the first aspect.

[0024] Optionally, the RTD simulator further includes a pulse output channel; the pulse output channel includes an optical coupling module, and the optical coupling module is connected to the field programmable gate array FPGA;

[0025] The optical coupling module is used to generate an isolated pulse signal when detecting a change in the resistance value output by the resistance simulation channel.

[0026] Optionally, the optical coupling module is specifically used for:

[0027] When a change in the resistance value output by the resistance simulation channel is detected, an isolation pulse signal is generated after a preset time length, wherein the preset time length is used to minimize the time difference between the rising edge of the isolation pulse signal and the change moment of the resistance value change.

[0028] Compared with the existing technology, this application has the following beneficial effects:

[0029] An embodiment of the present application provides a resistance simulation module and a resistance temperature detector (RTD) simulator. The resistance simulation module includes: a field programmable gate array (FPGA) and a resistance simulation channel. The resistance simulation channel includes a serial-to-parallel conversion circuit and a switch resistor array. The switch resistor array includes a plurality of resistors and a plurality of switch tubes, and each resistor has a unique corresponding switch tube. The FPGA, the serial-to-parallel conversion circuit, and the switch resistor array are connected in sequence. The FPGA is used to receive a resistance simulation instruction sent by a host computer, wherein the resistance simulation instruction indicates a resistance value to be simulated. The serial-to-parallel conversion circuit is used to determine a code value to be simulated by performing parallel BCD encoding on the resistance value to be simulated. The switch resistor array is used to control a first switch combination corresponding to the code value to be simulated to be in an on state, and connect a first resistor combination corresponding to the first switch combination to simulate the resistance value to be simulated. Therefore, the resistance simulation module provided in the embodiment of the present application not only realizes high-precision, high-accuracy, and programmable resistance simulation functions, but also allows relevant technicians to configure different resistance values to be simulated through the host computer without the need to manually adjust the physical resistance, greatly improving work efficiency. It also meets the strict requirements of high-precision detection fields such as nuclear power plants for resistance simulators, and can perform high-efficiency and high-accuracy T2 response time tests. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0031] Figure 1 A schematic diagram of a resistance simulation module provided in an embodiment of the present application;

[0032] Figure 2A A schematic diagram of the principle of an RTD simulator provided in an embodiment of the present application;

[0033] Figure 2B A functional schematic diagram of an RTD simulator provided in an embodiment of the present application;

[0034] Figure 3 A schematic diagram of a power supply circuit provided in an embodiment of the present application;

[0035] Figure 4 A schematic diagram of a switch resistor array provided in an embodiment of the present application;

[0036] Figure 5A A schematic diagram of the appearance of an RTD simulator provided in an embodiment of the present application;

[0037] Figure 5B A schematic diagram of the dimensions of an RTD simulator provided in an embodiment of the present application;

[0038] Figure 6 A schematic diagram of an RTD simulator interface provided in an embodiment of the present application. DETAILED DESCRIPTION

[0039] As previously mentioned, nuclear power plants typically use fixed resistance boxes to test the T2 response time of nuclear reactor protection systems. However, these boxes only provide preset fixed resistance values and cannot dynamically adjust resistance values according to test requirements. While technicians can simulate varying resistance values by manually switching between different resistance box combinations, this manual operation is not only time-consuming and labor-intensive, but also prone to errors due to operator error, making it difficult to meet the requirements for high-efficiency and high-accuracy testing.

[0040] After research, the inventors proposed a resistance simulation module and a resistance temperature detector (RTD) simulator. The resistance simulation module includes: a field programmable gate array (FPGA) and a resistance simulation channel. The resistance simulation channel includes a serial-to-parallel conversion circuit and a switch resistor array. The switch resistor array includes a plurality of resistors and a plurality of switch tubes, and each resistor has a unique corresponding switch tube. The FPGA, the serial-to-parallel conversion circuit and the switch resistor array are connected in sequence; the FPGA is used to receive a resistance simulation instruction sent by a host computer, wherein the resistance simulation instruction indicates a resistance value to be simulated; the serial-to-parallel conversion circuit is used to determine a code value to be simulated by performing parallel BCD encoding on the resistance value to be simulated; the switch resistor array is used to control a first switch combination corresponding to the code value to be simulated to be in an on state, and connect a first resistor combination corresponding to the first switch combination to simulate the resistance value to be simulated. Therefore, the resistance simulation module provided in the embodiment of the present application not only realizes high-precision, high-accuracy, and programmable resistance simulation functions, but also allows relevant technicians to configure different resistance values to be simulated through the host computer without the need to manually adjust the physical resistance, greatly improving work efficiency. It also meets the strict requirements of high-precision detection fields such as nuclear power plants for resistance simulators, and can perform high-efficiency and high-accuracy T2 response time tests.

[0041] In order to help those skilled in the art better understand the present invention, the following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of this application.

[0042] Example 1 Resistance simulation module

[0043] See also Figure 1 , which is a schematic diagram of a resistance simulation module provided by an embodiment of the present application. Figure 1 As can be seen, the resistance simulation module 100 includes a field programmable gate array (FPGA) 101 and a resistance simulation channel 102. The resistance simulation channel 102 includes a serial-to-parallel conversion circuit 103 and a switch resistor array 104. The switch resistor array 104 includes a plurality of resistors and a plurality of switches, with each resistor having a unique corresponding switch. The FPGA 101, the serial-to-parallel conversion circuit 103, and the switch resistor array 104 are connected in sequence.

[0044] FPGA 101 is configured to receive a resistance simulation instruction from a host computer, wherein the resistance simulation instruction indicates a resistance value to be simulated. It is understood that the resistance value to be simulated can be static (i.e., a single resistance value to be simulated) or dynamic (i.e., a sequence of resistance values to be simulated) to meet the needs of different test scenarios. This application does not limit this.

[0045] In one specific implementation, FPGA 101 not only receives real-time resistance simulation instructions but also records and compares historical resistance simulation instructions. Specifically, when FPGA 101 receives a real-time resistance simulation instruction, it first checks whether the real-time resistance simulation instruction is identical to the historical resistance simulation instruction (referring to the resistance simulation instruction last received by FPGA 101). If they are different, it indicates that the resistance value to be simulated needs to be updated. At this time, FPGA 101 sends the new resistance value to be simulated to serial-to-parallel conversion circuit 103. This mechanism ensures that the resistance simulation module 102 only responds to changing resistance simulation instructions, improving the efficiency and stability of the resistance simulation module.

[0046] The serial-to-parallel conversion circuit 103 is used to determine the simulated coded value by performing parallel BCD encoding on the resistance value to be simulated. BCD encoding is a coding method that uses 4 binary digits to represent 1 decimal digit and is suitable for representing values that require high precision, such as resistance values.

[0047] In a specific implementation, since the resistance value to be simulated is usually multi-digit, the serial-to-parallel conversion circuit 103 is specifically used to: convert each decimal digit of the resistance value to be simulated into a BCD code of a binary number, and splice the converted BCD codes to determine the code value to be simulated. Next, take the resistance value to be simulated as a 4-digit decimal number (hundreds, tens, units, decimal place) as an example for explanation: the first step is to decompose the resistance value to be simulated into hundreds, tens, units, and decimal places. For example, if the resistance value to be simulated is 123.4Ω, the resistance value to be simulated needs to be decomposed into: hundreds digit 1, tens digit 2, units digit 3, decimal place 4. The second step is to perform BCD encoding on the hundreds digit, tens digit, units digit, and decimal place respectively. For example, if the hundreds digit is 1, the tens digit is 2, the units digit is 3, and the decimal place is 4, then the encoding is 0001, 0010, 0011, 0100. The third step is to splice the converted BCD codes to determine the code value to be simulated.

[0048] The switch resistor array 104 is used to control a first switch combination corresponding to the code value to be simulated to be in an on state, and connect a first resistor combination corresponding to the first switch combination to simulate the resistance value to be simulated.

[0049] Each resistor in the switch resistor array 104 has a unique corresponding switch transistor, which is precisely controlled by the FPGA 101. For example, if the code value to be simulated is 0001001000110100, the FPGA 101 will control the switch resistor array 104 to turn on the corresponding 100Ω, 20Ω, 3Ω, and 0.4Ω resistor combinations.

[0050] The resistor network in the switch resistor array 104 is scientifically grouped, including hundreds (200Ω, 100Ω), tens (90Ω to 10Ω), units (9Ω to 1Ω), and decimals (0.9Ω to 0.1Ω), ensuring high-precision output over the entire range.

[0051] It should be noted that due to the resistor manufacturing process, temperature changes, or parasitic resistance in the circuit (such as wire resistance, contact resistance), there may be deviations between the theoretical value and the actual value of the resistor in the on state. In the embodiment of the present application, the following calibration method can be used to compensate for these deviations and improve the accuracy of the resistor simulation:

[0052] FPGA101 first determines that the difference between the actual resistance value and the theoretical resistance value of the target resistance combination is the deviation resistance value. For example, the theoretical resistance value of the target resistance combination A is 123.4Ω, and the actual resistance value is 123.6Ω, then the deviation resistance value is +0.2Ω. Subsequently, the serial-to-parallel conversion circuit 103 is used to determine the deviation coding value by performing parallel BCD encoding on the deviation resistance value. For example, the deviation resistance value of 0.2Ω is encoded as 0010. Finally, the switch resistor array 104 is used to adjust the resistance combination accordingly according to the positive and negative of the deviation coding value. Specifically, if the deviation coding value is a negative number, indicating that the actual resistance value is too small, the second switch combination is controlled to be in the on state, and the second resistance combination corresponding to the second switch combination is connected to simulate the resistance value to be simulated (i.e., an additional resistor is connected to increase the actual resistance value). If the deviation code value is a positive number, indicating that the actual resistance value is too large, the third switch combination corresponding to the deviation code value in the first switch combination is controlled to be in an off state, and the third resistor combination corresponding to the third switch combination is disconnected to simulate the resistance value to be simulated (i.e., the connected resistance value is reduced to reduce the actual resistance value).

[0053] In a specific implementation, the above compensation steps can be implemented using FPGA 101. The parallel processing capability of FPGA 101 can achieve fast and real-time calibration to meet high-precision requirements.

[0054] In another specific implementation, first, the deviation between the actual resistance value and the theoretical resistance value can be quantified by using software to execute an error calculation algorithm using the following code:

[0055] float calculate_error(float target,float actual){

[0056] return actual-target; / / Return the deviation resistance value (actual resistance value - target resistance value)

[0057] }

[0058] Subsequently, the compensation value generation algorithm can be used to guide the FPGA 101 to adjust the switch resistor array 104 through the following code:

[0059] float generate_compensation(float error){

[0060] return-error; / / Reverse compensation (when the error is +0.2Ω, compensate -0.2Ω)

[0061] }

[0062] It should be noted that after determining the deviation resistance value and the deviation code value, the deviation resistance value and the deviation code value can also be stored in a non-volatile memory such as EEPROM so that they can be quickly called when needed, thereby improving the response speed and calibration efficiency of the resistance simulation module.

[0063] It should also be noted that resistance simulation channel 102 also includes an isolation circuit, and FPGA 101, the isolation circuit, the serial-to-parallel conversion circuit 103, and the switch resistor array 104 are sequentially connected. The isolation circuit is used to isolate the electrical connection between FPGA 101 and resistance simulation channel 102, thereby improving the safety and stability of the resistance simulation module.

[0064] It should also be noted that the above embodiment uses an example in which the resistance simulation module includes a single resistance simulation channel. In actual applications, the resistance simulation module may include multiple resistance simulation channels, each electrically isolated from the other. This allows for simultaneous simulation of multiple resistance values, meeting the needs of various test scenarios.

[0065] To sum up, the embodiment of the present application provides a resistance simulation module. The resistance simulation module provided by the embodiment of the present application not only realizes high-precision, high-accuracy, and programmable resistance simulation functions, but also allows relevant technicians to configure different resistance values to be simulated through a host computer without the need to manually adjust the physical resistance, which greatly improves work efficiency. It also meets the strict requirements of high-precision detection fields such as nuclear power plants for resistance simulators, and can perform high-efficiency and high-accuracy T2 response time tests.

[0066] Example 2 RTD simulator

[0067] See also Figure 2A , which is a schematic diagram of the principle of an RTD simulator provided in an embodiment of the present application. Figure 2B , which is a functional schematic diagram of an RTD simulator provided in an embodiment of the present application.

[0068] The RTD simulator includes FPGA, resistance simulation channel, pulse output channel, etc.

[0069] First, let's explain the J1, J2, J3, and J4 interfaces of the RTD simulator:

[0070] J1 is the power input interface. The power input from J1 interface is converted into DC voltages such as +3.3V and +5V by the power circuit, thus providing a stable power supply for the components inside the RTD simulator.

[0071] See also Figure 3 , which is a schematic diagram of a power supply circuit provided by an embodiment of the present application. Figure 3 It can be seen that the power supply circuit includes a protection circuit, an isolated power supply module, two channel isolated power supplies (for example, can be represented as channel isolated power supply 1 and channel isolated power supply 2) and a low dropout regulator (Low Dropout Regulator, LDO).

[0072] Specifically, the protection circuit is used to provide reverse polarity protection and electromagnetic interference (EMI) filtering for the input voltage. Reverse polarity protection refers to a protective feature in which electronic equipment automatically detects and takes appropriate measures to prevent damage or malfunction when the power or signal polarity is reversed. EMI filtering is the process of suppressing or eliminating electromagnetic interference generated internally and externally by electronic equipment or systems through specific circuits or devices. Secondly, the isolated power supply module converts the voltage to VCC5V. Subsequently, the two-channel isolated power supply converts VCC5V to +5V for two isolated channels. Furthermore, the LDO converts VCC5V to VCC3V3. Thus, the power supply circuit can convert the input voltage (9V to 36V) into VCC5V CH1, VCC5V CH2, and VCC3V3. VCC5V_CH1 and VCC5V_CH2 are used by the two-channel isolated power supply, while VCC3V3 is used by the FPGA and RS485 chip.

[0073] J2 is the Modbus communication interface. It connects the host computer to the RS485 chip, enabling communication between the host computer and the FPGA. Using the Modbus protocol, the host computer can send resistance simulation commands and receive status information from the RTD simulator.

[0074] J3 and J4 are output interfaces, which are connected to the FPGA through the resistor analog channel and the pulse output channel.

[0075] Next, let's explain FPGA:

[0076] The FPGA, the main control chip, is the core of the RTD simulator. It receives resistance simulation commands (which indicate the resistance value to be simulated) from the host computer via the RS485 chip. Furthermore, the FPGA controls various functional modules (including the resistance simulation channel and pulse output channel) based on these electronic simulation commands.

[0077] Then, the resistance simulation channel is explained:

[0078] The resistor simulation channel includes an isolation circuit, a serial-to-parallel conversion circuit, and a switched resistor array. Specifically, the isolation circuit isolates the electrical connection between the FPGA and the resistor simulation channel, improving safety and stability. The isolation circuit also includes a calibration circuit to improve the accuracy of the resistor simulation.

[0079] The serial-to-parallel conversion circuit is used to perform parallel BCD encoding on the resistance value to be simulated to determine the code value to be simulated. Specifically, the serial-to-parallel conversion circuit is used to convert each decimal digit of the resistance value to be simulated into a binary BCD code and concatenate the converted BCD codes to determine the code value to be simulated.

[0080] The switch resistor array includes several resistors and several switch tubes, and each resistor has a unique corresponding switch tube. The switch resistor array is used to control the first switch combination corresponding to the code value to be simulated to be in the on state, and connect the first resistor combination corresponding to the first switch combination to simulate the resistance value to be simulated.

[0081] In a specific implementation, the FPGA is further used to determine the difference between the actual resistance value and the theoretical resistance value of the target resistor combination as a deviation resistance value; the serial-to-parallel conversion circuit is further used to determine the deviation coding value by performing parallel BCD encoding on the deviation resistance value; the switch resistor array is further used to, if the deviation coding value is a negative number, control the second switch combination to be in an on state and connect the second resistor combination corresponding to the second switch combination to simulate the resistance value to be simulated. If the deviation coding value is a positive number, control the third switch combination corresponding to the deviation coding value in the first switch combination to be in an off state and disconnect the third resistor combination corresponding to the third switch combination to simulate the resistance value to be simulated. In this way, these deviation resistance values can be compensated and the accuracy of the resistance simulation can be improved.

[0082] See also Figure 4 , which is a schematic diagram of a switch resistor array provided by an embodiment of the present application. Figure 4As you can see, a switched resistor array consists of several resistors and several switches, with each resistor having a unique corresponding switch. The FPGA can control the switched resistor array, which in turn controls the switches to switch the resistors on and off (i.e., each resistor is connected to the circuit via its corresponding switch).

[0083] It should be noted that in order to improve accuracy, a resistor with higher resolution can be used in the decimal place (such as Figure 4 The values of R12 and R15 in the circuit are 0.05Ω and 0.025Ω respectively, and the number of digits of the BCD code is increased (such as five digits, six digits, etc.). This application does not limit this.

[0084] Finally, the pulse output channel is explained:

[0085] The pulse output channel includes an optocoupler module connected to the FPGA. When the resistance value output by the resistor analog channel changes, the optocoupler module generates an isolated pulse signal. This signal can be used to trigger other devices or as a status indicator.

[0086] In a specific implementation, due to the inherent delays in the compensation circuit, such as the turn-on delay of the MOS switch tube (typical value 300-500ns), the signal transmission delay (about 200ns), and the response time of the optocoupler itself (50-100ns), the optocoupler module can also generate an isolated pulse signal after a preset time when a change in the resistance value output by the resistor analog channel is detected. The preset time is used to minimize the time difference between the rising edge of the isolated pulse signal and the moment when the resistance value changes. Therefore, in key applications such as nuclear power protection system testing, it is necessary to accurately measure the response time (T2 time) from the change in the sensor signal to the action of the protection device. This application ensures the reliability of time measurement.

[0087] In a specific implementation, Figure 2B As shown, when the host computer sends a new resistance simulation instruction to the FPGA via the Modbus protocol, the FPGA receives and parses the resistance simulation instruction and compares the real-time resistance value to be simulated indicated by the real-time resistance simulation instruction with the historical resistance simulation instruction (the resistance simulation instruction received on the FPGA). If they are equal, no action is triggered. If they are not equal, the resistance value to be simulated is sent to the serial-to-parallel conversion circuit. Thus, this mechanism ensures that the resistance simulation module 102 only responds to the changing resistance simulation instruction, improving the efficiency and stability of the resistance simulation module.

[0088] In a specific implementation, the resistance simulation channel further includes an isolation circuit, and the FPGA, the isolation circuit, the serial-to-parallel conversion circuit, and the switch resistor array are connected in sequence; the isolation circuit is used to isolate the electrical connection between the FPGA and the resistance simulation channel.

[0089] In a specific implementation, the resistance simulation module includes a plurality of resistance simulation channels, and electrical isolation exists between the plurality of resistance simulation channels.

[0090] In a specific implementation, the simulator communicates with the host computer via the Modbus protocol and responds to specific function codes to perform different operations. The function codes responded by the RTD simulator and their functions are shown in Table 1 below:

[0091] Table 1

[0092]

[0093] The register addresses, data types, and function descriptions in the RTD simulator are shown in Table 2 below:

[0094] Table 2

[0095]

[0096]

[0097] For example, to read the current resistance value of channel 1, send the function code 0x03 + address 0. To set the resistance of channel 2 to 150.25Ω, send the function code 0x06 + address 1 + value 15025 (due to 0.01Ω / code value).

[0098] Therefore, through the Modbus protocol and these function codes and registers, the host computer can easily communicate with the RTD simulator to realize operations such as reading and setting the resistance value and adjusting the pulse width.

[0099] See also Figure 5A , which is a schematic diagram of the appearance of an RTD simulator provided in an embodiment of the present application. Figure 5B , which is a schematic diagram of the size of an RTD simulator provided in an embodiment of the present application. Figure 5A and Figure 5B This is only an illustration of an RTD simulator, and this application does not limit this.

[0100] See also Figure 6 , which is a schematic diagram of an RTD simulator interface provided in an embodiment of the present application. Figure 6 P1 and P2 are pulse output interfaces, R1 and R2 are resistance output interfaces, A, B, and G are Modbus RS485 communication line interfaces, and POW+ / POW- are power input interfaces.

[0101] To sum up, the embodiment of the present application provides an RTD simulator, which not only realizes high-precision, high-accuracy, and programmable resistance simulation function, but also allows relevant technicians to configure different resistance values to be simulated through a host computer without the need to manually adjust the physical resistance, greatly improving work efficiency. It also meets the strict requirements of high-precision detection fields such as nuclear power plants for resistance simulators, and can perform high-efficiency and high-accuracy T2 response time tests.

[0102] The above is a detailed introduction to a resistance simulation module and a resistance temperature detector RTD simulator provided by the present application. The various embodiments in the specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same and similar parts between the various embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part description. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of this application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the scope of protection of the claims of this application.

[0103] It should also be noted that, in this specification, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variants thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus comprising the element.

[0104] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application should be included in the scope of protection of the present application.

Claims

1. A resistance simulation module, characterized in that: The resistance simulation module includes: a field programmable gate array (FPGA) and a resistance simulation channel, the resistance simulation channel includes a serial-to-parallel conversion circuit and a switch resistor array, the switch resistor array includes a plurality of resistors and a plurality of switch tubes, and each resistor has a unique corresponding switch tube, the FPGA, the serial-to-parallel conversion circuit and the switch resistor array are connected in sequence; The FPGA is used to receive a resistance simulation instruction sent by a host computer, wherein the resistance simulation instruction indicates a resistance value to be simulated; The serial-to-parallel conversion circuit is used to determine the code value to be simulated by performing parallel BCD encoding on the resistance value to be simulated; The switch resistor array is used to control a first switch combination corresponding to the code value to be simulated to be in an on state, and connect a first resistor combination corresponding to the first switch combination to simulate the resistance value to be simulated.

2. The resistance simulation module according to claim 1, wherein: The FPGA is further configured to determine a difference between an actual resistance value and a theoretical resistance value of the target resistor combination as a deviation resistance value; The serial-to-parallel conversion circuit is further configured to determine a deviation coding value by performing parallel BCD coding on the deviation resistance value; The switch resistor array is further configured to, if the deviation coding value is a negative number, control the second switch combination to be in an on state, and connect the second resistor combination corresponding to the second switch combination to simulate the resistance value to be simulated.

3. The resistance simulation module according to claim 2, characterized in that: The switch resistor array is further used for: If the deviation code value is a positive number, the third switch combination corresponding to the deviation code value in the first switch combination is controlled to be in an off state, and the third resistor combination corresponding to the third switch combination is disconnected to simulate the resistance value to be simulated.

4. The resistance simulation module according to claim 1, wherein: The serial-to-parallel conversion circuit is specifically used for: The code value to be simulated is determined by converting each decimal digit of the resistance value to be simulated into a BCD code of a binary number and splicing the converted BCD codes.

5. The resistance simulation module according to claim 1, wherein: The FPGA is specifically used for: When receiving a real-time resistance simulation instruction sent by a host computer, determining a historical resistance simulation instruction, wherein the historical resistance simulation instruction is a resistance simulation instruction received on the FPGA; If the real-time resistance value to be simulated indicated by the real-time resistance simulation instruction is not equal to the historical resistance value to be simulated indicated by the historical resistance simulation instruction, the resistance value to be simulated is sent to the serial-parallel conversion circuit.

6. The resistance simulation module according to claim 1, wherein: The resistance simulation channel also includes an isolation circuit, and the FPGA, the isolation circuit, the serial-to-parallel conversion circuit and the switch resistor array are connected in sequence; the isolation circuit is used to isolate the electrical connection between the FPGA and the resistance simulation channel.

7. The resistance simulation module according to claim 1, wherein: The resistance simulation module includes a plurality of resistance simulation channels, and electrical isolation exists between the plurality of resistance simulation channels.

8. A resistance temperature detector (RTD) simulator, characterized in that: The RTD simulator comprises the resistance simulation module according to any one of claims 1 to 7.

9. The RTD simulator according to claim 8, wherein: The RTD simulator further includes a pulse output channel; the pulse output channel includes an optical coupling module, and the optical coupling module is connected to the field programmable gate array FPGA; The optical coupling module is used to generate an isolated pulse signal when detecting a change in the resistance value output by the resistance simulation channel.

10. The RTD simulator according to claim 9, wherein the optical coupler module is specifically used for: When it is detected that the resistance value output by the resistance simulation channel changes, an isolation pulse signal is generated after a preset time period, wherein, The preset duration is used to minimize the time difference between the rising edge of the isolation pulse signal and the changing moment of the resistance value.

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