FPGA-based RBF neural network PID parameter setting method
By deploying the RBF neural network on the FPGA, adopting a three-stage pipeline structure and Taylor expansion to fit the radial basis function, the problem of difficult parameter tuning of the traditional PID controller in nonlinear time-varying systems is solved, the adaptive adjustment of PID parameters is achieved, and the real-time and adaptability of the control system are improved.
Patent Information
- Application Number
- CN202510857279.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2025-06-25
- Publication Date
- 2025-10-17
- Estimated Expiration
- 2045-06-25
AI Technical Summary
Traditional PID controllers have difficulty in parameter tuning and slow dynamic response in nonlinear and time-varying systems. Existing neural network-based PID control methods are difficult to meet the real-time requirements of industrial scenarios.
An FPGA-based RBF neural network PID parameter tuning method is adopted. The RBF neural network is deployed on the FPGA through the Verilog language. A three-stage pipeline structure design is used to collect the error signal and its differential in real time. The hidden layer calculates the nonlinear mapping in parallel, and the output layer linearly combines to generate PID parameters. The Taylor expansion is combined to fit the radial basis function.
It improves the real-time performance and efficiency of PID parameter tuning, realizes the adaptive adjustment of PID parameters, enhances the adaptability and robustness of the control system, and can better cope with complex and changing industrial environments.
Smart Images
Figure CN120428540B_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The application belongs to the field of intelligent control and FPGA embedded system, and particularly relates to a RBF neural network PID parameter setting method based on FPGA. BACKGROUND
[0002] Limitations of PID control
[0003] The traditional PID controller has problems such as difficult parameter setting and slow dynamic response in nonlinear and time-varying systems. Although the existing PID control method based on neural network has been proposed, the existing scheme is mostly based on software simulation or general-purpose processor implementation, which is difficult to meet the real-time requirements of industrial scenes.
[0004] Advantages of FPGA technology
[0005] FPGA has the characteristics of parallel computing, low delay and hardware reconfigurability, and has verified its high efficiency in the fields of neural network acceleration, real-time signal processing and industrial control. SUMMARY
[0006] The purpose of the application is to provide a RBF neural network PID parameter setting method based on FPGA. The RBF neural network is deployed on the FPGA using the Verilog language, and the adaptive optimization of the control system is realized. Based on the Xilinx Zynq platform, the radial basis function of the hidden layer is calculated through the Taylor expansion formula. Simulation experiments show that the deployment of the RBF neural network is accurate and effective, and the significant advantages of FPGA hardware acceleration in dynamic parameter setting are verified. The application solves the problem that the parameters of the traditional PID controller are fixed, the local control effect is good but the overall control effect is poor, and realizes the adaptive adjustment of the PID parameters through the RBF neural network. This multi-module collaborative design not only improves the calculation efficiency, but also ensures the accuracy of the calculation, so that the hidden layer can quickly and accurately complete the complex nonlinear mapping task.
[0007] To achieve the above purpose, the application adopts the following technical solutions and implementation steps:
[0008] The system realizes the deployment of the RBF-PID neural network algorithm based on FPGA, adopts a three-stage pipeline structure design: the input layer collects error signals (e(k)) and their derivatives (Δe(k)) in real time, the hidden layer constructs six Gaussian kernel functions to calculate the nonlinear mapping in parallel, and the output layer generates PID parameters (Kp, Ki, Kd) through linear combination; based on the Xilinx Zynq platform, the radial basis function of the hidden layer is fitted through the Taylor expansion formula and deployed to the FPGA, and the specific process includes the following steps:
[0009] Step 1: setting of the input layer, the specific process is as follows:
[0010] 1-1: input signal buffer
[0011] Register the actual value and the set value of the input, ensure the stability and synchronization of the data, and prepare for the subsequent error calculation;
[0012] 1-2: error calculation
[0013] Calculate the error between the set value and the actual value in real time, that is, the error value at the current time;
[0014] 1-3: error rate calculation
[0015] Calculate the error rate, that is, the difference between the error values of the adjacent two times, to reflect the dynamic change of the error;
[0016] 1-4: enable signal processing
[0017] Generate the output enable signal of the module by delaying the received enable signal, to control the output time of the data and ensure that the data is received by the subsequent module at the appropriate time point.
[0018] Step 2: The setting of the exponential calculation preprocessing module is mainly to preprocess the input error signal and error rate signal, calculate the exponential part of the radial basis function as formula (1), and the specific process includes the following sub-modules:
[0019]
[0020] where, is the radial basis function, , is a one-dimensional vector representing the input of two RBF networks, which are the error signal e(k) and its differential Δe(k), respectively, is the center value of the radial basis function, is the width of the radial basis function;
[0021] 2-1: enable signal processing
[0022] Delay the enable signal to generate enable signals at different stages, which are used to control the timing of the subsequent calculation process;
[0023] 2-2: error offset calculation
[0024] When the input enable signal is valid, calculate the difference between the error signal and the center value C in the radial basis function, and the difference between the error rate and the center value C, respectively;
[0025] 2-3: square calculation and denominator calculation
[0026] When the enable signal is valid, the square of the two difference values calculated in step 2-2 is stored in the corresponding register respectively; at the same time, the square of the parameter b is multiplied by 2, and the result is stored in the register, which is used as the denominator of the subsequent division operation;
[0027] 2-4: molecular calculation
[0028] When the enable signal is valid, the square of the two difference values calculated in step 2-3 is added to obtain the result stored in the register, which is used as the numerator of the subsequent division;
[0029] 2-5: fast division calculation module, calculate the quotient and remainder of the given dividend and divisor, the sub-modules are as follows:
[0030] 2-5-1: state definition
[0031] A plurality of states are defined for controlling the process of division operation, including idle (S0), shift (S1), judge (S2), expand (S3), calculate (S4), update (S5), error (S6) and success (S7);
[0032] 2-5-2: find the highest significant bit function
[0033] A function for finding the highest significant bit is defined, which is used to find the position of the highest significant bit of the given data, which is very important for determining the bit width and performing unique operations;
[0034] 2-5-3: judge data distance function
[0035] A function for judging the distance between two data is defined, which is used to determine the bit displacement distance between two data by comparing the highest significant bits of the two data;
[0036] 2-5-4: register initialization
[0037] Initialize the registers, including the dividend register, the divisor register, the divisor holding register, the remainder register, the shift register, the judge flag register, and the quotient register;
[0038] 2-5-5: state machine control
[0039] A finite state machine is used to control the flow of division operation. The state machine determines the next state according to the current state and the judge flag;
[0040] In the idle state (S0), if the start division signal is valid, enter the shift state (S1);
[0041] In the shift state (S1), calculate the bit displacement distance between the dividend and the divisor;
[0042] In the judging state (S2), according to the conditions whether the divisor is 0, whether the dividend is less than the divisor, etc., it is decided to enter the error state (S6), the success state (S7) or the expanding state (S3);
[0043] In the expanding state (S3), the divisor is left shifted to expand the bit;
[0044] In the calculating state (S4), the remainder of the dividend minus the divisor is calculated;
[0045] In the updating state (S5), the values of the dividend and the divisor are updated, and the quotient is accumulated;
[0046] 2-5-6: Division operation execution
[0047] If the start division signal is valid and the current state is the idle state, the dividend and the divisor are stored in the corresponding registers respectively, and the bit shift distance is calculated; according to the next state of the state machine, the corresponding operation is performed, including shifting, judging, expanding, calculating the remainder and updating the quotient;
[0048] 2-5-7: Output result
[0049] According to the current state of the state machine, the quotient, the remainder, the division completion signal and the error flag are output; in the error state (S6), the error flag is output and the quotient and the remainder are cleared; in the success state (S7), the quotient and the remainder are output, and the division completion signal is set;
[0050] 2-6: Exponent result calculation
[0051] The complement of the quotient is negated and 1 is added, and then stored in the corresponding exponent result intermediate variable, the purpose is to change this value into a negative number, because the radial basis function exponent part has a negative sign in front;
[0052] 2-7: Exponent result output
[0053] When the output enable signal is valid, the six exponent result intermediate variables are respectively assigned to the six output exponent results.
[0054] Step 3: Setting of the exponent judging preprocessing module, the main function of the module is to judge the exponent output by the exponent calculation preprocessing module, to provide the exponent value of the nearest expansion point and the point to be sought for the subsequent Taylor expansion module, the specific process includes the following sub-modules:
[0055] 3-1: Enable signal processing
[0056] The enable signal is delayed to generate enable signals at different stages, which are used to control the timing of the subsequent calculation process;
[0057] 3-2: Exponent negation
[0058] The input exponential result is negated and stored in the register, because the exponential part of the radial basis function is negative, and after negation it becomes positive, which is convenient for subsequent calculation;
[0059] 3-3: Determine the nearest expansion point
[0060] The value of the high four bits of the exponential result in the register of step 3-2 is added by one to determine the nearest expansion point, and the corresponding expansion point index value is stored in the register. This step is to determine which predefined expansion point to perform Taylor expansion calculation near, so as to improve the calculation accuracy and efficiency;
[0061] 3-4: Calculate the offset
[0062] Subtract 4095 (4095 corresponds to binary 12-bit full 1) from the low 12 bits of the value of the exponential result in the register of step 3-2. The value of this register represents the offset of the point to be calculated relative to the nearest expansion point, which is used for subsequent Taylor expansion calculation. The offset here is between 0 and 1;
[0063] 3-5: Output enable signal control
[0064] When the delay signal of the enable signal is valid, the output enable signal is generated to control the timing of the module output, which is convenient for the subsequent Taylor expansion module to further process
[0065] Step 4: Setting of Taylor expansion module. This module uses Taylor series expansion to calculate the approximate value of the exponential function according to the expansion value and offset provided by the index judgment preprocessing module. The specific process includes the following sub-modules:
[0066] 4-1: Enable signal delay processing
[0067] Delay processing of the enable signal to generate enable signals at different stages for controlling the timing of the subsequent calculation process;
[0068] 4-2: Exponential value registration
[0069] Store the input exponential value in the register to ensure that the exponential value used in subsequent calculations is the latest;
[0070] 4-3: Initialize Taylor expansion calculation
[0071] Set the initial term of Taylor expansion to 4095, because 4095 corresponds to binary 12-bit full 1;
[0072] 4-4: Calculation of each term of Taylor expansion
[0073] The calculation of the first to seventh terms of Taylor expansion is completed through addition, multiplication and shift operation, because the offset is between 0 and 1, so the expansion at zero point is selected;
[0074]
[0075] 4-5: Final result calculation
[0076] The final calculation result is input into the register to obtain the final Taylor expansion approximation value;
[0077] 4-6: Output enable signal control
[0078] When the delay signal of the enable signal is valid, the output enable signal becomes valid; ensure that the final result is stable and is output to the subsequent module at the right time for further processing.
[0079] Step 5: Setting of the hidden layer output module, which is a post-processing module for the exponential function approximation value calculated by the Taylor expansion module, combined with the exponential value of the nearest expansion point, to obtain the final exponential calculation result, the specific process includes the following sub-modules:
[0080] 5-1: Enable signal registration
[0081] Put the input enable signal into the register, which is used to synchronize the subsequent calculation process and ensure data processing within the time period when the enable signal is valid;
[0082] 5-2: Intermediate result calculation
[0083] When the input enable signal is valid, multiply the input exponential value of the nearest expansion point and the Taylor expansion calculation result, and store the result in the register to obtain the complete exponential calculation result;
[0084] 5-3: Final result output and enable signal control
[0085] Right shift the result in the register of step 5-2 by 12 bits as the final exponential calculation result output, and adjust the numerical precision back to Q12: At the same time, set the output enable signal to ensure that only during the time period when the enable signal is valid, the valid exponential calculation result will be output, avoiding incorrect data transmission.
[0086] Step 6: Output layer module setting, which is a module that weights and sums the six intermediate results calculated by the hidden layer, and performs amplitude limiting on the summed result, finally outputs as PID control parameters (Kp, Ki, Kd), which is the following sub-modules:
[0087] 6-1: Enable signal processing
[0088] Delay processing of the enable signal to generate enable signals at different stages for controlling the timing of the subsequent calculation process;
[0089] 6-2: Weighted calculation
[0090] When the input enable signal is valid, the input six intermediate results are multiplied by the corresponding weight parameters respectively, to obtain six weighted values;
[0091] 6-3: Intermediate sum calculation
[0092] When the delay signal of the enable signal is valid, the first three weighted values are added, and the last three weighted values are added, in order to simplify the subsequent sum calculation.
[0093] 6-4: Sum calculation and clipping processing
[0094] When the delay signal of the enable signal is valid, the two values of step 6-3 are added to obtain the sum, and clipping processing is performed to ensure that the output value is within a reasonable range, preventing excessively large or small values from affecting the stability of the control system;
[0095] 6-5: Result output and enable signal control
[0096] The value of step 6-4 is right shifted by 12 bits as the final output value, which is also to adjust the precision of the numerical value to Q12; At the same time, the output enable signal is set to ensure that only during the period when the enable signal is valid, the valid result will be output.
[0097] The beneficial effects of the present application are:
[0098] (1) The present application adopts a full FPGA architecture, which fully utilizes the parallel computing advantages of FPGA. Through the design of a three-stage pipeline structure, the error signal and its derivative are collected in real time in the input layer, the radial basis function is calculated in parallel in the hidden layer, and the PID parameter is generated by linear combination in the output layer, which significantly improves the real-time performance and efficiency of PID parameter tuning.
[0099] (2) In the implementation of the hidden layer, the present application adopts a unique four-level modular design: exponential calculation preprocessing module, exponential judgment preprocessing module, Taylor expansion module and hidden layer output module. This modular design not only improves the calculation efficiency, but also realizes the accurate calculation of the exponential function through Taylor expansion, avoiding the problem of insufficient calculation precision caused by traditional lookup table method.
[0100] (3) The output layer of the present application can generate PID parameters in real time according to the calculation results of the hidden layer, and has self-adaptive adjustment capability. Through the feedback mechanism, the system can dynamically optimize the PID parameters output by the RBF neural network according to the control effect, thereby improving the control effect. This mechanism greatly improves the adaptability and robustness of the control system, making it better cope with complex and variable industrial environments. BRIEF DESCRIPTION OF DRAWINGS
[0101] Figure 1It is a schematic diagram of an RBF neural network structure based on FPGA.
[0102] Figure 2 It is a whole simulation diagram of an input layer module of an RBF neural network based on FPGA.
[0103] Figure 3 It is a parameter verification simulation diagram of an input layer module of an RBF neural network based on FPGA.
[0104] Figure 4 It is an exponential calculation simulation diagram of an implicit layer module of an RBF neural network based on FPGA.
[0105] Figure 5 It is a radial basis output simulation result diagram of an implicit layer module of an RBF neural network based on FPGA.
[0106] Figure 6 It is a parameter input simulation diagram of an output layer module of an RBF neural network based on FPGA.
[0107] Figure 7 It is a parameter output simulation diagram of an output layer module of an RBF neural network based on FPGA.
[0108] Figure 8 It is a resource occupation diagram of RBF neural network deployment based on FPGA.
[0109] Figure 9 It is a flowchart of the present application. DETAILED DESCRIPTION
[0110] In order to make the purpose of the present application, the technical scheme and the gist more clear and explicit, the present application will be further described in detail below in combination with the drawings and the implementation examples. It should be understood that the specific implementation examples described herein are only used to explain the present application, and are not used to limit the present application.
[0111] The present system realizes the deployment of an RBF-PID neural network algorithm based on FPGA, adopts a three-stage pipeline structure design: the input layer collects error signals (e(k)) and their differentials (Δe(k)) in real time, the implicit layer constructs six Gaussian kernel functions and calculates the nonlinear mapping in parallel, and the output layer generates PID parameters (Kp, Ki, Kd) through linear combination. Based on the Xilinx Zynq platform, the radial basis function of the implicit layer is deployed into FPGA through Taylor expansion. Figure 1 It is a schematic diagram of an RBF neural network structure based on FPGA, which shows the structure and parameters of the deployed RBF neural network.
[0112] The implementation method of the system is as follows:
[0113] Step 1: Setting of the input layer, the specific process is as follows:
[0114] 1-1: Input signal buffer
[0115] The actual value and the set value of the input are registered to ensure the stability and synchronization of the data, and to prepare for the subsequent error calculation;
[0116] 1-2: Error calculation
[0117] The error between the set value and the actual value is calculated in real time, i.e. the error value at the current time;
[0118] 1-3: Error rate calculation
[0119] The error rate is calculated, i.e. the difference between the error values of the adjacent two time points, to reflect the dynamic change of the error;
[0120] 1-4: Enable signal processing
[0121] The output enable signal of the module is generated by delaying the received enable signal to control the output timing of the data, ensuring that the data is received by the subsequent module at the appropriate time point;
[0122] According to the simulation results of the input layer of the RBF neural network in Figure 2 and Figure 3 , the target speed is set to 1000 rpm, and the actual output speed can be seen from the simulation diagram, which can have a better tracking effect on the set speed; from Figure 3 , it can be seen that the position marked by the yellow solid line is set to 1000 rpm, the actual speed is 1013 rpm, the error is set-value-actual-value, which is -13, the current time error output calculation is correct, the error of the previous time is 2, so the error rate of the current time is -15, and the output is also correct; Therefore, the input layer of the deployed RBF network is correct.
[0123] Step 2: The setting of the exponential calculation preprocessing module is mainly to preprocess the input error signal and error rate signal, calculate the exponential part of the radial basis function as shown in formula (1), and the specific process includes the following sub-modules:
[0124]
[0125] where, is the radial basis function, , is a one-dimensional vector representing the input of the two RBF networks, which are the error signal e(k) and its differential Δe(k), is the center value of the radial basis function, is the width of the radial basis function;
[0126] 2-1: enable signal processing
[0127] The enable signal is delayed to generate different stage enable signals for controlling the timing of the subsequent calculation process;
[0128] 2-2: error offset calculation
[0129] When the input enable signal is valid, the difference between the error signal and the center value C in the radial basis function, and the difference between the error rate of change and the center value C, are calculated respectively;
[0130] 2-3: square calculation and denominator calculation
[0131] When the enable delay signal is valid, the square values of the two differences in step 2-2 are calculated respectively and stored in the corresponding registers; At the same time, the square of the parameter b is multiplied by 2, and then the result is stored in the register, which is used as the denominator of the subsequent division operation;
[0132] 2-4: numerator calculation
[0133] When the enable signal delay signal is valid, the result of adding the square values of the two differences calculated in step 2-3 is stored in the register, which is used as the numerator of the subsequent division;
[0134] 2-5: fast division calculation module, calculate the quotient and remainder of the given dividend and divisor, sub-modules as follows:
[0135] 2-5-1: state definition
[0136] A plurality of states are defined for controlling the process of division operation, including idle (S0), shift (S1), judge (S2), expand (S3), calculate (S4), update (S5), error (S6) and success (S7);
[0137] 2-5-2: find the highest significant bit function
[0138] Define a function to find the highest significant bit, which is used to find the position of the highest significant bit of the given data, which is very important for determining the bit width and performing unique operations;
[0139] 2-5-3: judge data distance function
[0140] Define a function to judge the distance between two data, which is used to determine the bit displacement distance between two data by comparing the highest significant bits of the two data;
[0141] 2-5-4: register initialization
[0142] Initialize various registers, including dividend register, divisor register, divisor hold register, remainder register, shift register, judge flag register, quotient register;
[0143] 2-5-5: State machine control
[0144] A finite state machine is used to control the flow of the division operation. The state machine decides the next state according to the current state and the judge flag;
[0145] In the idle state (S0), if the start division signal is valid, enter the shift state (S1);
[0146] In the shift state (S1), calculate the bit shift distance between the dividend and the divisor;
[0147] In the judge state (S2), according to the conditions whether the divisor is 0, whether the dividend is less than the divisor, etc., decide to enter the error state (S6), the success state (S7) or the expansion state (S3);
[0148] In the expansion state (S3), left shift the divisor to expand the bits;
[0149] In the calculation state (S4), calculate the remainder of the dividend minus the divisor;
[0150] In the update state (S5), update the values of the dividend and the divisor, and accumulate the quotient;
[0151] 2-5-6: Division operation execution
[0152] If the start division signal is valid and the current state is idle, store the dividend and the divisor in the corresponding registers, and calculate the bit shift distance; according to the next state of the state machine, perform the corresponding operation, including shift, judge, expand bits, calculate remainder and update quotient;
[0153] 2-5-7: Output result
[0154] According to the current state of the state machine, output the quotient, the remainder, the division completion signal and the error flag; in the error state (S6), output the error flag and clear the quotient and the remainder; in the success state (S7), output the quotient and the remainder, and set the division completion signal;
[0155] 2-6: Exponent result calculation
[0156] Store the one's complement of the quotient in the corresponding exponent result intermediate variable, the purpose is to change this value to a negative number, because the radial basis function exponent part has a negative sign in front;
[0157] 2-7: Exponent result output
[0158] When the output enable signal is valid, the six exponential results are assigned to the output of the six exponential results.
[0159] Step 3: Setting of the exponential judgment preprocessing module, the main function of which is to judge the exponential output by the exponential calculation preprocessing module, to provide the exponential value of the nearest expansion point and the point to be calculated for the subsequent Taylor expansion module, and the specific process includes the following sub-modules:
[0160] 3-1: Enable signal processing
[0161] The enable signal is delayed to generate enable signals at different stages, which are used to control the timing of the subsequent calculation process;
[0162] 3-2: Exponential negation
[0163] The input exponential result is negated and stored in the register, because the exponential part of the radial basis function is negative, and after negation it is positive, which is convenient for subsequent calculation;
[0164] 3-3: Judgment of the nearest expansion point
[0165] The high four bits of the exponential result in the register of step 3-2 are added by one to determine the nearest expansion point, and the corresponding expansion point exponential value is stored in the register. This step is to determine which predefined expansion point to perform Taylor expansion calculation around, in order to improve the calculation accuracy and efficiency;
[0166] 3-4: Calculation of offset
[0167] Subtract 4095 (4095 corresponds to full 1 of binary 12 bits) from the low 12 bits of the value of the exponential result in the register of step 3-2, which represents the offset of the point to be calculated relative to the nearest expansion point, and is used for subsequent Taylor expansion calculation. The offset here is between 0 and 1;
[0168] 3-5: Output enable signal control
[0169] When the delay signal of the enable signal is valid, the output enable signal is generated, which is used to control the timing of the module output, facilitating further processing by the subsequent Taylor expansion module
[0170] Step 4: Setting of the Taylor expansion module, which uses Taylor series expansion to calculate the approximate value of the exponential function according to the expansion value and offset provided by the exponential judgment preprocessing module, and the specific process includes the following sub-modules:
[0171] 4-1: Enable signal delay processing
[0172] The enable signal is delayed to generate enable signals at different stages, which are used to control the timing of the subsequent calculation process;
[0173] 4-2: Exponent value register
[0174] Store the input exponent value in the register to ensure the latest exponent value is used in the subsequent calculation;
[0175] 4-3: Initialization of Taylor expansion calculation
[0176] Set the initial term of Taylor expansion to 4095, because 4095 corresponds to 12-bit binary full 1;
[0177] 4-4: Calculation of each term of Taylor expansion
[0178] Complete the calculation of the first to seventh terms of Taylor expansion through addition, multiplication, and shift operations, because the offset is between 0 and 1, so choose to expand at zero;
[0179]
[0180] 4-5: Final result calculation
[0181] Input the final calculation result into the register to get the final Taylor expansion approximation value;
[0182] 4-6: Output enable signal control
[0183] When the delay signal of the enable signal is valid, the output enable signal becomes valid; ensure that the final result is stable and is output to the subsequent module for further processing at the right time point;
[0184] Step 5: Setting of the hidden layer output module, which is the post-processing of the exponential function approximation value calculated by the Taylor expansion module, combined with the exponent value of the nearest expansion point, to get the final exponential calculation result, the specific process includes the following sub-modules:
[0185] 5-1: Enable signal register
[0186] Put the input enable signal into the register, this step is used to synchronize the subsequent calculation process, to ensure that data processing is performed within the time period when the enable signal is valid;
[0187] 5-2: Intermediate result calculation
[0188] When the input enable signal is valid, multiply the input exponent value of the nearest expansion point and the Taylor expansion calculation result, and store the result in the register to get the complete exponential calculation result;
[0189] 5-3: Final result output and enable signal control
[0190] The result in the register of step 5-2 is right shifted by 12 bits to output the final exponent calculation result, and the numerical precision is adjusted back to Q12: at the same time, the output enable signal is set to ensure that only during the period when the enable signal is valid, the valid exponent calculation result is output, avoiding the error transmission of data.
[0191] Figure 4 And Figure 5 is the simulation result of the RBF neural network hidden layer, Figure 4 The position marked by the yellow solid line in expont shows -544, which is the output of the radial basis function exponent part, Figure 5 The position marked by the yellow solid line in result1 is the output of the first neuron in the hidden layer, and there are a total of 6 neurons in the hidden layer, so we only need to verify the correctness of one of them; we choose the output of the first neuron, according to the current error and error rate of change, the center value C11, C12 and the width b1, we can get the exponent calculation result at this time is -0.13285, then the Q12 precision used in FPGA, so we need to multiply a 12 times of 2, the result is -544.1536, which is consistent with the simulation result of the exponent of Figure 4 The output of the first neuron of the radial basis function is 0.875596421722, and after multiplying by 2 to the power of 12, it is 3586.44294337, which is consistent with the simulation result of result1 of Figure 5 Comparing the simulation results, the error is very small, which proves that the deployment of the RBF neural network hidden layer is correct.
[0192] Step 6: Output layer module setting, this module is to weight and sum the six intermediate results calculated by the hidden layer, and to limit the amplitude of the summed result, finally output the PID control parameters (Kp, Ki, Kd), which is the following sub-modules:
[0193] 6-1: enable signal processing
[0194] Delay processing of the enable signal to produce enable signals at different stages, used to control the timing of the subsequent calculation process;
[0195] 6-2: weighted calculation
[0196] When the input enable signal is valid, multiply the input six intermediate results by the corresponding weight parameters to get six weighted values;
[0197] 6-3: intermediate sum calculation
[0198] When the delay signal of the enable signal is valid, add the first three weighted values and the last three weighted values to simplify the subsequent sum calculation.
[0199] 6-4: Sum calculation and limiting processing
[0200] When the delay signal of the enable signal is valid, the two values of step 6-3 are added to obtain a sum, and limiting processing is performed to ensure that the output value is within a reasonable range, preventing excessively large or small values from affecting the stability of the control system;
[0201] 6-5: Result output and enable signal control
[0202] The value of step 6-4 is right-shifted by 12 bits as the final output value, which is also to adjust the precision of the numerical value to Q12; At the same time, the output enable signal is set to ensure that only during the period when the enable signal is valid, the valid result will be output;
[0203] Figure 6 And Figure 7 The simulation result graph of the output layer of the RBF neural network, since the output of RBF is the three parameters of PID, and is obtained by linear combination of the hidden layer output and weight, so in the simulation graph only the relevant signals of parameter P are pulled out to verify; From Figure 7 It can be seen that the outputs of the 6 radial basis functions of the hidden layer are 3832, 3832, 3782, 3782, 3782 and 3782, and the 6 weights of parameter P are 100, 100, 10, 100, 100 and 10, respectively. The value of P output in the simulation graph is 390, and the following theoretical calculation verification is performed. The linear addition of the hidden layer output and the weight is 1598440, which is divided by 2 raised to the power of 12 to convert it to Q12 precision format 390.244140625. It can be seen that the output layer deployment of RBF neural network is correct. Figure 8 The resource occupation graph of RBF neural network deployment implemented by FPGA.
[0204] The present application is a RBF neural network PID parameter tuning method based on FPGA, which provides a new solution for PID parameter tuning through reasonable system architecture design and efficient hardware implementation. This method has the advantages of fast calculation speed, high precision, strong adaptability, etc., which can significantly improve the performance and stability of the control system, and has broad application prospects in the field of industrial automation.
Claims
1. A RBF neural network PID parameter tuning method based on FPGA, characterized in that: The steps include: The system uses a three-stage pipeline structure: the input layer collects the error signal e(k) and its differential Δe(k) in real time, the hidden layer constructs a Gaussian kernel function to parallelly calculate the nonlinear mapping, and the output layer generates PID parameters through linear combination. Based on the Xilinx Zyn7020 platform, the radial basis function of the hidden layer is fitted using Taylor expansion and deployed on the FPGA. There are two input layers, namely error and rate of change of error; The number of neurons in the hidden layer is 6, which is used to realize the calculation of RBF radial basis function. The hidden layer includes four modules: exponential calculation preprocessing module, exponential judgment preprocessing module, Taylor expansion module and hidden layer output module; The exponential calculation preprocessing module is used to perform preliminary exponential operations on the input data. The exponential judgment preprocessing module determines the size range of the exponential part based on the data output by the exponential calculation preprocessing module, determines the most recently expanded data and the specific expansion position to be calculated; the Taylor expansion module will perform precise Taylor expansion calculations on the radial basis function to obtain accurate nonlinear mapping results; finally, the hidden layer output module calculates the final output result of the radial basis function; There are three output layers, which are the three parameters of PID: Kp, Ki, and Kd. The output layer generates the final PID parameters through linear combination according to the calculation results of the hidden layer.
2. The RBF neural network PID parameter tuning method based on FPGA according to claim 1, characterized in that: The input layer is set up as follows: 1-1: Input signal buffer Register the actual value and set value of the input; 1-2: Error calculation Calculate the error between the set value and the actual value in real time, that is, the error value at the current moment; 1-3: Error change rate calculation Calculate the rate of change of the error, that is, the difference between the error values at two adjacent moments, to reflect the dynamic changes of the error; 1-4: Enable signal processing By delaying the received enable signal, the module's output enable signal is generated to control the output timing of the data and ensure that the data is received by the subsequent module at the appropriate time.
3. The RBF neural network PID parameter tuning method based on FPGA according to claim 2, characterized in that: The exponential calculation preprocessing module is set up as follows: preprocess the input error signal and error change rate signal, and calculate the exponential part of the radial basis function as shown in formula (1): in, is the radial basis function, , Is a one-dimensional vector representing the input of the two RBF networks, which are the error signal e(k) and its differential Δe(k), is the center value of the radial basis function, is the width of the radial basis function; 2-1: Enable signal processing Delay processing of the enable signal to generate enable signals at different stages to control the timing of subsequent calculation processes; 2-2: Error offset calculation When the input enable signal is valid, the difference between the error signal and the center value C in the radial basis function, as well as the difference between the error change rate and the center value C are calculated respectively; 2-3: Square calculation and denominator calculation When the enable delay signal is valid, the square values of the two differences in step 2-2 are calculated respectively and stored in the corresponding registers respectively; at the same time, the square of parameter b is calculated and multiplied by 2, and then the result is stored in the register. This value is used as the denominator of the subsequent division operation; 2-4: Molecular Computing When the delay signal of the enable signal is valid, the result of adding the square values of the two differences calculated in steps 2-3 is stored in the register, and this value is used as the numerator of the subsequent division; 2-5: Fast division calculation module, calculates the quotient and remainder of a given dividend and divisor. The submodules are as follows: 2-5-1: Status Definition Define multiple states to control the process of division operation, including idle (S0), shift (S1), judgment (S2), expansion (S3), calculation (S4), update (S5), error (S6) and success (S7); 2-5-2: Find the most significant bit function Define a function to find the most significant bit, which is used to find the position of the most significant bit of the given data; 2-5-3: Determine data distance function Define a data distance judgment function to determine the displacement distance between two data. This function determines the number of bits that need to be shifted by comparing the most significant bits of the two data. 2-5-4: Register initialization Initialize each register, including the dividend register, divisor register, divisor holding register, remainder register, shift register, judgment flag register, and quotient register; 2-5-5: State Machine Control Use a finite state machine to control the process of division operation. The state machine determines the next state based on the current state and the judgment flag. In the idle state (S0), if the start division signal is valid, it enters the shift state (S1); In the shift state (S1), the displacement distance between the dividend and the divisor is calculated; In the judgment state (S2), the process enters the error state (S6), success state (S7) or extension state (S3) according to whether the divisor is 0 and whether the dividend is less than the divisor condition. In the extended state (S3), the divisor is shifted left to expand the position; In the calculation state (S4), the remainder of the dividend minus the divisor is calculated; In the update state (S5), the values of the dividend and divisor are updated, and the quotient is accumulated; 2-5-6: Division operation execution If the division start signal is valid and the current state is idle, the dividend and divisor are stored in the corresponding registers respectively, and the displacement distance is calculated; according to the next state of the state machine, the corresponding operations are performed, including shifting, judging, expanding, calculating the remainder and updating the quotient; 2-5-7: Output results According to the current state of the state machine, the quotient, remainder, division completion signal and error flag are output; in the error state (S6), the error flag is output and the quotient and remainder are cleared; in the success state (S7), the quotient and remainder are output and the division completion signal is set; 2-6: Index result calculation Take the complement of the quotient and add 1 to it, then store it in the corresponding exponential result intermediate variable to make this value negative; 2-7: Index result output When the output enable signal is valid, the six exponential result intermediate variables are assigned to the six output exponential results respectively.
4. The RBF neural network PID parameter tuning method based on FPGA according to claim 3, characterized in that: The setting method of the index judgment preprocessing module is as follows: 3-1: Enable signal processing Delay processing of the enable signal to generate enable signals at different stages to control the timing of subsequent calculation processes; 3-2: Exponent negation The input exponential result is inverted and stored in the register; 3-3: Determine the nearest expansion point The value obtained by adding one to the upper four bits of the exponent result in the register in step 3-2 is used to determine the nearest expansion point, and the corresponding expansion point exponent value is stored in the register; 3-4: Calculate the offset Subtract 4095 from the lower 12 bits of the exponent result of the register in step 3-2, and store the result in the register. The value of this register represents the offset of the point to be calculated relative to the nearest expansion point, which is used for subsequent Taylor expansion calculations. The offset here is between 0 and 1. 3-5: Output enable signal control When the delay signal of the enable signal is valid, an output enable signal is generated to control the timing of module output.
5. The RBF neural network PID parameter tuning method based on FPGA according to claim 4, characterized in that: The Taylor expansion module is set up as follows: 4-1: Enable signal delay processing Delay processing of the enable signal to generate enable signals at different stages to control the timing of subsequent calculation processes; 4-2: Index value storage Store the input exponent value in the register; 4-3: Initialize Taylor expansion calculation Set the initial term of Taylor expansion to 4095; 4-4: Calculations of Taylor expansion The calculation of the first to seventh terms of Taylor expansion is completed through addition, multiplication and shift operations, and the expansion is selected at zero point; 4-5: Final result calculation Input the final calculation result into the register to obtain the final Taylor expansion approximation; 4-6: Output enable signal control When the delayed version of the enable signal is valid, the output enable signal becomes valid.
6. The FPGA-based RBF neural network PID parameter tuning method according to claim 5, characterized in that: The setting method of the hidden layer output module is as follows: 5-1: Enable signal registration Put the input enable signal into the register; 5-2: Calculation of intermediate results When the input enable signal is valid, the exponential value of the input nearest expansion point is multiplied by the Taylor expansion calculation result, and the result is stored in the register to obtain the complete exponential calculation result; 5-3: Final result output and enable signal control Shift the result in the register in step 5-2 right by 12 bits to output the final exponential calculation result, and adjust the numerical precision back to Q12: At the same time, set the output enable signal to ensure that the valid exponential calculation result is output only during the time period when the enable signal is valid.
7. The FPGA-based RBF neural network PID parameter tuning method according to claim 6, characterized in that: The output layer module is set up as follows: 6-1: Enable signal processing Delay processing of the enable signal to generate enable signals at different stages to control the timing of subsequent calculation processes; 6-2: Weighted Calculation When the input enable signal is valid, the six intermediate results of the input are multiplied by the corresponding weight parameters to obtain six weighted values; 6-3: Intermediate sum calculation When the delayed signal of the enable signal is valid, the first three weighted values are added together, and the last three weighted values are added together; 6-4: Sum calculation and limit processing When the delayed signal of the enable signal is valid, the two values in step 6-3 are added together to obtain a sum, and a limiting process is performed; 6-5: Result output and enable signal control Shift the value in step 6-4 right by 12 bits as the final output value, adjust the precision of the value to Q12; and set the output enable signal at the same time.