A dynamic pole-compensated LDO circuit

Abstract

The present application relates to the technical field of LDO circuit, especially to a dynamic pole compensation LDO circuit, which eliminates the channel length modulation effect by dynamically mirroring the current of PM0 through PM1 and combining the current mirror structure composed of PM2, PM3, NM0 and NM1, adopts the super source follower composed of NM5, NM6 and NM7 to push the secondary pole of the LDO to the outside of the bandwidth, greatly improves the phase margin, mirrors the dynamic load current to PM9 (diode connection) through NM9, combines the capacitor C1 to form a dynamic zero point, compensates the secondary pole in real time following the load change, avoids the problem that the primary and secondary poles are too close in the traditional Muller compensation, introduces NM2 to break the degenerate point of the current mirror, ensures the normal starting and stable work of the circuit, adjusts the gm value of the super source follower through the dynamic current mirroring of PM5 and PM7, automatically adjusts the secondary pole frequency with the change of the load current, realizes the adaptive optimization of the pole in the full load range, and improves the stability consistency under light load and heavy load.

Description

Technical Field

[0001] This invention relates to the field of LDO circuit technology, and in particular to a dynamic pole-compensated LDO circuit. Background Technology

[0002] Low dropout regulators (LDOs) are primarily used to provide a stable operating voltage for the internal circuitry of a chip. Typically, an LDO has two main poles: one at the output stage of the error amplifier and one at the output stage of the power transistor. Since the pole at the power transistor's output stage varies with the load resistance in the connected circuit, when these two main poles are close together, it can cause the LDO circuit to oscillate.

[0003] Traditional LDOs often exhibit insufficient transient response of the output voltage under dynamic load changes, leading to increased power supply noise and impacting system stability and performance. This issue is particularly pronounced in high-precision and high-frequency applications. Furthermore, when existing LDO devices are cascaded, the mutual influence between each stage often causes stage point offset, further affecting the accuracy and stability of the output voltage.

[0004] The stability of LDOs under light and heavy loads is difficult to compromise, especially with large load capacitances, such as above μF. Furthermore, the phase margin difference between light and heavy loads is even greater under large current variations (0mA to 100mA), necessitating more effective compensation methods to ensure stable LDO operation. For example... Figure 1 The traditional compensation method, Miller zero-adjustment resistor compensation, involves introducing an adjustable resistor into the feedback network of the LDO to adjust the zero point position of the system, thereby compensating to some extent for phase margin changes caused by load variations. This is achieved by separating the dominant and secondary poles. However, this method is only suitable for compensation where the dominant pole is internal. When the load capacitance is large, the dominant pole is usually external. In this case, if a Miller capacitor is used, not only will the Miller capacitor be extremely large and inefficient, but the dominant and secondary poles may also be too close, causing the LDO to malfunction. Furthermore, the resistance value of the zero-adjustment resistor may change due to variations in the manufacturing process and temperature, leading to unstable compensation results. Summary of the Invention

[0005] To address the limitations of existing Miller zero-adjustment resistor compensation in practical applications, which leads to unstable compensation effects, this invention provides a dynamic pole-compensated LDO circuit. It employs a precise dynamic current mirror module to dynamically bias the super source follower, causing the LDO's second-to-third pole to change with the load current. This ensures the LDO's second-to-third pole remains at a relatively far position, preventing stability degradation due to load current variations. Furthermore, it eliminates the need for additional Miller zero-adjustment resistor compensation, avoiding instability issues caused by excessively large Miller capacitance, low efficiency, and close proximity of primary and secondary poles. This allows the LDO to operate stably under various load conditions.

[0006] This invention provides a dynamic pole-compensated LDO circuit, including an operational amplifier module, an output drive module, a current mirror bias module, a voltage buffer module, a dynamic compensation module, and a feedback control module. The operational amplifier module includes an operational amplifier, with its inverting input connected to a reference voltage Vref and its non-inverting input connected to a feedback voltage Vfb. The operational amplifier differentially amplifies the input reference voltage Vref and the feedback voltage Vfb, outputting a drive signal. The output drive module includes a PMOS transistor group and an NMOS transistor group. The PMOS transistor group includes PM0, PM1, PM2, PM3, and PM4. The drain of PM0 is connected to the output voltage Vout. PM1 dynamically mirrors the current of PM0. The sources of PM2 and PM3 are connected to the drains of PM1 and PM0, respectively, for receiving current signals. PM4 replicates the current of PM1. The NMOS transistor group includes NM0, NM1, and NM3. NM0 and NM1 are interconnected with the gates of PM2 and PM3 to form a current mirror, causing the drain-source voltage Vout of PM1 and PM0 to be offset. The current mirror module is consistent with the current signal transmission. NM3 replicates the current of NM1, and the current of PM4 is equal to the current of NM3. The current mirror bias module includes two sets of mirror units, which dynamically mirror the current of PM4 to adjust the transconductance gm value of the super source follower. The voltage buffer module includes NM8 and common-drain NM5, NM6, and NM7. NM5 mirrors the current of NM8. NM5, NM6, and NM7 constitute the super source follower, pushing the second-second pole of the LDO outside the bandwidth. The current mirror bias module is... NM5, NM6, and NM7 provide suitable gate voltages, and the source output follows the signal input to the gate. The dynamic compensation module includes NM9, PM9, and capacitor C1. NM9 mirrors the current of NM1 to PM9, and PM9 and capacitor C1 form a zero to compensate for the secondary pole of the LDO. The feedback control module includes resistors R1 and R2. Resistors R1 and R2 divide the output voltage Vout to generate a feedback voltage Vfb, which is sent back to the non-inverting input of the operational amplifier, forming a negative feedback closed loop. The super source follower pushes the secondary pole outside the bandwidth, and the secondary point is compensated by the dynamic zero, leaving only the primary pole of the LDO, which is equivalent to a single-pole system, effectively improving the stability and transient response speed of the LDO.

[0007] Furthermore, the two sets of mirror units include PM5, PM6 and PM7, PM8, which are mirror images of each other. PM5 and PM7 dynamically mirror the current of PM4. The gates of PM6 and PM8 are connected to VB1 and VB2, respectively, to provide quiescent current for PM6 and PM8. VB1 and VB2 provide a suitable quiescent operating point for the transistors, ensuring stable operation of the transistors in amplification mode.

[0008] Furthermore, the output driver module also includes NM2, with one source terminal grounded, the drain connected to a current mirror formed by NM0, NM1, PM2, and PM3, and the gate connected to VB3. This is used to break the degeneracy point of the current mirror, ensuring normal circuit startup.

[0009] Furthermore, the other end of the source of NM2 is connected to the load capacitor CL, and the other end of the load capacitor CL is connected to the output voltage Vout. The load capacitor CL, along with resistors R1 and R2, forms an RC network. This network is used to filter out high-frequency noise and ripple in the output voltage, thereby improving the power supply rejection ratio (PSR).

[0010] Furthermore, one end of capacitor C1 is connected to the gate and drain of PM9, and the other end is connected to the output of the operational amplifier. This results in a higher power supply rejection ratio (PSR).

[0011] Furthermore, one end of capacitor C1 is connected to the gate and drain of PM9, and the other end is grounded. This allows the secondary pole to be located further away from the primary pole, simplifying the circuit structure, reducing mutual interference between components, and further improving stability.

[0012] Furthermore, PM2, PM3, NM2, NM3, and PM4 are removed, and the gates of PM0, PM1 and NM0, NM1 are interconnected to form a current mirror. This simplifies the circuit structure and reduces area and power consumption.

[0013] Furthermore, NM8, NM5, and NM6 are removed, allowing the gate of NM7 to be connected to the operational amplifier output, the source to the current mirror bias module, and the drain to ground. This results in a simpler and more convenient circuit, avoiding the high-frequency noise problems that might arise from a super source follower.

[0014] Furthermore, the operational amplifier module also includes a phase compensation capacitor connected between the output terminal and the inverting input terminal of the operational amplifier to improve the stability of the circuit, reduce phase delay, and avoid oscillation.

[0015] Furthermore, it also includes an overcurrent protection module, which monitors the current of the output drive module and automatically cuts off the output when the current exceeds a set threshold to protect the circuit and load from damage.

[0016] The beneficial effects of this invention are as follows: (1) This invention provides a dynamic pole-compensated LDO circuit. By using a current mirror composed of PM2, PM3, NM1, and NM0, the VDS of PM1 and PM0 are made consistent, reducing the channel length modulation effect and making the dynamic current mirror more accurate. The addition of NM2 breaks the degeneracy point and ensures the normal start-up of the circuit. (2) This invention provides a dynamic pole compensation LDO circuit. The dynamic current mirrored from NM9 flows into PM9. PM9 is a diode connection with an equivalent resistance of 1 / gm. gm is proportional to the current. The equivalent resistance of PM9 and the capacitor C1 are connected in series to form a dynamic zero. Although the secondary point of LDO does not change, the primary point changes with the current of the load, thereby indirectly compensating the secondary point of LDO. Since the frequency of the secondary pole is far from the frequency of the primary point, the compensation of the secondary point does not require a large capacitor. Compared with the traditional Miller zero-adjustment resistor compensation, it greatly saves area. (3) The present invention provides a dynamic pole-compensated LDO circuit. By combining a dynamic super source follower with dynamic secondary point compensation, the dynamic super source follower pushes the secondary poles outside the bandwidth, and the secondary points are compensated by dynamic zeros, leaving only the LDO main pole, which is equivalent to a single-pole system, and the stability is greatly enhanced. Attached Figure Description

[0017] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort. Figure 1 It is a traditional Mile zero-adjustment resistor compensation; Figure 2 This is the circuit diagram for Example 1; Figure 3 This is the circuit diagram for Embodiment 2; Figure 4 This is the circuit diagram for Embodiment 3; Figure 5 This is the circuit diagram for Embodiment 4; Figure 6 It is the phase margin under light load; Figure 7 It is the phase margin under heavy load; Detailed Implementation

[0018] The technical solution of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments.

[0019] Example 1, as Figure 2As shown, a dynamic pole-compensated LDO circuit includes an operational amplifier module, an output driver module, a current mirror bias module, a voltage buffer module, a dynamic compensation module, and a feedback control module. It employs a precise dynamic current mirror to dynamically bias the super source follower, causing the LDO's second-order pole to change with the load current. Furthermore, the super source follower (1 / (gmgmro)) structure pushes the second-order pole further away than the original source follower (1 / gm) buffer, resulting in higher efficiency. The current mirror bias module can adjust the bias current of the super source follower in real time according to changes in the load current, ensuring that the LDO's second-order pole remains at a relatively far position, preventing stability degradation due to load current variations. Simultaneously, dynamic zero-point following compensation is used, canceling the secondary pole. Since the secondary pole frequency is further away from the primary pole frequency, the required capacitor is smaller, and the resistance can be adjusted using adjustable current, allowing for even smaller capacitors. The dynamic super source follower pushes the secondary pole out of the bandwidth, and the secondary point is dynamically zero-compensated, leaving only the primary pole of the LDO, which is equivalent to a single-pole system. This enhances stability, allowing it to operate stably even under large load capacitance, effectively improving the stability and transient response speed of the LDO.

[0020] Specifically, the operational amplifier module includes an operational amplifier. The inverting input of the operational amplifier is connected to the reference voltage Vref, and the non-inverting input is connected to the feedback voltage Vfb. The operational amplifier differentially amplifies the input reference voltage Vref and the feedback voltage Vfb to output a drive signal. By differentially amplifying the reference voltage Vref and the feedback voltage Vfb through the operational amplifier module, the stability of the output voltage Vout is ensured. The design of the operational amplifier enables the circuit to respond quickly to small changes in the input voltage, thereby maintaining the output voltage at a constant level.

[0021] The output drive module includes a PMOS transistor group and an NMOS transistor group. The PMOS transistor group includes PM0, PM1, PM2, PM3, and PM4. The drain of PM0 is connected to the output voltage Vout. PM1 dynamically mirrors the current of PM0. The sources of PM2 and PM3 are connected to the drains of PM1 and PM0, respectively, for receiving current signals. PM4 replicates the current of PM1. The NMOS transistor group includes NM0, NM1, and NM3. NM0 and NM1 are interconnected with the gates of PM2 and PM3 to form a current mirror, making the drain-source voltage VDS of PM1 and PM0 consistent for current signal transmission. NM3 replicates the current of NM1. The current of PM4 is equal to that of NM3. PM0 is the power transistor of the LDO. When the current of PM0 changes with the load, PM1 dynamically mirrors the current of PM0. When the load current fluctuates, PM2 and PM3 can quickly capture this change and accurately replicate and transmit the current through NM1 and NM0, thereby effectively adjusting the pole position of the LDO. PM2, PM3, NM0, and NM1 mirror each other, making the VDS of PM1 and PM0 consistent, eliminating the channel length modulation effect of PM1, ensuring that the current of PM0 can be accurately mirrored, and also ensuring that the mirrored current of PM1 can be accurately transmitted. The PMOS and NMOS transistor groups in the output drive module work together to achieve accurate transmission and dynamic adjustment of the current signal. The PMOS and NMOS transistor groups, through the current mirror structure, ensure accurate replication and transmission of the current signal, while maintaining the consistency of the drain-source voltage VDS, improving the efficiency and stability of the circuit.

[0022] The current mirror bias module includes two sets of mirror units. These units dynamically mirror the current of PM4 to adjust the transconductance (gm) of the super source follower. The super source follower is connected to the output of the LDO. By adjusting the transconductance (gm), the output impedance of the LDO can be dynamically adjusted. When the load current increases, the current of PM0 also increases. Through the dynamic mirroring of the current mirror bias module, the mirror units can quickly detect changes in the PM4 current and adjust the transconductance (gm) of the super source follower accordingly, thereby reducing the output impedance of the LDO and improving the transient response speed of the system. Conversely, when the load current decreases, the current of PM0 decreases. The mirror units can also dynamically adjust the transconductance (gm) of the super source follower, increasing the output impedance of the LDO and maintaining system stability. This dynamic adjustment mechanism ensures that the LDO circuit maintains good performance under various load conditions. By dynamically mirroring the current of PM4 and adjusting the transconductance (gm) of the super source follower, the current mirror bias module optimizes the frequency response and stability of the circuit.

[0023] The voltage buffer module includes NM8 and common-drain NM5, NM6, and NM7. NM5 mirrors the current of NM8. NM5, NM6, and NM7 form a super source follower, pushing the second-second pole of the LDO outside its bandwidth. The current mirror bias module provides suitable gate voltages for NM5, NM6, and NM7, and the source output follows the signal input to the gate. The super source follower structure of NM5, NM6, and NM7 further pushes the second-second pole of the LDO out of its bandwidth. The current mirror injection of the preceding dynamic currents PM5 and PM7 varies with the load current. When the load current is large, the injected current is large, gm increases, and the second-second pole of the LDO is pushed further out, resulting in higher stability for the LDO. The super source follower structure in the voltage buffer module pushes the second-second pole of the LDO out of its bandwidth, effectively reducing circuit noise and interference.

[0024] The dynamic compensation module includes NM9, PM9, and capacitor C1. One end of capacitor C1 is connected to the gate and drain of PM9, and the other end is connected to the output of the operational amplifier. NM9 mirrors the current of NM1 to PM9. PM9 and capacitor C1 form a zero point to compensate for the secondary pole of the LDO. NM9 mirrors the current of NM1, and PM9 and C1 form a zero point to compensate for the secondary pole of the LDO. Since NM9 mirrors the dynamic current that changes with the load, the zero point formed will also change with the load, thus compensating for the secondary pole of the LDO. PM9 is a diode connection with an equivalent resistance of 1 / gm. Since gm is proportional to the current, the equivalent resistance of PM9 and capacitor C1 are connected in series to form a dynamic zero point. Although the secondary pole of the LDO does not change, the primary pole changes with the load current, thus indirectly compensating for the secondary pole of the LDO. Since the frequency of the secondary pole is much higher than that of the primary pole, a large capacitor is not required to compensate for the secondary pole, which greatly saves area compared to the traditional Miller zero-adjustment resistor compensation. The dynamic compensation module compensates for the secondary poles of the LDO through the zero point formed by NM9, PM9 and capacitor C1, further improving the stability and transient response capability of the circuit.

[0025] The feedback control module includes resistors R1 and R2. Resistors R1 and R2 divide the output voltage Vout, generating a feedback voltage Vfb, which is then fed back to the non-inverting input of the operational amplifier, forming a negative feedback closed loop. R1 connects the output Vout to the load CL, and R2 connects Vfb to ground, forming a voltage divider feedback network that feeds a portion of the output voltage back to the negative input of the operational amplifier, achieving closed-loop control and ensuring precise control and stability of the output voltage.

[0026] The circuit comprises two sets of mirror units, PM5 and PM6, and PM7 and PM8, which are mirror images of each other. PM5 and PM7 dynamically mirror the current of PM4. The gates of PM6 and PM8 are connected to VB1 and VB2, respectively, to provide quiescent current for PM6 and PM8. PM5 and PM7 mirror PM4, providing dynamic mirror current, while PM8 and PM6 provide a certain quiescent current. When the load current changes, the current of PM0 also changes. Through the dynamic mirroring effect of PM1, the current of PM4 can reflect the current change of PM0 in real time. As mirror transistors, PM5 and PM7 provide dynamic mirror current in a certain proportional relationship with the current of PM4, thereby achieving a rapid response to changes in load current. At the same time, the quiescent current provided by PM8 and PM6 is used to maintain the basic current requirements of the circuit under stable operating conditions. This combination of dynamic and quiescent currents enables the entire circuit to maintain the stability and accuracy of the output voltage when the load changes.

[0027] The output driver module also includes NM2. One end of NM2's source is grounded, its drain is connected to a current mirror formed by NM0, NM1, PM2, and PM3, and its gate is connected to VB3. NM2 breaks the degeneracy point, ensuring that PM2, PM3, NM0, and NM1 can operate normally. VB3 serves as the gate voltage of NM2; through proper setting, NM2 can always be in an appropriate conduction state in the circuit, avoiding both overconduction leading to increased power consumption and underconduction affecting the normal function of the current mirror. This effectively solves the problem that the current mirror may enter an abnormal operating region due to input voltage or load changes under certain extreme conditions, improving the circuit's reliability and stability. Furthermore, the addition of NM2 further optimizes the circuit's transient response performance, enabling the circuit to adjust the output current more quickly and maintain stable output voltage when facing sudden load changes.

[0028] The other end of the source of NM2 is connected to the load capacitor CL, and the other end of the load capacitor CL is connected to the output voltage Vout. The load capacitor CL, along with resistors R1 and R2, forms an RC network. The RC network is used to stabilize the output voltage Vout and reduce its fluctuations. Resistors R1 and R2 are connected in series, with one end connected to the load capacitor CL and the other end grounded. By adjusting the values ​​of resistors R1 and R2, the time constant of the RC network can be set, thereby controlling the response speed and stability of the output voltage Vout. When the load changes abruptly, the load capacitor CL can charge and discharge rapidly to smooth the fluctuations in the output voltage Vout, while the RC network further suppresses the changes in output voltage by adjusting the current. This allows the circuit to maintain a constant output voltage when facing load changes, improving the performance of the LDO circuit.

[0029] To further improve circuit stability, the operational amplifier module also includes a phase compensation capacitor. This capacitor is connected between the output and inverting input of the operational amplifier to enhance circuit stability, reduce phase delay, and prevent oscillations. The addition of the phase compensation capacitor effectively improves the frequency response characteristics of the operational amplifier, especially at high frequencies. It compensates for phase hysteresis caused by internal parasitic capacitance and inductance, increasing the phase margin of the entire circuit. It also suppresses high-frequency noise interference to some extent, improving the signal-to-noise ratio and resulting in a cleaner and more stable LDO output.

[0030] To protect the circuit from damage, an overcurrent protection module is also included. This module monitors the current of the output drive module and automatically cuts off the output when the current exceeds a set threshold, protecting the circuit and load from damage. Further protection modules, such as over-temperature protection and short-circuit protection, can be included to enhance the circuit's safety and reliability. The over-temperature protection module monitors the circuit's operating temperature in real time and automatically cuts off the power or adjusts the operating state if the temperature exceeds a preset safe range, preventing circuit damage or fire caused by overheating. The short-circuit protection module responds quickly and limits the current when a short circuit is detected at the output, preventing excessive short-circuit current from damaging circuit components. These protection modules together ensure stable circuit operation under various extreme conditions.

[0031] Example 2, as Figure 3 As shown, the difference from Embodiment 1 is that one end of capacitor C1 is connected to the gate and drain of PM9, while the other end is grounded. Grounding capacitor C1, without connecting it to the operational amplifier (OP), pushes the secondary pole further away, requiring a smaller capacitance value for C1 and a smaller current to PM9, thus saving area and power consumption. Directly grounding capacitor C1 without connecting it to the OP effectively pushes the secondary pole to a higher frequency range, further away from the primary pole. This not only simplifies the circuit structure but also reduces mutual interference between components, further improving the stability of the entire power management system. Simultaneously, by reducing the use of operational amplifiers, the system's power consumption and cost are correspondingly reduced, making this solution more competitive in practical applications.

[0032] Example 3, as Figure 4As shown, the difference from Embodiment 1 is that PM2, PM3, NM2, NM3, and PM4 are removed, and the gates of PM0, PM1 and NM0, NM1 are interconnected to form a current mirror. Through precise calculations and simulations, it was found that removing these components not only does not affect the basic function of the circuit, but also further improves the circuit's efficiency and stability. The removal of power management components such as PM2 and PM3 reduces the complexity of the circuit and potential failure points, making the entire device more reliable. At the same time, it also reduces production costs and improves the product's market competitiveness. Although the current mirror is not as precise, the circuit is simpler and more convenient, reducing area and power consumption.

[0033] Example 4, as Figure 5 As shown, the difference from Embodiment 1 is that NM8, NM5, and NM6 are removed, so that the gate of NM7 is connected to the operational amplifier output, the source is connected to the current mirror bias module, and the drain is grounded. The dynamic super-source structure is removed, making it suitable when the power transistor size is not particularly large. The circuit is simpler and more convenient, saving area and power consumption, while avoiding the high-frequency noise problems that may be caused by the dynamic super-source.

[0034] like Figure 6 and 7 As shown in the simulation results, under light load, the phase margin is 65°, which is within a suitable range and avoids the slow frequency response caused by overcompensation; under heavy load, the phase margin is 81.79°, which is also kept at a stable level and prevents oscillation problems that may be caused by undercompensation.

[0035] The above description is illustrative only and not restrictive of the present invention. Those skilled in the art will understand that many modifications, variations or equivalents can be made without departing from the spirit and scope defined by the appended claims, and all such modifications, variations or equivalents will fall within the protection scope of the present invention.

Claims

1. A dynamic pole-compensated LDO circuit, characterized in that: It includes an operational amplifier module, an output driver module, a current mirror bias module, a voltage buffer module, a dynamic compensation module, and a feedback control module. The operational amplifier module includes an operational amplifier. The inverting input terminal of the operational amplifier is connected to a reference voltage Vref, and the non-inverting input terminal is connected to a feedback voltage Vfb. The operational amplifier differentially amplifies the input reference voltage Vref and the feedback voltage Vfb and outputs a drive signal. The output drive module includes a PMOS transistor group and an NMOS transistor group. The PMOS transistor group includes PM0, PM1, PM2, PM3, and PM4. The drain of PM0 is connected to the output voltage Vout. PM1 dynamically mirrors the current of PM0. The sources of PM2 and PM3 are connected to the drains of PM1 and PM0, respectively, for receiving current signals. PM4 replicates the current of PM1. The NMOS transistor group includes NM0, NM1, and NM3. NM0 and NM1 are interconnected with the gates of PM2 and PM3 to form a current mirror, ensuring that the drain-source voltage VDS of PM1 and PM0 are consistent for current signal transmission. NM3 replicates the current of NM1. The PM4 current is equal to the NM3 current; The current mirror bias module includes two sets of mirror units, which dynamically mirror the current of PM4 to adjust the transconductance gm value of the super source follower. The voltage buffer module includes NM8 and common-drain NM5, NM6, and NM7. NM5 mirrors the current of NM8. NM5, NM6, and NM7 form a super source follower, pushing the second-to-second pole of the LDO outside the bandwidth. The current mirror bias module provides suitable gate voltages for NM5, NM6, and NM7. The source output is a signal that follows the gate input. The dynamic compensation module includes NM9, PM9 and capacitor C1. The current of NM9 is mirrored to PM9. PM9 and capacitor C1 form a zero point to compensate for the secondary pole of the LDO. The feedback control module includes resistors R1 and R2. Resistors R1 and R2 divide the output voltage Vout to generate a feedback voltage Vfb, which is then sent back to the non-inverting input of the operational amplifier, forming a negative feedback closed loop.

2. The dynamic pole-compensated LDO circuit according to claim 1, characterized in that: The two sets of mirror units include PM5, PM6 and PM7, PM8, which are mirror images of each other. PM5 and PM7 dynamically mirror the current of PM4. The gates of PM6 and PM8 are connected to VB1 and VB2 respectively to provide static current for PM6 and PM8.

3. The dynamic pole-compensated LDO circuit according to claim 1, characterized in that: The output driving module also includes NM2, with one end of the source of NM2 grounded, the drain connected to a current mirror formed by NM0, NM1 and PM2, PM3, and the gate connected to VB3, which is used to break the degeneracy point of the current mirror.

4. The dynamic pole-compensated LDO circuit according to claim 3, characterized in that: The other end of the source of NM2 is connected to the load capacitor CL, and the other end of the load capacitor CL is connected to the output voltage Vout. The load capacitor CL, together with resistors R1 and R2, forms an RC network to filter out high-frequency noise in the output voltage.

5. The dynamic pole-compensated LDO circuit according to claim 1, characterized in that: One end of capacitor C1 is connected to the gate and drain of PM9, and the other end is connected to the output of the operational amplifier.

6. The dynamic pole-compensated LDO circuit according to claim 1, characterized in that: One end of the capacitor C1 is connected to the gate and drain of PM9, and the other end is grounded.

7. A dynamic pole-compensated LDO circuit according to claim 3, characterized in that: Remove PM2, PM3, NM2, NM3 and PM4 to interconnect the gates of PM0, PM1 and NM0, NM1 to form a current mirror.

8. The dynamic pole-compensated LDO circuit according to claim 1, characterized in that: Remove NM8, NM5, and NM6, and connect the gate of NM7 to the output of the operational amplifier, the source to the current mirror bias module, and the drain to ground.

9. A dynamic pole-compensated LDO circuit according to claim 1, characterized in that: The operational amplifier module also includes a phase compensation capacitor, which is connected between the output terminal and the inverting input terminal of the operational amplifier to improve the stability of the circuit.

10. A dynamic pole-compensated LDO circuit according to claim 1, characterized in that: It also includes an overcurrent protection module, which monitors the current of the output drive module and automatically cuts off the output when the current exceeds a set threshold.

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