Memory and data transmission method

Abstract

The present invention provides a memory and data transmission method. The memory includes a cache module; a memory access module that compares the amount of data to be transmitted in a transmission instruction with the storage space of the cache module. When the amount of data to be transmitted is less than or equal to the storage space of the cache module, the memory access module obtains the data to be transmitted according to the transmission instruction, integrates the data to be transmitted into corresponding data blocks, and transmits them to the cache module. When the amount of data to be transmitted is greater than the storage space of the cache module, the memory access module obtains the data to be transmitted according to the transmission instruction, integrates the obtained data to be transmitted into multiple data blocks according to a preset data amount, and gradually transmits the multiple data blocks to the cache module in sequence. A flash memory module is used to store data. The memory and data transmission method provided by the present invention can flexibly split data streams and transmit them in an orderly and efficient manner according to the adaptive block size based on the cache space status.

Description

Technical Field

[0001] The present invention relates to the field of storage, and in particular to a memory and a data transmission method. Background Art

[0002] In existing storage systems, especially those that include flash memory modules (such as eMMC), cache modules are usually included to speed up access. The memory access module of the memory is responsible for coordinating data exchange between external devices (such as the host) and the cache module and flash memory module. During a write operation, the external device sends write instructions and data to the memory, usually continuously sending the data to be written to the front-end memory access unit frame by frame. After receiving these data frames, the front-end memory access unit will send them directly to the cache module for temporary storage, and then the back-end memory access unit will be responsible for writing the data in the cache to the flash memory module. During a read operation, the back-end memory access unit responds to the read instruction and obtains data from the flash memory module, and often continuously sends data to the cache module frame by frame. Then, the data in the cache module is read out step by step and returned to the host through the front-end memory access unit.

[0003] This approach of directly sending frame data continuously and attempting to store it in the cache faces a significant problem: when the amount of data required by a single transfer instruction (whether read or write) exceeds the currently available storage space in the cache module, the data cannot be stored completely and smoothly. The external device may be forced to wait for cache space to be freed up, resulting in response delays. This problem is particularly common for large data transmission tasks, seriously reducing overall transmission efficiency and reliability. Therefore, there is room for improvement. Summary of the Invention

[0004] The present invention provides a memory and a data transmission method, which can flexibly split data streams and perform orderly and efficient transmission according to the adapted block size based on the cache space status.

[0005] The present invention provides a memory comprising:

[0006] Cache module;

[0007] a memory access module, configured to respond to a transmission instruction from an external device and compare the amount of data to be transmitted in the transmission instruction with the storage space of the cache module;

[0008] When the amount of data to be transmitted in the transmission instruction is less than or equal to the storage space of the cache module, obtaining the data to be transmitted according to the transmission instruction, integrating the data to be transmitted into corresponding data blocks, and transmitting the data to the cache module;

[0009] When the amount of data to be transmitted in the transmission instruction is greater than the storage space of the cache module, the data to be transmitted is obtained according to the transmission instruction, and the obtained data to be transmitted is integrated into a plurality of data blocks according to a preset data amount; and the plurality of data blocks are transmitted to the cache module step by step in sequence; wherein the preset data amount is less than or equal to the storage space of the cache module;

[0010] Flash memory module, used to store data.

[0011] In one embodiment of the present invention, the cache module includes a write cache unit; and the memory access module includes:

[0012] A front-end memory access unit is configured to respond to a write instruction of the transmission instruction and compare the amount of data to be transmitted in the write instruction with the storage space of the write cache unit;

[0013] When the amount of data to be transmitted in the write instruction is less than or equal to the storage space of the write cache unit, obtaining the data to be transmitted from the external device according to the write instruction, integrating the data to be transmitted into corresponding data blocks, and transmitting the data to the write cache unit;

[0014] When the amount of data to be transmitted in the write instruction is greater than the storage space of the write cache unit, the data to be transmitted is obtained from the external device according to the write instruction, and the obtained data to be transmitted is integrated into a plurality of data blocks according to a preset first data amount; and the plurality of data blocks are transmitted to the write cache unit step by step in sequence; wherein the preset first data amount is less than or equal to the storage space of the write cache unit;

[0015] A back-end memory access unit is used to write the data blocks in the write cache unit into the flash memory module.

[0016] In one embodiment of the present invention, the front-end memory access unit is further configured to determine, before aggregating the data to be transmitted from the external device to obtain a data block, whether the write cache unit:

[0017] When no cache data exists in the write cache unit, setting the first data amount to be less than or equal to the storage space of the write cache unit;

[0018] When cache data exists in the write cache unit, the first data amount is set to be smaller than or equal to the remaining storage space of the write cache unit.

[0019] In one embodiment of the present invention, the cache module further includes a read cache unit;

[0020] The back-end memory access unit is further configured to respond to a read instruction of the transfer instruction and compare the amount of data to be transferred in the read instruction with the storage space of the read cache unit:

[0021] When the amount of data to be transmitted in the read instruction is less than or equal to the storage space of the read cache unit, obtaining the data to be transmitted from the flash memory module according to the read instruction, integrating the data to be transmitted into corresponding data blocks, and transmitting the data to the read cache unit;

[0022] When the amount of data to be transmitted in the read instruction is greater than the storage space of the read cache unit, the data to be transmitted is obtained from the flash memory module according to the read instruction, and the obtained data to be transmitted is integrated into a plurality of data blocks according to a preset second data amount; and the plurality of data blocks are transmitted to the read cache unit step by step in sequence; wherein the preset second data amount is less than or equal to the storage space of the read cache unit;

[0023] The front-end memory access unit is further configured to read the data blocks in the read cache unit to the external device.

[0024] In one embodiment of the present invention, the back-end memory access unit is further configured to determine, before aggregating the data to be transmitted in the flash memory module to obtain a data block, whether the read cache unit:

[0025] When no cache data exists in the read cache unit, setting the second data amount to be less than or equal to the storage space of the read cache unit;

[0026] When cache data exists in the read cache unit, the second data amount is set to be less than or equal to the remaining storage space of the read cache unit.

[0027] In one embodiment of the present invention, the memory further includes a replay protection module;

[0028] The replay protection module is used to verify the data blocks in the write cache unit and obtain the verification results;

[0029] The back-end memory access unit is further configured to process the data blocks in the write cache unit according to the verification result.

[0030] In one embodiment of the present invention, the replay protection module is further configured to:

[0031] Calculate a corresponding hash authentication code according to a preset shared key and the data block in the write cache unit;

[0032] Compare the hash check code of the data block in the write cache unit with the corresponding hash authentication code:

[0033] When it is determined that the hash check code is identical to the corresponding hash authentication code, determining that the verification result is verification passed;

[0034] When it is determined that the hash check code is different from the corresponding hash authentication code, the verification result is determined to be verification failure.

[0035] In one embodiment of the present invention, the back-end memory access unit is further configured to:

[0036] When the verification result is verification passed, writing the data block in the write cache unit into the flash memory module;

[0037] When the verification result is verification failure, the data block in the write cache unit is deleted.

[0038] In one embodiment of the present invention, the replay protection module is further configured to calculate a corresponding hash authentication code based on a preset shared key and the data block in the read cache unit;

[0039] The front-end memory access unit is further configured to read out the data blocks and corresponding hash authentication codes in the read cache unit to an external device.

[0040] The present invention also provides a memory data transmission method, which is applied to the memory, wherein the memory includes a memory access module, a cache module, and a flash memory module. The data transmission method includes:

[0041] The memory access module responds to a transmission instruction from an external device and compares the amount of data to be transmitted in the transmission instruction with the storage space of the cache module.

[0042] When the amount of data to be transmitted in the transmission instruction is less than or equal to the storage space of the cache module, obtaining the data to be transmitted according to the transmission instruction, integrating the data to be transmitted into corresponding data blocks, and transmitting the data to the cache module;

[0043] When the amount of data to be transmitted in the transmission instruction is greater than the storage space of the cache module, the data to be transmitted is obtained according to the transmission instruction, and the obtained data to be transmitted is integrated into a plurality of data blocks according to a preset data amount; and the plurality of data blocks are transmitted to the cache module step by step in sequence; wherein the preset data amount is less than or equal to the storage space of the cache module;

[0044] The data blocks in the cache module are saved to the flash memory module, or the data blocks in the cache module are transmitted to an external device through the memory access module.

[0045] The beneficial effects of the present invention are as follows: through a dynamic cache capacity matching mechanism, the transmission congestion and inefficiency problems caused by traditional storage systems when the amount of transmitted data exceeds the cache space are effectively solved. Based on the memory access module, the amount of data to be transmitted is actively compared with the storage space of the cache module. When the amount of data is less than or equal to the cache space, the whole block is transmitted, and when it is greater than the cache space, the data is transmitted step by step in blocks according to the preset amount. This completely eliminates the host waiting delay caused by cache overflow and realizes uninterrupted transmission continuity; the block transmission mechanism ensures that the bus maintains efficient circulation in any data volume scenario, significantly improving bus utilization; at the same time, it avoids the risk of data loss or verification errors that may be caused by continuous frame transmission, and enhances the reliability of read and write operations. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present application, and together with the specification, are used to explain the principles of the present application. Obviously, the drawings described below are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be derived from these drawings without inventive effort.

[0047] In the attached figure:

[0048] Figure 1 A schematic diagram of the interaction between an external device and a memory provided by an embodiment of the present invention;

[0049] Figure 2 The present invention is a flowchart of a memory data transmission method provided in one embodiment of the present invention.

[0050] The reference numerals are as follows: 100, external device; 210, front-end memory access unit; 220, write cache unit; 230, read cache unit; 240, back-end memory access unit; 250, replay protection module; 260, flash memory module. DETAILED DESCRIPTION

[0051] The following describes the embodiments of the present invention through specific examples. Those skilled in the art will readily understand the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through various other specific embodiments. The details in this specification may be modified or altered based on different viewpoints and applications without departing from the spirit of the present invention. The following embodiments and features therein may be combined with one another without conflict.

[0052] It should be noted that the illustrations provided in the following embodiments are merely schematic illustrations of the basic concept of the present invention. The drawings only show components related to the present invention and are not drawn according to the number, shape, and size of components in actual implementation. In actual implementation, the type, quantity, and proportion of each component may be changed arbitrarily, and the component layout may also be more complex.

[0053] In the following description, numerous details are discussed to provide a more thorough explanation of the embodiments of the present invention. However, it will be apparent to those skilled in the art that the embodiments of the present invention may be practiced without these specific details. In other embodiments, well-known structures and devices are shown in block diagram form rather than in detail to avoid obscuring the embodiments of the present invention.

[0054] See also Figure 1 The present invention discloses a memory, which may include a memory access module, a cache module, a replay protection module 250, and a flash memory module 260.

[0055] In some embodiments, the memory access module may receive a transfer instruction (which may be a read instruction, a write instruction, or both) from the external device 100 (e.g., a CPU or a system bus of the external device). The transfer instruction specifies information such as the target address of the current transfer operation and the amount of data to be transferred (e.g., data size).

[0056] In some embodiments, the memory access module first compares the amount of data to be transferred, as specified in the transfer instruction, with the total storage capacity of the cache module itself (e.g., the storage space specified in the write cache unit 220 or the read cache unit 230, depending on the instruction type). By pre-comparing the amount of data to be transferred with the size of the cache module's storage space, it avoids the problem of discovering insufficient cache space during the transfer process, leading to transmission interruptions, failures, or data overwrite errors. This proactive judgment mechanism significantly improves transmission reliability and controllability.

[0057] In some embodiments, if the comparison result shows that the amount of data to be transmitted required by the transmission instruction is less than or equal to the storage space of the cache module, the memory access module will obtain the complete data to be transmitted from the external device 100 (for write operations) or the flash memory module (for read operations) according to the requirements of the transmission instruction. Then, the memory access module will integrate the obtained data into a complete data block corresponding to the requirements of the transmission instruction. Finally, the memory access module transfers this integrated single data block as a whole to the cache module for temporary storage. This operation is suitable for situations where the amount of data is small and the cache can accommodate it at one time. Its advantage is that the processing flow is direct and efficient, without the overhead of additional data splitting and multiple transmissions, and fully utilizes the cache space for batch operations, reducing access delays.

[0058] In some embodiments, if the comparison results indicate that the amount of data to be transmitted as specified in the transmission instruction exceeds the storage space available in the cache module, the memory access module will similarly begin acquiring the data to be transmitted from the external device 100 (for write operations) or the flash memory module (for read operations) in accordance with the transmission instruction. However, unlike the aforementioned scenario, the memory access module segments or consolidates the continuously acquired raw data to be transmitted according to a preset data size (fixed or configurable). This is done by segmenting and reassembling the large, single data stream that originally exceeded the cache capacity into multiple independent, appropriately sized data blocks. The preset data size is strictly set to be less than or equal to the storage space available in the cache module. The number of reassembled data blocks is determined by dividing the total data size by the preset data size. The memory access module sequentially processes (assembles and sends) one data block before moving on to the next, gradually and sequentially transferring these split data blocks to the cache module until all data to be transmitted has been processed.

[0059] In some embodiments, the cache module may include a write cache unit 220 and a read cache unit 230. The memory access module may include a front-end direct memory access unit 210 (FE DMA) and a back-end direct memory access unit 240 (BE DMA).

[0060] In some embodiments, the front-end memory access unit 210 can be configured to respond to a write instruction of a transfer instruction and compare the amount of data to be transferred in the write instruction with the storage space of the write cache unit 220. Specifically, the front-end memory access unit 210 can receive a write instruction from an external device 100 (e.g., a host). The write instruction includes a target address (the location to be written to the flash memory module 260) and the amount of data to be transferred (i.e., the total amount of data the host expects to write). By proactively predicting the matching relationship between the amount of data to be transferred and the cache space, an optimal strategy can be determined before the transfer begins.

[0061] In some embodiments, when the amount of data to be transmitted in the write instruction is less than or equal to the storage space of the write cache unit 220, the data to be transmitted is obtained from the external device 100 according to the write instruction, and the data to be transmitted is integrated into corresponding data blocks and transmitted to the write cache unit 220.

[0062] In some embodiments, if the comparison result indicates that the amount of data to be transmitted is less than or equal to the remaining space in the write cache unit 220, the front-end memory access unit 210 will directly obtain all the data to be transmitted from the external device 100 at once. The front-end memory access unit 210 will then integrate and encapsulate this data into a complete data block (this data block structure is generally suitable for cache management and subsequent flash memory writes). Finally, the front-end memory access unit 210 will transfer this integrated single data block as a whole to the write cache unit 220 for temporary storage.

[0063] In some embodiments, when the amount of data to be transmitted in a write instruction is greater than the storage space of the write cache unit 220, the data to be transmitted is obtained from an external device according to the write instruction, and the obtained data to be transmitted is integrated into multiple data blocks according to a preset first data amount; the multiple data blocks are gradually transmitted to the write cache unit in sequence; wherein the preset first data amount is less than or equal to the storage space of the write cache unit 220.

[0064] In some embodiments, if the comparison result shows that the amount of data to be transmitted is greater than the remaining space of the write cache unit 220, the front-end memory access unit 210 starts to obtain data from the external device 100, but adopts a block strategy. Specifically, based on a preset first data amount as a cutting standard, the front-end memory access unit 210 obtains data segment by segment from the data stream transmitted by the external device 100 according to the first data amount, and encapsulates each data segment into an independent data block. After successfully integrating a data block, the front-end memory access unit 210 immediately transmits it to the write cache unit 220. At the same time, the front-end memory access unit 210 can obtain, integrate and transmit the next data block until all the data to be transmitted are processed into data blocks and stored in the write cache unit 220.

[0065] In some embodiments, the front-end memory access unit 210 is also used to judge the write cache unit 220 before integrating the data to be transmitted from the external device 100 to obtain a data block: when there is no cached data in the write cache unit 220, the first data amount is set to be less than or equal to the storage space of the write cache unit 220; when there is cached data in the write cache unit 220, the first data amount is set to be less than or equal to the remaining storage space of the write cache unit 220.

[0066] In some embodiments, the absence of cached data means that the write cache unit 220 currently contains no valid data and is completely idle (remaining space = total storage space); the presence of cached data means that the write cache unit 220 already has some data temporarily stored in it but not yet written to the flash memory (remaining space < total storage space). When there is no cached data in the write cache unit 220, the first data amount can be set to be less than or equal to the total storage space of the write cache unit 220 (for example, set to 90% of the total cache capacity or a fixed upper limit). By fully utilizing the idle cache capacity, the size of a single data block transmitted is maximized, the number of block splits and protocol overhead are reduced, and efficiency is improved. When there is cached data in the write cache unit 220, the first data amount can be set to be less than or equal to the current remaining storage space of the write cache unit 220 (for example, 100% of the remaining space or slightly less to allow for buffering). By strictly ensuring that the new data block fits into the current remaining space, the incoming data block will never fail due to insufficient space, and overwriting of existing cached data is avoided.

[0067] In some embodiments, the backend memory access unit 240 may be used to write data blocks in the write cache unit 220 to the flash memory module 260. After successfully writing data, the backend memory access unit 240 may release the corresponding data block space in the write cache unit 220 for subsequent pre-fetching and reuse.

[0068] In some embodiments, the backend memory access unit 240 may be configured to respond to a read instruction of a transfer instruction and compare the amount of data to be transferred in the read instruction with the storage space of the read cache unit 230. Specifically, after receiving the read instruction from the external device 100, the frontend memory access unit 210 may transmit the read instruction to the backend memory access unit 240. The read instruction specifies the source address of the data to be read (the location in the flash memory module 260) and the amount of data to be transferred.

[0069] In some embodiments, when the amount of data to be transmitted in the read instruction is less than or equal to the storage space of the read cache unit 230, the data to be transmitted is obtained from the flash memory module 260 according to the read instruction, and the data to be transmitted is integrated into corresponding data blocks and transmitted to the read cache unit 230.

[0070] In some embodiments, if the comparison result indicates that the amount of data to be transmitted is less than or equal to the remaining space in the read cache unit 230, the back-end memory access unit 240 will directly retrieve all the data to be transmitted from the flash memory module 260 at once. The back-end memory access unit 240 will then consolidate and encapsulate this data into a complete data block (this data block structure is typically suitable for cache management and subsequent flash memory writes). Finally, the back-end memory access unit 240 will transfer this consolidated single data block as a whole to the read cache unit 230 for temporary storage.

[0071] In some embodiments, when the amount of data to be transmitted in a read instruction is greater than the storage space of the read cache unit 230, the data to be transmitted is obtained from the flash memory module according to the read instruction, and the obtained data to be transmitted is integrated into multiple data blocks according to a preset second data amount; the multiple data blocks are gradually transmitted to the read cache unit 230 in sequence; wherein the preset second data amount is less than or equal to the storage space of the read cache unit 230.

[0072] In some embodiments, if the comparison result shows that the amount of data to be transmitted is greater than the remaining space of the read cache unit 230, the back-end memory access unit 240 starts to obtain data from the flash memory module 260, but adopts a block strategy. Specifically, based on a preset second data amount as a cutting standard, the back-end memory access unit 240 obtains data segment by segment from the data stream transmitted by the flash memory module 260 according to the second data amount, and encapsulates each data segment into an independent data block. After successfully integrating a data block, the back-end memory access unit 240 immediately transmits it to the read cache unit 230. At the same time, the back-end memory access unit 240 can obtain, integrate and transmit the next data block until all data to be transmitted are processed into data blocks and stored in the read cache unit 230.

[0073] In some embodiments, the back-end memory access unit 240 is also used to judge the read cache unit 230 before integrating the data to be transmitted of the flash memory module 260 to obtain a data block: when there is no cached data in the read cache unit 230, the second data amount is set to be less than or equal to the storage space of the read cache unit 230; when there is cached data in the read cache unit 230, the second data amount is set to be less than or equal to the remaining storage space of the read cache unit 230.

[0074] In some embodiments, the absence of cached data means that the read cache unit 230 currently does not have any valid data and is in a completely idle state (remaining space = total storage space); the presence of cached data means that the read cache unit 230 already has some data temporarily stored but not written to the flash memory (remaining space < total storage space). When there is no cached data in the read cache unit 230, the second data amount can be set to be less than or equal to the total storage space of the read cache unit 230 (for example, set to 90% of the total cache capacity or a fixed upper limit value). By making full use of the idle cache capacity, the size of the data block transmitted in a single time is maximized, the number of block splits and protocol overhead are reduced, and efficiency is improved. When there is cached data in the read cache unit 230, the second data amount can be set to be less than or equal to the current remaining storage space of the read cache unit 230 (for example, 100% of the remaining space or slightly less to leave a buffer). By strictly ensuring that the new data block fits the current remaining space, the newly incoming data block will never fail due to insufficient space, while avoiding overwriting of existing cached data.

[0075] In some embodiments, the front-end memory access unit 210 is further configured to read data blocks in the read cache unit 230 to the external device 100. After successfully reading the data, the front-end memory access unit 210 may release the corresponding data block space in the read cache unit 230 for subsequent pre-fetching and reuse.

[0076] In some embodiments, the replay protection module 250 may be configured to verify the data blocks in the write cache unit 220 and obtain a verification result. Specifically, the replay protection module 250 may be configured to calculate a corresponding hash authentication code based on a preset shared key and the data blocks in the write cache unit 220; compare the hash check code of the data blocks in the write cache unit 220 with the corresponding hash authentication code; and determine that the verification result is a pass if the hash check code is determined to be identical to the corresponding hash authentication code; and determine that the verification result is a fail if the hash check code is determined to be different from the corresponding hash authentication code.

[0077] In some embodiments, when a data block enters the write cache unit 220 (which can be triggered in real time or batch-processed on a fixed cycle), the replay protection module 250 is activated and performs the following security operations on the target data block: It extracts a preset shared key that is pre-set and strictly confidential between the memory and the external device 100 (this shared key is securely negotiated when the external device 100 and the memory are paired); combines this shared key with the entire content of the data block in the write cache unit 220 (including user data and metadata), and generates a hash authentication code corresponding to the data block in real time using a preset cryptographic hash algorithm (such as SHA-256 or HMAC). Subsequently, a hash check code embedded by the external device 100 during data generation can be extracted from a specific field of the same data block (this hash check code can be pre-calculated and generated by the external device 100 using the same shared key and algorithm). Finally, the real-time generated hash authentication code can be strictly compared with the hash check code embedded in the external device 100.

[0078] In some embodiments, the replay protection module 250 may calculate the hash authentication code according to the following steps:

[0079] Step S10: Calculate the internal padding key based on the shared key and the internal padding vector; , expressed as: ,in, Represented as a shared key, Represented as an internal fill vector, Represented as a bitwise exclusive OR operation (Bitwise Exclusive OR);

[0080] Step S20: Calculate the internal hash input value based on the internal filling key and the data block; the internal hash input value , expressed as: ,in, Represents the original data after stripping the shared key and HMAC value from the data block to be verified. It means concatenating the 64-byte internal key with the original data.

[0081] Step S30: Calculate the internal hash value based on the internal hash input value and the hash algorithm; , expressed as: ,in, Indicates the execution of the SHA-256 hash algorithm;

[0082] Step S40: Calculate the external padding key based on the shared key and the external padding vector; , expressed as: ,in, Represented as an internal fill vector;

[0083] Step S50: Calculate the hash authentication input value based on the external filling key and the internal hash value; , expressed as: ;

[0084] Step S60: Calculate the hash authentication code based on the hash authentication input value and the hash algorithm; , expressed as: .

[0085] In some embodiments, if and only if the real-time hash authentication code completely matches the hash checksum embedded in the data block, the data block is confirmed to have not been tampered with, has a trusted source, and has complete content, and the verification result is a passed verification. If there is any inconsistency between the real-time hash authentication code and the embedded hash checksum, the data block is determined to have been tampered with, has a forged source, or has been damaged in transmission (such as a replay attack, man-in-the-middle attack, or unexpected error), and the verification result is a failed verification.

[0086] In some embodiments, the backend memory access unit 240 is further configured to process the data blocks in the write cache unit 220 based on the verification result. Specifically, if the verification result is "passed," the data blocks in the write cache unit 220 are written to the flash memory module 260 of the memory; if the verification result is "failed," the data blocks in the write cache unit 220 are deleted. The flash memory module 260 can be used to store data.

[0087] In some embodiments, the back-end memory access unit 240 can perform differentiated operations based on the verification results issued by the replay protection module 250: the back-end memory access unit 240 will normally migrate the verified data blocks to the target address of the flash memory module 260 to complete the persistent storage of the data, and only authenticate valid data to be written to the flash memory module 260, thereby ensuring the purity and credibility of the non-volatile storage medium and preventing malicious data or erroneous data from contaminating the storage space; the back-end memory access unit 240 will immediately delete the cached data and permanently delete the corresponding data blocks that have not passed the verification in the write cache unit 220 to release the space they occupy. At the same time, it can synchronously trigger a security alarm (such as an interrupt notification system software or external device 100) to prompt potential security threats.

[0088] In some embodiments, the replay protection module 250 may be further configured to calculate a corresponding hash authentication code based on a preset shared key and the data block in the read cache unit 230 .

[0089] In some embodiments, before a data block stored in the read cache unit 230 is accessed by the front-end memory access unit 210 (or when a read is triggered), the replay protection module 250 intervenes to perform security enhancement operations: it calls the shared key pre-negotiated securely between the memory and the external device 100; extracts the entire content of the data block in the read cache unit 230 (including user data and associated metadata); and, in conjunction with a preset cryptographic hash algorithm (such as HMAC-SHA256), uses the shared key to perform real-time calculations on the data block to generate a unique corresponding hash authentication code. The replay protection module 250 can write the generated hash authentication code into a reserved secure metadata field within the data block. The hash authentication code is embedded in a specific field of the data block (such as the security header or trailer check area), forming an inseparable secure data packet with the original content.

[0090] In some embodiments, the front-end memory access unit 210 is further configured to read the data blocks and corresponding hash authentication codes from the read cache unit 230 to the external device 100. Specifically, the front-end memory access unit 210 can perform the final data read, reading the complete secure data block (including user data, original metadata, and associated hash authentication codes) from the read cache unit 230. Subsequently, the database is transparently transmitted to the external device 100 via a standard communication protocol. Finally, after confirming that the data transfer was successful, the front-end memory access unit 210 can release the corresponding space in the read cache unit 230.

[0091] It can be seen that in the above scheme, the dynamic cache capacity matching mechanism is used to effectively solve the transmission congestion and inefficiency problems caused by the traditional storage system when the amount of transmitted data exceeds the cache space. Based on the memory access module, the amount of data to be transmitted is actively compared with the storage space of the cache module. When the data amount is less than or equal to the cache space, the whole block is transmitted, and when it is greater than the cache space, the data is transmitted step by step in blocks according to the preset amount. This completely eliminates the host waiting delay caused by cache overflow and realizes uninterrupted transmission continuity. The block transmission mechanism ensures that the bus maintains efficient circulation in any data volume scenario, significantly improving bus utilization. At the same time, it avoids the risk of data loss or verification errors caused by continuous frame transmission, and enhances the reliability of read and write operations.

[0092] See also Figure 2 The present invention also provides a data transmission method for a memory, which can be applied to the above-mentioned memory. The data transmission method may include the following steps:

[0093] Step S100: The memory access module responds to a transmission instruction from an external device and compares the amount of data to be transmitted in the transmission instruction with the storage space of the cache module:

[0094] Step S200: When the amount of data to be transmitted in the transmission instruction is less than or equal to the storage space of the cache module, the data to be transmitted is obtained according to the transmission instruction, and the data to be transmitted is integrated into corresponding data blocks and transmitted to the cache module;

[0095] Step S300: When the amount of data to be transmitted in the transmission instruction is greater than the storage space of the cache module, the data to be transmitted is obtained according to the transmission instruction, and the obtained data to be transmitted is integrated into multiple data blocks according to a preset data amount; and the multiple data blocks are gradually and sequentially transmitted to the cache module; wherein the preset data amount is less than or equal to the storage space of the cache module;

[0096] Step S400: Save the data blocks in the cache module to the flash memory module, or transmit the data blocks in the cache module to an external device through the memory access module.

[0097] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.

Claims

1. A memory, characterized in that: include: Cache module; a memory access module, configured to respond to a transmission instruction from an external device and compare the amount of data to be transmitted in the transmission instruction with the storage space of the cache module; When the amount of data to be transmitted in the transmission instruction is less than or equal to the storage space of the cache module, obtaining the data to be transmitted according to the transmission instruction, integrating the data to be transmitted into corresponding data blocks, and transmitting the data to the cache module; When the amount of data to be transmitted in the transmission instruction is greater than the storage space of the cache module, the data to be transmitted is obtained according to the transmission instruction, and the obtained data to be transmitted is integrated into multiple data blocks according to the preset data amount; gradually and sequentially transmitting a plurality of data blocks to the cache module; wherein the preset data volume is less than or equal to the storage space of the cache module; Flash memory module, used to store data.

2. The memory according to claim 1, wherein The cache module includes a write cache unit; The memory access module includes: A front-end memory access unit is configured to respond to a write instruction of the transmission instruction and compare the amount of data to be transmitted in the write instruction with the storage space of the write cache unit; When the amount of data to be transmitted in the write instruction is less than or equal to the storage space of the write cache unit, obtaining the data to be transmitted from the external device according to the write instruction, integrating the data to be transmitted into corresponding data blocks, and transmitting the data to the write cache unit; When the amount of data to be transmitted in the write instruction is greater than the storage space of the write cache unit, the data to be transmitted is obtained from the external device according to the write instruction, and the obtained data to be transmitted is integrated into a plurality of data blocks according to a preset first data amount; and the plurality of data blocks are transmitted to the write cache unit step by step in sequence; wherein the preset first data amount is less than or equal to the storage space of the write cache unit; A back-end memory access unit is used to write the data blocks in the write cache unit into the flash memory module.

3. The memory according to claim 2, wherein: The front-end memory access unit is further configured to determine, before aggregating the data to be transmitted from the external device to obtain a data block, whether the write cache unit: When no cache data exists in the write cache unit, setting the first data amount to be less than or equal to the storage space of the write cache unit; When cache data exists in the write cache unit, the first data amount is set to be smaller than or equal to a remaining storage space of the write cache unit.

4. The memory according to claim 2, wherein: The cache module also includes a read cache unit; The back-end memory access unit is further configured to respond to a read instruction of the transfer instruction and compare the amount of data to be transferred in the read instruction with the storage space of the read cache unit: When the amount of data to be transmitted in the read instruction is less than or equal to the storage space of the read cache unit, obtaining the data to be transmitted from the flash memory module according to the read instruction, integrating the data to be transmitted into corresponding data blocks, and transmitting the data to the read cache unit; When the amount of data to be transmitted in the read instruction is greater than the storage space of the read cache unit, obtaining the data to be transmitted from the flash memory module according to the read instruction, and integrating the obtained data to be transmitted into multiple data blocks according to a preset second data amount; gradually and sequentially transmitting a plurality of data blocks to the read cache unit; wherein the preset second data amount is less than or equal to the storage space of the read cache unit; The front-end memory access unit is further configured to read the data blocks in the read cache unit to the external device.

5. The memory according to claim 4, wherein: The back-end memory access unit is further configured to determine, before integrating the data to be transmitted in the flash memory module to obtain a data block, whether the read cache unit: When no cache data exists in the read cache unit, setting the second data amount to be less than or equal to the storage space of the read cache unit; When cache data exists in the read cache unit, the second data amount is set to be less than or equal to the remaining storage space of the read cache unit.

6. The memory according to claim 4, wherein: The memory also includes a replay protection module; The replay protection module is used to verify the data blocks in the write cache unit and obtain the verification results; The back-end memory access unit is further configured to process the data blocks in the write cache unit according to the verification result.

7. The memory according to claim 6, wherein: The replay protection module is further configured to: Calculate a corresponding hash authentication code according to a preset shared key and the data block in the write cache unit; Compare the hash check code of the data block in the write cache unit with the corresponding hash authentication code: When it is determined that the hash check code is identical to the corresponding hash authentication code, determining that the verification result is verification passed; When it is determined that the hash check code is different from the corresponding hash authentication code, the verification result is determined to be verification failure.

8. The memory according to claim 6, wherein: The back-end memory access unit is further configured to: When the verification result is verification passed, writing the data block in the write cache unit into the flash memory module; When the verification result is verification failure, the data block in the write cache unit is deleted.

9. The memory according to claim 6, wherein: The replay protection module is further configured to calculate a corresponding hash authentication code based on a preset shared key and a data block in the read cache unit; The front-end memory access unit is further configured to read out the data blocks and corresponding hash authentication codes in the read cache unit to an external device.

10. A data transmission method for a memory, characterized in that: Applied to the memory according to any one of claims 1 to 9, the memory comprising a memory access module, a cache module, and a flash memory module, the data transmission method comprising: The memory access module responds to a transmission instruction from an external device and compares the amount of data to be transmitted in the transmission instruction with the storage space of the cache module. When the amount of data to be transmitted in the transmission instruction is less than or equal to the storage space of the cache module, obtaining the data to be transmitted according to the transmission instruction, integrating the data to be transmitted into corresponding data blocks, and transmitting the data to the cache module; When the amount of data to be transmitted in the transmission instruction is greater than the storage space of the cache module, the data to be transmitted is obtained according to the transmission instruction, and the obtained data to be transmitted is integrated into a plurality of data blocks according to a preset data amount; and the plurality of data blocks are transmitted to the cache module step by step in sequence; wherein the preset data amount is less than or equal to the storage space of the cache module; The data blocks in the cache module are saved to the flash memory module, or the data blocks in the cache module are transmitted to an external device through the memory access module.

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