A fast floating-point division and square root operation method based on radix-4 SRT algorithm

Abstract

The application relates to the field of computer technology, in particular to a fast floating-point division and square root operation method based on a Radix4 SRT algorithm, which comprises the following steps: data preprocessing is performed on operation data to obtain operation standard data, a residual error saved in a CSA form is obtained according to an operation number of the operation standard data, an iteration part of a mantissa is obtained, a partial sum is matched with a preset QDS lookup table to obtain quotient bits / root bits, expressed in a redundant numeral base, the quotient bits / root bits expressed in the redundant numeral base are converted into a standard binary complement form quotient / root according to a fast conversion algorithm; auxiliary bits are generated according to the partial sum of the mantissa and carry information to obtain r / s bits; and finally, a division / square root result is obtained according to the r / s bits and a rounding mode. The application adopts a common lookup table mode, reduces the area requirement of different lookup tables for division and square root, can significantly save hardware resources, and can quickly judge zero remainder and negative remainder conditions in advance through a sign bit detection technology.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computer, in particular to a fast floating-point division and square root operation method based on Radix4 SRT algorithm. BACKGROUND

[0002] Radix-4 SRT algorithm is a high-efficiency algorithm for fast division and square root operation, especially in hardware implementation.

[0003] The traditional method can only process a small number of bits each iteration, resulting in the need for more iteration times to get the result, so the operation speed is slow, especially when processing large-scale data, the time complexity is high; and the traditional method usually needs to design different lookup tables for division and square root, which occupies a large amount of storage space, especially in FPGA or ASIC design, which may cause waste of hardware resources; and the sign bit detection and quotient bit selection process of the traditional method may have more delay, especially when processing negative parts and cases, the calculation of the mantissa quotient may need additional steps to complete correctly, which makes the critical path of the operation process longer, and thus affects the efficiency and working frequency of the entire calculation; and the traditional method is slow due to the full-add operation of CSA, and cannot achieve higher working frequency. SUMMARY

[0004] The technical problem to be solved by the present application is to overcome the shortcomings of the prior art and provide a fast floating-point division and square root operation method based on Radix4 SRT algorithm.

[0005] The technical solution adopted to solve the above technical problems is: a fast floating-point division and square root operation method based on Radix4 SRT algorithm, comprising:

[0006] Obtaining operation data, pre-processing the operation data to obtain operation standard data, and obtaining the mantissa of the operation standard data;

[0007] For division operation, the operation standard data includes standard dividend and standard divisor, the size relationship between the standard dividend and the standard divisor is judged, the bit domain of the mantissa result of the division operation is determined according to the size relationship, the sign bit and the exponent bit of the division operation / square root operation are calculated, and the bias of the operation standard data is restored;

[0008] According to the operand of the operation standard data, the residual error saved in the form of CSA is obtained, the iteration part and the partial sum of the mantissa are obtained, the partial sum is matched with the preset QDS lookup table to obtain the quotient bit / root bit, the redundant numeral base is expressed, and the redundant numeral base expression is converted into the standard binary complement form of quotient / root according to the fast conversion algorithm;

[0009] The auxiliary bit is generated according to the partial sum and the carry information to obtain r / s bits, and the final division / square root result is obtained according to the r / s bits and the rounding mode;

[0010] The zero remainder and the negative remainder are quickly judged in advance according to the sign bit detection of the division / square root operation, and the process is parallel to the normal calculation process.

[0011] Preferably, the operation data is preprocessed to obtain standard operation data, including:

[0012] The operation data is detected for abnormality to determine whether the operation data is abnormal, wherein the abnormality detection includes detection of NaN, detection of Inf and detection of division by zero;

[0013] If the operation data is abnormal, an exception is triggered, corresponding flag bits are directly generated and the result is output, and the subsequent calculation is terminated;

[0014] It is determined whether the operation data is a non-normalized number;

[0015] If the operation data is a non-normalized number, the operation data is normalized and aligned to obtain standard operation data.

[0016] Preferably, the size relationship between the standard dividend and the standard divisor is determined, and the bit field of the remainder result of the division operation is determined according to the size relationship, including:

[0017] The difference between the standard dividend and the standard divisor is calculated by subtraction;

[0018] The sign of the difference is calculated;

[0019] If the difference sign is negative, the division remainder result is between 0 and 1;

[0020] If the difference sign is positive, the division remainder result is between 1 and 2.

[0021] Preferably, the partial sum is matched with a preset QDS lookup table to obtain quotient bits / root bits, including:

[0022] For the division operation, the sum value and the carry value of the partial remainder are determined according to the remainder value in the form of CSA, and then the quotient bits are selected from the QDS lookup table according to the value of the partial remainder, the QDS lookup table provides quotient bits according to the approximate value of the standard dividend and the standard divisor, and the range of the quotient bits is from-2 times the normalized divisor to 2 times the normalized divisor;

[0023] According to the quotient bit, the partial remainder is calculated, wherein the partial remainder is obtained by subtracting the value of the determined quotient bit from the partial remainder of the last iteration;

[0024] According to the partial remainder and the divisor, the QDS lookup table is searched, and the next quotient bit is determined according to the result;

[0025] The iteration is continued, and at the last iteration, the result is corrected according to the current partial remainder, wherein the correction is that if the partial remainder is negative, the quotient is reduced by one; otherwise, the quotient is the original value.

[0026] Preferably, the partial sum is matched with the preset QDS lookup table to obtain the quotient bit / root bit, and the method further comprises:

[0027] For the square root operation, the operation data comprises a square root number, and a polynomial algorithm of A and B is initialized;

[0028] The addition item is calculated according to the initial value of the polynomial algorithm of A and B, wherein the calculation of the addition item is adjusted according to the coefficients of the polynomial algorithm of A and B and the size of the square root number;

[0029] At each iteration, the A and B values are updated by the addition item and the current A and B values to approximate the root bit;

[0030] After multiple iterations, the precision is adjusted to make the root bit meet the expected precision.

[0031] Preferably, the auxiliary bit is generated according to the partial sum of the mantissa and the carry information to obtain the r / s bit, and the final division / square root result is obtained according to the r / s bit and the rounding mode, comprising:

[0032] The partial sum of the mantissa and the carry information are combined to form the final r / s bit.

[0033] According to the sign bit, the exponent value, the mantissa value, the r / s bit and the rounding mode, the final division / square root result is obtained.

[0034] Preferably, according to the sign bit detection of the division / square root operation, zero remainder and negative remainder are quickly judged in advance, comprising:

[0035] According to the QDS lookup table, the partial sum and the carry information, a lookup table of zero remainder and negative remainder is obtained, and the zero remainder and the negative remainder are judged according to the lookup table of zero remainder and negative remainder;

[0036] The zero remainder and the negative remainder are quickly judged in advance according to the sign bit detection of the division / square root operation, which is parallel to the iteration calculation process and does not occupy the main operation path.

[0037] Preferably, the polynomial algorithm of A and B is initialized, comprising:

[0038] By default, the A value is 1 and the B value is 0 in the first iteration. The vertical axis of the QDS table is 1100, and the horizontal axis is the high 7 bits of the partial sum of the first iteration in CSA form.

[0039] Preferably, matching the partial sum with a preset QDS lookup table to obtain the quotient / root position further includes:

[0040] For normalized divisors of 1x and 2x, the subsequent operations are as follows: for operands of 1x, invert the divisor first and then add 1; for operands of 2x, invert the divisor first and then add 1, and then shift the result one bit to the left.

[0041] The result of adding 1 is merged into the Carry value of the previous iteration result and does not occupy the main operation path.

[0042] The beneficial effects of this invention are as follows: (1) This invention uses the Radix4 SRT algorithm to perform floating-point division and square root operations, which can greatly improve the operation speed. It utilizes a larger radix to accelerate the estimation of the quotient / root digit, and each iteration can process more bits, thereby reducing the number of iterations; (2) This invention adopts a shared lookup table approach, which reduces the area requirement of different lookup tables for division and square root. Specifically, division and square root share the QDS lookup table, which can significantly save hardware resources. Especially in FPGA or ASIC design, it can reduce the area occupied by storage and lookup tables, and the residual is carried over. Save format helps improve computational efficiency and avoids carry propagation in real time during each addition operation, thereby improving the parallelism and speed of the operation; (3) This invention avoids unnecessary delays in sign judgment and calculation through a fast sign bit detection method and residual compensation mechanism. In particular, the processing of quotient / root bits is optimized by adding 1 bit to merge them into the end of CSA-Sum for calculation. This makes the sign path and quotient / root bit selection no longer appear in the critical path, thereby speeding up the entire operation process. In each iteration, the precision can be dynamically controlled through r / s bit generation and rounding decision, ensuring that the final result meets the standard of floating point operation. Especially when performing division and square root operations, it can effectively avoid rounding errors and provide high-precision operation results. Attached Figure Description

[0043] Figure 1 This is a schematic diagram of the overall method steps in one embodiment of the present invention. Detailed Implementation

[0044] Example 1, as Figure 1 As shown, the present invention proposes a fast floating-point division and square root operation method based on the Radix4 SRT algorithm, comprising:

[0045] S1, obtain operation data, perform data preprocessing on the operation data to obtain operation standard data, and obtain the mantissa of the operation standard data;

[0046] S2, for division operation, the operation standard data includes standard dividend and standard divisor, judge the size relationship between the standard dividend and the standard divisor, determine the bit field of the mantissa result of the division operation according to the size relationship, calculate the sign bit and the exponent bit of the division operation / root operation, and restore the bias of the operation standard data;

[0047] S3, according to the operand of the operation standard data, obtain the residual saved in the form of CSA, obtain the partial sum of the mantissa, match the partial sum with the preset QDS lookup table to obtain the quotient bit / root bit, express in the form of redundant numeral base, and convert the redundant numeral base expression into the quotient / root in the form of standard binary complement according to the fast conversion algorithm;

[0048] S4, generate auxiliary bits according to the partial sum of the mantissa and the carry information to obtain r / s bits, and obtain the final division / root result according to the r / s bits and the rounding mode;

[0049] S5, according to the sign bit detection of the division / root operation, the zero remainder and the negative remainder are judged in advance, and the process is parallel to the normal calculation process.

[0050] In the application, CSA is an adder for efficient multi-bit addition, which is very useful when handling carry, and can save time and reduce delay in multiple addition operations, especially in multi-bit binary addition; QDS is the abbreviation of "Quotient Digit Set", which refers to the digit set of the quotient, and in Radix-4 SRT algorithm, the lookup table can be used to quickly determine each bit of the quotient (or each bit of the root); when performing division or root calculation, the sign of the final result needs to be judged, and the sign bit is usually 0 (positive) or 1 (negative); according to the type of operation and the sign of the value, the sign bit is calculated; when performing division, if the remainder is zero, the quotient should be completely divisible; if the remainder is negative, it means that the sign of the quotient will change value and needs to be corrected; during the division and root process, it is very important to correctly and quickly handle the zero remainder and the negative remainder.

[0051] In example two, the application provides a fast floating point division and root operation method based on Radix4 SRT algorithm, compared with example one, the embodiment further includes: performing data preprocessing on the operation data to obtain operation standard data, including:

[0052] A1, performing an exception detection on the operation data to determine whether the operation data has an exception, wherein the exception detection comprises detecting NaN, detecting Inf, and detecting division by zero;

[0053] A2, if the operation data has an exception, triggering an exception, directly generating a corresponding flag bit and outputting a result, and terminating subsequent calculation;

[0054] A3, determining whether the operation data is a denormalized number;

[0055] A4, if the operation data is a denormalized number, performing data normalization alignment on the operation data to obtain operation standard data.

[0056] In this embodiment, the exception detection refers to checking the input operands to ensure that they meet the expected specification range or have no special exception conditions (such as NaN, Inf, division by zero, etc.). If an exception is detected, the system will trigger the related exception flag and terminate subsequent calculation to ensure the correctness and safety of the operation result. NaN is a special floating-point number value used to represent an invalid number. Inf is an infinite large or small floating-point number, representing a very large or very small number. Division by zero refers to the situation where the divisor is zero in floating-point calculation. Data normalization alignment refers to adjusting the non-normalized number to a standard floating-point number representation form that meets the specification.

[0057] In an optional embodiment, the size relationship between the standard dividend and the standard divisor is determined, and the bit field of the mantissa result of the division operation is determined according to the size relationship, comprising:

[0058] B1, calculating the difference between the standard dividend and the standard divisor according to subtraction;

[0059] B2, calculating the sign of the difference;

[0060] B3, if the difference sign is negative, the division mantissa result is between [0, 1);

[0061] B4, if the difference sign is positive, the division mantissa result is between [1, 2).

[0062] In an optional embodiment, the partial sum is matched with a preset QDS lookup table to obtain the quotient bit / root bit, comprising:

[0063] C1, for the division operation, first determine the sum of partial remainders and the carry value according to the mantissa value, save in the form of CSA, then select the quotient digit from the QDS lookup table according to the value of the partial remainder, the QDS lookup table provides the quotient digit according to the approximate value of the standard dividend and the standard divisor, the range of the quotient digit is from -2 times the normalized divisor to 2 times the normalized divisor;

[0064] C2, calculate the partial remainder according to the quotient digit, wherein the partial remainder is obtained by subtracting the value of the determined quotient digit from the partial remainder of the last iteration;

[0065] C3, continue to search in the QDS lookup table according to the partial remainder and the divisor, and determine the next quotient digit according to the result;

[0066] C4, continue iteration, and at the last iteration, correct the result according to the current partial remainder, wherein the correction is that if the partial remainder is negative, the quotient is reduced by one; otherwise, the quotient is the original value.

[0067] It should be noted that the carry-lookahead adder is an adder that calculates the carry of each bit addition in advance, thereby speeding up the addition operation. Unlike the traditional "serial carry" adder, the carry-lookahead adder calculates the carry "in advance" in multiple addition operations, reducing the delay. It should be noted that the QDS lookup table is a lookup table for floating point division, which stores pre-calculated quotient digits, and is usually used to quickly select the preliminary approximation of the quotient of division. It quickly obtains the first quotient digit based on the approximate value of the standard dividend and the standard divisor. The purpose of the design of the QDS lookup table is to speed up the division operation and avoid complete bit-by-bit calculation.

[0068] In an optional embodiment, matching the partial sum with the preset QDS lookup table to obtain the quotient digit / root digit further includes:

[0069] C5, for the square root operation, the operation data includes the square root number, initialize the polynomial expressions of A and B;

[0070] C6, calculate the addition term according to the initial value of the polynomial expressions of A and B, wherein the calculation of the addition term is adjusted according to the coefficients of the polynomial expressions of A and B and the size of the square root number;

[0071] C7, update the value of A and B by the addition term and the current value of A and B at each iteration to approximate the root digit;

[0072] C8, after multiple iterations, adjust the precision to make the root digit meet the expected precision.

[0073] It should be noted that the polynomial expression of A and B is usually a mathematical expression representing two auxiliary values used in a certain iteration step, A and B represent two variables or estimates, which are used to approximate the final result (i.e. the value of the square root), and the polynomial expression is used to represent the change rule of the two values in the iteration process.

[0074] In an optional embodiment, the partial sum of the mantissa and the carry information are used to generate auxiliary bits to obtain r / s bits, and according to the r / s bits and the rounding mode, the final division / square root result is obtained, including:

[0075] D1, combining the partial sum of the mantissa and the carry information to form the final r / s bit;

[0076] D2, according to the sign bit, the exponent value, the mantissa value, the r / s bit and the rounding mode, obtaining the final division / square root result.

[0077] In an optional embodiment, according to the sign bit detection of the division / square root operation, the zero remainder and the negative remainder are quickly judged in advance, including:

[0078] E1, according to the QDS lookup table, the partial sum and the carry information, obtaining the lookup table of zero remainder and negative remainder, and judging the zero remainder and the negative remainder according to the lookup table of zero remainder and negative remainder;

[0079] E2, according to the sign bit detection of the division / square root operation, the zero remainder and the negative remainder are quickly judged in advance, which is parallel to the iteration calculation process and does not occupy the main operation path.

[0080] In an optional embodiment, the polynomial algorithm of A and B is initialized, including:

[0081] The default A value of the first iteration is 1, the B value is 0, the vertical axis of the QDS table is 1100, and the horizontal axis is the high 7 bits of the partial sum in the form of CSA of the first iteration.

[0082] It should be noted that according to this implementation step, no additional initial PLA table is needed to perform normal iteration.

[0083] In an optional embodiment, the partial sum is matched with the preset QDS lookup table to obtain the quotient bit / root bit, and further including:

[0084] For 1 times and 2 times of normalized divisor, the subsequent operation is specifically that 1 times of operation number is first negated and then added by 1, and 2 times of operation number is first negated and then added by 1, and the result is uniformly left shifted by one bit;

[0085] The result of the part of adding 1 is merged into the Carry value of the iteration result of the last round, and does not occupy the main operation path.

[0086] The embodiments of the present application are described in detail above with reference to the accompanying drawings, but the present application is not limited to the embodiments, and various changes can be made by those skilled in the art within the scope of knowledge acquired from the present disclosure, without departing from the spirit of the present application.

Claims

1. A fast floating-point division or square root operation method based on the Radix4 SRT algorithm, characterized in that, include: Acquire computational data, perform data preprocessing on the computational data to obtain computational standard data, and obtain the last digit of the computational standard data; For division operations, the standard data for the operation includes a standard dividend and a standard divisor. The size relationship between the standard dividend and the standard divisor is determined. Based on the size relationship, the bit field of the mantissa result of the division operation is determined. The sign bit and exponent bit of the division operation or square root operation are calculated. The bias voltage of the standard data for the operation is restored. The residual stored in CSA form is obtained based on the operands of the standard data. The iterative partial sum of the mantissa is obtained and matched with the preset QDS lookup table to obtain the quotient or root. The redundant digital base is represented by a supersonic conversion algorithm and converted into the standard binary two's complement form of the quotient or root. Auxiliary bits are generated based on the partial sum of the mantissa and the carry information to obtain the r / s bits. Based on the r / s bits and the rounding mode, the final division or square root result is obtained. Based on the QDS lookup table, partial sum and carry information, lookup tables for zero remainder and negative remainder are obtained. Zero remainder and negative remainder are determined based on the lookup tables for zero remainder and negative remainder. Zero remainder and negative remainder are determined in advance based on the sign bit detection of division or square root operation. The process of determining zero remainder and negative remainder in advance is carried out in parallel with the iterative calculation process.

2. The fast floating-point division or square root operation method based on the Radix4 SRT algorithm according to claim 1, characterized in that, The computational data is preprocessed to obtain computational standard data, including: Anomaly detection is performed on the computational data to determine whether there are any anomalies in the computational data. The anomaly detection includes detecting NaN, detecting Inf, and detecting division by zero. If the computational data is abnormal, an exception is triggered, the corresponding flag bit is generated directly, the result is output, and subsequent calculations are terminated. Determine whether the calculated data is a denormalized number; If the computational data is a denormalized number, then the computational data is normalized and aligned to obtain standard computational data.

3. The fast floating-point division or square root operation method based on the Radix4 SRT algorithm according to claim 2, characterized in that, Determining the relationship between the standard dividend and the standard divisor, and determining the bit field of the mantissa result of the division operation based on the relationship, includes: The difference between the standard dividend and the standard divisor is calculated by subtraction. Calculate the sign of the difference; If the difference is negative, the result of the division will be between [0, 1). If the sign of the difference is positive, the result of the division will be between [1, 2).

4. The fast floating-point division or square root operation method based on the Radix4 SRT algorithm according to claim 3, characterized in that, The partial sum is matched against a preset QDS lookup table to obtain the quotient or root position, including: For the division operation, firstly, the sum of the remainders and the carry-in value are determined based on the last digit and stored in the form of CSA. Then, based on the sum of the remainders and the carry-in value, the quotient is selected from the QDS lookup table. The QDS lookup table provides the quotient based on the approximate values ​​of the standard dividend and the standard divisor. The range of the quotient is from -2 times the normalized divisor to 2 times the normalized divisor. A partial remainder is calculated based on the quotient, wherein the partial remainder is obtained by subtracting the partial remainder of the previous iteration from the value of the determined quotient; Based on the remainder and divisor, continue searching in the QDS lookup table and determine the next quotient based on the result; Continue iterating. In the last iteration, the result is corrected based on the current partial remainder. Specifically, if the partial remainder is negative, the quotient is reduced by one; otherwise, the quotient remains the original value.

5. A fast floating-point division or square root operation method based on the Radix4 SRT algorithm according to claim 4, characterized in that, The process of matching the aforementioned portion with a preset QDS lookup table to obtain the quotient or root position also includes: For the square root operation, the operation data includes the square root number and the polynomial expression for initializing A and B, where A and B represent two variables or estimated values; The addition term is calculated based on the initial values ​​of the polynomial expressions A and B, wherein the calculation of the addition term is adjusted according to the coefficients of the polynomial expressions A and B and the size of the square root. In each iteration, the values ​​of A and B are updated using the addition terms and the current values ​​of A and B to approximate the root position. After multiple iterations, the precision is adjusted to ensure that the root position meets the expected precision.

6. The fast floating-point division or square root operation method based on the Radix4 SRT algorithm according to claim 5, characterized in that, Auxiliary bits are generated based on the mantissa and carry information to obtain the r / s bits. Based on the r / s bits and the rounding mode, the final division or square root result is obtained, including: The mantissa portion is combined with the carry information to form the final r / s bit; The final division or square root result is obtained based on the sign bit, exponent value, mantissa value, r / s bit, and rounding mode.

7. A fast floating-point division or square root operation method based on the Radix4 SRT algorithm according to claim 6, characterized in that, Initialize the polynomial operations for A and B, including: By default, the A value is 1 and the B value is 0 in the first iteration. The vertical axis of the QDS table is 1100, and the horizontal axis is the high 7 bits of the partial sum of the first iteration in CSA form.

8. A fast floating-point division or square root operation method based on the Radix4 SRT algorithm according to claim 7, characterized in that, The partial sum is matched against a preset QDS lookup table to obtain the quotient or root position, and also includes: For normalized divisors of 1x and 2x, the subsequent operations are as follows: for operands of 1x, invert the divisor first and then add 1; for operands of 2x, invert the divisor first and then add 1, and then shift the result one bit to the left. The results of inverting the operand by 1 and then adding 1, and inverting the operand by 2 and then adding 1, are merged into the carry value of the previous iteration result.

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