Laptop multi-scenario stress testing method and system for factory inspection

Abstract

The present invention provides a notebook multi-scenario stress testing method and system for factory inspection. First, a hardware configuration parameter set of a target notebook and a factory test scenario parameter set containing multiple test scenario modes are obtained. A multi-scenario test instruction set is generated based on the correlation between the two. The target notebook is triggered to perform stress testing in multiple scenarios and collect a runtime performance data set. Then, anomaly detection processing is performed on the runtime performance data set to generate a hardware component anomaly detection result set and a system stability evaluation result. Finally, a hardware optimization strategy set is generated based on the above results and fed back to the production line control system to trigger the configuration adjustment operation of the target notebook, thereby enabling a comprehensive and accurate evaluation of the notebook performance, realizing closed-loop management from detection to optimization, and improving product quality and production efficiency.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a multi-scenario stress testing method and system for notebook computers applied to factory inspection. Background Art

[0002] In the production and manufacturing process of notebook computers, the factory inspection link is crucial to ensuring product quality. With the increasing richness of notebook functions and the diversification of hardware configurations, traditional factory inspection methods are often difficult to comprehensively and accurately evaluate the performance of notebooks in various actual usage scenarios. At present, existing technologies usually only test notebooks in a single scenario or simple multiple scenarios, and the testing process lacks in-depth consideration of the correlation between hardware configuration parameters and test scenarios, resulting in the inability to fully explore the potential problems of notebooks in different complex scenarios. In addition, after the test is completed, the existing technology does not make full use of the test results, making it difficult to directly provide effective guidance for the hardware configuration adjustment of the production line, and unable to timely optimize the hardware performance of the notebook, which in turn affects the overall quality and market competitiveness of the product. Therefore, there is a need for a more comprehensive, intelligent and directly guided production optimization factory inspection method. Summary of the Invention

[0003] In view of the above-mentioned problems, in combination with the first aspect of the present invention, an embodiment of the present invention provides a multi-scenario stress testing method for a notebook computer applied to factory inspection, the method comprising:

[0004] Obtaining a hardware configuration parameter set and a factory test scenario parameter set of a target notebook, wherein the factory test scenario parameter set includes multiple test scenario modes;

[0005] generating a multi-scenario test instruction set based on the association between the hardware configuration parameter set and the test scenario mode, wherein the multi-scenario test instruction set is used to trigger a stress test operation of the target notebook under multiple test scenario modes;

[0006] Executing the multi-scenario test instruction set to collect runtime performance data sets of the target notebook under different test scenario modes;

[0007] Performing anomaly detection processing on the runtime performance data set to generate an anomaly detection result set of hardware components and a system stability assessment result;

[0008] A hardware optimization strategy set is generated based on the anomaly detection result set and the system stability evaluation result, and the hardware optimization strategy set is fed back to the production line control system to trigger a configuration adjustment operation of the target notebook.

[0009] On the other hand, an embodiment of the present invention also provides a notebook multi-scenario stress testing system for factory inspection, including a processor and a machine-readable storage medium, the machine-readable storage medium is connected to the processor, the machine-readable storage medium is used to store programs, instructions or codes, and the processor is used to execute the programs, instructions or codes in the machine-readable storage medium to implement the above method.

[0010] Based on the above aspects, the embodiment of the present invention obtains the hardware configuration parameter set of the target notebook and the factory test scenario parameter set containing multiple test scenario modes, and generates a multi-scenario test instruction set based on the correlation between the two, which can comprehensively and accurately simulate various complex scenarios of the notebook in actual use, making the stress test closer to the actual usage, thereby more accurately evaluating the performance of the notebook. After executing the multi-scenario test instruction set and collecting the runtime performance data set, the data is processed for anomaly detection, which not only generates an anomaly detection result set of the hardware components, but also obtains the system stability evaluation results, providing rich and accurate information for a comprehensive understanding of the notebook performance. Finally, a hardware optimization strategy set is generated based on these results and fed back to the production line control system, realizing closed-loop management from detection to optimization, and being able to adjust the hardware configuration of the target notebook in a timely and effective manner, significantly improving the overall quality and production efficiency of the product. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 The present invention provides a schematic diagram of the execution flow of a multi-scenario stress testing method for a notebook computer applied to factory inspection.

[0012] Figure 2 This is a schematic diagram of exemplary hardware and software components of a notebook multi-scenario stress testing system for factory inspection provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0013] The present invention will be described in detail below with reference to the accompanying drawings. Figure 1 This is a flow chart of a multi-scenario stress testing method for a notebook computer applied to factory inspection provided by an embodiment of the present invention. The multi-scenario stress testing method for a notebook computer applied to factory inspection is introduced in detail below.

[0014] Step S110: Acquire a hardware configuration parameter set and a factory test scenario parameter set of the target notebook, wherein the factory test scenario parameter set includes a plurality of test scenario modes.

[0015] In this embodiment, in order to conduct a comprehensive factory inspection on the target notebook, it is necessary to first obtain relevant data. The hardware configuration parameter set of the target notebook can be obtained by calling the system information interface provided by the notebook operating system. Taking the Windows system as an example, the WMI (Windows Management Instrumentation) interface can be used to query hardware information. Let the hardware configuration parameter set be H, which includes processor-related parameters H_p, memory-related parameters H_m, graphics card-related parameters H_g, storage device-related parameters H_s, etc. Among them, the processor-related parameters H_p may include processor model, number of cores, number of threads, etc.; memory-related parameters H_m include memory capacity, memory type, memory frequency, etc.; graphics card-related parameters H_g include graphics card model, video memory capacity, video memory frequency, etc.; storage device-related parameters H_s include storage device type (such as mechanical hard disk, solid-state hard disk), storage capacity, etc.

[0016] The factory test scenario parameter set S can be obtained from a preset database. This database stores a variety of test scenario modes for different types of laptops. For example, for laptops designed for gaming and office use, the test scenario modes may include a high-load gaming scenario S_g, a scenario where multiple office applications are running simultaneously S_o, a video editing scenario S_v, and so on. These test scenario modes have different stress levels and resource requirements.

[0017] Step S120: generating a multi-scenario test instruction set based on the association between the hardware configuration parameter set and the test scenario mode, wherein the multi-scenario test instruction set is used to trigger a stress test operation of the target notebook under multiple test scenario modes.

[0018] After obtaining the hardware configuration parameter set H and the factory test scenario parameter set S, we need to analyze the correlation between them to generate a multi-scenario test instruction set. Different hardware configurations will have different performance in different test scenarios. By establishing this correlation, we can develop reasonable test instructions.

[0019] Step S121: extracting processor model parameters, memory capacity parameters, and graphics card specification parameters from the hardware configuration parameter set.

[0020] Extract key parameters from the hardware configuration parameter set H. Let's denote the processor model parameter P_model, whose specific identifier can be obtained through system information queries. The memory capacity parameter is M_capacity, which reflects the amount of available memory on the laptop. The graphics card specification parameter is G_spec, which includes information such as the graphics card model and video memory. These parameters are extracted because they play a key role in different test scenarios. Test instructions will be generated based on how well these parameters match the test scenarios.

[0021] Step S122: determining a resource occupation threshold range required for each test scenario mode according to the scenario stress level corresponding to the test scenario mode.

[0022] For each test scenario mode, the corresponding scenario stress level determines the required resource usage threshold range. For example, the high-load gaming scenario S_g is a high-stress scenario with high resource usage requirements for the processor, memory, and graphics card. The processor resource usage threshold range in this scenario is P_th_g, which is an interval consisting of a lower limit value P_th_g_min and an upper limit value P_th_g_max. The memory resource usage threshold range is M_th_g, which also consists of a lower limit value M_th_g_min and an upper limit value M_th_g_max. The graphics card resource usage threshold range is G_th_g, which consists of a lower limit value G_th_g_min and an upper limit G_th_g_max. For the scenario S_o where multiple office applications are running simultaneously, this is a medium-stress scenario with relatively smaller resource usage threshold ranges. For example, the processor resource usage threshold range is P_th_o, the memory resource usage threshold range is M_th_o, and the graphics card resource usage threshold range is G_th_o. The resource usage threshold ranges for different scenarios can be obtained by statistically analyzing the test data of a large number of notebooks of the same type in the scenario.

[0023] Step S123: Match the processor model parameter with the resource occupancy threshold range of the first test scenario mode to generate a first test instruction subset.

[0024] The first test scenario mode here can be a high-load game running scenario S_g. Match the processor model parameter P_model with the resource occupancy threshold range P_th_g of the processor in this scenario. Different processor models have different performance. For high-performance processors, higher resource occupancy may be required to achieve the test effect. Suppose there is a mapping table T_p between processor model and resource occupancy, and the corresponding resource occupancy reference value P_ref is found in the mapping table according to P_model. If P_ref is within the P_th_g range, the corresponding first test instruction subset I_p is generated. The first test instruction subset I_p contains instructions that trigger the target notebook to perform a stress test on the processor in this scenario, such as starting a specific game program, setting the game's picture quality and resolution, etc., to ensure that the processor's resource occupancy in this scenario is within a reasonable range.

[0025] Step S124: matching the memory capacity parameter with the resource occupancy threshold range of the second test scenario mode to generate a second test instruction subset.

[0026] The second test scenario mode can be a scenario S_o where multiple office software are running simultaneously. Match the memory capacity parameter M_capacity with the memory resource occupancy threshold range M_th_o in this scenario. Different memory capacities will result in different resource occupancy in this scenario. There is also a mapping table T_m of memory capacity and resource occupancy, and the corresponding resource occupancy reference value M_ref is found in the mapping table according to M_capacity. If M_ref is within the range of M_th_o, a second test instruction subset I_m is generated. The second test instruction subset I_m contains instructions that trigger the target notebook to perform a stress test on the memory in this scenario, such as opening multiple office software at the same time, setting the software's operating parameters, etc., to test the performance of the memory.

[0027] Step S125: matching the graphics card specification parameters with the resource occupancy threshold range of the third test scenario mode to generate a third test instruction subset.

[0028] The third test scenario mode can be a video editing scenario S_v. Match the graphics card specification parameter G_spec with the resource occupancy threshold range G_th_v of the graphics card in this scenario. Different graphics card specifications have different performance in the video editing scenario. There is a mapping table T_g of graphics card specifications and resource occupancy, and the corresponding resource occupancy reference value G_ref is found in the mapping table according to G_spec. If G_ref is within the range of G_th_v, a third test instruction subset I_g is generated. The third test instruction subset I_g contains instructions that trigger the target notebook to perform a stress test on the graphics card in this scenario, such as starting video editing software, importing video materials of a specific resolution and length, etc., to test the graphics processing capabilities of the graphics card.

[0029] Step S126: generating the multi-scenario test instruction set by merging the first test instruction subset, the second test instruction subset, and the third test instruction subset according to their priority order.

[0030] Determine the priority order of the first test instruction subset I_p, the second test instruction subset I_m, and the third test instruction subset I_g. The priority can be determined based on factors such as the importance of the test scenario and the criticality of the hardware. Assuming that the high-load game running scenario has high requirements for processor performance, its corresponding first test instruction subset I_p has the highest priority; the scenario of running multiple office software at the same time has certain requirements for memory performance, and the second test instruction subset I_m has the second priority; the video editing scenario has high requirements for graphics card performance, and the third test instruction subset I_g has the third priority. According to this priority order, the three test instruction subsets are merged into a multi-scenario test instruction set I. During the merging process, the order and integrity of the instructions are ensured so that the target notebook can perform stress tests of different scenarios in a reasonable order.

[0031] Step S130: executing the multi-scenario test instruction set to collect a set of runtime performance data of the target notebook in different test scenario modes.

[0032] After generating the multi-scenario test instruction set I, start executing the multi-scenario test instruction set I to collect runtime performance data of the target notebook under different test scenario modes.

[0033] Step S131: calling the test execution engine to load the multi-scenario test instruction set, and triggering the target notebook to enter multiple test scenario modes in sequence according to a preset test sequence.

[0034] Use the test execution engine E to load the multi-scenario test instruction set I. The test execution engine E is a program module specifically used to execute test instructions. It can parse each instruction in the multi-scenario test instruction set I and trigger the target laptop to enter different test scenario modes in sequence according to the preset test sequence. The preset test sequence can be determined based on the characteristics of the test scenario and the relevance of the hardware. For example, the processor-related high-load game running scenario test is performed first, followed by the memory-related multi-office software running scenario test, and finally the graphics card-related video editing scenario test.

[0035] Step S132: In the first test scenario mode, core temperature data, clock frequency fluctuation data, and thread load balancing data of the processor are collected in real time.

[0036] In the high-load game running scenario S_g, a temperature sensor is used to collect the core temperature data T_p of the processor in real time. The temperature sensor is installed near the processor and can accurately measure the temperature changes of the processor. At the same time, the system monitoring tool collects the clock frequency fluctuation data F_p of the processor in real time. This clock frequency fluctuation data F_p reflects the frequency adjustment of the processor under different loads. In addition, thread load balancing data L_p is collected, which indicates the load distribution of each thread of the processor. This data can be obtained through the performance monitoring interface provided by the operating system. The collected core temperature data T_p, clock frequency fluctuation data F_p, and thread load balancing data L_p are integrated to form the runtime performance data subset D_p1 of the processor in this scenario.

[0037] Step S133: In the second test scenario mode, the read and write rate data, cache hit rate data and virtual memory occupancy rate data of the memory are collected in real time.

[0038] In the scenario S_o where multiple office software are running simultaneously, a memory monitoring tool is used to collect the memory read and write rate data R_m in real time. The read and write rate data R_m reflects the read and write speed of the memory data and can be obtained by counting the time and data volume of the memory operation. At the same time, the cache hit rate data H_m is collected, which indicates the proportion of data hits in the memory cache, reflecting the effectiveness of the cache. In addition, the virtual memory occupancy data V_m is collected, which indicates the usage of the virtual memory. These data can also be obtained through the performance monitoring interface provided by the operating system. The collected read and write rate data R_m, cache hit rate data H_m and virtual memory occupancy data V_m are integrated to form the runtime performance data subset D_m1 of the memory in this scenario.

[0039] Step S134: In the third test scenario mode, the rendering frame rate data, the video memory bandwidth utilization data and the graphics processing delay data of the graphics card are collected in real time.

[0040] In the video editing scenario S_v, a graphics card monitoring tool is used to collect the rendering frame rate data F_g of the graphics card in real time. The rendering frame rate data reflects the speed of the graphics card in processing graphics, which can be obtained by counting the number of frames rendered per unit time. At the same time, the video memory bandwidth utilization data U_g is collected, which indicates the usage ratio of the video memory bandwidth and reflects the working efficiency of the video memory. In addition, the graphics processing delay data D_g is collected, which indicates the time delay from the input of the graphics data to the completion of the graphics card processing and output. These data can be obtained through the monitoring interface provided by the graphics card driver. The collected rendering frame rate data F_g, video memory bandwidth utilization data U_g and graphics processing delay data D_g are integrated to form the runtime performance data subset D_g1 of the graphics card in this scenario.

[0041] Step S135: Integrate the core temperature data, clock frequency fluctuation data, thread load balancing data, read and write rate data, cache hit rate data, virtual memory occupancy data, rendering frame rate data, video memory bandwidth utilization data and graphics processing delay data into the runtime performance data set.

[0042] The runtime performance data subset D_p1 of the processor in a high-load gaming scenario, the runtime performance data subset D_m1 of the memory in a scenario with multiple office applications running simultaneously, and the runtime performance data subset D_g1 of the graphics card in a video editing scenario are integrated to form the runtime performance data set D. During the integration process, the accuracy and completeness of the data are ensured to provide comprehensive data support for subsequent anomaly detection and processing.

[0043] Step S140: performing anomaly detection processing on the runtime performance data set to generate an anomaly detection result set of the hardware components and a system stability evaluation result.

[0044] After obtaining the runtime performance data set D, it is necessary to perform anomaly detection processing on it to find out possible anomalies of hardware components and evaluate the stability of the system.

[0045] Step S141: performing multi-dimensional feature alignment processing on each feature dimension data in the runtime performance data set, performing range normalization based on the statistical distribution range of each data dimension, and generating a standardized runtime feature matrix.

[0046] The runtime performance data set D contains data from multiple feature dimensions, such as the core temperature of the processor, clock frequency fluctuations, memory read and write rates, cache hit rates, graphics card rendering frame rates, memory bandwidth utilization, etc. First, these feature dimension data are subjected to multi-dimensional feature alignment to ensure that the data of each feature dimension is aligned in time series. Then, range normalization is performed based on the statistical distribution range of each data dimension. Let the data set of a certain data dimension be D_i, its minimum value is D_i_min, and its maximum value is D_i_max. For each data point x in D_i, the result after range normalization is (x-D_i_min) / (D_i_max-D_i_min). This standardization process is performed on all data dimensions, and finally a standardized runtime feature matrix M is generated.

[0047] Step S142: Construct an anomaly detection model based on a variational autoencoder, wherein the encoder network uses a bidirectional long short-term memory network to extract contextual association features across time steps, and the decoder network uses a gated convolutional network to reconstruct the input feature sequence.

[0048] An anomaly detection model based on a variational autoencoder was constructed. This anomaly detection model consists of an encoder network and a decoder network. The encoder network uses a bidirectional long short-term memory (Bi-LSTM) network to extract contextual features across time steps. Bi-LSTM networks can simultaneously consider both forward and backward information in time series data, thereby better capturing the contextual relationships of the data. The decoder network uses a gated convolutional network to reconstruct the input feature sequence. By introducing a gating mechanism, the gated convolutional network can better control the transmission of features and the flow of information.

[0049] Step S1421: constructing an independent encoder branch and decoder branch for each hardware component type, wherein the input layer of the encoder branch receives the processor feature sub-matrix, memory feature sub-matrix and graphics card feature sub-matrix after the standardized runtime feature matrix is ​​split.

[0050] Separate encoder and decoder branches are constructed for each hardware component type: processor, memory, and graphics card. The standardized runtime feature matrix M is partitioned by hardware component type, yielding the processor feature submatrix M_p, the memory feature submatrix M_m, and the graphics card feature submatrix M_g. The encoder branch's input layer receives these submatrices, allowing the features of each hardware component to be processed independently.

[0051] Step S1422: In the encoder branch, the forward and reverse hidden state calculations in the time dimension are performed on the input feature submatrix through a bidirectional long short-term memory network, and the forward output vector and the reverse output vector are spliced ​​according to the time step to generate a fused feature vector containing context associations across time steps.

[0052] In the encoder branch, a bidirectional long short-term memory network processes the input feature submatrix. For the processor feature submatrix M_p, the bidirectional long short-term memory network performs forward and backward hidden state calculations. Let the forward hidden state sequence be H_f_p and the backward hidden state sequence be H_b_p. These are concatenated by time step to obtain a fused feature vector V_p that contains contextual associations across time steps. The same method is applied to the memory feature submatrix M_m and the graphics card feature submatrix M_g, resulting in fused feature vectors V_m and V_g, respectively.

[0053] Step S1423: Input the fused feature vector into the multi-head self-attention module of the encoder branch, divide the feature vector into multiple subspaces, calculate the correlation weight matrix between features at different time steps, and generate an attention-enhanced temporal feature representation through weighted summation.

[0054] The fused feature vectors V_p, V_m, and V_g are fed into the multi-head self-attention module in the encoder branch. The module partitions the feature vectors into multiple subspaces and calculates the correlation weight matrix between features at different time steps in each subspace. By taking a weighted sum of these correlation weight matrices, it generates the attention-enhanced temporal feature representations A_p, A_m, and A_g. The module can better capture long-range dependencies between features, improving the model's feature extraction capabilities.

[0055] Step S1424: Map the temporal feature representation into a mean vector and a variance vector of a latent space through the fully connected layer of the encoder branch, and calculate the KL divergence between the mean vector and the variance vector and a preset Gaussian prior distribution based on the mean vector and the variance vector.

[0056] The attention-enhanced temporal feature representations A_p, A_m, and A_g are mapped through the fully connected layers of the encoder branch, respectively, to obtain the mean vectors μ_p, μ_m, μ_g and variance vectors σ_p, σ_m, σ_g of the latent space. The KL divergence between these mean and variance vectors and the preset Gaussian prior distribution is then calculated. The KL divergence measures the difference between two probability distributions. By calculating the KL divergence, the model can learn the distribution characteristics of the latent space.

[0057] Step S1425: In the decoder branch, the latent variable sequence after reparameterization sampling is input into the gated convolutional network, and the multi-scale temporal dependency is captured by stacking causal convolutional layers with different expansion rates. The output of each convolutional layer is element-wise multiplied with the gated linear unit to control the feature transfer path.

[0058] In the decoder branch, the mean and variance vectors of the latent space are reparameterized and sampled to obtain the latent variable sequences Z_p, Z_m, and Z_g. These latent variable sequences are fed into a gated convolutional network (GCN). GCNs capture multi-scale temporal dependencies by stacking causal convolutional layers with varying dilation rates. The output of each convolutional layer is element-wise multiplied by a gated linear unit (GLU). This GLU controls the feature transfer path, enabling the model to better learn the temporal characteristics of the data.

[0059] Step S1426: introducing residual connections between adjacent layers of the gated convolutional network, adding shallow convolution outputs and deep gated outputs channel by channel, and generating a multi-level fused reconstructed feature sequence.

[0060] Residual connections are introduced between adjacent layers of the gated convolutional network. Residual connections can alleviate the vanishing gradient problem, allowing the model to more effectively learn deep features. The shallow convolution output is added channel by channel with the deep gated output to generate a multi-level fused reconstructed feature sequence R_p, R_m, and R_g.

[0061] Step S1427: The mean square error between the reconstructed feature sequence and the original input feature submatrix is ​​used as the reconstruction loss term, and the KL divergence and the reconstruction loss term are added according to a preset weight coefficient to construct a joint loss function of the variational autoencoder.

[0062] Calculate the mean squared error between the reconstructed feature sequences R_p, R_m, and R_g and the original input feature submatrices M_p, M_m, and M_g as the reconstruction loss terms L_r_p, L_r_m, and L_r_g. Add the previously calculated KL divergence to the reconstruction loss terms using preset weights to construct the joint loss functions L_p, L_m, and L_g for the variational autoencoder. This joint loss function comprehensively accounts for both reconstruction error and differences in the latent space distribution, enabling the model to better learn the characteristics of the data.

[0063] Step S1428: Adopting an adversarial training strategy, the latent variable sequence is input into the discriminant network for true and false classification, an adversarial loss term is generated, and the adversarial loss term is gradient-weighted fused with the joint loss function to complete the parameter optimization of the variational autoencoder.

[0064] An adversarial training strategy is used to further optimize the parameters of the variational autoencoder. The latent variable sequences Z_p, Z_m, and Z_g are fed into the discriminant network for true / false classification, generating adversarial loss terms L_a_p, L_a_m, and L_a_g. The adversarial loss terms are then gradient-weightedly fused with the joint loss function. The variational autoencoder parameters are then updated using a backpropagation algorithm, enabling the model to better learn the distribution characteristics of the data and improve the accuracy of anomaly detection.

[0065] Step S143: Split the standardized runtime feature matrix into a processor feature sub-matrix, a memory feature sub-matrix, and a graphics card feature sub-matrix according to the hardware component type, and input them into the encoder network to generate latent space probability distribution parameters respectively.

[0066] After constructing the standardized runtime feature matrix, we segment it by hardware component type. The standardized runtime feature matrix is ​​denoted as M, and the resulting sub-matrixes are the processor feature matrix M_p, the memory feature matrix M_m, and the graphics card feature matrix M_g. This is because the performance characteristics of different hardware components have different characteristics and correlations. Separate processing helps more accurately detect anomalies in each component.

[0067] Afterwards, these three feature sub-matrices are input into the already constructed encoder network. The encoder network consists of a bidirectional long short-term memory network and a multi-head self-attention module. Taking the processor feature sub-matrix M_p as an example, the bidirectional long short-term memory network calculates its forward and reverse hidden states in the time dimension, concatenating the forward output vector and the reverse output vector by time step to obtain a fused feature vector V_p containing contextual associations across time steps. Next, the multi-head self-attention module processes V_p, dividing it into multiple subspaces and calculating the correlation weight matrix between features at different time steps. The weighted summation generates an attention-enhanced temporal feature representation A_p. Finally, after passing through the fully connected layer of the encoder branch, A_p is mapped to the mean vector μ_p and variance vector σ_p of the latent space. These two vectors constitute the probability distribution parameters of the processor components in the latent space. The same process is applied to the memory feature submatrix M_m and the graphics card feature submatrix M_g to obtain the latent space probability distribution parameters μ_m and σ_m of the memory component, and the latent space probability distribution parameters μ_g and σ_g of the graphics card component, respectively.

[0068] Step S144: reparameterize and sample the parameters of the latent space probability distribution based on a preset Gaussian distribution prior to generate a latent variable sequence that conforms to the characteristic distribution of the hardware component during normal operation, and reconstruct the corresponding output feature sequence through the decoder network.

[0069] After obtaining the parameters for the latent space probability distribution of each hardware component, reparameterization sampling is performed based on a preset Gaussian distribution prior. This Gaussian distribution prior represents the ideal distribution of the latent space when the hardware component is operating normally. Taking the processor component as an example, based on its mean vector μ_p and variance vector σ_p, a reparameterization technique is used to sample the latent variable sequence Z_p from the preset Gaussian distribution. The purpose of reparameterization is to enable efficient backpropagation during model training, thereby optimizing model parameters.

[0070] The generated latent variable sequence Z_p is input into the decoder network. The decoder network uses a gated convolutional network, which captures multi-scale temporal dependencies by stacking causal convolutional layers with different dilation rates. The output of each convolutional layer is element-wise multiplied by a gated linear unit to control the feature transfer path. Simultaneously, residual connections are introduced between adjacent layers of the gated convolutional network, and the shallow convolution outputs are added channel-by-channel with the deep gated outputs to generate a multi-level fused reconstructed feature sequence R_p. The same process is performed on the latent variable sequence Z_m of the memory component and the latent variable sequence Z_g of the graphics card component, resulting in the reconstructed feature sequences R_m and R_g of the memory and graphics card components, respectively.

[0071] Step S145: A windowed Euclidean distance algorithm is used to calculate the local timing deviation value between the input feature sequence and the reconstructed feature sequence of each hardware component, and the timing anomaly score of the hardware component is generated by combining the time step importance weight output by the bidirectional long short-term memory network.

[0072] For each hardware component, a windowed Euclidean distance algorithm is used to calculate the local timing deviation between the input feature sequence and the reconstructed feature sequence. For the processor component, for example, the input feature sequence is the processor feature submatrix M_p, and the reconstructed feature sequence is R_p. M_p and R_p are divided into multiple windows based on time steps. Within each window, the Euclidean distance is calculated to obtain a series of local timing deviation values. Euclidean distance measures the spatial distance between two vectors, and in this case, represents the degree of difference between the input and reconstructed features at a local time step.

[0073] When processing input features, the bidirectional long short-term memory network outputs importance weights for each time step. These weights reflect the importance of features at different time steps to the overall feature representation. The local timing deviation value for each window is multiplied by the corresponding time step importance weight, and the results are accumulated across all windows to obtain the timing anomaly score S_p for the processor component. The same method is applied to the memory component and the graphics card component, resulting in the timing anomaly scores S_m and S_g for the memory and graphics card components, respectively.

[0074] Step S146: Input the time series anomaly score into a pre-trained graph neural network classifier, perform graph convolution aggregation based on the topological dependency between hardware components, and generate anomaly propagation paths and key anomaly node identifiers.

[0075] The timing anomaly scores S_p, S_m, and S_g of each hardware component are input into a pre-trained graph neural network classifier. Graph neural networks are capable of processing data with topological structures, where the topology refers to the topological dependencies between hardware components. Hardware components have certain connections and interactions. For example, the processor and memory require frequent data exchange, while the processor and graphics card also have data transmission and collaborative work relationships.

[0076] The graph neural network classifier aggregates time series anomaly scores through graph convolution operations. During the graph convolution process, each node (i.e., hardware component) is updated based on the information of its neighboring nodes, thereby capturing the propagation of anomalies across hardware components. After multiple graph convolution operations, an anomaly propagation path is generated. This path describes how an anomaly propagates from one hardware component to other components. Furthermore, based on the output of the graph neural network, key anomaly nodes are identified. Key anomaly nodes are nodes that play a crucial role in the anomaly propagation process. Handling anomalies at these nodes is crucial for resolving anomaly issues across the entire system.

[0077] Step S147: Calculate the composite abnormality probability value of the hardware component according to the influence weight of the node in the abnormal propagation path and the attenuation coefficient of the time series abnormality score, and generate an abnormality type classification label based on the key abnormal node identifier.

[0078] Each node (hardware component) in the anomaly propagation path has a certain influence weight. This weight indicates the node's importance in the anomaly propagation process. For example, as a core component of a system, the processor's influence weight may be relatively high. Furthermore, the time series anomaly score has an attenuation coefficient, which reflects the degree to which the anomaly weakens during propagation.

[0079] Taking the processor component as an example, the composite anomaly probability value P_p of the processor component is calculated based on the influence weight W_p of the processor node in the anomaly propagation path, the timing anomaly score S_p, and the attenuation coefficient α_p. The composite anomaly probability value comprehensively considers the anomaly of the node itself and the impact of the anomaly during the propagation process.

[0080] Based on the identification of key abnormal nodes and predefined abnormality classification rules, an abnormality classification label is generated. For example, if the key abnormal node is the processor and its composite abnormality probability value is high, the corresponding abnormality classification label may be "Processor Performance Abnormal." The same method is applied to the memory component and the graphics card component, respectively, to obtain the composite abnormality probability value P_m and abnormality classification label for the memory component, and the composite abnormality probability value P_g and abnormality classification label for the graphics card component.

[0081] Step S148: jointly encode the composite abnormality probability value and the abnormality type classification label of the same hardware component to generate an abnormality detection result set of the hardware component.

[0082] The composite anomaly probability value and anomaly type classification label for the same hardware component are jointly encoded. Taking the processor component as an example, its composite anomaly probability value P_p and anomaly type classification label T_p are encoded to form an encoding vector E_p containing the anomaly information. The same process is repeated for the memory and graphics card components, resulting in encoding vectors E_m and E_g for the memory and graphics card, respectively. These encoding vectors are combined to generate the hardware component anomaly detection result set R, which includes the anomaly detection results for the processor, memory, and graphics card components.

[0083] Step S149: Extract the time series of the composite abnormality probability values ​​of all hardware components, construct a multi-dimensional abnormality evolution tensor, and extract the spatiotemporal correlation features of the abnormal pattern through the spatiotemporal convolutional neural network.

[0084] Extract the time series of the composite anomaly probability values ​​for all hardware components. For example, for the processor component, its composite anomaly probability values ​​at different time steps form a time series P_p_t. Similarly, the memory component and graphics card component have time series P_m_t and P_g_t, respectively. These time series are combined to construct a multidimensional anomaly evolution tensor, T. This multidimensional anomaly evolution tensor reflects the evolution of anomalies across time and space (for different hardware components).

[0085] The multidimensional anomaly evolution tensor T is input into the spatiotemporal convolutional neural network. The spatiotemporal convolutional neural network can process information in both time and space dimensions simultaneously.

[0086] Step S1491: Expand the multi-dimensional abnormal evolution tensor according to the time dimension and the hardware component dimension to construct a spatiotemporal grid data structure.

[0087] The multidimensional anomaly evolution tensor T is expanded along the time and hardware component dimensions. The time dimension represents different time steps, while the hardware component dimension represents components such as the processor, memory, and graphics card. This expansion constructs a spatiotemporal grid data structure G. In this spatiotemporal grid data structure G, each grid point corresponds to the composite anomaly probability value of a hardware component at a specific time step. For example, grid point G(i, j) represents the composite anomaly probability value of the i-th hardware component at the j-th time step. This spatiotemporal grid data structure facilitates subsequent spatiotemporal feature extraction.

[0088] Step S1492: Construct a spatial dependency graph based on the physical connection relationship between hardware components, and use graph convolution operation to aggregate the abnormality probability values ​​of hardware components with direct dependency relationships to generate a spatial dependency feature graph.

[0089] A spatial dependency graph S is constructed based on the physical connections between hardware components. The physical connections between hardware components determine how they transmit data and work together. For example, the processor and memory are connected via a bus, and the processor and graphics card also have specific interfaces. In the spatial dependency graph S, nodes represent hardware components, and edges represent the physical connections between components.

[0090] Graph convolution is used to process the spatial dependency graph S. For each node (hardware component), the anomaly probability values ​​of its direct neighboring nodes are aggregated. For example, for a processor node, the anomaly probability values ​​of its directly connected memory and graphics nodes are aggregated. Multiple graph convolution operations are performed to generate a spatial dependency feature graph F_s. This spatial dependency feature graph reflects the impact of spatial dependencies between hardware components on anomaly probability.

[0091] Step S1493: Separable convolution kernels are used in the time dimension to extract short-term fluctuation patterns and long-term trend patterns respectively, and multi-scale time series features are fused through a gating mechanism.

[0092] In the time dimension, separable convolution kernels are used to process the spatiotemporal grid data structure G. Separable convolution kernels decompose the convolution operation into multiple smaller convolution operations, reducing the computational effort. Separable convolution kernels of different sizes are used to extract short-term fluctuation patterns and long-term trend patterns. Short-term fluctuation patterns reflect rapid changes in anomaly probability over a short period of time, while long-term trend patterns reflect the overall trend of anomaly probability over a longer period of time.

[0093] A gating mechanism is used to fuse multi-scale time series features. The gating mechanism can control the transmission of information based on the importance of the features. For example, for short-term fluctuation patterns and long-term trend patterns, a weight is calculated through the gating unit, and the two patterns are weightedly fused based on this weight to obtain the fused time series feature F_t.

[0094] Step S1494: perform tensor splicing on the spatial dependency feature map and the fused temporal features, and input the tensors into a three-dimensional convolutional layer to extract joint correlation pattern features across time and space.

[0095] The spatial dependency feature map F_s is concatenated with the fused temporal feature F_t to obtain the concatenated feature F_st. F_st is then fed into a 3D convolutional layer. This layer simultaneously processes information in the temporal, spatial, and feature dimensions, extracting the cross-temporal and spatial joint correlation pattern feature F_c through convolution. This cross-temporal and spatial joint correlation pattern feature reflects the comprehensive temporal and spatial correlation of anomalies and is crucial for a comprehensive understanding of anomaly patterns.

[0096] Step S1495: perform channel attention weighting on the joint correlation pattern features, map the weighted features to a low-dimensional embedding space, and generate a spatiotemporal correlation feature vector for subsequent Transformer encoder processing.

[0097] Perform channel-wise attention weighting on the joint correlation pattern feature F_c. The channel-wise attention mechanism calculates the importance weight of each channel and weights the channels accordingly, highlighting important feature channels. After channel-wise attention weighting, the weighted feature F_cw is obtained.

[0098] The weighted features F_cw are mapped to a low-dimensional embedding space. Through linear transformations and other operations, the high-dimensional features F_cw are converted into a low-dimensional feature vector F_es. This low-dimensional feature vector is the spatiotemporal correlation feature vector, which contains the spatiotemporal correlation information of the abnormal pattern and serves as the input to the subsequent Transformer encoder.

[0099] Step S150: generating a hardware optimization strategy set based on the anomaly detection result set and the system stability evaluation result, and feeding the hardware optimization strategy set back to the production line control system to trigger a configuration adjustment operation of the target notebook.

[0100] After obtaining the hardware component anomaly detection result set R and the system stability assessment results, a hardware optimization strategy set is generated based on these results. The anomaly detection result set R contains the anomaly information of each hardware component, and the system stability assessment results reflect the stability of the entire system.

[0101] Step S151: Determine the optimization direction that needs to be performed on each hardware component based on the anomaly type classification label and the compound anomaly probability value in the anomaly detection result set.

[0102] For the processor component, if the exception type classification label is "Processor Performance Abnormal" and the composite abnormality probability value is high, you may need to optimize the processor's cooling strategy or adjust the processor's operating frequency. For the memory component, if the exception type classification label is "Memory Read / Write Abnormal", you may need to optimize the memory allocation strategy or check whether the memory hardware is faulty. For the graphics card component, if the exception type classification label is "Graphics Card Rendering Abnormal", you may need to update the graphics card driver or adjust the graphics card settings.

[0103] Step S152: Based on the system stability evaluation results, the optimization direction of each hardware component is comprehensively considered and adjusted.

[0104] The system stability assessment results reflect the overall system operating status. If system stability is poor, comprehensive adjustments to the optimization strategies of multiple hardware components may be necessary. For example, if both processor and memory anomalies significantly impact system stability, it may be necessary to optimize both processor cooling and memory allocation strategies to improve overall system stability.

[0105] Step S153: Generate a specific hardware optimization strategy based on the determined optimization direction.

[0106] For the processor component, if it's determined that cooling optimization is necessary, hardware optimization strategies can be generated, including increasing the speed of the cooling fan and improving the design of the cooling channel. If the processor's operating frequency needs to be adjusted, specific parameters and rules for frequency adjustment can be generated. For the memory component, if the memory allocation strategy needs to be optimized, a strategy for dynamically adjusting the memory allocation ratio can be generated. For the graphics card component, if the graphics card driver needs to be updated, instructions can be generated to download and install the latest driver.

[0107] Step S154: Combine the generated hardware optimization strategies into a hardware optimization strategy set, and feed it back to the production line control system.

[0108] The specific hardware optimization policies generated for each hardware component are combined to form a hardware optimization policy set O. This hardware optimization policy set O is fed back to the production line control system C. The production line control system C adjusts the target laptop's configuration based on these optimization policies. For example, if the hardware optimization policy set includes a policy for adjusting the processor's operating frequency, the production line control system will adjust the processor's operating frequency through the corresponding control interface; if it includes a policy for updating the graphics card driver, the production line control system will automatically download and install the latest graphics card driver.

[0109] Furthermore, the method may further include:

[0110] Step S210: Determine a test intensity parameter of a storage performance test scenario according to the storage device type parameter in the hardware configuration parameter set.

[0111] After obtaining the hardware configuration parameter set H, the storage device type parameter H_s_type is extracted. Different storage device types have different performance characteristics and applicable scenarios. For example, mechanical hard drives and solid-state drives differ in read and write speeds, durability, and other aspects. Based on the storage device type parameter H_s_type, the test intensity parameter I_s for the storage performance test scenario is determined by referring to the preset storage performance test intensity parameter table T_s. The storage performance test intensity parameter I_s determines the difficulty and requirements of subsequent storage performance testing.

[0112] Step S220: Generate a storage stress test instruction subset according to the test intensity parameter, where the storage stress test instruction subset is used to trigger a storage performance test of the target notebook in a continuous read and write scenario.

[0113] Based on the determined storage performance test intensity parameter I_s, a storage stress test instruction subset I_s_sub is generated. This storage stress test instruction subset I_s_sub contains specific instructions for triggering the target laptop to perform a storage performance test in a continuous read / write scenario. For example, if the test intensity parameter is high, the instruction subset may include instructions for simultaneously writing and reading a large number of files, as well as instructions for setting parameters such as file size and read / write frequency.

[0114] Step S230: adding the storage stress test instruction subset to the multi-scenario test instruction set, and updating the test scenario mode in the factory test scenario parameter set.

[0115] The generated storage stress test instruction subset I_s_sub is added to the previously generated multi-scenario test instruction set I, resulting in an updated multi-scenario test instruction set I_updated. Simultaneously, the test scenario modes in the factory test scenario parameter set S are updated, and the storage performance test scenario S_s is added to the test scenario mode list. This way, in subsequent testing, the target laptop will have the storage performance test scenario added to it.

[0116] Furthermore, step S130 may further include:

[0117] Step S136: In the storage stress test scenario mode, continuous write rate data, random read latency data and bad block detection results of the storage device are collected in real time.

[0118] In the storage stress test scenario mode S_s, a specialized storage performance monitoring tool is used to collect real-time data related to the storage device. Continuous write operations are performed on the storage device to measure the continuous write rate data R_w. This data reflects the speed performance of the storage device when continuously writing data. Random read operations are also performed to record the random read latency data D_r. This data represents the response time of the storage device when randomly reading data. Furthermore, a bad block detection algorithm is used to test the storage device, generating a bad block detection result B. This bad block detection result indicates whether there are any damaged storage blocks in the storage device.

[0119] Step S137: performing decay cycle analysis on the continuous write rate data to generate a write performance decay curve.

[0120] Perform decay cycle analysis on the collected continuous write rate data R_w. By observing and analyzing the changes in the continuous write rate data over time, identify its decay patterns and cycles. Draw a write performance decay curve C_w with time as the horizontal axis and the continuous write rate as the vertical axis. The write performance decay curve can intuitively reflect the performance changes of the storage device during the continuous write process, such as whether there is a trend of gradual performance decline.

[0121] Step S138: performing distribution statistics processing on the random read delay data to generate a delay distribution histogram.

[0122] Perform distribution statistics on the random read latency data D_r. The frequency of data occurrence within different latency time intervals is counted, and a latency distribution histogram H_d is generated, with the latency time interval as the horizontal axis and the frequency as the vertical axis. The latency distribution histogram can show the distribution of random read latency data, such as whether data within certain latency time intervals appears more frequently, which may indicate potential problems with the storage device.

[0123] Step S139: determining the storage performance abnormality type according to the slope of the write performance decay curve and the peak position of the delay distribution histogram.

[0124] The storage performance anomaly type is determined based on the slope of the write performance decay curve C_w and the peak position of the latency distribution histogram H_d. If the slope of the write performance decay curve is large, it indicates that the storage device's write performance is degrading rapidly, possibly due to issues such as storage media aging or insufficient write cache. If the peak position of the latency distribution histogram is biased towards a larger delay time interval, it indicates that the storage device has high random read latency, possibly due to internal read / write conflicts or poor storage controller performance. Based on these characteristics and pre-defined anomaly type classification rules, the storage performance anomaly type T_s_anomaly is determined.

[0125] Furthermore, step S140 may further include:

[0126] Step S1410: Add the storage performance anomaly type to the anomaly detection result set.

[0127] The storage performance anomaly type T_s_anomaly is added to the previously generated anomaly detection result set R. The anomaly detection result set R already includes anomaly detection results for the processor, memory, and graphics card components. Information related to the storage performance anomaly type is now incorporated into it. Specifically, the storage performance anomaly type T_s_anomaly is encoded to maintain consistency in data structure and format with the anomaly detection results for the processor, memory, and graphics card components, facilitating unified processing and analysis. Each storage performance anomaly type is assigned a unique identifier and associated with its corresponding composite anomaly probability value (which can be obtained from storage performance data using a similar anomaly probability calculation method for hardware components, such as combining continuous write rate data, random read latency data, and bad block detection results, denoted as P_s_anomaly) to form a new encoding vector E_s_anomaly. This new encoding vector E_s_anomaly is then added to the anomaly detection result set R, resulting in an updated anomaly detection result set R_updated. This updated anomaly detection result set now fully encompasses anomaly detection information for all hardware components, including storage devices.

[0128] Furthermore, step S150 may further include:

[0129] Step S155: When the storage performance abnormality type is a specified type, a storage controller optimization policy is generated, where the storage controller optimization policy includes adjusting a cache policy or enabling a redundancy check mechanism.

[0130] In the updated anomaly detection result set R_updated, the system determines whether the storage performance anomaly type T_s_anomaly is a specified type. Specified types are predefined anomaly types that require optimization, such as severe degradation of storage device read / write performance or frequent bad blocks. If the storage performance anomaly type T_s_anomaly is a specified type, a corresponding storage controller optimization policy is generated based on the specific anomaly.

[0131] If the anomaly manifests as slow read and write speeds on the storage device, it may be due to an inappropriate cache policy. In this case, the generated storage controller optimization policy is to adjust the cache policy. This can include increasing the cache size to temporarily store more data, reducing frequent read and write operations on the storage media, and thus improving read and write speeds. It can also involve adjusting the cache replacement algorithm, for example, from a simple first-in-first-out algorithm to a more intelligent least recently used algorithm, to improve cache hit rates.

[0132] If the anomaly manifests as an issue with stored data accuracy, such as a bad block or data check error, the resulting storage controller optimization policy is to enable a redundancy check mechanism. This mechanism performs additional checksum calculations on stored data, such as parity and cyclic redundancy checks, to verify data integrity during read and write operations. If data errors are detected, the redundant information can be used to correct them, ensuring data accuracy.

[0133] Step S156: Add the storage controller optimization policy to the hardware optimization policy set.

[0134] The generated storage controller optimization policy is added to the hardware optimization policy set O. Similarly, the storage controller optimization policy needs to be properly encoded and formatted so that it can be consistent with the hardware optimization policy previously generated for the processor, memory, and graphics card components in data structure and format. For example, a specific identifier is assigned to the storage controller optimization policy, and it is associated with the corresponding optimization operation (such as adjusting the specific parameters of the cache policy, the specific method of enabling the redundancy check mechanism) to form a new policy encoding vector E_s_opt. This new policy encoding vector E_s_opt is then added to the hardware optimization policy set O to obtain the updated hardware optimization policy set O_updated. In this way, the updated hardware optimization policy set contains optimization policies for all hardware components (including storage devices).

[0135] Furthermore, the method may further include:

[0136] Step S310: monitoring the output parameters of the power adapter of the target notebook in real time, and collecting input voltage fluctuation data and current stability data.

[0137] During the execution of the multi-scenario test instruction set, the output parameters of the target laptop's power adapter are monitored in real time. A dedicated power monitoring device is connected to the output terminal of the power adapter. This monitoring device can accurately measure the output voltage and current of the power adapter. By continuously sampling the output voltage, the input voltage fluctuation data V_fluctuation is collected. The input voltage fluctuation data reflects the changes in the output voltage of the power adapter within the set time, including information such as voltage rise, fall, and fluctuation amplitude. At the same time, the output current is monitored and the current stability data I_stability is collected. The current stability data indicates the stability of the output current of the power adapter, and whether there is a sudden increase or decrease in the current.

[0138] Step S320: performing peak-valley value detection processing on the input voltage fluctuation data to generate a voltage fluctuation range.

[0139] Perform peak-to-valley detection on the collected input voltage fluctuation data (V_fluctuation). By traversing each data point in the input voltage fluctuation data, the maximum and minimum values ​​are found. The maximum value represents the peak value of the voltage fluctuation, and the minimum value represents the valley value of the voltage fluctuation. The maximum and minimum values ​​are recorded to form the voltage fluctuation range (V_range). The voltage fluctuation range can intuitively reflect the degree of fluctuation in the power adapter's output voltage, providing an important basis for subsequently determining whether the power adapter is functioning properly.

[0140] Step S330: Using a sliding window mean filtering algorithm to perform noise filtering on the current stability data to generate an effective current curve.

[0141] To remove noise from the current stability data, I_stability, a sliding window mean filter algorithm is used. The basic principle of the sliding window mean filter algorithm is to slide a fixed-size window over the current stability data, average the data within the window, and then use the average value as the new data value at the center of the window. As the window slides, the average value of the data within each window is calculated in turn, resulting in a new filtered data sequence. This new data sequence is plotted as a curve to obtain the effective current curve, I_effective. The effective current curve can more accurately reflect the actual changes in the power adapter's output current, eliminate the influence of noise, and facilitate subsequent analysis of current stability.

[0142] Step S340: Dynamically calculate a reasonable fluctuation range of the current peak value based on the adapter specification parameters, and generate a power adapter replacement strategy when the voltage fluctuation range or the current peak value exceeds the dynamically adjusted threshold.

[0143] Dynamically calculate the reasonable fluctuation range of the peak current, I_range, based on the power adapter's specifications, such as rated voltage and rated current. The power adapter's specifications define its voltage and current range during normal operation. Combining these parameters with actual test results can determine the reasonable fluctuation range of the peak current under different operating conditions.

[0144] The calculated acceptable current peak fluctuation range (I_range) is compared with the actual current peak value collected, and the voltage fluctuation range (V_range) is compared with the pre-set voltage fluctuation threshold. If the voltage fluctuation range exceeds the voltage fluctuation threshold, or the current peak value exceeds the dynamically adjusted acceptable current peak fluctuation range, the power adapter may be faulty or have unstable performance. At this point, a power adapter replacement strategy is generated. The power adapter replacement strategy includes information such as the model and specifications of the appropriate replacement power adapter and the specific replacement steps.

[0145] Step S350: Add the power adapter replacement policy to the hardware optimization policy set.

[0146] The generated power adapter replacement policy is added to the hardware optimization policy set O_updated. Similarly, the power adapter replacement policy is encoded and formatted so that it can be consistent with other hardware optimization policies in the set in terms of data structure and format. A specific identifier is assigned to the power adapter replacement policy, and it is associated with the corresponding replacement operation information (such as the model of the replacement power adapter, replacement steps, etc.) to form a new policy encoding vector E_pa_opt. The new policy encoding vector E_pa_opt is then added to the hardware optimization policy set O_updated to obtain the final hardware optimization policy set O_final, which contains optimization policies for all hardware components such as processors, memory, graphics cards, storage devices, and power adapters.

[0147] Furthermore, the method may further include:

[0148] Step S410: re-execute the updated multi-scenario test instruction set and collect the optimized runtime performance data set.

[0149] After the final set of hardware optimization strategies, O_final, is fed back to the production line control system C, the production line control system adjusts the configuration of the target notebook based on these strategies. After the adjustments are completed, the updated multi-scenario test instruction set, I_updated, is re-executed. During the retesting process, the runtime performance data of the target notebook under different test scenario modes is collected according to the same methods and processes as before. This data is integrated to obtain the optimized runtime performance data set, D_optimized. The optimized runtime performance data set reflects the performance of the target notebook in various test scenarios after the hardware configuration adjustment.

[0150] Step S420: performing secondary anomaly detection processing on the optimized runtime performance data set to generate an optimization verification result.

[0151] Secondary anomaly detection is performed on the optimized runtime performance data set D_optimized. The process for secondary anomaly detection is essentially the same as the previous anomaly detection process for the runtime performance data set D. First, multi-dimensional feature alignment is performed on each feature dimension in the optimized runtime performance data set. Range normalization is performed based on the statistical distribution range of each data dimension to generate a standardized optimized runtime feature matrix M_optimized. The standardized optimized runtime feature matrix is ​​then segmented into processor feature sub-matrices, memory feature sub-matrices, graphics card feature sub-matrices, and storage device feature sub-matrices based on hardware component type. These sub-matrices are then input into the previously constructed variational autoencoder-based anomaly detection model. The encoder network generates latent space probability distribution parameters, which are then reparameterized and sampled based on a preset Gaussian distribution prior to generate a latent variable sequence that matches the normal operating characteristic distribution of the hardware component. The decoder network then reconstructs the corresponding output feature sequence. A windowed Euclidean distance algorithm is used to calculate the local temporal deviation between the input feature sequence and the reconstructed feature sequence for each hardware component. This is combined with the time step importance weights output by the bidirectional long short-term memory network to generate a temporal anomaly score for the hardware component. The time series anomaly scores are fed into a pre-trained graph neural network classifier. Graph convolution aggregation is performed based on the topological dependencies between hardware components to generate anomaly propagation paths and key anomaly node identifiers. Based on the influence weights of the nodes in the anomaly propagation paths and the attenuation coefficients of the time series anomaly scores, the composite anomaly probability of the hardware component is calculated. Anomaly type classification labels are generated based on the key anomaly node identifiers. The composite anomaly probability and anomaly type classification labels for the same hardware component are jointly encoded to generate an anomaly detection result for that hardware component. The anomaly detection results for all hardware components are combined to form the optimized verification result R_validation.

[0152] Step S430: Assign weight coefficients according to the degree of impact of the abnormality type on system stability, calculate the weighted comprehensive score of all abnormality detection results in the optimization verification result, and when the weighted comprehensive score is lower than the preset qualified threshold, mark the target notebook as having passed the factory inspection.

[0153] For each anomaly detection result in the optimized validation result R_validation, a weight coefficient is assigned based on the anomaly type's impact on system stability. Different anomaly types have varying degrees of impact on system stability. For example, processor performance anomalies may have a significant impact on the overall system performance and stability, while minor storage device read / write anomalies may have a relatively small impact on system stability. Therefore, different weight coefficients are assigned to different anomaly types, denoted as W_anomaly.

[0154] Calculate the weighted comprehensive score S_validation for all anomaly detection results in the optimization validation results. For each anomaly detection result, multiply its composite anomaly probability value by the corresponding weight coefficient, then add all the results together to obtain the weighted comprehensive score S_validation. Compare the weighted comprehensive score S_validation with the preset pass threshold S_threshold. If the weighted comprehensive score is lower than the pass threshold, it indicates that the hardware configuration adjustment has effectively improved the anomaly of the target notebook and that system stability has reached an acceptable level. At this point, the target notebook is marked as having passed factory inspection.

[0155] Step S440: When the number of abnormal detection results in the optimization verification result is higher than the qualified threshold, the iterative optimization strategy set is regenerated and a new round of configuration adjustment operation is triggered.

[0156] If the number of anomaly detection results in the optimization verification results is higher than the qualified threshold, it means that after one hardware configuration adjustment, the target notebook still has many anomalies and the system stability does not meet the requirements. At this time, it is necessary to regenerate the iterative optimization strategy set. Re-analyze the optimization verification results R_validation to find out the hardware components that still have anomalies and their anomaly types. Based on this anomaly information, combined with previous optimization experience and the performance characteristics of the hardware components, re-formulate the optimization strategy for these anomalies. Combine these new optimization strategies together to form the iterative optimization strategy set O_iteration. Feedback the iterative optimization strategy set O_iteration to the production line control system C to trigger a new round of configuration adjustment operations. After the new round of configuration adjustment operations is completed, execute the updated multi-scenario test instruction set I_updated again, collect runtime performance data, and perform anomaly detection processing. Repeat the above steps until the weighted comprehensive score of the target notebook is lower than the qualified threshold and passes the factory inspection.

[0157] Throughout the entire process, data collection and processing must strictly comply with relevant laws and regulations to ensure the legality, compliance, and security of the data. For privacy-sensitive data collected, such as hardware configuration parameters and runtime performance data, encryption technology is used to protect the privacy and prevent data leakage. During data transmission, secure transmission protocols such as SSL / TLS are used to encrypt data. For data storage, a secure storage system is used to encrypt data and implement strict access control to ensure that only authorized personnel can access and process this data.

[0158] Figure 2A schematic diagram illustrates exemplary hardware and software components of a multi-scenario stress testing system 100 for a notebook computer used for factory inspection, which can implement the concepts of the present application, as provided in some embodiments of the present application. For example, the processor 120 can be used in the multi-scenario stress testing system 100 for a notebook computer used for factory inspection and to perform the functions described in the present application.

[0159] The notebook multi-scenario stress testing system 100 for factory inspection can be a general-purpose server or a special-purpose server, both of which can be used to implement the notebook multi-scenario stress testing method for factory inspection of this application. Although only one server is shown in this application, for convenience, the functions described in this application can be implemented in a distributed manner on multiple similar platforms to balance the processing load.

[0160] For example, the notebook multi-scenario stress testing system 100 applied to factory inspection may include a network port 110 connected to the network, one or more processors 120 for executing program instructions, a communication bus 130, and different forms of storage media 140, such as a disk, ROM, or RAM, or any combination thereof. Exemplarily, the notebook multi-scenario stress testing system 100 applied to factory inspection may also include program instructions stored in ROM, RAM, or other types of non-temporary storage media, or any combination thereof. The method of the present application can be implemented according to these program instructions. The notebook multi-scenario stress testing system 100 applied to factory inspection also includes an I / O interface 150 between the computer and other input and output devices.

[0161] For ease of explanation, only one processor is described in the notebook multi-scenario stress testing system 100 for factory inspection. However, it should be noted that the notebook multi-scenario stress testing system 100 for factory inspection in this application may also include multiple processors, so the steps performed by one processor described in this application may also be performed jointly or individually by multiple processors. For example, if the processor of the notebook multi-scenario stress testing system 100 for factory inspection executes step A and step B, it should be understood that step A and step B may also be performed jointly by two different processors or individually in one processor. For example, the first processor executes step A, the second processor executes step B, or the first processor and the second processor execute steps A and B together.

[0162] In addition, an embodiment of the present invention further provides a readable storage medium, in which computer-executable instructions are preset. When a processor executes the computer-executable instructions, the multi-scenario stress testing method for a notebook computer applied to factory inspection as described above is implemented.

[0163] It should be noted that in order to simplify the description of the present invention and thus help understand one or more embodiments of the invention, in the foregoing description of the embodiments of the present invention, multiple features are sometimes combined into one embodiment, figure or description thereof.

Claims

1. A multi-scenario stress testing method for notebook computers used in factory inspection, characterized in that: The method comprises: Obtaining a hardware configuration parameter set and a factory test scenario parameter set of a target notebook, wherein the factory test scenario parameter set includes multiple test scenario modes; generating a multi-scenario test instruction set based on the association between the hardware configuration parameter set and the test scenario mode, wherein the multi-scenario test instruction set is used to trigger a stress test operation of the target notebook under multiple test scenario modes; Executing the multi-scenario test instruction set to collect runtime performance data sets of the target notebook under different test scenario modes; Performing anomaly detection processing on the runtime performance data set to generate an anomaly detection result set of hardware components and a system stability assessment result; generating a hardware optimization strategy set based on the anomaly detection result set and the system stability assessment result, and feeding the hardware optimization strategy set back to the production line control system to trigger a configuration adjustment operation of the target notebook; The generating of a multi-scenario test instruction set based on the association between the hardware configuration parameter set and the test scenario mode includes: Extracting processor model parameters, memory capacity parameters, and graphics card specification parameters from the hardware configuration parameter set; Determining a resource occupation threshold range required for each test scenario mode according to the scenario stress level corresponding to the test scenario mode; Matching the processor model parameter with a resource occupancy threshold range of a first test scenario mode to generate a first test instruction subset; Matching the memory capacity parameter with a resource occupancy threshold range of a second test scenario mode to generate a second test instruction subset; Matching the graphics card specification parameters with the resource occupancy threshold range of the third test scenario mode to generate a third test instruction subset; The multi-scenario test instruction set is generated by merging the first test instruction subset, the second test instruction subset, and the third test instruction subset in order of priority.

2. The notebook multi-scenario stress testing method for factory inspection according to claim 1 is characterized in that: The executing the multi-scenario test instruction set and collecting a set of runtime performance data of the target notebook in different test scenario modes includes: Calling a test execution engine to load the multi-scenario test instruction set, and triggering the target notebook to enter multiple test scenario modes in sequence according to a preset test sequence; In the first test scenario mode, core temperature data, clock frequency fluctuation data, and thread load balancing data of the processor are collected in real time; In the second test scenario mode, real-time data on the read and write speeds, cache hit rate, and virtual memory occupancy of the memory are collected; In the third test scenario mode, real-time collection of rendering frame rate data, video memory bandwidth utilization data, and graphics processing delay data of the graphics card; The core temperature data, clock frequency fluctuation data, thread load balancing data, read and write rate data, cache hit rate data, virtual memory occupancy data, rendering frame rate data, video memory bandwidth utilization data and graphics processing delay data are integrated into the runtime performance data set.

3. The notebook multi-scenario stress testing method for factory inspection according to claim 1 is characterized in that: The performing anomaly detection processing on the runtime performance data set to generate an anomaly detection result set of hardware components and a system stability evaluation result includes: Performing multi-dimensional feature alignment processing on each feature dimension data in the runtime performance data set, performing range normalization based on the statistical distribution range of each data dimension, and generating a standardized runtime feature matrix; Build an anomaly detection model based on a variational autoencoder, where the encoder network uses a bidirectional long short-term memory network to extract contextual features across time steps, and the decoder network uses a gated convolutional network to reconstruct the input feature sequence; Splitting the standardized runtime feature matrix into a processor feature sub-matrix, a memory feature sub-matrix, and a graphics card feature sub-matrix according to hardware component type, and inputting each of the sub-matrix into the encoder network to generate latent space probability distribution parameters; Reparameterize and sample the parameters of the latent space probability distribution based on a preset Gaussian distribution prior to generate a latent variable sequence that matches the characteristic distribution of the hardware component during normal operation, and reconstruct the corresponding output feature sequence through the decoder network; A windowed Euclidean distance algorithm is used to calculate the local timing deviation between the input feature sequence and the reconstructed feature sequence of each hardware component. This is combined with the time step importance weight output by the bidirectional long short-term memory network to generate a timing anomaly score for the hardware component. Input the time series anomaly score into a pre-trained graph neural network classifier, perform graph convolution aggregation based on the topological dependency relationship between hardware components, and generate anomaly propagation paths and key anomaly node identifiers; Calculate the composite anomaly probability value of the hardware component based on the influence weight of the node in the anomaly propagation path and the attenuation coefficient of the time series anomaly score, and generate an anomaly type classification label based on the key anomaly node identifier; Jointly encoding the composite anomaly probability value and the anomaly type classification label of the same hardware component to generate an anomaly detection result set of the hardware component; Extract the time series of composite anomaly probability values ​​of all hardware components, construct a multidimensional anomaly evolution tensor, and extract the spatiotemporal correlation features of anomaly patterns through a spatiotemporal convolutional neural network; The spatiotemporal correlation features are input into a multi-layer Transformer encoder, and a self-attention mechanism is used to capture global abnormal dependencies to generate a system stability feature vector; The system stability feature vector is input into a fully connected discriminant network, a system stability score is generated through nonlinear activation function mapping, and the level division of the system stability evaluation result is determined according to the score interval threshold.

4. The notebook multi-scenario stress testing method for factory inspection according to claim 3 is characterized in that: The construction of an anomaly detection model based on a variational autoencoder includes: Constructing an independent encoder branch and decoder branch for each hardware component type, wherein the input layer of the encoder branch receives the processor feature sub-matrix, the memory feature sub-matrix, and the graphics card feature sub-matrix after the standardized runtime feature matrix is ​​split; In the encoder branch, forward and reverse hidden state calculations are performed on the input feature submatrix in the time dimension through a bidirectional long short-term memory network, and the forward output vector and the reverse output vector are concatenated according to the time step to generate a fused feature vector containing context associations across time steps; Input the fused feature vector into the multi-head self-attention module of the encoder branch, divide the feature vector into multiple subspaces, calculate the correlation weight matrix between features at different time steps, and generate attention-enhanced temporal feature representation through weighted summation; Mapping the temporal feature representation into a mean vector and a variance vector of a latent space through a fully connected layer of an encoder branch, and calculating a KL divergence between the mean vector and the variance vector and a preset Gaussian prior distribution; In the decoder branch, the reparameterized sampled latent variable sequence is input into a gated convolutional network. Multi-scale temporal dependencies are captured by stacking causal convolutional layers with different dilation rates. The output of each convolutional layer is element-wise multiplied with a gated linear unit to control the feature transfer path. Residual connections are introduced between adjacent layers of the gated convolutional network, and shallow convolution outputs and deep gated outputs are added channel by channel to generate a multi-level fused reconstructed feature sequence; The mean square error between the reconstructed feature sequence and the original input feature submatrix is ​​used as the reconstruction loss term, the KL divergence and the reconstruction loss term are added according to a preset weight coefficient to construct a joint loss function of the variational autoencoder; An adversarial training strategy is adopted to input the latent variable sequence into the discriminant network for true and false classification, generate an adversarial loss term, and perform gradient weighted fusion of the adversarial loss term and the joint loss function to complete the parameter optimization of the variational autoencoder.

5. The notebook multi-scenario stress testing method for factory inspection according to claim 3 is characterized in that: The extraction of spatiotemporal correlation features of abnormal patterns through a spatiotemporal convolutional neural network includes: Expanding the multidimensional anomaly evolution tensor according to the time dimension and the hardware component dimension to construct a spatiotemporal grid data structure; A spatial dependency graph is constructed based on the physical connection relationships between hardware components. Graph convolution operations are used to aggregate the abnormality probability values ​​of hardware components with direct dependencies to generate a spatial dependency feature graph. In the time dimension, separable convolution kernels are used to extract short-term fluctuation patterns and long-term trend patterns respectively, and multi-scale time series features are fused through a gating mechanism; The spatial dependency feature map and the fused temporal features are tensor-concatenated and input into a three-dimensional convolutional layer to extract joint correlation pattern features across time and space; The joint correlation pattern features are weighted by channel attention, and the weighted features are mapped to a low-dimensional embedding space to generate a spatiotemporal correlation feature vector for subsequent Transformer encoder processing.

6. The notebook multi-scenario stress testing method for factory inspection according to claim 1 is characterized in that: After obtaining the hardware configuration parameter set and the factory test scenario parameter set of the target notebook, the method further includes: Determining a test intensity parameter of a storage performance test scenario according to a storage device type parameter in the hardware configuration parameter set; generating a storage stress test instruction subset according to the test intensity parameter, wherein the storage stress test instruction subset is used to trigger a storage performance test of the target notebook in a continuous read and write scenario; Adding the storage stress test instruction subset to the multi-scenario test instruction set, and updating the test scenario mode in the factory test scenario parameter set; The step of executing the multi-scenario test instruction set and collecting a set of runtime performance data of the target notebook in different test scenario modes further includes: In the storage stress test scenario mode, real-time collection of continuous write rate data, random read latency data and bad block detection results of the storage device; Performing decay cycle analysis on the continuous write rate data to generate a write performance decay curve; Performing distribution statistics processing on the random read delay data to generate a delay distribution histogram; Determining a storage performance abnormality type according to the slope of the write performance decay curve and the peak position of the delay distribution histogram; Adding the storage performance anomaly type to the anomaly detection result set; Generating a hardware optimization strategy set based on the anomaly detection result set and the system stability evaluation result further includes: When the storage performance abnormality type is a specified type, generating a storage controller optimization strategy, the storage controller optimization strategy including adjusting a cache strategy or enabling a redundancy check mechanism; The storage controller optimization policy is added to the hardware optimization policy set.

7. The notebook multi-scenario stress testing method for factory inspection according to claim 1 is characterized in that: After executing the multi-scenario test instruction set, the method further includes: Real-time monitoring of the target laptop's power adapter output parameters, collecting input voltage fluctuation data and current stability data; Performing peak-valley value detection processing on the input voltage fluctuation data to generate a voltage fluctuation range; The sliding window mean filter algorithm is used to filter the noise of the current stability data and generate the effective current curve; Dynamically calculate the reasonable fluctuation range of the current peak based on the adapter's specification parameters. When the voltage fluctuation range or current peak exceeds the dynamically adjusted threshold, a power adapter replacement strategy is generated. Add the power adapter replacement policy to the hardware optimization policy set.

8. The notebook multi-scenario stress testing method for factory inspection according to claim 1 is characterized in that: After feeding back the hardware optimization strategy set to the production line control system to trigger the configuration adjustment operation of the target notebook, the method further includes: Re-execute the updated multi-scenario test instruction set and collect the optimized runtime performance data set; Performing secondary anomaly detection processing on the optimized runtime performance data set to generate an optimization verification result; Assigning weight coefficients based on the degree of impact of anomaly types on system stability, calculating a weighted comprehensive score for all anomaly detection results in the optimization verification results, and marking the target notebook as having passed factory inspection when the weighted comprehensive score is lower than a preset pass threshold; When the number of abnormal detection results in the optimization verification result is higher than the qualified threshold, the iterative optimization strategy set is regenerated and a new round of configuration adjustment operation is triggered.

9. A notebook multi-scenario stress testing system for factory inspection, characterized in that: It includes a processor and a memory, the memory is connected to the processor, the memory is used to store programs, instructions or codes, and the processor is used to execute the programs, instructions or codes in the memory to implement the notebook multi-scenario stress testing method for factory inspection as described in any one of claims 1 to 8 above.

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