Electronic system and operating method for electronic system
By writing the update data to the memory circuit under the control of the controller and loading it into the programmable circuit, the update problem when the controller is long and the FPGA is solved, and remote update operation is realized.
Patent Information
- Application Number
- CN202411508377.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2024-02-02
- Filing Date
- 2024-10-28
- Publication Date
- 2025-08-05
AI Technical Summary
In the prior art, when the distance between the controller and the FPGA is long, firmware update cannot be performed through the JTAG standard transmission method.
The switching circuit is used to receive the control signals of the controller to realize the connection between the programmable circuit and the memory circuit. The switching circuit writes the updated data to the memory circuit, and loads the data into the programmable circuit at the appropriate time to realize the remote update operation.
It realizes that without the need for JTAG standard transmission mode, the transmission distance limitation is eliminated and the programmable circuit can be renewed remotely.
Smart Images
Figure CN120429249A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to an electronic system and an operation method for an electronic system. Background Art
[0002] An electronic system may include a controller and a field programmable gate array (FPGA). The controller may use a transmission method compliant with the Joint Test Action Group (JTAG) specification to perform firmware update on the FPGA.
[0003] However, the transmission method compliant with the JTAG specification has a limitation on the transmission distance. Generally, the effective transmission distance of the above transmission method is about 1 meter. In other words, when the distance between the controller and the FPGA is long, the controller cannot use the above transmission method to perform firmware update on the FPGA. Summary of the Invention
[0004] The present disclosure provides an electronic system and an operation method for an electronic system, which can perform remote update operation on the programmable circuit of the electronic system.
[0005] The electronic system of the present disclosure includes a programmable circuit, a memory circuit, a controller, and a switching circuit. The controller provides a first control signal. The switching circuit has a control terminal, a first terminal, a second terminal, and a third terminal. The first terminal is coupled to the programmable circuit. The second terminal is coupled to the memory circuit. The control terminal and the third terminal are coupled to the controller. The switching circuit receives the first control signal through the control terminal, causing the second terminal to be connected to the third terminal, so that update data is stored in the memory circuit.
[0006] The operation method of the present disclosure is used for an electronic system. The electronic system includes a programmable circuit, a memory circuit, a switching circuit, and a controller. The switching circuit has a control terminal, a first terminal, a second terminal, and a third terminal. The first terminal is coupled to the programmable circuit. The second terminal is coupled to the memory circuit. The control terminal and the third terminal are coupled to the controller. The operation method includes: the controller provides a first control signal; the switching circuit receives the control signal through the control terminal, so that the third terminal is connected to the second terminal; and the controller stores an update data from the third terminal to the memory circuit.
[0007] Based on the above, the switching circuit receives the update data and writes the update data into the memory circuit. The present disclosure does not require the controller to use the transmission method compliant with the Joint Test Action Group (JTAG) specification to update the programmable circuit. Therefore, the update operation of the present disclosure has no limitation on the transmission distance. Brief Description of the Drawings
[0008] Figure 1 is a schematic diagram of an electronic system illustrated according to an embodiment of the present disclosure.
[0009] Figure 2 is a flowchart of an operation method illustrated according to an embodiment of the present disclosure.
[0010] Figure 3 is a schematic diagram of an electronic system illustrated according to an embodiment of the present disclosure.
[0011] Figure 4 is a flowchart of an operation method illustrated according to an embodiment of the present disclosure.
[0012] Among them, the reference numerals are explained as follows:
[0013] 100, 200: Electronic systems
[0014] 110, 210: Programmable circuits
[0015] 120, 220: Memory circuits
[0016] 130, 230: Controllers
[0017] 140, 240: Switching circuits
[0018] 250: Converter
[0019] CB1: First circuit board
[0020] CB2: Second circuit board
[0021] FT1: First communication protocol
[0022] FT2: Second communication protocol
[0023] L1: Bus conforming to I2C interface
[0024] L2: Connection line
[0025] LSPI1, LSPI2, LSPI3: SPI buses
[0026] S100, S200: Operation methods
[0027] S110~S160, S210~S270: Steps
[0028] SC1: First control signal
[0029] SC2: Second control signal
[0030] SUD: Update data
[0031] T1: First terminal
[0032] T2: The second terminal
[0033] T3: The third terminal
[0034] TC: The control terminal Detailed implementation manners
[0035] Some embodiments of the present disclosure will be described in detail in conjunction with the accompanying drawings. For the component symbols cited in the following description, when the same component symbols appear in different drawings, they will be regarded as the same or similar components. These embodiments are only a part of the present disclosure and do not disclose all the implementable manners of the present disclosure. More precisely, these embodiments are only examples in the claims of the present disclosure.
[0036] Please refer to Figure 1 , Figure 1 which is a schematic diagram of an electronic system shown according to an embodiment of the present disclosure. In this embodiment, the electronic system 100 includes a programmable circuit 110, a memory circuit 120, a controller 130, and a switching circuit 140. For example, the electronic system 100 may be, for example, a server rack including multiple servers or a facility including a server rack, but the present disclosure is not limited thereto. For example, the programmable circuit 110 may be, for example, a Field Programmable Gate Array (FPGA) or used for power-on setting of at least one server in the server rack, but the present disclosure is not limited thereto.
[0037] In this embodiment, the switching circuit 140 includes a control terminal TC, a first terminal T1, a second terminal T2, and a third terminal T3. The first terminal T1 is coupled to the programmable circuit 110. The second terminal T2 is coupled to the memory circuit 120. The control terminal TC and the third terminal T3 are coupled to the controller 130.
[0038] In this embodiment, the controller 130 controls the connection states among the first terminal T1, the second terminal T2, and the third terminal T3 of the switching circuit 140. The controller 130 provides a first control signal SC1. The switching circuit 140 receives the first control signal SC1 through the control terminal TC. The switching circuit 140 receives updated data SUD through the third terminal T3. The switching circuit 140 connects the third terminal T3 to the second terminal T2 according to the first control signal SC1. Therefore, the switching circuit 140 writes (or burns) the received updated data SUD into the memory circuit 120 through the third terminal T3.
[0039] In this embodiment, the controller 130 provides the second control signal SC2 based on the condition that the memory circuit 120 has stored the update data SUD. The switching circuit 140 receives the second control signal SC2 through the control terminal TC to connect the second terminal T2 to the first terminal T1. Therefore, the update data SUD stored in the memory circuit 120 is loaded into the programmable circuit 110. Therefore, the programmable circuit 110 can use the update data SUD stored in the memory circuit 120 to perform an update operation.
[0040] It is worth mentioning here that the switching circuit 140 receives the update data SUD through the third terminal T3 and writes the update data SUD into the memory circuit 120. The electronic system 100 does not require the controller 130 to update the programmable circuit 110 by using the transmission method of the Joint Test Action Group (JTAG) specification. Therefore, there is no limitation on the transmission distance for the update operation of the programmable circuit 110 by the controller 130.
[0041] In this embodiment, the controller 130 provides the second control signal SC2. The control terminal TC of the switching circuit 140 receives the second control signal SC2. The switching circuit 140 connects the second terminal T2 to the first terminal T1 according to the second control signal SC2. Therefore, the programmable circuit 110 is connected to the memory circuit 120 through the switching circuit 140. Therefore, the update data SUD stored in the memory circuit 120 is loaded into the programmable circuit 110.
[0042] In this embodiment, the update data SUD can be provided by the controller 130. In some embodiments, the update data SUD can be provided by other circuits.
[0043] In this embodiment, the timing for the controller 130 to provide the first control signal SC1 can be during the period when the update data SUD is to be loaded. For example, during the operation of multiple servers in a server cabinet, the switching circuit 140 writes the received update data SUD into the memory circuit 120. The timing for the controller 130 to provide the second control signal SC2 can be during the period when the update data SUD has been stored in the memory circuit 120 and during the update of the programmable circuit 110. For example, the timing for the controller to provide the second control signal SC2 can be during the startup of multiple servers in the server cabinet. During the startup of multiple servers in the server cabinet, the programmable circuit 110 uses the update data SUD stored in the memory circuit 120 to perform an update operation.
[0044] In this embodiment, the memory circuit 120 may include an Electrically-Erasable Programmable Read-Only Memory (EEPROM) or other storage elements well known to those skilled in the art.
[0045] In this embodiment, the controller 130 may include, for example, a Board Management Controller (BMC) for monitoring at least one server cabinet in the facility.
[0046] Please refer to Figure 1 and Figure 2 , Figure 2 is a flowchart of an operation method illustrated according to an embodiment of the present disclosure. In this embodiment, the operation method S100 is applicable to the electronic system 100. The operation method S100 includes steps S110 to S160. In step S110, the controller 130 provides a first control signal SC1. In step S120, the switching circuit 140 receives the first control signal SC1 through the control terminal TC to connect the third terminal T3 to the second terminal T2. In step S130, the controller 130 stores the update data SUD from the third terminal T3 into the memory circuit 120. In step S140, based on the memory circuit 120 having stored the update data, the controller 130 provides a second control signal SC2. In step S150, the switching circuit 140 receives the second control signal SC2 through the control terminal TC to connect the second terminal T2 to the first terminal T1. In step S160, the update data SUD stored in the memory circuit 120 is loaded into the programmable circuit 110.
[0047] Please refer to Figure 3 , Figure 3 is a schematic diagram of an electronic system illustrated according to an embodiment of the present disclosure. In this embodiment, the electronic system 200 includes a programmable circuit 210, a memory circuit 220, a controller 230, a switching circuit 240, and a converter 250. For example, the electronic system 200 may be, for example, a server rack including multiple servers or a facility including server racks, but the present disclosure is not limited thereto. For example, the programmable circuit 210 may be, for example, a Field Programmable Gate Array (FPGA) or used for power-on setting of at least one server in the server rack, but the present disclosure is not limited thereto.
[0048] In this embodiment, the switching circuit 240 includes a first terminal T1, a second terminal T2, a third terminal T3, and a control terminal TC. The first terminal T1 is coupled to the programmable circuit 210. The second terminal T2 is coupled to the memory circuit 220. The control terminal TC is coupled to the controller 230. The converter 250 is coupled to the controller 230 and the third terminal T3. Further, the converter 250 is coupled to the controller 230 through a first communication protocol FT1 and coupled to the third terminal T3 through a second communication protocol FT2. The converter 250 converts the interfaces of two different communication protocols. The controller 230 provides the update data SUD to the third terminal T3 through the converter 250. The converter 250 receives the update data SUD provided by the controller 230 through the first communication protocol FT1, and then provides it to the third terminal T3 of the switching circuit 240 through the second communication protocol FT2. The first communication protocol FT1 is, for example, an Inter-Integrated Circuit (I2C) interface, and the second communication protocol FT2 is, for example, a Serial Peripheral Interface Bus (SPI).
[0049] The controller 230 provides a first control signal SC1. The control terminal TC of the switching circuit 240 receives the first control signal SC1. The switching circuit 240 connects the third terminal T3 to the second terminal T2 according to the first control signal SC1. Therefore, the switching circuit 240 writes the received update data SUD into the memory circuit 220.
[0050] In this embodiment, the controller 230 can further provide a second control signal SC2. The control terminal TC of the switching circuit 240 receives the second control signal SC2. The switching circuit 240 connects the second terminal T2 to the first terminal T1 according to the second control signal SC2. Therefore, the programmable circuit 210 is connected to the memory circuit 220 through the switching circuit 240. Therefore, the update data SUD stored in the memory circuit 220 is loaded into the programmable circuit 210.
[0051] In this embodiment, the controller 230 is disposed on the first circuit board CB1. The programmable circuit 210 is disposed on the second circuit board CB2. The controller 230 is allowed to perform an update operation on the programmable circuit 210 over a long distance. Therefore, the controller 230 can transmit update data SUD to the converter 250 located remotely through, for example, a bus L1 compliant with the I2C interface. In addition, the controller 230 can be connected to the control terminal TC of the switching circuit 240 through, for example, a connection line L2 compliant with the General-purpose input / output (GPIO) communication protocol. Therefore, the controller 230 can control the switching operation of the remotely located switching circuit 240 through, for example, the connection line L2. For example, the first circuit board CB1 having the controller 230 can be disposed at a first location. The second circuit board CB2 having the programmable circuit 210, the memory circuit 220, the switching circuit 240, and the converter 250 can be disposed in a facility at a second location, and the distance between the first location and the second location exceeds 1 meter. Therefore, the controller 230 performs a remote update operation on the programmable circuit 210.
[0052] In this embodiment, the first terminal T1 can be connected to the programmable circuit 210 through, for example, a Serial Peripheral Interface bus LSPI1. The second terminal T2 can be connected to the memory circuit 22, for example, through an SPI bus LSPI2. The converter 250 can be connected to the third terminal T3 through, for example, an SPI bus LSPI3. However, the present disclosure is not limited to the above connection manners of the switching circuit 240.
[0053] Please refer to Figure 3 and Figure 4 , Figure 4 is a flowchart of an operation method illustrated according to an embodiment of the present disclosure. In this embodiment, the operation method S200 is applicable to the electronic system 200. The operation method S200 includes steps S210 to S270. In step S210, the controller 230 provides a first control signal SC1. In step S220, the controller 230 provides update data SUD to the third terminal T3 through the converter 250. In step S230, the switching circuit 240 receives the first control signal SC1 through the control terminal TC to connect the third terminal T3 to the second terminal T2. In this embodiment, steps S220 and S230 can be performed simultaneously. In some embodiments, step S220 is earlier than step S230. In some embodiments, step S220 is later than step S230.
[0054] In step S240, the controller 230 stores the updated data SUD from the third terminal T3 into the memory circuit 220. In step S250, based on the memory circuit 220 having stored the updated data, the controller 230 provides the second control signal SC2. In step S260, the switching circuit 240 receives the second control signal SC2 via the control terminal TC to connect the second terminal T2 to the first terminal T1. In step S270, the updated data SUD stored in the memory circuit 220 is loaded into the programmable circuit 210.
[0055] In summary, the switching circuit receives the updated data and writes the updated data into the memory circuit. The present disclosure does not require the controller to update the FPGA by using the transmission method of the JTAG specification. Therefore, there is no limitation on the transmission distance in the update operation of the present disclosure.
[0056] Although the present disclosure has been disclosed as above by way of embodiments, it is not intended to limit the present disclosure. Any person having ordinary knowledge in the technical field to which the present disclosure pertains may make some modifications and refinements without departing from the spirit and scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to that defined by the appended claims.
Claims
1. An electronic system, characterized in that: include: a programmable circuit; a memory circuit; a controller adapted to provide a first control signal; as well as a switching circuit having a control terminal, a first terminal, a second terminal, and a third terminal, wherein the first terminal is coupled to the programmable circuit, the second terminal is coupled to the memory circuit, and the control terminal and the third terminal are coupled to the controller; The switching circuit is adapted to receive the first control signal via the control terminal, causing the second terminal to be connected to the third terminal, so that an update data is stored in the memory circuit.
2. The electronic system according to claim 1, wherein: The controller further provides the update data. When the switching circuit receives the first control signal via the control terminal, the update data is stored in the memory circuit via the second terminal and the third terminal.
3. The electronic system according to claim 1, wherein: The controller provides a second control signal based on the memory circuit having stored the update data; The switching circuit is adapted to receive the second control signal via the control terminal to connect the second terminal to the first terminal, so that the update data stored in the memory circuit is adapted to be loaded into the programmable circuit.
4. The electronic system according to claim 1, wherein: The programmable circuit includes a field programmable logic gate array.
5. The electronic system according to claim 1, wherein: The controller includes a universal input / output pin. The controller is coupled to the control end of the switching circuit through the universal input / output pin.
6. The electronic system according to claim 1, wherein: The controller is arranged on a first circuit board, and the programmable circuit is arranged on a second circuit board.
7. The electronic system according to claim 1, wherein: Also includes: A converter is coupled to the controller via a first communication protocol and coupled to the third end via a second communication protocol. The controller provides the update data to the third end via the converter.
8. The electronic system according to claim 7, wherein: The first communication protocol includes an internal integrated circuit interface (ICI), and the second communication protocol includes a serial peripheral interface (SPI).
9. A method for operating an electronic system, characterized in that: The electronic system includes a programmable circuit, a memory circuit, a switching circuit, and a controller, wherein the switching circuit has a control terminal, a first terminal, a second terminal, and a third terminal, the first terminal being coupled to the programmable circuit, the second terminal being coupled to the memory circuit, and the control terminal and the third terminal being coupled to the controller. The operating method includes: The controller provides a first control signal; The switching circuit receives the control signal via the control terminal to connect the third terminal to the second terminal; and The controller stores updated data in the memory circuit via the third terminal.
10. The operating method according to claim 9, characterized in that: The invention also includes an updating operation step, which includes: The controller provides a second control signal based on the memory circuit having stored the update data; and The switching circuit receives the second control signal via the control terminal to connect the second terminal to the first terminal, so that the update data stored in the memory circuit is suitable for loading into the programmable circuit.
11. The operating method according to claim 9, wherein: The electronic system further includes a converter coupled to the controller via a first communication protocol and coupled to the third terminal via a second communication protocol. The operating method further includes: The controller provides the update data to the third terminal through the converter.