Register design method, electronic device and medium

Abstract

The present invention relates to the field of chip technology, and in particular to a register design method, electronic device, and medium. The method comprises steps S1, constructing a first register description reconstruction set {A1, A2, ..., A m ,...,A M}, the second register describes the reconstruction set {B1, B2, ..., B n ,...,B N} and the third register describes the reconstruction set {C1, C2, ..., C k ,...,C K}; Step S2, obtain target A corresponding to the target design m Target B n and Objective-C k ; Step S3, based on target A m Target B n and Objective-C k Generate register design code corresponding to the target design. The present invention improves the design efficiency of registers, thereby improving the chip development efficiency.

Description

Technical Field

[0001] The present invention relates to the field of chip technology, and in particular to a register design method, electronic equipment, and medium. Background Art

[0002] In the chip development process, registers are particularly important, and each chip function is realized by configuring one or more registers. Therefore, in the chip development process, a series of registers need to be designed to realize the various functions of the chip. However, the chip scale is huge, so the number of registers is also very large. In the chip design and development process, it is necessary to build the register transfer level circuit (Register Transfer Level, RTL for short) design code corresponding to the register hardware design. In the existing technology, engineers are required to manually write the RTL code for the register hardware design, which is inefficient, and due to the large number of registers, it is easy to cause omissions and errors, which reduces the efficiency of chip development. It can be seen from this that how to improve the generation efficiency of the register design code, thereby improving the chip development efficiency, has become a technical problem that needs to be solved urgently. Summary of the Invention

[0003] The present invention aims to provide a register design method, electronic device and medium, which improve the design efficiency of registers and thus improve the chip development efficiency.

[0004] According to a first aspect of the present invention, a register design method is provided, comprising:

[0005] Step S1: Construct the first register description reconstruction set {A1, A2, ..., A m ,...,A M}, the second register describes the reconstruction set {B1, B2, ..., B n ,...,B N} and the third register describes the reconstruction set {C1, C2, ..., C k ,...,C K}, where A m The description and reconstruction information of the register group corresponding to the mth chip IP, the value range of m is 1 to M, M is the total number of chip IPs in the chip design, B n The description reconstruction information of the nth register, the value range of n is 1 to N, N is the total number of registers in the chip design, C k The description reconstruction information of the kth register domain, where k ranges from 1 to K, and K is the total number of register domains of all registers in the chip design. The register group corresponding to the chip IP includes at least one register or includes at least one register group and register, and the register includes at least one register domain.

[0006] Step S2: Obtain target A corresponding to the target design m Target B n and Objective-C k , the target design is a chip IP, a subsystem chip composed of chip IPs, or a SoC chip, wherein the chip IP includes registers of a register group corresponding to the chip IP; the registers in the subsystem chip include registers of the chip IP contained in the subsystem chip and registers at the subsystem chip level; the SoC chip includes registers in the subsystem chip, registers of the chip IP, and registers at the SoC level;

[0007] Step S3: Based on target A m Target B n and Objective-C k Generate register design code corresponding to the target design.

[0008] According to a second aspect of the present invention, an electronic device is provided, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being configured to execute the method described in the first aspect of the present invention.

[0009] According to a third aspect of the present invention, a computer-readable storage medium is provided, storing computer-executable instructions, wherein the computer instructions are used to execute the method according to the first aspect of the present invention.

[0010] The present invention has significant advantages and beneficial effects compared to the prior art. By utilizing the above technical solution, the register design method, electronic device, and medium provided by the present invention can achieve considerable technological advancement and practicality, and have wide industrial application value, with at least the following beneficial effects:

[0011] The present invention constructs register description reconstructions at different levels, stores the attribute information of registers in a hierarchical manner in the register description reconstruction, and then automatically generates the register design code corresponding to the target design based on the register description reconstruction of each level corresponding to the target design, thereby improving the design efficiency of the register and further improving the chip development efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0013] Figure 1This is a flow chart of the register design method provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0014] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making any creative efforts shall fall within the scope of protection of the present invention.

[0015] The embodiment of the present invention provides a register (register, reg for short) design method, such as Figure 1 Shown, including:

[0016] Step S1: Construct the first register description reconstruction set {A1, A2, ..., A m ,...,A M}, the second register describes the reconstruction set {B1, B2, ..., B n ,...,B N} and the third register describes the reconstruction set {C1, C2, ..., C k ,...,C K}, where A m The description and reconstruction information of the register group (reg block) corresponding to the mth chip IP, the value range of m is 1 to M, M is the total number of chip IP (Intellectual Property) in the chip design, B n The description reconstruction information of the nth register, the value range of n is 1 to N, N is the total number of registers in the chip design, C k The description reconstruction information of the kth register field (reg field) is provided. The value of k ranges from 1 to K, where K is the total number of register fields of all registers in the chip design. The register group corresponding to the chip IP includes at least one register or at least one register group and register, and the register includes at least one register field.

[0017] It should be noted that the registers within a chip IP constitute a register group. If the chip IP is large, the large chip IP can be further divided into multiple blocks. Each block is considered a small chip IP, and each chip IP is assigned a register group. Therefore, a register group can include registers and register groups, or a register array (reg array), which contains multiple identical registers. Register domains are nested within registers. A register can contain one or more register domains. Register domains within a register are continuous, while valid register domains can be discrete. For example, a register may have four register domains, F1, F2, F3, and F4, where F1 and F3 are valid. Multiple chip IPs can be constructed into a chip subsystem. The chip IPs and / or chip subsystems form a system-on-a-chip (SoC). The registers in the second register description reconstruction set are not necessarily registers in the register array. They can also be registers within a chip subsystem or system-on-chip that are not part of the chip IP, namely registers at the subsystem chip level and registers at the SoC level.

[0018] Step S2: Obtain target A corresponding to the target design m Target B n and Objective-C k The target design is a chip IP, a subsystem chip composed of chip IP, or a SoC chip, wherein the chip IP includes the registers of the register group corresponding to the chip IP; the registers in the subsystem chip include the registers of the chip IP contained in the subsystem chip and the registers at the subsystem chip level; the SoC chip includes the registers in the subsystem chip, the registers of the chip IP, and the registers at the SoC level.

[0019] It should be noted that the first register description based on the reconstruction set {A1, A2, ..., A m ,...,A M}, the second register describes the reconstruction set {B1, B2, ..., B n ,...,B N} and the third register describes the reconstruction set {C1, C2, ..., C k ,...,C K}It can automatically generate register design code for any design of chip IP, subsystem chip composed of chip IP, or SoC chip.

[0020] Step S3: Based on target A m Target B n and Objective-C k Generate register design code corresponding to the target design.

[0021] It should be noted that Target A m Target B n and Objective-C k The hierarchical structure defines description reconstruction information of registers corresponding to the target design. Based on the description reconstruction information of the registers corresponding to the target design, register design codes corresponding to the target design can be accurately and quickly generated.

[0022] As an example, A m Including A m Corresponding register name list, A m The corresponding address mapping file (map) name, A m The corresponding register address width, A m The corresponding total register width, A m Corresponding path information, A m Corresponding reset information, A m The corresponding output granularity and A m The corresponding access attributes, address mapping file includes design name, design instance name, starting address and address range. m The corresponding register address width can be set to 10 bits, 16 bits, 32 bits, etc. m The corresponding reset information includes synchronous reset information and asynchronous reset information. m The corresponding output granularity includes register granularity and register domain granularity. n Including B n Corresponding register name, B n The corresponding address mapping file name, B n The corresponding address width, B n The corresponding address offset, B n Corresponding path information, B n Corresponding reset information, B n The corresponding access attribute. C k Including C k The corresponding address width, C k The corresponding access attributes, C k Corresponding path information, C k The corresponding register domain interval, C k The corresponding reset value.

[0023] It should be noted that registers can be mapped to address mapping files. External access is addressed through address mapping files, and the same address can be mapped to different address mapping files. A register group can correspond to multiple address mapping files, but only a valid address mapping file can be selected during access. Address mapping files can be nested to form a hierarchical structure for address space addressing, resulting in address superposition. Each address mapping file corresponds to a base address. Registers do not have base addresses, but do have offset addresses. Therefore, the base address and offset address must be superimposed to form an absolute address to achieve direct access to the register.

[0024] C k with C k Belong to B n The same attribute information in C does not conflict, and k The attribute information in B covers n The corresponding attribute information in, for example, A m The corresponding register address width is set to 32 bits, then A m The corresponding register B n The corresponding address width can be 32 bits or a number smaller than 32 bits. m The corresponding access attribute is read-only, then A m The corresponding register B n The corresponding attributes in can only be read-only. m The corresponding access attribute is readable and writable, then A m The corresponding register B n The corresponding attributes can be readable and writable, read-only, or write-only.

[0025] B n With B n A m The same attribute information in B does not conflict, and n The attribute information in A covers m The corresponding attribute information in .

[0026] As an example, the access attributes include read-only, write-only, read and write, clear when writing 1, and clear when writing 0. Clear when writing 1 means that when the value is 1, the corresponding data is cleared and the data is set to 0. Clear when writing 0 means that when the value is 0, the corresponding data is cleared and the data is set to 0.

[0027] As an embodiment, the method further comprises the following steps: m Corresponding path information, B n The corresponding path information, and C k Corresponding path information:

[0028] Step S10: Obtain chip design component information {D1, D2, ..., D x ,...,D X ,HC}, where D x The xth component module designed for the chip, D x The minimum component unit or the module composed of the interconnected minimum component units. The value range of x is 1 to X. X is the total number of component modules of the chip design. The component module hierarchy of the X chip design has no submodules, and the top module has no parent module. All components except the minimum unit and the top module have parent modules and submodules. HC is X D x The parent-child structure information between them;

[0029] Step S20: Generate an identifier for each port based on the interconnection information between the chip components;

[0030] Step S30: According to X D x The parent-child structure information between A and m The port identifiers of the corresponding chip IP are concatenated to generate A m The corresponding path information, according to X D x The parent-child structure information between B is sorted in a top-down order. n The port identifiers passed by the corresponding registers are concatenated to generate B n The corresponding path information, according to X D x The parent-child structure information between C is arranged in a top-down order. k The port identifiers passed by the corresponding register domain are concatenated to generate C k The corresponding path information.

[0031] As an example, A m Also includes A m Corresponding designer information, A m The corresponding address virtualization information, A m Corresponding security level information, A m Corresponding description information, A m Corresponding design document information. B n Also includes B n The corresponding description information, B n The corresponding address virtualization information, B n Corresponding security level information, B n Corresponding design document information, if B n The corresponding register is a register array, then B n Also includes register bank depth; C k Also includes C kCorresponding description information. It should be noted that when the physical address is insufficient, virtual addresses can be used to meet the address requirements. In this case, address virtualization can be achieved by setting address virtualization information. Security level information can set the security level of different users, so that different users have different access rights. By setting design document information, documents for the target design can be automatically generated, further improving chip development efficiency.

[0032] As an embodiment, step S2 includes:

[0033] Step S21, obtain the target design. If the target design is a chip IP, execute step S22; if the target design is a subsystem chip, execute step S23; if the target design is a SoC chip, execute step S24.

[0034] It should be noted that the target design can be flexibly specified according to application requirements.

[0035] Step S22: Determine the register group corresponding to the chip IP as the target register group, determine the register included in the chip IP as the target register, and execute step S25.

[0036] It should be noted that if the target design is a chip IP, the register group corresponding to the chip IP is determined as the target register group. If a valid chip IP is nested in the chip IP of the target design, the register group of the nested chip IP is also required to be used as the target register group, and all registers in the target register group are determined as target registers.

[0037] Step S23: determine the register group corresponding to the chip IP included in the subsystem chip as the target register group, determine the registers of the chip IP included in the subsystem chip and the registers at the subsystem chip level as the target registers, and execute step S25.

[0038] It should be noted that the chip IP contained in a subsystem chip also includes the chip IP nested within that chip IP. Subsystem chip-level registers refer to registers located at the subsystem chip level and not in a register group. Such registers may or may not exist, depending on the specific design.

[0039] Step S24: Determine the register group corresponding to the chip IP contained in the subsystem chip included in the SoC chip and the register group corresponding to the chip IP contained in the SoC chip as the target register group, determine the registers in the subsystem chip included in the SoC chip, the registers of the chip IP and the registers at the SoC level as the target registers, and execute step S25.

[0040] It should be noted that the register groups corresponding to the chip IP contained in the subsystem chip within the SoC chip, as well as the chip IP contained in the SoC chip, also include the chip IP nested within the chip IP. SoC-level registers are located at the SoC level and not in register groups. Subsystem chip-level registers and SoC-level registers may or may not exist, depending on the specific design.

[0041] Step S25: A corresponding to the target register group m Determined as Target A m , the B corresponding to the target register n Determined as Target B n , the C corresponding to the target register k Determined as Objective C k .

[0042] As an embodiment, step S3 includes:

[0043] Step S31: Based on target A m Corresponding register name list, path information, address mapping file name, A m The corresponding register address width, A m The corresponding total register width, target B n Corresponding path information, address mapping file name, address width and address offset, target C k The corresponding address width, C k The corresponding path information is address decoded.

[0044] Step S32: Based on target A m Corresponding register name list, path information, reset information, B n Corresponding register name, path information, reset information, C k The corresponding path information and reset value generate the reset logic corresponding to the target design.

[0045] Step S33: Based on target A m Corresponding register name list, path information, access attributes, target B n Corresponding register name, path information, access attributes, target C k The corresponding path information and access attributes generate one or more of a read control signal, a write control information number, a read code, and a write code.

[0046] Step S34: Generate register design code corresponding to the target design based on the generated address decoding, reset logic, read control signal, write control information number, read code, and write code.

[0047] It should be noted that the register name and path information can uniquely determine the location of the register. m Target B n and Objective-C k The corresponding attribute information can automatically generate the address decoding, reset logic, read control signal, write control information number, read code, and write code corresponding to the target design, and generate the register design code corresponding to the target design based on the generated address decoding, reset logic, read control signal, write control information number, read code, and write code.

[0048] In order to optimize the area of ​​the target design, the step S31 may further include:

[0049] Step S30: Target A m Target B n and Objective-C k Divide into different groups, for each group target A m Target B n and Objective-C k Execute steps S31 to S34 respectively.

[0050] It should be noted that automatically generating register design code for the target design by grouping can significantly reduce design area. Furthermore, when evaluating area, you can also reduce design area by disabling all read logic functions and uniformly setting asynchronous resets to synchronous resets.

[0051] As an embodiment, the output granularity includes register level and register domain level. If A m The corresponding output granularity is the register level, then the port list in the register design code corresponding to the generated target design is the register port list. If A m The corresponding output granularity is the register domain level, and the port list corresponding to the generated target design is the register domain port list.

[0052] In the process of generating the register design code corresponding to the target design, different functions can be set to further improve the accuracy of the generation of the register design code corresponding to the target design. As an embodiment, in the process of generating the register design code corresponding to the target design, step S3 further includes:

[0053] Step C1: Detect whether there is illegal address access, and if so, generate a prompt message.

[0054] For example, if a block of addresses 0-63 is defined and bits 0-31 are currently set to be valid, if bits 32-63 are accessed during the generation of register design code corresponding to the target design, a prompt message will be generated.

[0055] Step C2: determine whether an external interface is enabled. If so, generate a corresponding register external interface.

[0056] It should be noted that by setting up the register external interface, it is easy to implement the design of some special registers.

[0057] Step C3: If the value return mode is set to the first mode, the read value is used as the return value; if the value return mode is set to the second mode, the read value is used as the return value after a preset number of cycles.

[0058] It should be noted that by setting different return modes, the design requirements of special registers are met.

[0059] It should be noted that some exemplary embodiments are described as processes or methods depicted as flowcharts. Although the flowcharts describe the steps as sequential processes, many of the steps can be performed in parallel, concurrently, or simultaneously. In addition, the order of the steps can be rearranged. A process can be terminated when its operation is completed, but can also have additional steps not included in the accompanying drawings. A process can correspond to a method, function, procedure, subroutine, subprogram, etc.

[0060] An embodiment of the present invention also provides an electronic device, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are configured to execute the method described in the embodiment of the present invention.

[0061] An embodiment of the present invention further provides a computer-readable storage medium storing computer-executable instructions, wherein the computer instructions are used to execute the method described in the embodiment of the present invention.

[0062] The embodiment of the present invention constructs register description reconstructions at different levels, stores the attribute information of the registers hierarchically in the register description reconstruction, and then automatically generates the register design code corresponding to the target design based on the register description reconstruction of each level corresponding to the target design, thereby improving the design efficiency of the registers and further improving the chip development efficiency.

[0063] The above description is merely a preferred embodiment of the present invention and does not constitute any form of limitation to the present invention. Although the present invention has been disclosed as a preferred embodiment, it is not intended to limit the present invention. Any technician familiar with the present profession can make slight changes or modifications to equivalent embodiments using the technical contents disclosed above without departing from the scope of the technical solution of the present invention. However, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention are still within the scope of the technical solution of the present invention.

Claims

1. A register design method, characterized in that: include: Step S1: Construct the first register description reconstruction set {A1, A2, ..., A m ,...,A M }, the second register describes the reconstruction set {B1, B2, ..., B n ,...,B N } and the third register describes the reconstruction set {C1, C2, ..., C k ,...,C K }, where A m The description and reconstruction information of the register group corresponding to the mth chip IP, the value range of m is 1 to M, M is the total number of chip IPs in the chip design, B n The description reconstruction information of the nth register, the value range of n is 1 to N, N is the total number of registers in the chip design, C k The description reconstruction information of the kth register domain, where k ranges from 1 to K, and K is the total number of register domains of all registers in the chip design. The register group corresponding to the chip IP includes at least one register or includes at least one register group and register, and the register includes at least one register domain. Step S2: Obtain target A corresponding to the target design m Target B n and Objective-C k , the target design is a chip IP, a subsystem chip composed of chip IPs, or a SoC chip, wherein the chip IP includes registers of a register group corresponding to the chip IP; the registers in the subsystem chip include registers of the chip IP contained in the subsystem chip and registers at the subsystem chip level; the SoC chip includes registers in the subsystem chip, registers of the chip IP, and registers at the SoC level; Step S3: Based on target A m Target B n and Objective-C k Generate register design code corresponding to the target design.

2. The method according to claim 1, characterized in that A m Including A m Corresponding register name list, A m The corresponding address mapping file name, A m The corresponding register address width, A m The corresponding total register width, A m Corresponding path information, A m Corresponding reset information, A m The corresponding output granularity and A m The corresponding access attributes,the address mapping file includes the design name, design instance name,,start address and address range; B n Including B n Corresponding register name, B n The corresponding address mapping file name, B n The corresponding address width, B n The corresponding address offset, B n Corresponding path information, B n Corresponding reset information, B n The corresponding access attributes; C k Including C k The corresponding address width, C k The corresponding access attributes, C k Corresponding path information, C k The corresponding register domain interval, C k The corresponding reset value; C k with C k Belong to B n The same attribute information in C does not conflict, and k The attribute information in B covers n The corresponding attribute information in B n With B n A m The same attribute information in B does not conflict, and n The attribute information in A covers m The corresponding attribute information in .

3. The method according to claim 2, characterized in that Access attributes include read-only, write-only, read and write, clear when write 1, and clear when write 0.

4. The method according to claim 1, wherein The step S2 comprises: Step S21, obtain the target design. If the target design is a chip IP, execute step S22; if the target design is a subsystem chip, execute step S23; if the target design is a SoC chip, execute step S24; Step S22: Determine the register group corresponding to the chip IP as the target register group, determine the register included in the chip IP as the target register, and execute step S25; Step S23: Determine the register group corresponding to the chip IP included in the subsystem chip as the target register group, determine the register of the chip IP included in the subsystem chip and the register at the subsystem chip level as the target register, and execute step S25; Step S24: Determine the register group corresponding to the chip IP included in the subsystem chip included in the SoC chip and the register group corresponding to the chip IP included in the SoC chip as the target register group; determine the registers in the subsystem chip included in the SoC chip, the registers of the chip IP, and the registers at the SoC level as the target registers, and execute step S25; Step S25: A corresponding to the target register group m Determined as Target A m , the B corresponding to the target register n Determined as Target B n , the C corresponding to the target register k Determined as Objective C k .

5. The method according to claim 2, characterized in that The step S3 comprises: Step S31: Based on target A m Corresponding register name list, path information, address mapping file name, register address width, register total width, target B n Corresponding path information, address mapping file name, address width and address offset, target C k The corresponding address width and path information are used for address decoding; Step S32: Based on target A m Corresponding register name list, path information, reset information, target B n Corresponding register name, path information, reset information, target C k The corresponding path information and reset value generate the reset logic corresponding to the target design; Step S33: Based on target A m Corresponding register name list, path information, access attributes, target B n Corresponding register name, path information, access attributes, target C k The corresponding path information and access attributes generate one or more of a read control signal, a write control information number, a read code, and a write code; Step S34: Generate register design code corresponding to the target design based on the generated address decoding, reset logic, read control signal, write control information number, read code, and write code.

6. The method according to claim 5, characterized in that Before step S31, the following steps are also included: Step S30: Target A m Target B n and Objective-C k Divide into different groups, for each group target A m Target B n and Objective-C k Execute steps S31 to S34 respectively.

7. The method according to claim 5, characterized in that The output granularity includes register level and register field level. If A m The corresponding output granularity is the register level, then the port list in the register design code corresponding to the generated target design is the register port list. If A m The corresponding output granularity is the register domain level, and the port list corresponding to the generated target design is the register domain port list.

8. The method according to claim 1, characterized in that In the process of generating the register design code corresponding to the target design, step S3 further includes: Step C1: Detect whether there is illegal address access, and if so, generate a prompt message; Step C2: determine whether an external interface is enabled, and if so, generate a corresponding register external interface; Step C3: If the value return mode is set to the first mode, the read value is used as the return value; if the value return mode is set to the second mode, the read value is used as the return value after a preset number of cycles.

9. An electronic device, characterized in that: include: at least one processor; and, a memory communicatively coupled to the at least one processor; The memory stores instructions that can be executed by the at least one processor, and the instructions are configured to execute the method according to any one of claims 1 to 8.

10. A computer-readable storage medium, characterized in that The computer-executable instructions are stored, and the computer-executable instructions are used to execute the method according to any one of the preceding claims 1 to 8.

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