Heterogeneous CPU design space exploration method and device and storage medium

Abstract

The invention provides a heterogeneous CPU (Central Processing Unit) design space exploration method and a heterogeneous CPU design space exploration device, the method and the system aim at a universal heterogeneous multi-core processor design space exploration method and system, the optimal core configuration and resource management strategy under the maximum core area constraint condition is found, and the adopted exploration method can be used for solving the problem that on the premise of ensuring the search effect, the search efficiency is greatly improved. And the search time is greatly reduced. According to the method, firstly, a high-quality design space generation method is introduced to generate a robust heterogeneous multi-core processor design space, and comprehensive exploration is effectively supported; secondly, a prediction-based unified evaluation method is provided to reduce the dependence on time-consuming evaluation, so that the comprehensive exploration of a Cartesian product design space is realized; and finally, in order to improve the exploration precision, an iterative refining exploration method is adopted, key design points are selected in each round, and iterative training is performed on the prediction model.

Description

Technical Field

[0001] The present invention relates to technical fields including processors and machine learning, and more particularly to a design space exploration (DSE) method, device, and storage medium for a heterogeneous multi-core processor (HMP). Background Art

[0002] Designing heterogeneous multicore processors has become a key architectural paradigm for improving performance and energy efficiency in modern computing. This approach leverages different core types and seeks optimal resource management (RM) based on workload characteristics. Heterogeneous multicore processors achieve superior energy efficiency by utilizing high-performance cores (performance cores) for compute-intensive tasks and energy-efficient, low-power cores (efficiency cores) for lighter workloads. The ability to balance workloads across different core types ensures efficient resource utilization, thereby improving overall system performance.

[0003] Recently, a large body of work has focused on design space exploration or resource management strategy exploration (RMSE) for heterogeneous multicore processors. RMSE refers to the exploration of resource management strategies within a specific heterogeneous multicore processor design, with the goal of finding the optimal evaluation metric to exploit potential performance and energy efficiency. Previous work has proposed dynamic frequency scaling and task scheduling algorithms for specific heterogeneous multicore processors.

[0004] Heterogeneous multi-core processor design space exploration RMSE refers to a systematic approach that aims to find the ideal balance between performance, power consumption and area under a specific resource management strategy by considering various design choices (such as different core types). Previous methods used brute force to explore the design space of heterogeneous multi-core processors, but it took too long. In order to reduce the time spent on brute force evaluation of heterogeneous combinations, the existing technology has proposed a variety of strategies, such as using a clustering strategy to determine a selected number of representative cores. Another strategic approach is to diversify the core selection, which shortens the exploration time of heterogeneous combinations by 99% compared to the baseline. Another strategic approach is to use the heuristic algorithm simulated annealing to explore the design space of heterogeneous core processors.

[0005] Existing technologies separate the exploration of the design space of heterogeneous multi-core processors or the exploration of resource management strategies, which greatly limits the exploration space and overall exploration efficiency. In practical applications, heterogeneous multi-core processor design and resource management are interrelated and mutually constrained, and the synergy between them is crucial to achieving optimal performance and energy efficiency. Previous fragmented research methods have hindered a comprehensive understanding of the true performance of heterogeneous multi-core processors under different workloads and scenarios. Therefore, there is an urgent need for a novel HMP×RM DSE method to unify the exploration of the design space of heterogeneous multi-core processors and the exploration of resource management strategies, where the "×" symbol represents the Cartesian product, which represents the space formed by the orthogonal intersection of two dimensions. Since these two methods have complementary effects in improving the performance and energy efficiency of heterogeneous multi-core processors, the unification of these two methods is crucial. Existing technologies have three main defects:

[0006] Defect 1. Low-quality design space generation. Previous work on design space generation has not been able to support the full development of the design space. Previous work has shown that increasing microarchitectural diversity in the core set can enhance the flexibility of resource management strategies, thereby improving performance. Expanding the candidate core space from 5 to 25 can unlock the potential of heterogeneous multi-core processor designs. However, the size of the design space of heterogeneous multi-core processors has increased significantly, resulting in unacceptable evaluation time for heterogeneous multi-core processor design space exploration and posing greater challenges for unified exploration. Therefore, the size of the generated design space must be appropriate while maintaining high quality. The spaces generated by previous methods are too limited, which prevents them from fully realizing the potential of the comprehensive design space.

[0007] Flaw 2: Unbearable design space evaluation time. Directly combining heterogeneous multicore processor design space exploration and resource management strategy exploration presents a challenge in exploring a unified design space and achieving optimal results within a feasible timeframe. The unified exploration space for heterogeneous multicore processor designs and resource management strategies is enormous. Directly exploring all resource management strategies for each heterogeneous multicore processor design point significantly increases evaluation time, often exceeding reasonable limits. Ultimately, this approach may fail to complete the entire design space exploration process, resulting in suboptimal results.

[0008] Flaw 3: Low-precision design space exploration. Previous exploration methods have been unable to achieve high-precision, unified exploration of heterogeneous multi-core processor designs and resource management strategies. Even with existing exploration methods, achieving high-precision, unified exploration remains challenging. This challenge arises from relying on heuristic search and utilizing evaluation metrics exclusively for evaluated design points. Furthermore, these methods neglect the use of state-of-the-art data-driven machine learning models to accurately predict unevaluated designs, hindering improvements in exploration accuracy. Summary of the Invention

[0009] The purpose of the present invention is to solve the problem of low exploration efficiency in the above-mentioned prior art, and proposes a method and system for exploring the design space of a general-purpose heterogeneous multi-core processor microarchitecture. The present invention implements a method and system for exploring the design space of a general-purpose heterogeneous multi-core processor, and finds the most optimal core configuration and resource management strategy under the maximum core area constraint. The exploration method adopted can significantly reduce the search time while ensuring the search effect. The present invention first introduces a high-quality design space generation method to generate a robust heterogeneous multi-core processor design space, which effectively supports comprehensive exploration; secondly, the present invention proposes a unified evaluation method based on prediction to reduce dependence on time-consuming evaluation, thereby realizing comprehensive exploration of the Cartesian product design space; finally, in order to improve the accuracy of exploration, an iterative refinement exploration method is adopted, and key design points are selected in each round to iteratively train the prediction model.

[0010] Specifically, the present invention proposes a heterogeneous CPU design space exploration method, which includes:

[0011] Step S1: obtaining a plurality of single-core design spaces, each of which includes a plurality of single-core design space parameters, selecting a design point in the single-core design space to obtain a current single-core design point of each single-core design space; and obtaining a plurality of workloads;

[0012] Step S2: Evaluate the first performance indicator of each single-core design point in the current single-core design point; for each workload, use the first performance indicator of each single-core design point in the current single-core design point to train a first performance indicator model to obtain a first performance indicator model corresponding to each workload, and use the first performance indicator model to predict the first performance indicators of design points in the single-core design space other than the current single-core design point;

[0013] Step S3: Merge the single-core design points with the best first performance indicator under each workload to obtain a multi-core design point set, and select the design points in the multi-core design point set that meet the CPU target design constraints as the HMP design space;

[0014] Step S4: Cartesian product the RM strategy space with multiple resource management strategies with the HMP design space to obtain an HMP×RM design space, and generate an initial sampling evaluation point set of the HMP×RM design space;

[0015] Step S5: Evaluate the second performance index of each design point in the initial sampling evaluation point set to train a second performance index prediction model, and use the second performance index prediction model to predict the second performance index of the design points other than the initial sampling evaluation point set in the HMP×RM design space;

[0016] Step S6: Select the design point with the best second performance indicator in the HMP×RM design space as the heterogeneous CPU design space exploration result.

[0017] The heterogeneous CPU design space exploration method, wherein step S2 includes: evaluating the first performance indicator of each single-core design point in the current single-core design point, and using the evaluated single-core design point as a single-core evaluation sample; according to the Pareto optimal solution set of the current single-core design point, obtaining the super-volume improvement of the first performance indicator of the design points in the single-core design space other than the current single-core design point, selecting the single-core design point with the largest super-volume improvement as the current single-core design point, and executing step S2 again until the number of single-core evaluation samples reaches a set threshold.

[0018] The heterogeneous CPU design space exploration method, wherein step S3 includes adopting a metric-centric encoding method to add performance indicator metrics of various cores to the HMP design point encoding.

[0019] The heterogeneous CPU design space exploration method, wherein the first performance indicator model is a single-objective prediction model obtained by strengthening the GBRT tree model through the gradient boosting ensemble learning method.

[0020] The present invention also proposes a heterogeneous CPU design space exploration device, which includes:

[0021] An initialization module is used to obtain multiple single-core design spaces, each single-core design space including multiple single-core design space parameters, select a design point in the single-core design space, obtain a current single-core design point of each single-core design space; and obtain multiple workloads;

[0022] a first evaluation module configured to evaluate a first performance indicator of each single-core design point in the current single-core design point; for each workload, using the first performance indicator of each single-core design point in the current single-core design point to train a first performance indicator model to obtain a first performance indicator model corresponding to each workload; and using the first performance indicator model to predict the first performance indicators of design points in the single-core design space other than the current single-core design point;

[0023] a merging and screening module, configured to merge the single-core design points with the best first performance indicator under each workload to obtain a multi-core design point set, and screen out design points in the multi-core design point set that meet the CPU target design constraint conditions as the HMP design space;

[0024] A Cartesian product module is used to perform a Cartesian product between the RM strategy space having multiple resource management strategies and the HMP design space to obtain an HMP×RM design space and generate an initial sampling evaluation point set of the HMP×RM design space;

[0025] a second evaluation module, configured to evaluate a second performance index of each design point in the initial sampling evaluation point set to train a second performance index prediction model, and use the second performance index prediction model to predict the second performance index of design points other than the initial sampling evaluation point set in the HMP×RM design space;

[0026] The design result output module is used to select the design point with the best second performance indicator in the HMP×RM design space as the heterogeneous CPU design space exploration result.

[0027] The heterogeneous CPU design space exploration device, wherein the first evaluation module includes: evaluating the first performance indicator of each single-core design point in the current single-core design point, and using the evaluated single-core design point as a single-core evaluation sample; obtaining the super-volume improvement of the first performance indicator of the design points in the single-core design space other than the current single-core design point based on the Pareto optimal solution set of the current single-core design point, selecting the single-core design point with the largest super-volume improvement as the current single-core design point, and calling the first evaluation module again until the number of single-core evaluation samples reaches a set threshold.

[0028] The heterogeneous CPU design space exploration device, wherein the merging and screening module includes a metric-centric encoding method to add performance indicator metrics of various cores to the HMP design point encoding.

[0029] The heterogeneous CPU design space exploration device, wherein the first performance indicator model is a single-objective prediction model obtained by strengthening the GBRT tree model through the gradient boosting ensemble learning method.

[0030] The present invention also proposes a server, which includes a heterogeneous CPU design space exploration device as described in claims 5-8.

[0031] The present invention also proposes a storage medium for storing a computer program for executing the heterogeneous CPU design space exploration method described in claims 1-4.

[0032] From the above scheme, it can be seen that the advantages of the present invention are:

[0033] Experiments on the general CPU load test set SPEC CPU 2017 show that compared with the most advanced design space exploration framework FARSI, under similar exploration time, the proposed method reduces the energy-delay product (ED) by 55% and the delay-energy squared product (E-S) by 62%. 2 D), reducing the energy consumption delay square product (ED 2 ), improving energy efficiency by 5.1 times (BIPS 3 / W). BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 This is the execution flow chart of the Heterogeneous CPU Design Space Exploration Framework HetDSE of the present invention; DETAILED DESCRIPTION

[0035] When conducting research on heterogeneous CPU design space exploration, the inventors analyzed the three challenges discovered above.

[0036] In response to the above-mentioned defect 1, the present invention introduces a high-quality design space generation method to create a robust heterogeneous multi-core processor design space to effectively support comprehensive exploration. First, the present invention realizes that it is necessary to generate high-quality single-core design points, such as the Pareto optimal set under various loads, and then cross-operate the obtained cores and filter out the heterogeneous multi-core processor design space that meets the system constraints (such as the maximum core area). The heterogeneous multi-core processor design space obtained in this way is of moderate size and can provide support for subsequent exploration. At the same time, each heterogeneous multi-core processor design point is composed of high-quality single cores, and the achievable evaluation indicators are better, such as less execution delay or lower energy consumption.

[0037] In response to defect 2, the present invention found that the use of a prediction model can help shorten the evaluation time and quickly predict the evaluation indicators of heterogeneous multi-core processor design and resource management strategies in a unified manner without the need for a large number of evaluations. At the same time, during analysis, it was found that the encoding directly centered on the number of cores is extremely sparse, its feature space is largely sparse, and the distribution in the area near the origin is extremely biased, which poses a challenge to the training of the prediction model. Therefore, the present invention considers using a metric-centered encoding method to encode the design points of heterogeneous multi-core processors. The distribution of metrics is relatively flat, which can effectively improve the learning effect of the prediction model.

[0038] To address defect 3, the present invention discovered that previous methods only utilized heuristic search and evaluation metrics for already evaluated design points. The present invention utilizes a predictive model to evaluate the evaluation metrics of unknown design points. Simultaneously, this data drives a machine learning model to estimate the reliability of the predictions. Using an iterative refinement exploration method, key design points are selected in each round, and the predictive model is iteratively trained. This allows the design to maximize the potential of the entire design space.

[0039] In summary, in order to achieve the above technical effects, the present invention includes the following key technical points:

[0040] Key point 1: A high-quality design space generation method. Compared with previous core selection methods, this technology performs a set and merge operation based on the Pareto optimal set of single-core cores generated by the single-core explorer, uses representative selection and crossover to generate high-quality heterogeneous multi-core processor design points, and filters out heterogeneous multi-core processor design points that meet system constraints, thereby improving the processor performance ceiling of design space exploration.

[0041] Key Point 2: A unified prediction-based evaluation method for heterogeneous multi-core processors and resource management strategies. This method proposes a metric-centric feature encoding method for training samples and designs a performance prediction model that directly predicts performance evaluation metrics for heterogeneous multi-core processors and resource management strategy design points, reducing reliance on time-consuming evaluations and enabling a comprehensive exploration of the Cartesian product design space of heterogeneous multi-core processors and resource management strategies.

[0042] Key point 3: An efficient iterative exploration method for the design space; using an iterative refinement exploration method, each round selects design points where the evaluation index is expected to improve to the extreme value, and iteratively trains the prediction model to effectively improve the exploration accuracy.

[0043] To illustrate the above-mentioned features and effects of the present invention more clearly and easily, the following embodiments are specifically described below with reference to the accompanying drawings. This specification discloses one or more embodiments incorporating the features of the present invention. The disclosed embodiments are for illustrative purposes only. The scope of protection of the present invention is not limited to the disclosed embodiments; the present invention is defined by the appended claims.

[0044] This paper proposes an accurate heterogeneous CPU DSE framework using an iterative mechanism. The process of the framework is as follows Figure 1 The heterogeneous CPU design space exploration framework HetDSE is shown in the figure. HetDSE consists of four key components: a single-core design space generator that generates a single-core design space, a set of single-core explorers (denoted as Single-core Explorer_i), each of which explores the optimal design point under a specific workload, a heterogeneous multi-core processor HMP design space generator (used to generate high-quality HMP design space), an HMP explorer (used to explore a unified exploration space to obtain the best heterogeneous multi-core processor HMP design and resource management RM strategy).

[0045] Step 1: Input and select the microarchitecture parameters of interest (see Table 1 for the single-core design space parameter list) to form a single-core design point s i Space:

[0046] Table 1 Single core design space parameter list

[0047] Parameter number Microarchitecture parameter name Candidate value 1 Emission width 2 / 4 / 5 / 6 2 Decoding width 2 / 3 / 4 / 5 3 ROB Depth 32 / 64 / 128 / 256 4 branch predictor Gshare / TAGE 5 BP, ALU, number of multiplication and division ports 1 / 2，1 / 2，1 / 2 6 Floating-point ALU, multiplication port number 1 / 2，1 / 2 7 Read, write back, read-write back ports 1 / 2，1 / 2，0 / 2 8 L1 instruction cache associativity 2 / 4 / 8-way 9 Level 1 data cache associativity 2 / 4 / 8-way 10 L2 cache associativity 4 / 8-way

[0048] s i = <arg1,...,arg 10 >

[0049] Where arg is the parameter number of the single-core design space. All single-core design points form the single-core design space D core ;

[0050] D core ={s1,s2,...,s n}

[0051] An initial set of single-core design points was obtained using an orthogonal sampling method, generating an initial set of design points. Orthogonal sampling, which samples the space, is characterized by evenly distributing the design points, ensuring that each value within each parameter appears an equal number of times, and that the logarithms of any two parameters appear an equal number of times. The orthogonal sampling results for the required number of parameters and the possible number of values for each parameter can be obtained by consulting a publicly available website.

[0052] Step 2: Use evaluation tools such as simulators and power estimators to obtain performance metrics for a single-core design point. The performance metrics include at least latency and energy consumption.

[0053] Specifically, the evaluated design point is called a single-core evaluation sample. This paper uses a cycle-accurate simulator to evaluate delay. The simulator is implemented in C and simulates the RISC-V RV64GC instruction set at the specific microarchitecture configuration corresponding to the design point. It simulates each component of the microarchitecture at the cycle level to ultimately obtain the execution time (delay). The performance monitor counters collect various event data, which are then fed into the power estimator to calculate energy consumption.

[0054] Step 3: For each workload (computing task), a workload is a software program running on the CPU. A common workload set is SPEC CPU 2017, which is the most typical workload set for general-purpose processors. One such workload is gcc (a compiler program). SPEC CPU 2017 contains a total of 23 workloads. The performance metrics of the single-core evaluation samples are used to train single-objective prediction models (SMs) for latency and energy consumption. Each workload corresponds to a single-objective prediction model. The single-objective prediction model is based on a GBRT tree model enhanced with a gradient boosting ensemble learning method. These models are then used to predict the performance metrics of the remaining design points. These single-core prediction models (SMs) are subsequently used in the RepreSelection and HMPExplorer processes.

[0055] Step 4: Explore the single-core design space by considering both latency and energy consumption.

[0056] For a set of design points S and n objectives (n is 2 in this solution, f1 is delay, f2 is energy consumption), if f i (s * )≤f i (s); f j (s * ) <f j (s), then s is s * dominated by, i.e. s * <s, otherwise s is not s * dominated, that is Among all the design points, a set of design points that are not dominated by other design points is called the Pareto optimal solution set Ω. The Pareto-optimal solution set is defined as the Pareto-optimal solution set for a single-core design point set obtained by traversing the sampled design points and performing sequential evaluations. Based on the Pareto-optimal solution set for the currently sampled single-core design point set, the hypervolume improvement of the predicted values for all unevaluated single-core design points is calculated. The single-core design point with the largest hypervolume improvement is selected as the next single-core evaluation sample. Steps 2-4 are repeated until the number of single-core evaluation samples reaches a set threshold (e.g., 100).

[0057] Step 5: HqHMP generates a high-quality HMP design space through representative selection (RepreSelection) and crossover. The Pareto optimal sets generated by the single-core explorer are merged, the resulting cores are crossovered, and the HMP design space that satisfies system constraints (such as maximum core area) is filtered out. Among them, the representative selection is the Pareto optimal solution set obtained in step 4. The design points of the Pareto optimal solution set are all representative design points in the entire single-core design space, so the process of obtaining the Pareto optimal solution set is called representative selection. Crossover refers to the process of performing a Cartesian product operation on the merged core space, that is, the process of forming heterogeneous multi-cores from single cores.

[0058] Step 6: Use the metric-centered encoding method to encode the HMP design points. The original core-centered encoding is to form the number of each type of core into a vector form.

[0059] x= <n1,…,n K >,

[0060] However, due to typical system constraints, only a small number of n jNon-zero, extremely sparse. The present invention proposes to reduce the sparsity of the original core-centered encoding. Encoding refers to a way of characterizing the HMP design points so that they can be input into subsequent models for training. Without encoding, it is difficult to carry out the subsequent prediction model establishment process. Metric-centered encoding refers to adding the performance indicator measurement of each core to the original core number vector to form a combination of encoding. This encoding can reduce the sparsity of its encoding and improve the learning effect of the subsequent prediction model.

[0061]

[0062] Where T(s i ) represents the latency and energy performance metrics for all loads and all core frequencies, W set represents a workload set (e.g., all 23 workloads from SPEC CPU 2017), F set Represents the candidate core frequency set (such as F set ={1GHz, 1.5GHz, 2GHz, 3GHz}), SM represents the single-core prediction model, which is used to predict latency and energy consumption indicators.

[0063] The RM strategy space is user-specified and consists of several resource management strategies. The HMP design space and the RM strategy space are combined using a Cartesian product operation to generate the HMP × RM design space. The combination of HMP design points and RM strategies is called an HMP-RM evaluation point. An initial set of sampled HMP-RM evaluation points is generated. The set of unsampled HMP-RM evaluation points is U.

[0064] Step 7: Evaluate the HMP-RM evaluation points to obtain delay and energy consumption metrics, based on which the target evaluation metric (e.g., delay-energy product ED) is calculated. The evaluated HMP-RM design points are called HMP-RM samples. The evaluation tools used in the present invention are also based on a cycle-accurate simulator and a power estimator.

[0065] Step 8: Train the prediction model HMPPerfModel based on the evaluation results of the HMP-RM samples. The features x of the training set samples are the combination of the metric-centric HMP encoding and the RM strategy encoding.

[0066] χ= <n1,T(s1),...,n K ,T(s K ),rm>,

[0067] where n i is the number of cores in class i, rm is the encoding of the resource management policy, and the sample label y is the target evaluation metric (e.g., y = ED(x)). The prediction model can use a random forest or other predictive classifier. The trained model is used to predict the evaluation metrics for the remaining HMP-RM evaluation points.

[0068] Because each load situation is different, the Pareto optimal solution set has a large number of candidate core types (about 60), including high-performance cores (low latency and high energy consumption) and high-energy consumption cores (high latency and low energy consumption), as well as several balanced types in between. It is generated by step 5.

[0069] Step 9: Use the EI-Explorer to select the next HMP-RM evaluation sample. The EI-Explorer calculates the expected improvement for each unevaluated HMP-RM design point x.

[0070] EI(x)=μ(x)-λ×σ(χ),

[0071] Where μ(χ) is the evaluation index predicted by HMPPerfModel, σ(x) is the standard deviation of the HMPPerfModel prediction, and λ is a hyperparameter to balance the exploration ratio (set to 0.05). Since the performance indicators are different (for example, the smaller the delay-energy product, the better the performance, and the larger the energy efficiency, the better the performance), the present invention unifies them into a minimization problem (for example, energy efficiency, using a negative value), so the exploration selector selects the design point χ that minimizes EI *

[0072] χ * =argmin x∈U EI(x),

[0073] This is used as the HMP-RM design point for the next round of iterative evaluation. If the number of HMP-RM evaluation samples is less than a set threshold (e.g., 100), the process returns to step 7 or step 9. Step 7 is preferred, with the next HMP-RM evaluation sample selected. Its performance metric is only an estimate of the prediction model. The actual performance metric must be evaluated in step 7, added to the training set, and HMPPerfModel trained again to improve the prediction performance. Therefore, returning to step 7 yields better results than step 9. Otherwise, the optimal HMP design point and RM strategy are output in step 10.

[0074] The following is a system embodiment corresponding to the above method embodiment. This embodiment can be implemented in conjunction with the above embodiment. The relevant technical details mentioned in the above embodiment are still valid in this embodiment and will not be repeated here to reduce repetition. Accordingly, the relevant technical details mentioned in this embodiment can also be applied to the above embodiment.

[0075] The present invention also proposes a heterogeneous CPU design space exploration device, which includes:

[0076] An initialization module is used to obtain multiple single-core design spaces, each single-core design space including multiple single-core design space parameters, select a design point in the single-core design space, obtain a current single-core design point of each single-core design space; and obtain multiple workloads;

[0077] a first evaluation module configured to evaluate a first performance indicator of each single-core design point in the current single-core design point; for each workload, using the first performance indicator of each single-core design point in the current single-core design point to train a first performance indicator model to obtain a first performance indicator model corresponding to each workload; and using the first performance indicator model to predict the first performance indicators of design points in the single-core design space other than the current single-core design point;

[0078] a merging and screening module, configured to merge the single-core design points with the best first performance indicator under each workload to obtain a multi-core design point set, and screen out design points in the multi-core design point set that meet the CPU target design constraint conditions as the HMP design space;

[0079] A Cartesian product module is used to perform a Cartesian product between the RM strategy space having multiple resource management strategies and the HMP design space to obtain an HMP×RM design space and generate an initial sampling evaluation point set of the HMP×RM design space;

[0080] a second evaluation module, configured to evaluate a second performance index of each design point in the initial sampling evaluation point set to train a second performance index prediction model, and use the second performance index prediction model to predict the second performance index of design points other than the initial sampling evaluation point set in the HMP×RM design space;

[0081] The design result output module is used to select the design point with the best second performance indicator in the HMP×RM design space as the heterogeneous CPU design space exploration result.

[0082] The heterogeneous CPU design space exploration device, wherein the first evaluation module includes: evaluating the first performance indicator of each single-core design point in the current single-core design point, and using the evaluated single-core design point as a single-core evaluation sample; obtaining the super-volume improvement of the first performance indicator of the design points in the single-core design space other than the current single-core design point based on the Pareto optimal solution set of the current single-core design point, selecting the single-core design point with the largest super-volume improvement as the current single-core design point, and calling the first evaluation module again until the number of single-core evaluation samples reaches a set threshold.

[0083] The heterogeneous CPU design space exploration device, wherein the merging and screening module includes a metric-centric encoding method to add performance indicator metrics of various cores to the HMP design point encoding.

[0084] The heterogeneous CPU design space exploration device, wherein the first performance indicator model is a single-objective prediction model obtained by strengthening the GBRT tree model through the gradient boosting ensemble learning method.

[0085] The present invention also proposes a server, which includes the heterogeneous CPU design space exploration device.

[0086] The present invention also proposes a storage medium for storing a computer program for executing the heterogeneous CPU design space exploration method.

[0087] Although the embodiments of the present invention have been disclosed above, they are not limited to the applications listed in the description and implementation methods. They can be fully applied to various fields suitable for the present invention. For those familiar with the art, additional modifications can be easily implemented. Therefore, without departing from the general concept defined by the claims and the scope of equivalents, the present invention is not limited to the specific details and illustrations shown and described herein.

Claims

1. A heterogeneous CPU design space exploration method, characterized in that: include: Step S1: obtaining a plurality of single-core design spaces, each of which includes a plurality of single-core design space parameters, selecting a design point in the single-core design space, and obtaining a current single-core design point of each single-core design space; and acquire multiple workloads; Step S2: Evaluate the first performance indicator of each single-core design point in the current single-core design point; for each workload, use the first performance indicator of each single-core design point in the current single-core design point to train a first performance indicator model to obtain a first performance indicator model corresponding to each workload, and use the first performance indicator model to predict the first performance indicators of design points in the single-core design space other than the current single-core design point; Step S3: Merge the single-core design points with the best first performance indicator under each workload to obtain a multi-core design point set, and select the design points in the multi-core design point set that meet the CPU target design constraints as the HMP design space; Step S4: Cartesian product the RM strategy space with multiple resource management strategies with the HMP design space to obtain an HMP×RM design space, and generate an initial sampling evaluation point set of the HMP×RM design space; Step S5: Evaluate the second performance index of each design point in the initial sampling evaluation point set to train a second performance index prediction model, and use the second performance index prediction model to predict the second performance index of the design points other than the initial sampling evaluation point set in the HMP×RM design space; Step S6: Select the design point with the best second performance indicator in the HMP×RM design space as the heterogeneous CPU design space exploration result.

2. The heterogeneous CPU design space exploration method according to claim 1, wherein: This step S2 includes: evaluating the first performance index of each single-core design point in the current single-core design point, and using the evaluated single-core design point as a single-core evaluation sample; obtaining the super-volume improvement of the first performance index of the design points other than the current single-core design point in the single-core design space based on the Pareto optimal solution set of the current single-core design point, selecting the single-core design point with the largest super-volume improvement as the current single-core design point, and executing step S2 again until the number of single-core evaluation samples reaches a set threshold.

3. The heterogeneous CPU design space exploration method according to claim 1, wherein: The step S3 includes adopting a metric-centric encoding method to add various core performance indicator metrics to the HMP design point encoding.

4. The heterogeneous CPU design space exploration method according to claim 1, wherein: The first performance indicator model is a single-target prediction model obtained by strengthening the GBRT tree model through the gradient boosting ensemble learning method.

5. A heterogeneous CPU design space exploration device, characterized in that: include: An initialization module is used to obtain a plurality of single-core design spaces, each of which includes a plurality of single-core design space parameters, select a design point in the single-core design space, and obtain a current single-core design point of each single-core design space; and acquire multiple workloads; a first evaluation module configured to evaluate a first performance indicator of each single-core design point in the current single-core design point; for each workload, using the first performance indicator of each single-core design point in the current single-core design point to train a first performance indicator model to obtain a first performance indicator model corresponding to each workload; and using the first performance indicator model to predict the first performance indicators of design points in the single-core design space other than the current single-core design point; a merging and screening module, configured to merge the single-core design points with the best first performance indicator under each workload to obtain a multi-core design point set, and screen out design points in the multi-core design point set that meet the CPU target design constraint conditions as the HMP design space; A Cartesian product module is used to perform a Cartesian product between the RM strategy space having multiple resource management strategies and the HMP design space to obtain an HMP×RM design space and generate an initial sampling evaluation point set of the HMP×RM design space; a second evaluation module, configured to evaluate a second performance index of each design point in the initial sampling evaluation point set to train a second performance index prediction model, and use the second performance index prediction model to predict the second performance index of design points other than the initial sampling evaluation point set in the HMP×RM design space; The design result output module is used to select the design point with the best second performance indicator in the HMP×RM design space as the heterogeneous CPU design space exploration result.

6. The heterogeneous CPU design space exploration device according to claim 5, characterized in that: The first evaluation module includes: evaluating the first performance index of each single-core design point in the current single-core design point, and using the evaluated single-core design point as a single-core evaluation sample; obtaining the super-volume improvement of the first performance index of the design points other than the current single-core design point in the single-core design space based on the Pareto optimal solution set of the current single-core design point, selecting the single-core design point with the largest super-volume improvement as the current single-core design point, and calling the first evaluation module again until the number of single-core evaluation samples reaches a set threshold.

7. The heterogeneous CPU design space exploration device according to claim 5, characterized in that: The merged screening module includes a metric-centric encoding method to add various core performance indicator metrics to the HMP design point encoding.

8. The heterogeneous CPU design space exploration device according to claim 5, wherein: The first performance indicator model is a single-target prediction model obtained by strengthening the GBRT tree model through the gradient boosting ensemble learning method.

9. A server, characterized in that: It includes a heterogeneous CPU design space exploration device as described in claims 5-8.

10. A storage medium for storing a computer program for executing the heterogeneous CPU design space exploration method according to claims 1-4.

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