Storage medium access method and device

Abstract

The embodiment of the invention provides a storage medium access method and device, and the method comprises the steps that a first processor core determines N first access requests, the first access requests are access requests which are generated by the first processor core and are not executed, and the first access requests are used for requesting to access a storage area in a first access range of a storage medium; the first processor core determines a target access request from the N first access requests and executes the target access request, the target access request being a first access request independent of the second access request, the second access request is generated earlier than the depended first access request, and a second access range corresponding to the second access request is overlapped with a first access range corresponding to the depended first access request. The first processor core is any processor core in the multi-core processor, and the plurality of processor cores do not need to compete for an exclusive lock of a storage medium and can execute respective first access requests in parallel, so that the concurrency capability of the multi-core processor can be improved.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to a method and apparatus for accessing a storage medium. Background Technology

[0002] With the rapid development of computer technology, the performance limitations of single-core processors have become increasingly apparent. To improve processor efficiency, multi-core processors have emerged. However, as the number of processor cores in multi-core processors increases, the competition among multiple processor cores to access the same storage medium also intensifies. Taking RAM as an example, when multiple processor cores need to access RAM, regardless of whether the storage areas they are accessing are the same, all processor cores must compete for the exclusive lock of the RAM. After one processor core acquires the exclusive lock, it can access the RAM, while other processor cores must wait for the first core to release its exclusive lock before they can compete for the lock and access the RAM. This reduces the concurrency capability of multi-core processors, leading to lower processing efficiency. Therefore, how to improve the concurrency capability of multi-core processors when multiple processor cores access the same storage medium is a pressing technical problem that needs to be solved. Summary of the Invention

[0003] This application provides a method and apparatus for accessing a storage medium, which is used to improve the concurrency capability of a multi-core processor when multiple processor cores access the same storage medium.

[0004] In a first aspect, embodiments of this application provide a method for accessing a storage medium. The execution subject of this method is a first processor core, a module within the first processor core, or a chip within the first processor core in a multi-core processor. The first processor core can be any processor core in the multi-core processor; the method is described here using the first processor core as the execution subject. The method includes: the first processor core first determining N first access requests, wherein each first access request is an access request generated by the first processor core but not yet executed, and the first access request is used to request access to a storage area within a first access range of the storage medium, where N is an integer greater than 0. The first processor core then determines a target access request from the N first access requests. The target access request is a first access request that does not depend on a second access request. The second access request is an access request generated by any processor core in the multi-core processor but not yet executed, and the second access request was generated earlier than the dependent first access request, and the second access range corresponding to the second access request overlaps with the first access range corresponding to the dependent first access request. Afterward, the first processor core executes the target access request.

[0005] In the above method, after determining the N first access requests to be executed, each processor core in the multi-core processor selects a first access request that does not depend on the second access request from the N first access requests. Each processor core executes the selected first access request that does not depend on the second access request in parallel. In the above process, multiple processor cores do not need to compete for the exclusive lock of the storage medium and can execute their respective selected first access requests that do not depend on the second access request in parallel, which is beneficial to improving the concurrency capability of the multi-core processor and thus improving the processing efficiency of the multi-core processor.

[0006] In one possible design, the first processor core determines the target access request from N first access requests, which may include: for each of the N first access requests, performing the following steps: the first processor core determines a second access request that one of the N first access requests depends on; the first processor core determines the target access request from the N first access requests based on the second access requests that each of the N first access requests depends on. This design provides a method for determining a target access request.

[0007] In one possible design, each processor core in a multi-core processor maintains a range tree. Each range tree includes multiple nodes, each node corresponds to an access request, and each access request includes an access range. An access request requests access to a storage region within an access range of the storage medium. The first processor core determines a second access request that depends on one of N first access requests. This can be achieved by: the first processor core determining a target node from the nodes in the range trees corresponding to the multiple processor cores in the multi-core processor; wherein the access range in the access request corresponding to the target node overlaps with the first access range in a first access request, and the access request corresponding to the target node was generated earlier than a first access request; and the first processor core determines the access request corresponding to the target node as a second access request that depends on a first access request. In this design, since the time complexity of the range tree search operation is O(log n), the first processor core can quickly and efficiently determine a second access request that depends on a first access request by searching the range trees corresponding to the multiple processor cores.

[0008] In one possible design, the first processor core determines the target access request from the N first access requests based on the second access requests that each of the N first access requests depends on. This can include: the first processor core first determining the number of dependent requests corresponding to each of the N first access requests based on the number of second access requests each of the N first access requests depends on; then determining the first access request with zero dependent requests as the target access request. In this design, the first processor core can quickly determine the target access request from the N first access requests based on the number of dependent requests corresponding to each of the N first access requests.

[0009] In one possible design, the first processor core determines the target access request from the N first access requests based on the second access requests that each of the N first access requests depends on. This can include: for each of the N first access requests, performing the following steps: the first processor core determines an access sequence for a first access request based on the second access request that one of the N first access requests depends on; the access sequence is used to identify the second access request that a first access request depends on; the first processor core determines the first access request corresponding to the access sequence that satisfies a preset condition as the target access request. In this design, the first processor core can quickly and accurately determine the target access request from the N first access requests based on the access sequence of each of the N first access requests.

[0010] In one possible design, the access sequence includes M bits, which are used to indicate the dependency between a first access request and M access requests, where M are access requests generated by the multi-core processor but not yet executed, and M is an integer greater than 0.

[0011] In one possible design, the first processor identifies the first access request corresponding to an access sequence that satisfies preset conditions as the target access request. This can include: the first processor identifying the first access request corresponding to an access sequence where all M bits have a first value as the target access request, where the first value indicates that the first access request is not dependent on the M access requests. In this design, the first processor quickly determines the target access request from N first access requests directly based on the values ​​of the M bits in the access sequence.

[0012] Secondly, embodiments of this application also provide a storage medium access device, which includes a method for performing the method provided in the first aspect above. The storage medium access device includes: a determining module and an execution module.

[0013] The determination module is used to determine N first access requests. The first access request is an access request generated by the first processor core but not executed. The first access request is used to request access to a storage area within the first access range of the storage medium; N is an integer greater than 0.

[0014] The determination module is also used to determine the target access request from N first access requests. The target access request is a first access request that does not depend on the second access request. The second access request is an access request generated by any processor core in the multi-core processor and not executed. The second access request is generated earlier than the first access request that it depends on, and the second access range corresponding to the second access request overlaps with the first access range corresponding to the first access request that it depends on.

[0015] The execution module is used to execute the target access request.

[0016] In one possible design, the determination module is specifically used to: for N first access requests, perform the following steps respectively: determine the second access request that one of the N first access requests depends on; and determine the target access request from the N first access requests based on the second access requests that each of the N first access requests depends on.

[0017] In one possible design, each processor core in a multi-core processor maintains a range tree, which includes multiple nodes. Each node corresponds to an access request, and each access request includes an access range. An access request is used to request access to a storage area within an access range of the storage medium. The determining module is specifically used to: determine a target node from the nodes in the range trees corresponding to the multiple processor cores in the multi-core processor; the access range in the access request corresponding to the target node overlaps with a first access range in a first access request, and the access request corresponding to the target node was generated earlier than the first access request; and determine the access request corresponding to the target node as a second access request that a first access request depends on.

[0018] In one possible design, the determining module is specifically used to: determine the number of dependent requests corresponding to each of the N first access requests based on the number of second access requests that each of the N first access requests depends on; and determine the first access request with a number of dependent requests of zero as the target access request.

[0019] In one possible design, the determining module is specifically used to: for N first access requests, perform the following steps respectively: based on the second access request that one of the N first access requests depends on, determine an access sequence of a first access request, the access sequence being used to identify the second access request that a first access request depends on; and determine the first access request corresponding to the access sequence that satisfies the preset conditions as the target access request.

[0020] In one possible design, the access sequence includes M bits, which are used to indicate the dependency between a first access request and M access requests, where M are access requests generated by the multi-core processor but not yet executed, and M is an integer greater than 0.

[0021] In one possible design, the determining module is specifically used to: determine the first access request corresponding to the access sequence in which all M bits have a first value as the target access request, where the first value is used to characterize that the first access request has no dependency relationship with the M access requests.

[0022] Thirdly, embodiments of this application also provide a computer program product containing instructions that, when executed by a multi-core processor, cause the multi-core processor to perform the method provided in the first aspect above.

[0023] Fourthly, embodiments of this application also provide a storage medium including computer program instructions, which, when executed by a multi-core processor, execute the method provided in the first aspect above.

[0024] Fifthly, embodiments of this application also provide a computing device, including a multi-core processor and a memory, wherein the memory stores computer-executable instructions; the multi-core processor is used to execute the computer-executable instructions stored in the memory, and the multi-core processor executes the method provided in the first aspect above.

[0025] Sixthly, embodiments of this application also provide a chip containing instructions that, when executed by a multi-core processor, cause the multi-core processor to perform the method provided in the first aspect above.

[0026] In a seventh aspect, embodiments of this application provide a chip system containing instructions that, when executed by a multi-core processor, cause the multi-core processor to perform the method provided in the first aspect above. This chip system may be composed of chips or may include chips and other discrete devices. Attached Figure Description

[0027] Figure 1 This is a schematic diagram of the structure of an interval tree provided in an embodiment of this application;

[0028] Figure 2 A system architecture diagram provided for an embodiment of this application;

[0029] Figure 3 A flowchart illustrating a method for accessing a storage medium provided in an embodiment of this application;

[0030] Figure 4 This is a schematic diagram of the structure of an interval tree provided in an embodiment of this application;

[0031] Figure 5 A flowchart illustrating a method for determining a target access request, provided in an embodiment of this application;

[0032] Figure 6 A flowchart illustrating a method for determining a second access request, provided as an embodiment of this application;

[0033] Figure 7 A flowchart illustrating a method for determining a target node provided in an embodiment of this application;

[0034] Figure 8 A flowchart illustrating a method for determining a target access request, provided in an embodiment of this application;

[0035] Figure 9 A flowchart illustrating a method for determining a target access request, provided in an embodiment of this application;

[0036] Figure 10 A flowchart illustrating a method for determining a target access request, provided in an embodiment of this application;

[0037] Figure 11 A schematic diagram of the structure of a storage medium access device provided in an embodiment of this application;

[0038] Figure 12 This is a schematic diagram of the structure of a storage medium access device provided in an embodiment of this application. Detailed Implementation

[0039] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. The terms "first," "second," and corresponding reference numerals in the specification, claims, and drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such terms can be used interchangeably where appropriate; this is merely a way of distinguishing objects with the same attributes in the embodiments of this application. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion, so that a process, method, system, product, or apparatus that comprises a series of units is not necessarily limited to those units, but may include other units not explicitly listed or inherent to these processes, methods, products, or apparatuses.

[0040] The following explanations of some terms used in the embodiments of this application are provided to facilitate understanding by those skilled in the art.

[0041] An interval tree is an extension of a balanced tree. It supports operations on dynamic sets of intervals, where each interval represents a consecutive range of values. Interval operations include insertion, search, and deletion. The time complexity for insertion is O(n*logn), and the time complexity for search or deletion is O(log n), where O represents the time complexity and n is the number of intervals.

[0042] An interval tree can be determined based on at least one interval. An interval tree includes at least one node, and each node corresponds to an interval.

[0043] Furthermore, each node in the interval tree corresponds to a key value, which is the left endpoint of the interval corresponding to that node. Each node in the interval tree also corresponds to a maximum value, which is the maximum value of the endpoints of all intervals in the subtree rooted at that node.

[0044] Taking the three intervals [15,20], [10,30], and [17,19] as an example, the generation process of the interval tree is described in detail. First, an empty interval tree is generated, and then the interval [15,20] is inserted into the interval tree to generate the root node of the interval tree. The interval tree after inserting the interval [15,20] is as follows. Figure 1 As shown in (a) of the diagram. Wherein, Figure 1 In the interval tree shown in (a), the key value of the root node is 15, the left endpoint of the interval [15, 20]. Because... Figure 1 The interval tree shown in (a) has only one root node, so the maximum value corresponding to the root node is the right endpoint value 20 in the interval [15,20].

[0045] Next, the interval [10,30] is inserted into the interval tree. Since the left endpoint value of interval [10,30], 10, is less than the key value of the root node, 15, the interval [10,30] is inserted into the left subtree of the root node in the interval tree. The interval tree after inserting interval [10,30] is as follows. Figure 1 As shown in (b) of the diagram. Wherein, Figure 1 In the interval tree shown in (b), the key value of the left child node is 10, which is the left endpoint of the interval [10, 30]. Figure 1In the interval tree shown in (b), the subtree rooted at the root node includes the root node and the left child node. Since the maximum value of the endpoints in the interval [15,20] corresponding to the root node and the interval [10,30] corresponding to the left child node is 30, the maximum value corresponding to the root node is updated to 30. The subtree rooted at the left child node only includes the left child node. Since the maximum value of the endpoints in the interval [10,30] corresponding to the left child node is 30, the maximum value corresponding to the left child node is also 30.

[0046] Finally, the interval [17,19] is inserted into the interval tree. Since the left endpoint value 17 of the interval [17,19] is greater than the key value 15 of the root node, the interval [17,19] is inserted into the right subtree of the root node in the interval tree. The interval tree after inserting the interval [17,19] is as follows. Figure 1 As shown in (c) of the diagram. Wherein, Figure 1 In the interval tree shown in (c), the key value of the right child node is 17, the left endpoint of the interval [17, 19]. Figure 1 In the interval tree shown in (c), the subtree rooted at the root node includes the root node, the left child node, and the right child node. Since the maximum value of the endpoints in the intervals [15,20] corresponding to the root node, [10,30] corresponding to the left child node, and [17,19] corresponding to the right child node is 30, the maximum value corresponding to the root node is also 30. The subtree rooted at the right child node only includes the right child node. Since the maximum value of the endpoints in the interval [17,19] corresponding to the right child node is 19, the maximum value corresponding to the right child node is also 19.

[0047] according to Figure 1 The interval tree shown in (c) is used to determine whether the intervals [5,12] and [40,50] are related to... Figure 1 Taking the example of overlapping intervals in the interval tree shown, the search process of the interval tree is explained in detail.

[0048] To determine whether any two intervals overlap, the following judgment can be made: if the intervals [left1, right1] and [left2, right2] overlap, then the left and right endpoint values ​​of the two intervals satisfy the following relationship: left1 <= right2, and left2 <= right1.

[0049] For the interval [5,12], first determine if the interval [15,20] corresponding to the root node overlaps with the interval [5,12]. Since the left endpoint value 15 of interval [15,20] does not satisfy the condition that it is less than the right endpoint value 12 of interval [5,12], interval [5,12] and interval [15,20] do not overlap. Since the maximum value 30 corresponding to the root node comes from the left subtree of the root node, there may be an interval in the left subtree of the root node that overlaps with interval [5,12]. For the interval [10,30] corresponding to the left child node in the interval tree, since the left endpoint value 5 of interval [5,12] is less than the right endpoint value 30 of interval [10,30], and the left endpoint value 10 of interval [10,30] is less than the right endpoint value 12 of interval [5,12], interval [5,12] overlaps with interval [10,30]. In summary, interval [5,12] and... Figure 1 The intervals [10,30] in the interval tree shown in (c) overlap.

[0050] For the interval [40, 50], first determine if the interval [15, 20] corresponding to the root node overlaps with the interval [40, 50]. Since the left endpoint value 40 of the interval [40, 50] does not satisfy the condition that it is less than the right endpoint value 20 of the interval [15, 20], the intervals [40, 50] and [15, 20] do not overlap. Since the maximum value 30 of the left subtree of the root node is less than the left endpoint value 40 of the interval [40, 50], there cannot be an interval overlapping with the interval [40, 50] in the left subtree of the root node. We can continue searching the right subtree of the root node. For the interval [17, 19] corresponding to the right child node in the interval tree, since the left endpoint value 40 of the interval [40, 50] does not satisfy the condition that it is less than the right endpoint value 19 of the interval [17, 19], the intervals [40, 50] and [17, 19] do not overlap. Since the maximum value of 19 in the right subtree of the root node is less than the left endpoint value of 40 in the interval [40, 50], there is no interval in the right subtree of the root node that overlaps with the interval [40, 50]. Therefore, the interval [40, 50] and... Figure 1 In the interval tree shown in (c), no intervals overlap.

[0051] The embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0052] Figure 2 A system architecture diagram is provided for an embodiment of this application. Figure 2In the system architecture shown, the multi-core processor includes S processor cores, and the S processor cores can access the same storage medium. The storage medium may include, but is not limited to, registers, cache, memory, flash memory, and magnetic-disk storage. The magnetic-disk storage may be a hard disk, a disk, etc., which is not limited here.

[0053] Combination Figure 2 The system architecture diagram shown in this application illustrates a method for accessing a storage medium. This method can be implemented by... Figure 2 The first processor core in the multi-core processor shown executes the commands, where the first processor core can be any processor core in the multi-core processor. See also... Figure 3 As shown, the process of this method includes:

[0054] S301, the first processor core determines N first access requests, where N is an integer greater than 0.

[0055] In the embodiments of this application, the first processor core can generate a corresponding access request based on the task to be processed. It should be understood that the first processor core can generate one access request or multiple access requests based on a task to be processed, and this is not limited thereto.

[0056] In the access requests generated by the first processor core, the unexecuted access requests can be considered as the first access requests. The first access request may include a first access range, which is used to request access to a storage area within the first access range of the storage medium.

[0057] It should be understood that the first access range can include a starting address and an ending address; that is, the address range located between the starting address and the ending address is the first access range. The first access range can also include a starting address and an address range length; that is, the address range determined by the starting address and the address range length is the first access range. The first access range can also take other forms, which are not limited here. For ease of description later, the following explanation will use the example of a first access range including a starting address and an ending address.

[0058] It should be understood that the scope of the first access request in different first access requests may be the same or different, and this is not limited here.

[0059] Optionally, the first access request may also include a request identifier, which is used to uniquely identify the first access request.

[0060] Optionally, the first access request may also include a request generation time, which is used to identify the time when the first processor core generates the first access request.

[0061] In this embodiment of the application, after determining N first access requests, the first processor core can record the information of the N first access requests through any one of the following implementation methods A1 or A2, wherein the information of the first access request includes at least the request identifier, the request generation time, and the first access range in the first access request.

[0062] In implementation method A1, the first processor core obtains the request identifier, request generation time, and first access range from each of the N first access requests, and adds the obtained request identifier, request generation time, and first access range to the information record table corresponding to the first processor core.

[0063] In this embodiment, the request identifier, request generation time, and first access range can be added to the information record table in key-value pair format, or in other formats, without limitation. For ease of description later, the following explanation will use the example of adding the request identifier, request generation time, and first access range to the information record table in key-value pair format, where the request identifier is the key, and the request generation time and first access range are both values.

[0064] In the embodiments of this application, the information record table may be stored in a storage medium or in other locations, which is not limited here.

[0065] In this embodiment, each processor core in the multi-core processor generates its own corresponding information record table. The information record table for each processor core can be used to record the request identifier, request generation time, and access scope of access requests generated by each processor core but not executed. The method for other processor cores in the multi-core processor to generate information record tables can refer to the method for the first processor core to generate information record tables, and will not be elaborated here.

[0066] For example, the first processor core identifies three first access requests and adds the information of the three first access requests to the information record table corresponding to the first processor core. The information record table corresponding to the first processor core is shown below:

[0067] <id1,t1,[15,20]>

[0068] <id2,t2,[10,30]>

[0069] <id3,t3,[17,19]>

[0070] In the first access request, the request identifier is id1, the request generation time is t1, and the starting address and ending address are 15 and 20, respectively. In the second access request, the request identifier is id2, the request generation time is t2, and the starting address and ending address are 10 and 30, respectively. In the third access request, the request identifier is id3, the request generation time is t3, and the starting address and ending address are 17 and 19, respectively.

[0071] In implementation method A2, the first processor core obtains a request identifier, a request generation time, and a first access range from each of the N first access requests, and generates a range tree corresponding to the first processor core based on the obtained request identifier, request generation time, and first access range. The range tree corresponding to the first processor core includes N nodes, and each node in the range tree corresponds to one first access request. The value in a node includes the request identifier, request generation time, and first access range of a first access request.

[0072] It should be understood that the process by which the first processor core generates the interval tree corresponding to the first processor core based on the request identifier, the request generation time, and the first access range can refer to the interval tree generation process described above, and will not be repeated here.

[0073] In this embodiment of the application, each processor core in the multi-core processor generates its own interval tree based on its own generated but not executed access requests. An interval tree includes multiple nodes, each node corresponds to one access request, and each access request includes a request identifier, a request generation time, and an access range. An access request is used to request access to a storage area within an access range of the storage medium.

[0074] It should be understood that the method for generating interval trees by other processor cores in a multi-core processor can refer to the method for generating interval trees by the first processor core, and will not be elaborated here.

[0075] For example, the first processor core identifies three first access requests, and the information for the three first access requests is as follows:

[0076] <id1,t1,[15,20]>

[0077] <id2,t2,[10,30]>

[0078] <id3,t3,[17,19]>

[0079] In the first access request, the request identifier is id1, the request generation time is t1, and the starting address and ending address are 15 and 20, respectively. In the second access request, the request identifier is id2, the request generation time is t2, and the starting address and ending address are 10 and 30, respectively. In the third access request, the request identifier is id3, the request generation time is t3, and the starting address and ending address are 17 and 19, respectively.

[0080] The first processor core can generate, based on the information from the above three first access requests, as follows: Figure 4 The interval tree shown. From Figure 4 As shown in the interval tree, the value of the root node in the interval tree is...<id1,t1,[15,20]> The value of the left child node in the interval tree<id2,t2,[10,30]> The value of the right child node in the interval tree<id3,t3,[17,19]> .

[0081] For ease of description later, information on access requests generated but not executed by each processor core is recorded using a range tree.

[0082] S302, the first processor core determines the target access request from N first access requests.

[0083] In this embodiment of the application, the first processor core can be configured as follows: Figure 5 The following steps are shown to determine the target access request.

[0084] S501, the first processor core performs the following steps for each of the N first access requests: the first processor core determines the second access request that one of the N first access requests depends on.

[0085] In the embodiments of this application, for one of the N first access requests, the first access request may depend on multiple second access requests, or it may depend on one second access request, or it may not depend on any second access request.

[0086] In this embodiment, the second access request is an access request generated by any processor core in the multi-core processor and not yet executed. The second access request may include a second access range, which is used to request access to a storage area within the second access range of the storage medium.

[0087] Optionally, the second access request may also include a request identifier, which is used to uniquely identify the second access request.

[0088] Optionally, the second access request may also include a request generation time, which is used to identify the generation time of the second access request.

[0089] In this embodiment of the application, if a first access request depends on a second access request, then the first access request and the second access request it depends on satisfy the following relationship: the second access request was generated earlier than the first access request it depends on, and the second access range corresponding to the second access request overlaps with the first access range corresponding to the first access request it depends on. It should be understood that the overlap between the second access range and the first access range corresponding to the first access request it depends on can be understood as complete overlap, partial overlap, etc., and is not limited here.

[0090] For example, the first access request id1 is generated at time t1, and its corresponding first access range is [left1, right1]. The second access request id2 is generated at time t2, and its corresponding second access range is [left2, right2]. If the request generation time t2 is less than the request generation time t1, and the first and second access ranges satisfy the following relationship: left1 <= right2, and left2 <= right1, then the first access request id1 depends on the second access request id2.

[0091] In this embodiment of the application, for one first access request among N first access requests, it can be achieved through... Figure 6 The steps shown determine the second access request that the first access request depends on.

[0092] S601, the first processor core determines the target node from the nodes in the interval tree corresponding to the multiple processor cores in the multi-core processor.

[0093] In the above S601, taking the first interval tree in the interval tree corresponding to each of the multiple processor cores as an example, the first interval tree can be any interval tree in the interval tree corresponding to each of the multiple processor cores, and can be executed... Figure 7 The following steps, as shown, determine the target node from the first interval tree.

[0094] S701, the first processor core acquires the read lock of the first interval tree.

[0095] In this embodiment of the application, after the first processor core acquires the read lock of the first interval tree, the processor core corresponding to the first interval tree cannot acquire the write lock of the first interval tree, that is, the processor core corresponding to the first interval tree cannot modify the first interval tree. The read lock of the first interval tree can be used to ensure that the first interval tree is not modified when the nodes in the first interval tree are read.

[0096] Furthermore, after the first processor core acquires the read lock of the first interval tree, other processor cores can still acquire the read lock of the first interval tree and traverse the nodes in the first interval tree. This can effectively ensure that each processor core determines the second access request on which its corresponding first access request depends in parallel, thereby ensuring the concurrency capability of the multi-core processor.

[0097] S702, the first processor core determines the target node from the nodes in the first interval tree.

[0098] In this embodiment of the application, the first processor core obtains a node in the first interval tree. If the access range in the access request corresponding to the node overlaps with the first access range in the first access request, and the access request corresponding to the node was generated earlier than the first access request, then the node is the target node.

[0099] It should be understood that the first processor core can determine whether the access request corresponding to the node was generated earlier than the first access request by checking whether the request generation time in the access request corresponding to the node is less than the request generation time in the first access request.

[0100] It should be understood that the process of the first processor core traversing the first interval tree to determine the target node in the above S702 can refer to the interval tree search process described above, and will not be repeated here.

[0101] In S703, after the first processor core finishes traversing the first interval tree, it releases the read lock on the first interval tree.

[0102] In this embodiment of the application, if the read lock of the first interval tree is not acquired by any processor core, the processor core corresponding to the first interval tree can acquire the write lock of the first interval tree and modify the first interval tree.

[0103] pass Figure 7 In the steps described, before traversing the first interval tree to obtain the target node, the first processor core first acquires a read lock on the first interval tree. This effectively prevents the first interval tree from being modified during traversal, thereby ensuring the accuracy of the determined second access request.

[0104] S602, the first processor core determines the access request corresponding to the target node as the second access request that the first access request depends on.

[0105] In this embodiment of the application, the first processor core can use the access request corresponding to the request identifier in the target node as the second access request on which the first access request depends.

[0106] In the above Figure 6In the steps shown, since the time complexity of the interval tree search operation is O(log n), the first processor core can quickly and effectively determine the second access request that a first access request depends on by searching the interval trees corresponding to multiple processor cores.

[0107] S502, the first processor core determines the target access request from the N first access requests based on the second access requests that each of the N first access requests depends on. The target access request is a first access request that does not depend on any of the second access requests.

[0108] exist Figure 5 The steps shown provide a method for identifying a target access request.

[0109] In the embodiments of this application, the target access request can be determined by any of the following implementation methods B1, B2, or B3.

[0110] Implementation method B1 includes, for example: Figure 8 The following steps are shown.

[0111] S801, the first processor core determines the number of dependent requests corresponding to each of the N first access requests based on the number of second access requests that each of the N first access requests depends on.

[0112] In one possible implementation, the first processor core takes the number of second access requests that one of the N first access requests depends on as the number of dependent requests corresponding to that first access request.

[0113] S802, the first processor core will determine the first access request, which depends on the number of requests being zero, as the target access request.

[0114] In the above implementation method B1, the first processor core can quickly determine the target access request from the N first access requests based on the number of dependent requests corresponding to the N first access requests.

[0115] Implementation method B2 includes, for example: Figure 9 The following steps are shown.

[0116] S901, the first processor core performs the following steps for each of the N first access requests: the first processor core determines the access sequence of a first access request based on a second access request that one of the N first access requests depends on. The access sequence can be used to identify the second access request that the first access request depends on.

[0117] In one possible implementation, the access sequence includes M bits, where M is an integer greater than 0. The M bits in the access sequence of a first access request can be used to indicate the dependency relationship between the first access request and the M access requests, which are all access requests generated by the multi-core processor but not yet executed. The M access requests may or may not include the first access request. For ease of implementation of the embodiments in this application, the following explanation will use the example of the M access requests including the first access request.

[0118] In one possible implementation, one bit out of M bits in the access sequence of a first access request corresponds to one of the M access requests. If the bit is a first value, it indicates that the first access request does not depend on the access request corresponding to that bit; if the bit is a second value, it indicates that the first access request depends on the access request corresponding to that bit. The first value can be 1, and the second value can be 0. Alternatively, the first value can be 0, and the second value can be 1. Or, the first and second values ​​can be other values, which are not limited here.

[0119] For example, a multi-core processor includes two processor cores, processor core 1 and processor core 2. The information for two access requests generated but not executed by processor core 1 is as follows:

[0120] <id1,t1,[15,20]>

[0121] <id2,t2,[10,30]>

[0122] In the first access request generated by processor core 1, the request identifier is id1, the request generation time is t1, and the start address and end address are 15 and 20, respectively. In the second access request generated by processor core 1, the request identifier is id2, the request generation time is t2, and the start address and end address are 10 and 30, respectively.

[0123] The information for the two access requests generated but not executed by processor core 2 is as follows:

[0124] <id4,t4,[16,18]>

[0125] <id5,t5,[25,30]>

[0126] In the first access request generated by processor core 2, the request identifier is id4, the request generation time is t4, and the start address and end address are 16 and 18, respectively. In the second access request generated by processor core 2, the request identifier is id5, the request generation time is t5, and the start address and end address are 25 and 30, respectively.

[0127] Set the processor core 1 as the first processor core, and the above two access requests generated by the processor core 1 are both first access requests. Set the request generation times t1, t2, t4, and t5 to satisfy the following relationship: t2 < t1 < t4 < t5. At the same time, set the first value to 1 and the second value to 0.

[0128] For the first access request id1, it can be determined that the second access request on which the first access request id1 depends includes the access request id2. Therefore, the first sequence of the first access request id1 can be "0100". Among them, the "0" corresponding to the first position in "0100" indicates that the first access request id1 does not depend on the access request id1, the "1" corresponding to the second position in "0100" indicates that the first access request id1 depends on the access request id2, the "0" corresponding to the third position in "0100" indicates that the first access request id1 does not depend on the access request id4, and the "0" corresponding to the fourth position in "0100" indicates that the first access request id1 does not depend on the access request id5.

[0129] For the first access request id2, it can be determined that the first access request id2 does not depend on any second access request. Therefore, the first sequence of the first access request id2 can be "0000". Among them, the "0" corresponding to the first position in "0000" indicates that the first access request id2 does not depend on the access request id1, the "0" corresponding to the second position in "0000" indicates that the first access request id2 does not depend on the access request id2, the "0" corresponding to the third position in "0000" indicates that the first access request id2 does not depend on the access request id4, and the "0" corresponding to the fourth position in "0000" indicates that the first access request id2 does not depend on the access request id5.

[0130] S902. The first processor core determines the first access request corresponding to the access sequence that meets the preset conditions as the target access request.

[0131] In the above S902, the first processor core can determine the first access request corresponding to the access sequence with all M bit positions being the first value as the target access request. The preset condition is that all M bit positions are the first value.

[0132] In a possible implementation, for any one of the access sequences corresponding to N first access requests, the following two methods can be used to determine whether all M bit positions in the access sequence are the second value.

[0133] The first possible implementation method is that the first processor core traverses the M bit positions in the access sequence in a loop, respectively obtains the values of the M bit positions, and sequentially determines whether the values of the M bit positions are all the first value.

[0134] In the second possible implementation, when the first value is 0, the first processor core can directly determine whether the access sequence is 0. If the access sequence is 0, it means that all M bits in the access sequence are the first value. This implementation can quickly determine whether all M bits in the access sequence are the first value.

[0135] In the above-described embodiment B2, the first processor core can quickly and accurately determine the target access request from the N first access requests based on the access sequence of each of the N first access requests.

[0136] Implementation method B3 includes, for example: Figure 10 The following steps are shown.

[0137] S1001, for each of the N first access requests, the first processor core performs the following steps: The first processor core determines the processor core sequence of the first access request based on the processor core of the second access request that the first access request depends on. The processor core sequence can be used to identify the processor core of the second access request that the first access request depends on.

[0138] In one possible implementation, the processor core sequence includes multiple bits, each corresponding one-to-one with a processor core in a multi-core processor. One bit in the processor core sequence of a first access request corresponds to one of the processor cores. If this bit is a third value, it indicates that the first access request is an access request that is not generated by the processor core corresponding to this bit and has not been executed; if this bit is a fourth value, it indicates that the first access request is an access request that is generated by the processor core corresponding to this bit and has not been executed. The third value can be 1, and the fourth value can be 0. Alternatively, the third value can be 0, and the fourth value can be 1. Alternatively, the third and fourth values ​​can be other values, which are not limited here.

[0139] For example, a multi-core processor includes two processor cores, processor core 1 and processor core 2. The information for two access requests generated but not executed by processor core 1 is as follows:

[0140] <id1,t1,[15,20]>

[0141] <id2,t2,[10,30]>

[0142] Among them, the request identifier of the first access request generated by processor core 1 is id1, the request generation time is t1, and the start address and end address are 15 and 20 respectively. The request identifier of the second access request generated by processor core 1 is id2, the request generation time is t2, and the start address and end address are 10 and 30 respectively.

[0143] The information of 2 unexecuted access requests generated by processor core 2 is as follows:

[0144] <id4,t4,[16,18]>

[0145] <id5,t5,[25,30]>

[0146] Among them, the request identifier of the first access request generated by processor core 2 is id4, the request generation time is t4, and the start address and end address are 16 and 18 respectively. The request identifier of the second access request generated by processor core 2 is id5, the request generation time is t5, and the start address and end address are 25 and 30 respectively.

[0147] Set processor core 1 as the first processor core, and the above 2 access requests generated by processor core 1 are both first access requests. Set the request generation times t1, t2, t4, and t5 to satisfy the following relationship: t2 < t1 < t4 < t5. At the same time, set the first value to 1 and the second value to 0.

[0148] For the first access request id, it can be determined that the second access request on which the first access request id1 depends includes access request id2. Since access request id2 is generated by processor core 1, the second sequence of the first access request id1 can be "I0". Among them, the "1" corresponding to the first position in "10" indicates that the first access request id1 depends on the access request located in processor core 1, and the "0" corresponding to the second position in "10" indicates that the first access request id1 does not depend on the access request located in processor core 2.

[0149] For the first access request id2, it can be determined that the first access request id2 does not depend on any second access request. Therefore, the second sequence of the first access request id2 can be "00". Among them, the "0" corresponding to the first position in "00" indicates that the first access request id2 does not depend on the access request located in processor core 1, and the "0" corresponding to the second position in "00" indicates that the first access request id2 does not depend on the access request located in processor core 2.

[0150] S1002. The first processor core determines the first access request corresponding to the processor core sequence that meets the reference conditions as the target access request.

[0151] In S1002 above, the first processor core can determine the first access request corresponding to a sequence of processor cores where multiple bits are all of the third value as the target access request. The reference condition is that multiple bits are all of the third value.

[0152] It should be understood that the method by which the first processor core determines whether multiple bits in the processor core sequence are all third values ​​can be referred to the method by which the first processor core determines whether M bits in the access sequence are all first values, and will not be elaborated here.

[0153] In the above-described embodiment B3, the first processor core can quickly and accurately determine the target access request from the N first access requests based on the processor core sequence of each of the N first access requests.

[0154] S303, the first processor core executes the target access request.

[0155] In one possible implementation, the first processor core can access the storage area within the first access range corresponding to the target access request.

[0156] In this embodiment of the application, each processor core in the multi-core processor can be... Figure 3 The steps in the process determine the target access request corresponding to each processor core, and each processor core can execute the target access request determined by each processor core in parallel.

[0157] exist Figure 3 In the method shown, after determining the N first access requests to be executed, each processor core in the multi-core processor selects a first access request that is independent of the second access request from the N first access requests, and each processor core executes the selected first access request in parallel. In this process, multiple processor cores do not need to compete for exclusive locks on the storage medium and can execute their respective selected first access requests in parallel, which improves the concurrency capability of the multi-core processor and thus improves its processing efficiency.

[0158] Based on the above embodiments, this application also provides a storage medium access device, which is used for accessing storage media. Figure 2 The system architecture shown is used to implement Figure 3 The illustrated embodiment provides a method for accessing a storage medium. See also... Figure 11 As shown, the access device for the storage medium includes: a determination module 1101 and an execution module 1102. Wherein:

[0159] The determination module 1101 is used to determine N first access requests, where the first access request is an access request generated by the first processor core but not executed, and the first access request is used to request access to a storage area within the first access range of the storage medium; N is an integer greater than 0;

[0160] The determining module 1101 is further configured to determine a target access request from N first access requests, wherein the target access request is a first access request that does not depend on the second access request; the second access request is an access request generated by any processor core in the multi-core processor and not executed, wherein the second access request is generated earlier than the first access request that it depends on, and the second access range corresponding to the second access request overlaps with the first access range corresponding to the first access request that it depends on.

[0161] Execution module 1102 is used to execute the target access request.

[0162] In one possible implementation, the determining module 1101 is specifically used to: for N first access requests, perform the following steps respectively: determine the second access request that one of the N first access requests depends on; and determine the target access request from the N first access requests based on the second access requests that each of the N first access requests depends on.

[0163] In one possible implementation, each processor core in a multi-core processor maintains a range tree, which includes multiple nodes. Each node corresponds to an access request, and each access request includes an access range. An access request is used to request access to a storage area within an access range of the storage medium. The determining module 1101 is specifically used to: determine a target node from the nodes in the range trees corresponding to the multiple processor cores in the multi-core processor; the access range in the access request corresponding to the target node overlaps with a first access range in a first access request, and the access request corresponding to the target node was generated earlier than the first access request; and determine the access request corresponding to the target node as a second access request that a first access request depends on.

[0164] In one possible implementation, the determining module 1101 is specifically used to: determine the number of dependent requests corresponding to each of the N first access requests based on the number of second access requests that each of the N first access requests depends on; and determine the first access request with a number of dependent requests of zero as the target access request.

[0165] In one possible implementation, the determining module 1101 is specifically used to: for N first access requests, perform the following steps respectively: based on the second access request that one of the N first access requests depends on, determine an access sequence of a first access request, the access sequence being used to identify the second access request that a first access request depends on; and determine the first access request corresponding to the access sequence that satisfies the preset conditions as the target access request.

[0166] In one possible implementation, the access sequence includes M bits, which are used to indicate the dependency between a first access request and M access requests, where M are access requests generated by the multi-core processor but not yet executed, and M is an integer greater than 0.

[0167] In one possible implementation, the determining module 1101 is specifically used to: determine the first access request corresponding to the access sequence in which all M bits have the first value as the target access request, where the first value is used to characterize that the first access request has no dependency relationship with the M access requests.

[0168] In the embodiments of this application, both the determining module and the execution module can be implemented in software or in hardware. For example, the implementation of the determining module will be described below. Similarly, the implementation of the execution module can refer to the implementation of the determining module.

[0169] As an example of a software functional unit, a module can include code running on a compute instance. A compute instance can include at least one of a physical host (compute device), a virtual machine, or a container. Furthermore, the compute instance can be one or more. For example, a module can include code running on multiple hosts / virtual machines / containers. It should be noted that the multiple hosts / virtual machines / containers used to run the code can be distributed within the same region or in different regions. Further, the multiple hosts / virtual machines / containers used to run the code can be distributed within the same availability zone (AZ) or in different AZs, each AZ comprising one or more geographically proximate data centers. Typically, a region can include multiple AZs.

[0170] Similarly, multiple hosts / virtual machines / containers used to run this code can be distributed within the same Virtual Private Cloud (VPC) or across multiple VPCs. Typically, a VPC is set up within a region. Communication between two VPCs within the same region, as well as between VPCs in different regions, requires a communication gateway to be set up within each VPC to enable interconnection between VPCs.

[0171] As an example of a hardware functional unit, a module can include at least one computing device, such as a server. Alternatively, a module can also be a device implemented using an application-specific integrated circuit (ASIC) or a programmable logic device (PLD). The PLD can be implemented using a complex programmable logical device (CPLD), a field-programmable gate array (FPGA), generic array logic (GAL), or any combination thereof.

[0172] The multiple computing devices included in the module can be distributed within the same region or in different regions. Similarly, the multiple computing devices included in the module can be distributed within the same Availability Zone (AZ) or in different AZs. Likewise, the multiple computing devices included in the module can be distributed within the same Virtual Private Cloud (VPC) or multiple VPCs. These multiple computing devices can be any combination of computing devices such as servers, ASICs, PLDs, CPLDs, FPGAs, and GALs.

[0173] It should be noted that, in other embodiments, the determining module determines N first access requests, which are access requests generated by a first processor core but not executed, and are used to request access to a storage area within a first access range of the storage medium; N is an integer greater than 0; a target access request is determined from the N first access requests, which is a first access request that does not depend on a second access request; the second access request is an access request generated by any processor core in the multi-core processor but not executed, which is generated earlier than the first access request it depends on, and the second access range corresponding to the second access request overlaps with the first access range corresponding to the first access request it depends on; the execution module is used to execute the target access request.

[0174] The steps to be implemented by the determination module and the execution module can be specified as needed. By implementing different steps in the storage medium access method through the determination module and the execution module, the full functionality of the storage medium access device can be achieved.

[0175] In one possible implementation, Figure 12 The storage medium access device shown can be deployed in Figure 2 In each processor core of the multi-core processor shown in the system architecture, the processor core may include the following functional modules: an information maintenance module 1201, a dependency determination module 1202, and an access request management module 1203. The information maintenance module 1201 can communicate with the dependency determination module 1202, and the dependency determination module 1202 can communicate with the access request management module 1203. Furthermore, the dependency determination module 1202 in the first processor core can also communicate with the information maintenance modules in other processor cores.

[0176] The following is a detailed explanation of the function of each module in the first processor core, as detailed below:

[0177] The information maintenance module 1201, after determining N first access requests, obtains a request identifier, request generation time, and first access range from each of the N first access requests, and adds the obtained request identifier, request generation time, and first access range to the information record table corresponding to the first processor core. Alternatively, the information maintenance module 1201, after determining N first access requests, obtains a request identifier, request generation time, and first access range from each of the N first access requests, and generates an interval tree corresponding to the first processor core based on the obtained request identifier, request generation time, and first access range.

[0178] The dependency determination module 1202 is used to determine the second access requests that each of the N first access requests depends on. Specifically, for one of the N first access requests, the dependency determination module 1202 can access the interval tree generated by the information maintenance module 1201 in multiple processor cores, and determine the target node from the nodes in the interval trees corresponding to the multiple processor cores, and determine the access request corresponding to the target node as the second access request that the first access request depends on.

[0179] The access request management module 1203 is used to determine the target access request from N first access requests. The target access request is a first access request that does not depend on any second access requests. Specifically, the access request management module 1203 can access the second access requests that the N first access requests depend on, as determined by the dependency determination module 1202, and determine the target access request from the N first access requests based on these second access requests.

[0180] The access request management module 1203 is also used to execute target access requests.

[0181] This application also provides a computing device, which includes a multi-core processor and a memory, wherein the memory stores computer-executable instructions; the multi-core processor is used to execute the computer-executable instructions stored in the memory, and the multi-core processor can execute methods for accessing the storage medium.

[0182] This application also provides a computer program product containing instructions. The computer program product may be a software or program product containing instructions capable of running on a multi-core processor or stored on any available medium. When the computer program product runs on at least one multi-core processor, it causes the at least one multi-core processor to execute a storage medium access method.

[0183] This application also provides a storage medium. The storage medium can be any available medium capable of being stored by a multi-core processor, or a data storage device such as a data center containing one or more available media. The storage medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid-state drive). The storage medium includes instructions that instruct the multi-core processor to execute a storage medium access method.

[0184] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the protection scope of the technical solutions of the embodiments of the present invention.

[0185] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0186] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to this application. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0187] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0188] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0189] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. An access method for a storage medium, characterized by, A first processor core applied to a multi-core processor, the method comprises: determining N first access requests, the first access requests being access requests generated by the first processor core and not executed, the first access requests being used to request access to a storage area in a first access range of the storage medium; N being an integer greater than 0; determining a target access request from the N first access requests, the target access request being a first access request not dependent on a second access request; the second access request being an access request generated by any processor core in the multi-core processor and not executed, the second access request being generated earlier than a dependent first access request, and a second access range corresponding to the second access request overlapping a first access range corresponding to the dependent first access request; executing the target access request.

2. The method of claim 1, wherein, The determining of the target access request from the N first access requests comprises: for the N first access requests, the following steps are respectively performed: determining a second access request dependent on one first access request in the N first access requests; determining the target access request from the N first access requests according to the second access requests respectively dependent on the N first access requests.

3. The method of claim 2, wherein, A processor core in the multi-core processor maintains an interval tree, an interval tree comprising a plurality of nodes, one node corresponding to one access request, the one access request comprising an access range, the one access request being used to request access to a storage area in the access range of the storage medium; The determining of the second access request dependent on one first access request in the N first access requests comprises: determining a target node from nodes in interval trees respectively corresponding to a plurality of processor cores in the multi-core processor; the access range in an access request corresponding to the target node overlapping a first access range in the one first access request, and the access request corresponding to the target node being generated earlier than the one first access request; determining the access request corresponding to the target node as the second access request dependent on the one first access request.

4. The method of any one of claims 2-3, wherein, The determining of the target access request from the N first access requests according to the second access requests respectively dependent on the N first access requests comprises: determining a dependent request quantity respectively corresponding to the N first access requests according to a quantity of the second access requests respectively dependent on the N first access requests; determining a first access request with a dependent request quantity of zero as the target access request.

5. The method of any one of claims 2-3, wherein, The determining of the target access request from the N first access requests according to the second access requests respectively dependent on the N first access requests comprises: for the N first access requests, the following steps are respectively performed: determining an access sequence of one first access request in the N first access requests according to a second access request dependent on the one first access request, the access sequence being used to identify the second access request dependent on the one first access request; determining a first access request corresponding to an access sequence satisfying a preset condition as the target access request.

6. The method of claim 5, wherein, The access sequence includes M bits, the M bits are used to indicate a dependency relationship between the one first access request and M access requests, the M access requests are access requests generated by the multi-core processor and not executed, and M is an integer greater than 0.

7. The method of claim 6, wherein, The first access request corresponding to the access sequence satisfying the preset condition is determined as the target access request, including: The first access request corresponding to the access sequence with the M bits being first values is determined as the target access request, the first values are used to represent that the first access request has no dependency relationship with the M access requests.

8. An access device for a storage medium, characterized in that Including: A determination module is configured to determine N first access requests, the N first access requests are access requests generated by the first processor core and not executed, and the first access request is used to request to access a storage area in a first access range of the storage medium; N is an integer greater than 0; The determination module is further configured to determine a target access request from the N first access requests, the target access request is a first access request not dependent on a second access request; the second access request is an access request generated by any processor core in the multi-core processor and not executed, the second access request is generated earlier than a dependent first access request, and a second access range corresponding to the second access request overlaps with a first access range corresponding to the dependent first access request; An execution module is configured to execute the target access request.

9. A computing device, comprising: A computing device includes a multi-core processor and a memory; the memory stores computer executable instructions; the multi-core processor is used to execute the computer executable instructions stored in the memory, so that the computing device executes the method in any one of claims 1-7.

10. A storage medium, characterized by Computer program instructions are included, when the computer program instructions are executed by a multi-core processor, the multi-core processor executes the method in any one of claims 1-7.

11. A computer program product comprising instructions, characterized in that, When the instructions are run by a multi-core processor, the multi-core processor executes the method in any one of claims 1-7.

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