Low-power-consumption write assist circuit and static random access memory

Abstract

The invention provides a low-power-consumption write auxiliary circuit and a static random access memory. The low-power-consumption write auxiliary circuit comprises a write driving circuit, a write auxiliary module and a memory unit. And the writing auxiliary module is responsible for coupling a 0-writing signal to a negative voltage level in a writing period and ensuring that a 1-writing signal is not influenced, so that the voltage difference of the processed bit line is increased, the writing capability of the memory unit is enhanced, the charging and discharging times of a coupling signal line are reduced, and the reliability of the memory unit is improved. Therefore, the power consumption caused by charging and discharging of the coupling signal line is reduced. According to the embodiment of the invention, the write auxiliary module does not pull down a signal for writing 1, and does not need to pull up again subsequently (namely, the bit line voltage clamping circuit is not turned on, or the bit line voltage clamping circuit is not arranged), so that the power consumption is reduced, and the overall energy efficiency of the memory is improved.

Description

Technical Field

[0001] The present application relates to the field of memory technology, and in particular to a low-power write assist circuit and a static random access memory. Background Art

[0002] As semiconductor transistor process geometries continue to shrink, the proportion of SRAM memory arrays in system-on-chip (SOC) and multi-core CPU chips has increased significantly. To reduce chip area, the size of the basic memory unit (bitcell) has been continuously compressed. At the same time, the supply voltage has also been reduced with process advancements to reduce power consumption. However, this trend brings a serious challenge: the ability to write data to the bitcell is reduced, which may lead to a decline in chip yield and even system failure.

[0003] To address the insufficient write performance of SRAM, especially HD bitcells, SRAM IP often integrates a write assist (WA) module. This module effectively improves the write performance of the bitcell by increasing the voltage difference between the bitline and the complementary bitline (bitline bar), enabling stable operation at lower voltages. The write assist module is particularly critical in high-density static memories and advanced process technologies.

[0004] However, the introduction of write assist circuitry significantly increases the dynamic power consumption of SRAM due to the need to charge and discharge a large capacitor. The power consumption difference between enabling WA and disabling WA can reach approximately 30%. Therefore, reducing the additional power consumption after enabling WA has become a pressing technical challenge.

[0005] In the existing write-assist negative voltage generation circuit, the principle of capacitive coupling between large metal wires is utilized to arrange coupled signal lines on both sides of the write data signal line. For example, when writing data 0, the first signal line is stable at a low level, the second signal line is stable at a high level, and the coupled signal line is triggered to generate a falling edge signal. Due to the charge coupling effect between adjacent metal wires, the first signal line and the second signal line will be coupled by a certain proportion (for example, 20%). The low-level signal forms a negative voltage after coupling, and although the high-level signal is also coupled and pulled down, it is then pulled up again by the bit line voltage clamping circuit. The problem is that the existing write-assist circuit exerts a downward coupling effect on the write data signal line (WDC / WDT), causing the high-level signal to be pulled down unnecessarily, and due to the large capacitance of the coupled signal line, the power consumption loss of charging and discharging it is large. At the same time, the subsequent pull-up operation of the bit line voltage clamping circuit also increases unnecessary power consumption. Summary of the Invention

[0006] The purpose of the embodiments of the present application is to provide a low-power write assist circuit and a static random access memory, so as to solve the problem that the existing write assist negative voltage generating circuit couples both the first signal line and the second signal line, resulting in power waste.

[0007] An embodiment of the present application provides a low-power write assist circuit, comprising: a write driver circuit, a write assist module, and a memory unit;

[0008] The write driver circuit and the write assist module are connected via complementary signal lines, the complementary signal lines including a first signal line and a second signal line, the first signal line is used to transmit a signal WDC, and the second signal line is used to transmit a signal WDT; the write assist module is also connected to the memory unit;

[0009] The write driver circuit is used to obtain a signal WDC and a signal WDT according to the data signal, and transmit the signal WDC and the signal WDT to the write assist module;

[0010] The write assist module is used to control the write 0 signal in the control signal WDC and the signal WDT to be coupled to the negative voltage during the write cycle, and the write 1 signal in the control signal WDC and the signal WDT is not affected during the write cycle; the processed signal WDC and the signal WDT are transmitted to the memory unit.

[0011] In the above technical solution, the write assist module is responsible for coupling the write-0 signal to a negative voltage level during the write cycle, while ensuring that the write-1 signal remains unaffected. This process increases the bit line voltage difference, enhances the write capability of the memory cell, and reduces the number of charge and discharge cycles on the coupled signal line, thereby reducing the power consumption caused by the charge and discharge of the coupled signal line. The write assist module of this embodiment does not pull down the write-1 signal, and there is no need to pull it up again later (i.e., the bit line voltage clamp circuit is not activated, or the bit line voltage clamp circuit is not provided), thereby reducing power consumption and improving the overall energy efficiency of the memory.

[0012] This solution is suitable for high-density SRAM (HD bitcell) and advanced process nodes (such as below 7nm), and has significant advantages in power-sensitive scenarios such as mobile devices and AI chips.

[0013] In some optional implementations, the write driver circuit includes: a trigger module and a write signal generating module;

[0014] The trigger module is used to obtain a trigger output signal WDCX and an inverted signal WDTX of the trigger output signal according to the data signal and the write clock signal;

[0015] The write signal generating module is used to obtain the signal WDT and the signal WDC according to the signal WDCX, the signal WDTX and the first enable signal NegB1.

[0016] In the above technical solution, the trigger module generates complementary signals WDCX and WDTX based on the data signal (Din) and the write clock (WCLK). The write signal generation module generates signals WDT and WDC in conjunction with the enable signal (NegBl). The enable signal NegBl controls the 0-level ends of signals WDT and WDC to float. For example, when writing data 0, signal WDC is floated, allowing subsequent coupling to a negative voltage; when writing data 1, signal WDT is floated, allowing subsequent coupling to a negative voltage.

[0017] In some optional embodiments, the write assist module includes: a first metal line and a second metal line placed on both sides of the first signal line, and a third metal line and a fourth metal line placed on both sides of the second signal line;

[0018] The first metal line and the first signal line are capacitively coupled, the second metal line and the first signal line are capacitively coupled, the third metal line and the second signal line are capacitively coupled, and the fourth metal line and the second signal line are capacitively coupled.

[0019] In some optional implementations, the write assist module further includes: a third NOR logic gate and a fourth NOR logic gate;

[0020] A first input terminal of the third NOR logic gate inputs a signal WDCX, a second input terminal of the third NOR logic gate inputs a signal Negcap0, an output terminal of the third NOR logic gate is connected to a first metal line after passing through an inverter, and an output terminal of the third NOR logic gate is connected to a second metal line after passing through an inverter;

[0021] The first input terminal of the fourth NOR logic gate inputs the signal WDTX, the second input terminal of the fourth NOR logic gate inputs the signal Negcap1, the output terminal of the fourth NOR logic gate is connected to the third metal line after passing through an inverter, and the output terminal of the fourth NOR logic gate is also connected to the fourth metal line after passing through an inverter.

[0022] In the above technical solution, transient voltage changes are generated between metal lines and signal lines through capacitive coupling. The first signal line is flanked by first and second metal lines. Capacitive coupling is used to couple the write-0 signal to a negative voltage during a write cycle, preventing it from affecting the write-1 signal. The second signal line is flanked by third and fourth metal lines. Capacitive coupling is used to couple the write-0 signal to a negative voltage during a write cycle, preventing it from affecting the write-1 signal.

[0023] The third NOR logic gate's inputs are WDCX and Negcap0, and its output controls the first and second metal lines. The fourth NOR logic gate's inputs are WDTX and Negcap1, and its output controls the third and fourth metal lines. The Negcap0 / Negcap1 signals selectively activate the coupling effect, ensuring that only write-0 signals are coupled to the negative voltage.

[0024] When the written data is 0, the write driver circuit outputs WDC as a low level and WDT as a high level:

[0025] WDCX is at a low level, Negcap0 changes from a high level to a low level, triggering the output of the third NOR logic gate to change from a low level to a high level. After passing through the inverter, the first and second metal lines are driven from a high level to a low level. The low-level first and second metal lines couple the WDC of write 0 to a negative voltage through capacitive coupling.

[0026] WDTX is high, Negcap1 changes from high to low, the output of the fourth NOR logic gate remains low, and after passing through the inverter, the third and fourth metal lines are driven to remain high, so that the WDT of writing 1 is not affected.

[0027] Therefore, when writing data 0, the WDC for writing 0 is coupled to the negative voltage, and the WDT for writing 1 is not affected, thereby enhancing the write capability of the memory cell and reducing the number of charge and discharge times of the high-level signal line. Moreover, since the WDT for writing 1 is not affected in the write auxiliary module, there is no need to pull it up again through the bit line clamping circuit subsequently.

[0028] When the write data is 1, the write driver circuit outputs WDC as high level and WDT as low level:

[0029] WDCX is at a high level, Negcap0 changes from a high level to a low level, the output of the third NOR logic gate remains at a low level, and after passing through the inverter, the first and second metal lines are driven to remain at a high level, so that the WDC of write 1 is not affected.

[0030] WDTX is at a low level, Negcap1 changes from a high level to a low level, triggering the output of the fourth NOR logic gate to change from a low level to a high level, and after passing through the inverter, driving the third and fourth metal lines from a high level to a low level. The low-level third and fourth metal lines couple the WDT that writes 0 to a negative voltage through capacitive coupling.

[0031] Therefore, when writing data 1, the WDT for writing 0 is coupled to the negative voltage, and the WDC for writing 1 is not affected, thereby enhancing the write capability of the memory cell and reducing the number of charge and discharge times of the high-level signal line. Moreover, since the WDC for writing 1 is not affected in the write auxiliary module, there is no need to pull it up again through the bit line clamping circuit subsequently.

[0032] In this embodiment, the metal capacitance coupling effect on both sides is applied to WDC / WDT to obtain a larger negative voltage, thereby obtaining a stronger write assist capability.

[0033] In some optional implementations, the writing assistant module includes:

[0034] A fifth metal line is placed on one side of the first signal line, and a sixth metal line is placed on one side of the second signal line.

[0035] In some optional implementations, the write assist module further includes: a fifth NOR logic gate and a sixth NOR logic gate;

[0036] A first input terminal of the fifth NOR logic gate inputs a signal WDCX, a second input terminal of the fifth NOR logic gate inputs a signal Negcap0, and an output terminal of the fifth NOR logic gate is connected to a fifth metal line after passing through an inverter;

[0037] A first input terminal of the sixth NOR logic gate inputs a signal WDTX, a second input terminal of the sixth NOR logic gate inputs a signal Negcap1, and an output terminal of the sixth NOR logic gate is connected to a sixth metal line after passing through an inverter.

[0038] In the above technical solution, transient voltage changes are generated between the metal line and the signal line through capacitive coupling. A fifth metal line is arranged on one side of the first signal line. This capacitive coupling couples the write-0 signal to a negative voltage during a write cycle, while preventing it from affecting the write-1 signal. A sixth metal line is arranged on one side of the second signal line. This capacitive coupling couples the write-0 signal to a negative voltage during a write cycle, while preventing it from affecting the write-1 signal.

[0039] The fifth NOR logic gate's inputs are WDCX and Negcap0, and its output controls the fifth metal line. The sixth NOR logic gate's inputs are WDTX and Negcap1, and its output controls the sixth metal line. The Negcap0 / Negcap1 signals selectively activate the coupling effect, ensuring that only write-0 signals couple to the negative voltage.

[0040] When the write data is 0, the write driver circuit outputs WDC as a low level and WDT as a high level:

[0041] WDCX is at a low level, Negcap0 changes from a high level to a low level, triggering the output of the fifth NOR logic gate to change from a low level to a high level, and after passing through the inverter, drives the fifth metal line from a high level to a low level. The low-level fifth metal line couples the WDC of write 0 to a negative voltage through capacitive coupling.

[0042] WDTX is high, Negcap1 changes from high to low, the output of the sixth NOR logic gate remains low, and after passing through the inverter, the sixth metal line is driven to remain high, so that the WDT of writing 1 is not affected.

[0043] Therefore, when writing data 0, the WDC for writing 0 is coupled to the negative voltage, and the WDT for writing 1 is not affected, thereby enhancing the write capability of the memory cell and reducing the number of charge and discharge times of the high-level signal line. Moreover, since the WDT for writing 1 is not affected in the write auxiliary module, there is no need to pull it up again through the bit line clamping circuit subsequently.

[0044] When the write data is 1, the write driver circuit outputs WDC as high level and WDT as low level:

[0045] WDCX is at a high level, Negcap0 changes from a high level to a low level, the output of the fifth NOR logic gate remains at a low level, and after passing through the inverter, the fifth metal line is driven to remain at a high level, so that the WDC of write 1 is not affected.

[0046] WDTX is at a low level, Negcap1 changes from a high level to a low level, triggering the output of the sixth NOR logic gate to change from a low level to a high level, and after passing through the inverter, drives the sixth metal line from a high level to a low level. The low-level sixth metal line couples the WDT that writes 0 to a negative voltage through capacitive coupling.

[0047] Therefore, when writing data 1, the WDT for writing 0 is coupled to the negative voltage, and the WDC for writing 1 is not affected, thereby enhancing the write capability of the memory cell and reducing the number of charge and discharge times of the high-level signal line. Moreover, since the WDC for writing 1 is not affected in the write auxiliary module, there is no need to pull it up again through the bit line clamping circuit subsequently.

[0048] This embodiment applies the effect of unilateral metal capacitor coupling on WDC / WDT, thereby obtaining a negative voltage and saving the area occupied by the metal capacitor.

[0049] In some optional implementations, the trigger module includes: a trigger, a first inverter, a second inverter, and a fourth inverter;

[0050] The D terminal of the trigger inputs the data signal, the Clk terminal of the trigger inputs the write clock signal, and the Q terminal of the trigger outputs the signal WDCX after passing through the first inverter and the second inverter;

[0051] The Q end of the trigger also outputs a signal WDTX after passing through the fourth inverter.

[0052] In some optional implementations, the write signal generating module includes: a first NOR logic gate, a second NOR logic gate, a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third PMOS transistor, a fourth PMOS transistor, and a third inverter;

[0053] An input terminal of the third inverter inputs a signal NegBl, and an output terminal of the third inverter outputs a signal NegBlEn;

[0054] A first input terminal of the first NOR logic gate receives an input signal WDCX, a second input terminal of the first NOR logic gate receives an input signal NegBlEn, an output terminal of the first NOR logic gate is connected to the gate of the first PMOS transistor, and the output of the first NOR logic gate is also connected to the gate of the first NMOS transistor; a source of the first PMOS transistor is connected to a power supply VDD, a drain of the first PMOS transistor is connected to the source of the second PMOS transistor, a drain of the second PMOS transistor is connected to the drain of the first NMOS transistor, and a source of the first NMOS transistor is grounded;

[0055] A first input terminal of the second NOR logic gate is input with a signal WDTX, a second input terminal of the second NOR logic gate is input with a signal NegBlEn, an output terminal of the second NOR logic gate is connected to the gate of the second PMOS transistor, and the output of the second NOR logic gate is also connected to the gate of the second NMOS transistor; a source of the second PMOS transistor is connected to a power supply VDD, a drain of the second PMOS transistor is connected to the source of the fourth PMOS transistor, the drain of the fourth PMOS transistor is connected to the drain of the second NMOS transistor, and the source of the second NMOS transistor is grounded;

[0056] The gate of the third PMOS transistor is connected to the drain of the fourth PMOS transistor, the gate of the fourth PMOS transistor is connected to the drain of the third PMOS transistor, the drain of the third PMOS transistor outputs a signal WDT, and the drain of the fourth PMOS transistor outputs a signal WDC.

[0057] In the above technical solution, the enable signal NegBl controls the low-level end of WDC / WDT to float, specifically including:

[0058] When writing data 0, WDCX is low, WDTX is high, and NegBl (high) is converted to a low level by the inverter. The first NOR logic gate receives two low inputs, and its output wdcin is high. The second NOR logic gate receives one high and one low input, and its output wdtin is low. This controls the first PMOS transistor to be turned off, the first NMOS transistor to be turned on, the second PMOS transistor to be turned on, and the second NMOS transistor to be turned off. At this point, WDC is low, and WDT is high. The enable signal NegBl changes from high to low, and NegBlEn changes to high. The outputs of the first and second NOR logic gates are both low, turning on the first and second PMOS transistors and turning off the first and second NMOS transistors. At this point, the outputs WDC and WDT maintain their previous levels. The WDC for writing 0 is left floating, allowing the write assist module to subsequently couple the WDC for writing 0 to a negative voltage.

[0059] When writing data 1, WDCX is high, WDTX is low, and NegBl (high) is converted to a low level by the inverter. The inputs of the first NOR logic gate are a low level and a high level, and the output wdcin of the first NOR logic gate is low. The inputs of the second NOR logic gate are two low levels, and the output wdtin of the second NOR logic gate is high. This turns on the first PMOS transistor, turns off the first NMOS transistor, turns off the second PMOS transistor, and turns on the second NMOS transistor. At this time, WDC is high and WDT is low. The enable signal NegBl changes from high to low, and NegBlEn changes to high. The outputs of the first and second NOR logic gates are both low, turning on the first and second PMOS transistors and turning off the first and second NMOS transistors. At this time, the outputs WDC and WDT maintain the same levels as at the previous moment. The WDT for writing 0 is floated to facilitate coupling of the WDT for writing 0 to a negative voltage in the write assist module.

[0060] In some alternative embodiments, the memory cells are connected to bit lines, word lines, and power supply lines.

[0061] In some optional implementations, the method further includes: a bit line voltage clamping circuit; the bit line voltage clamping circuit is connected between the read / write signal line and the memory cell.

[0062] An embodiment of the present application provides a static random access memory, comprising a low-power write assist circuit as described in any one of the above items. BRIEF DESCRIPTION OF THE DRAWINGS

[0063] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments of the present application. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without creative work.

[0064] Figure 1 A functional module diagram of a low-power write assist circuit provided in an embodiment of the present application;

[0065] Figure 2 A schematic diagram of the circuit structure of a write assist module provided in an embodiment of the present application;

[0066] Figure 3 This is a signal waveform diagram when writing data 0 according to an embodiment of the present application;

[0067] Figure 4 A schematic diagram of the circuit structure of a write assist module provided in another embodiment of the present application;

[0068] Figure 5 A schematic diagram of the write driver circuit structure provided in an embodiment of the present application;

[0069] Figure 6 This is a schematic diagram of the memory cell and bit line voltage clamping circuit structure provided in an embodiment of the present application. DETAILED DESCRIPTION

[0070] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application.

[0071] Please refer to Figure 1 , Figure 1 A functional module diagram of a low-power write assist circuit provided in an embodiment of the present application includes: a write drive circuit, a write assist module and a memory unit.

[0072] Among them, the write drive circuit and the write assist module are connected through complementary signal lines, and the complementary signal lines include a first signal line and a second signal line, the first signal line is used to transmit signal WDC, and the second signal line is used to transmit signal WDT; the write assist module is also connected to the memory unit; the write drive circuit is used to obtain signal WDC and signal WDT according to the data signal, and transmit signal WDC and signal WDT to the write assist module; the write assist module is used to control the signal of writing 0 in signal WDC and signal WDT to be coupled to the negative voltage during the write cycle, and the signal of writing 1 in control signal WDC and signal WDT is not affected during the write cycle; the processed signal WDC and signal WDT are transmitted to the memory unit.

[0073] Among them, the signal WDC and the signal WDT are complementary signals; when data 0 is written to the memory cell, the signal WDC is low and the signal WDT is high; when data 1 is written to the memory cell, the signal WDC is high and the signal WDT is low.

[0074] In the above technical solution, the write assist module is responsible for coupling the write-0 signal to a negative voltage level during the write cycle, while ensuring that the write-1 signal remains unaffected. This process increases the bit line voltage difference, enhances the write capability of the memory cell, and reduces the number of charge and discharge cycles on the coupled signal line, thereby reducing the power consumption caused by the charge and discharge of the coupled signal line. The write assist module of this embodiment does not pull down the write-1 signal, and there is no need to pull it up again later (i.e., the bit line voltage clamp circuit is not activated, or the bit line voltage clamp circuit is not provided), thereby reducing power consumption and improving the overall energy efficiency of the memory.

[0075] This solution is suitable for high-density SRAM (HD bitcell) and advanced process nodes (such as below 7nm), and has significant advantages in power-sensitive scenarios such as mobile devices and AI chips.

[0076] In some optional implementations, the write driver circuit includes: a trigger module and a write signal generating module.

[0077] The trigger module is configured to generate a trigger output signal WDCX and an inverted signal WDTX of the trigger output signal according to the data signal and the write clock signal. The write signal generation module is configured to generate a signal WDT and a signal WDC according to the signal WDCX, the signal WDTX, and the first enable signal NegB1.

[0078] In the above technical solution, the trigger module generates complementary signals WDCX and WDTX based on the data signal (Din) and the write clock (WCLK). The write signal generation module generates signals WDT and WDC in conjunction with the enable signal (NegBl). The enable signal NegBl controls the 0-level ends of signals WDT and WDC to float. For example, when writing data 0, signal WDC is floated, allowing subsequent coupling to a negative voltage; when writing data 1, signal WDT is floated, allowing subsequent coupling to a negative voltage.

[0079] Please refer to Figure 2 , Figure 2 A schematic diagram of the circuit structure of a write assist module provided in one embodiment of the present application. It should be noted that in the diagrams of one or more embodiments of the present application, the capacitance between the signal line and the metal line is a representation of capacitive coupling between the metal line and the signal line, and does not indicate the presence of an additional capacitor between the signal line and the metal line.

[0080] The write assist module of this embodiment includes: a first metal line and a second metal line placed on both sides of a first signal line, and a third metal line and a fourth metal line placed on both sides of the second signal line; capacitive coupling between the first metal line and the first signal line, capacitive coupling between the second metal line and the first signal line, capacitive coupling between the third metal line and the second signal line, and capacitive coupling between the fourth metal line and the second signal line.

[0081] The write assist module further includes a third NOR logic gate N3 and a fourth NOR logic gate N4. A first input terminal of the third NOR logic gate N3 receives a signal WDCX, a second input terminal receives a signal Negcap0, an output terminal of the third NOR logic gate N3 is connected to a first metal line via an inverter, and an output terminal of the third NOR logic gate N3 is further connected to a second metal line via an inverter. A first input terminal of the fourth NOR logic gate N4 receives a signal WDTX, a second input terminal receives a signal Negcap1, an output terminal of the fourth NOR logic gate N4 is connected to a third metal line via an inverter, and an output terminal of the fourth NOR logic gate N4 is further connected to a fourth metal line via an inverter.

[0082] In the above technical solution, transient voltage changes are generated between metal lines and signal lines through capacitive coupling. The first signal line (for transmitting signal WDC) is flanked by a first metal line (for transmitting signal Metalcap0) and a second metal line (for transmitting signal Metalcap1). Capacitive coupling is used to couple the Write 0 signal to a negative voltage during a write cycle, while preventing any impact on the Write 1 signal during the write cycle. The second signal line (for transmitting signal WDT) is flanked by a third metal line (for transmitting signal Metalcap2) and a fourth metal line (for transmitting signal Metalcap3). Capacitive coupling is used to couple the Write 0 signal to a negative voltage during a write cycle, while preventing any impact on the Write 1 signal during the write cycle.

[0083] The inputs to the third NOR logic gate N3 are WDCX and Negcap0, and the output of the third NOR logic gate N3 controls the first and second metal lines. The inputs to the fourth NOR logic gate N4 are WDTX and Negcap1, and the output of the fourth NOR logic gate N4 controls the third and fourth metal lines. The coupling effect is selectively activated by the Negcap0 / Negcap1 signals, ensuring that only the write-0 signal is coupled to the negative voltage.

[0084] Please refer to Figure 3 , Figure 3 This is a signal waveform diagram when writing data 0 provided in an embodiment of the present application. When the written data is 0, the write driver circuit outputs WDC as a low level and WDT as a high level:

[0085] WDCX is at a low level, Negcap0 changes from a high level to a low level, triggering the output of the third NOR logic gate N3 to change from a low level to a high level, and after passing through the inverter, driving the first metal line and the second metal line from a high level to a low level. The low-level first metal line and the second metal line couple the WDC of write 0 to a negative voltage through capacitive coupling.

[0086] WDTX is high, Negcap1 changes from high to low, the output of the fourth NOR logic gate N4 remains low, and after passing through the inverter, the third metal line and the fourth metal line are driven to remain high, so that the WDT of write 1 is not affected.

[0087] Therefore, when writing data 0, the WDC for writing 0 is coupled to the negative voltage, and the WDT for writing 1 is not affected, thereby enhancing the write capability of the memory cell and reducing the number of charge and discharge times of the high-level signal line. Moreover, since the WDT for writing 1 is not affected in the write auxiliary module, there is no need to pull it up again through the bit line clamping circuit subsequently.

[0088] Similarly, when the write data is 1, the write driver circuit outputs WDC as a high level and WDT as a low level:

[0089] WDCX is at a high level, Negcap0 changes from a high level to a low level, the output of the third NOR logic gate N3 remains at a low level, and after passing through the inverter, the first and second metal lines are driven to remain at a high level, so that the WDC of write 1 is not affected.

[0090] WDTX is at a low level, Negcap1 changes from a high level to a low level, triggering the output of the fourth NOR logic gate N4 to change from a low level to a high level, and after passing through the inverter, driving the third and fourth metal lines from a high level to a low level. The low-level third and fourth metal lines couple the WDT writing 0 to a negative voltage through capacitive coupling.

[0091] Therefore, when writing data 1, the WDT for writing 0 is coupled to the negative voltage, and the WDC for writing 1 is not affected, thereby enhancing the write capability of the memory cell and reducing the number of charge and discharge times of the high-level signal line. Moreover, since the WDC for writing 1 is not affected in the write auxiliary module, there is no need to pull it up again through the bit line clamping circuit subsequently.

[0092] In this embodiment, the metal capacitance coupling effect on both sides is applied to WDC / WDT to obtain a larger negative voltage, thereby obtaining a stronger write assist capability.

[0093] Please refer to Figure 4 , Figure 4 A schematic diagram of the circuit structure of a write assist module provided in another embodiment of the present application.

[0094] The write assist module of this embodiment includes: a fifth metal line (for transmitting signal Metalcap0) placed on one side of the first signal line (for transmitting signal WDC), and a sixth metal line (for transmitting signal Metalcap1) placed on one side of the second signal line (for transmitting signal WDT).

[0095] The write assist module of this embodiment further includes a fifth NOR logic gate N5 and a sixth NOR logic gate N6.

[0096] Among them, the first input terminal of the fifth NOR logic gate N5 inputs the signal WDCX, the second input terminal of the fifth NOR logic gate N5 inputs the signal Negcap0, and the output terminal of the fifth NOR logic gate N5 is connected to the fifth metal line after passing through an inverter; the first input terminal of the sixth NOR logic gate N6 inputs the signal WDTX, the second input terminal of the sixth NOR logic gate N6 inputs the signal Negcap1, and the output terminal of the sixth NOR logic gate N6 is connected to the sixth metal line after passing through an inverter.

[0097] In the above technical solution, transient voltage changes are generated between the metal line and the signal line through capacitive coupling. A fifth metal line is arranged on one side of the first signal line. This capacitive coupling couples the write-0 signal to a negative voltage during a write cycle, while preventing it from affecting the write-1 signal. A sixth metal line is arranged on one side of the second signal line. This capacitive coupling couples the write-0 signal to a negative voltage during a write cycle, while preventing it from affecting the write-1 signal.

[0098] The inputs of the fifth NOR logic gate N5 are WDCX and Negcap0, and the output of the fifth NOR logic gate N5 controls the fifth metal line. The inputs of the sixth NOR logic gate N6 are WDTX and Negcap1, and the output of the sixth NOR logic gate N6 controls the sixth metal line. The coupling effect is selectively activated by the Negcap0 / Negcap1 signals, ensuring that only the write-0 signal is coupled to the negative voltage.

[0099] When the write data is 0, the write driver circuit outputs WDC as a low level and WDT as a high level:

[0100] WDCX is at a low level, Negcap0 changes from a high level to a low level, triggering the output of the fifth NOR logic gate N5 to change from a low level to a high level, and after passing through the inverter, drives the fifth metal line from a high level to a low level. The low-level fifth metal line couples the write-0 WDC to a negative voltage through capacitive coupling.

[0101] WDTX is high, Negcap1 changes from high to low, the output of the sixth NOR logic gate N6 remains low, and after passing through the inverter, the sixth metal line is driven to remain high, so that the WDT of writing 1 is not affected.

[0102] Therefore, when writing data 0, the WDC for writing 0 is coupled to the negative voltage, and the WDT for writing 1 is not affected, thereby enhancing the write capability of the memory cell and reducing the number of charge and discharge times of the high-level signal line. Moreover, since the WDT for writing 1 is not affected in the write auxiliary module, there is no need to pull it up again through the bit line clamping circuit subsequently.

[0103] Similarly, when the write data is 1, the write driver circuit outputs WDC as a high level and WDT as a low level:

[0104] WDCX is at a high level, Negcap0 changes from a high level to a low level, the output of the fifth NOR logic gate N5 remains at a low level, and after passing through the inverter, the fifth metal line is driven to remain at a high level, so that the WDC of write 1 is not affected.

[0105] WDTX is at a low level, Negcap1 changes from a high level to a low level, triggering the output of the sixth NOR logic gate N6 to change from a low level to a high level, and after passing through the inverter, drives the sixth metal line from a high level to a low level. The low-level sixth metal line couples the WDT writing 0 to a negative voltage through capacitive coupling.

[0106] Therefore, when writing data 1, the WDT for writing 0 is coupled to the negative voltage, and the WDC for writing 1 is not affected, thereby enhancing the write capability of the memory cell and reducing the number of charge and discharge times of the high-level signal line. Moreover, since the WDC for writing 1 is not affected in the write auxiliary module, there is no need to pull it up again through the bit line clamping circuit subsequently.

[0107] This embodiment applies the effect of unilateral metal capacitor coupling on WDC / WDT, thereby obtaining a negative voltage and saving the area occupied by the metal capacitor.

[0108] Please refer to Figure 5 , Figure 5 This is a schematic diagram of the structure of a write driver circuit provided in an embodiment of the present application. The write driver circuit includes a trigger module and a write signal generating module.

[0109] Specifically, the trigger module includes a trigger, a first inverter, a second inverter, and a fourth inverter. The trigger's D terminal receives a data signal DatIn, the trigger's Clk terminal receives a write clock signal WCLK, and the trigger's Q terminal outputs a signal WDCX after passing through the first and second inverters. The trigger's Q terminal also outputs a signal WDTX after passing through the fourth inverter. The trigger in this embodiment is a D-type flip-flop with a single data input terminal D. Under the influence of a clock signal, the trigger's output state is consistent with the D input.

[0110] The write signal generating module includes: a first NOR logic gate N1, a second NOR logic gate N2, a first PMOS transistor PMOS1, a second PMOS transistor PMOS2, a first NMOS transistor NMOS1, a second NMOS transistor NMOS2, a third PMOS transistor PMOS3, a fourth PMOS transistor PMOS4, and a third inverter; an input terminal of the third inverter receives an input signal NegBl, and an output terminal of the third inverter receives an output signal NegBlEn; a first input terminal of the first NOR logic gate N1 receives an input signal WDCX, a second input terminal of the first NOR logic gate N1 receives an input signal NegBlEn, an output terminal of the first NOR logic gate N1 is connected to a gate of the first PMOS transistor PMOS1, and an output terminal of the first NOR logic gate N1 is also connected to a gate of the first NMOS transistor NMOS1; a source electrode of the first PMOS transistor PMOS1 is connected to a power supply VDD, a drain electrode of the first PMOS transistor PMOS1 is connected to a source electrode of the second PMOS transistor PMOS2, and a drain electrode of the second PMOS transistor PMOS2 is connected to the first NMOS transistor NMOS1 The drain of the first NMOS transistor NMOS1 is grounded; a first input terminal of the second NOR logic gate N2 is input with a signal WDTX, a second input terminal of the second NOR logic gate N2 is input with a signal NegBlEn, an output terminal of the second NOR logic gate N2 is connected to the gate of the second PMOS transistor PMOS2, and the output of the second NOR logic gate N2 is also connected to the gate of the second NMOS transistor NMOS2; a source of the second PMOS transistor PMOS2 is connected to the power supply VDD, a drain of the second PMOS transistor PMOS2 is connected to the source of the fourth PMOS transistor PMOS4, the drain of the fourth PMOS transistor PMOS4 is connected to the drain of the second NMOS transistor NMOS2, and the source of the second NMOS transistor NMOS2 is grounded; a gate of the third PMOS transistor PMOS3 is connected to the drain of the fourth PMOS transistor PMOS4, the gate of the fourth PMOS transistor PMOS4 is connected to the drain of the third PMOS transistor PMOS3, the drain of the third PMOS transistor PMOS3 outputs a signal WDT, and the drain of the fourth PMOS transistor PMOS4 outputs a signal WDC.

[0111] In the above technical solution, the enable signal NegBl controls the low-level end of WDC / WDT to float, specifically including:

[0112] When writing data 0 (refer to Figure 3(waveform diagram), WDCX is low, WDTX is high, and NegBl (high) is converted to a low level through the inverter. The first NOR logic gate N1 has two low-level inputs, and its output wdcin is high. The second NOR logic gate N2 has one high and one low-level inputs, and its output wdtin is low. As a result, the first PMOS transistor PMOS1 is turned off, the first NMOS transistor NMOS1 is turned on, the second PMOS transistor PMOS2 is turned on, and the second NMOS transistor NMOS2 is turned off. At this time, WDC is low and WDT is high. The enable signal NegBl changes from a high level to a low level, NegBlEn changes to a high level, and the outputs of the first NOR logic gate N1 and the second NOR logic gate N2 are both low levels, controlling the first PMOS transistor PMOS1 and the second PMOS transistor PMOS2 to turn on, and the first NMOS transistor NMOS1 and the second NMOS transistor NMOS2 to turn off. At this time, the output WDC and WDT maintain the levels of the previous moment unchanged, wherein the WDC for writing 0 is floated so that the WDC for writing 0 can be coupled to a negative voltage in the subsequent write auxiliary module.

[0113] When writing data 1, WDCX is high, WDTX is low, and NegBl (high) is converted to a low level through the inverter. The inputs of the first NOR logic gate N1 are a low level and a high level, and the output wdcin of the first NOR logic gate N1 is low. The inputs of the second NOR logic gate N2 are two low levels, and the output wdtin of the second NOR logic gate N2 is high. As a result, the first PMOS transistor PMOS1 is turned on, the first NMOS transistor NMOS1 is turned off, the second PMOS transistor PMOS2 is turned off, and the second NMOS transistor NMOS2 is turned on. At this time, WDC is high and WDT is low. The enable signal NegBl changes from a high level to a low level, and NegBlEn changes to a high level. The outputs of the first NOR logic gate N1 and the second NOR logic gate N2 are both low levels, which control the first PMOS tube PMOS1 and the second PMOS tube PMOS2 to be turned on, and the first NMOS tube NMOS1 and the second NMOS tube NMOS2 to be turned off. At this time, the output WDC and WDT maintain the level of the previous moment unchanged, among which the WDT for writing 0 is floated so that the WDT for writing 0 can be coupled to a negative voltage in the write auxiliary module later.

[0114] Please refer to Figure 6 , Figure 6 This is a schematic diagram of the memory cell and bit line voltage clamping circuit structure provided in an embodiment of the present application.

[0115] The memory cell is connected to the bit line BLT / BLC, the word line WL, and the power line. The memory cell is a 6-transistor memory, including: a fifth PMOS transistor PMOS5, a sixth PMOS transistor PMOS6, a third NMOS transistor NMOS3, a fourth NMOS transistor NMOS4, a fifth NMOS transistor NMOS5, and a sixth NMOS transistor NMOS6; wherein the third NMOS transistor NMOS3 and the fourth NMOS transistor NMOS4 are pull-down transistors, the fifth PMOS transistor PMOS5 and the sixth PMOS transistor PMOS6 are riser transistors, and the fifth NMOS transistor NMOS5 and the sixth NMOS transistor NMOS6 are transmission transistors; the source electrodes of the fifth PMOS transistor PMOS5 and the sixth PMOS transistor PMOS6 are connected to the memory cell operating power supply VDD, and the drain electrodes of the fifth PMOS transistor PMOS5 and the sixth PMOS transistor PMOS6 are respectively connected to the third NMOS transistor NMOS4. OS3 and the drain of the fourth NMOS transistor NMOS4; the gate of the fifth PMOS transistor PMOS5 is connected to the gate of the fifth NMOS transistor NMOS5 to form a first storage node, and the gate of the sixth PMOS transistor PMOS6 is connected to the gate of the sixth NMOS transistor NMOS6 to form a second storage node; the sources of the fifth NMOS transistor NMOS5 and the sixth NMOS transistor NMOS6 are connected to the ground line; the source of the third NMOS transistor NMOS3 is connected to the signal BLT, the drain of the third NMOS transistor NMOS3 is connected to the first storage node, and the gate of the third NMOS transistor NMOS3 is connected to the word line WL; the source of the fourth NMOS transistor NMOS4 is connected to the signal BLC, the drain of the fourth NMOS transistor NMOS4 is connected to the second storage node, and the gate of the fourth NMOS transistor NMOS4 is connected to the bit line WL.

[0116] It should be noted that, in other embodiments, the memory cell may also be of other types, such as an 8-transistor memory.

[0117] The low power auxiliary circuit of this embodiment further includes: a bit line voltage clamping circuit; the bit line voltage clamping circuit is connected between the read / write signal line and the memory cell.

[0118] Specifically, the bit line voltage clamping circuit includes a seventh NMOS transistor NMOS7, an eighth NMOS transistor NMOS8, a seventh PMOS transistor PMOS7, and an eighth PMOS transistor PMOS8. The source of the seventh PMOS transistor PMOS7 is connected to a power supply VDD, the source of the eighth PMOS transistor PMOS8 is connected to a power supply VDD, the gate of the seventh PMOS transistor PMOS7 is connected to a bit line BLC, the gate of the eighth PMOS transistor PMOS8 is connected to a bit line BLT, the drain of the seventh PMOS transistor PMOS7 is connected to a bit line BLT, and the drain of the eighth PMOS transistor PMOS8 is connected to a bit line BLC. The bit line BLT is connected to a read / write signal line via the seventh NMOS transistor NMOS7, the bit line BLC is connected to a read / write signal line via the eighth NMOS transistor NMOS8, and the seventh NMOS transistor NMOS7 and the eighth NMOS transistor NMOS8 are connected via a signal line WCS.

[0119] The bit line voltage clamping circuit of this embodiment is a Zener diode clamping circuit. In other implementations, a diode clamping circuit may also be used.

[0120] An embodiment of the present application provides a static random access memory, comprising a low-power write assist circuit as described in any one of the above items.

[0121] In the embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some communication interface, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0122] In addition, the units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0123] Furthermore, the functional modules in each embodiment of the present application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0124] In this document, relational terms such as first and second, etc. are used merely to distinguish one entity or operation from another entity or operation, but do not necessarily require or imply any actual relationship or order between these entities or operations.

[0125] The above description is merely an embodiment of the present application and is not intended to limit the scope of protection of the present application. For those skilled in the art, various modifications and variations of the present application are possible. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A low-power write assist circuit, characterized in that: include: Write driver circuit, write assist module and memory unit; The write driver circuit and the write assist module are connected via complementary signal lines, the complementary signal lines including a first signal line and a second signal line, the first signal line is used to transmit a signal WDC, and the second signal line is used to transmit a signal WDT; the write assist module is also connected to the memory unit; The write driver circuit is used to obtain a signal WDC and a signal WDT according to the data signal, and transmit the signal WDC and the signal WDT to the write assist module; The write assist module is used to control the signal WDC and the signal WDT to couple the write 0 signal to the negative voltage during the write cycle, and the signal WDC and the signal WDT to write 1 signal are not affected during the write cycle; the processed signal WDC and the signal WDT are transmitted to the memory unit.

2. The circuit according to claim 1, wherein The write drive circuit includes: a trigger module and a write signal generating module; The trigger module is used to obtain a trigger output signal WDCX and an inverted signal WDTX of the trigger output signal according to a data signal and a write clock signal; The write signal generating module is used to obtain the signal WDT and the signal WDC according to the signal WDCX, the signal WDTX and the first enable signal NegB1.

3. The circuit according to claim 2, wherein: The write assist module includes: a first metal line and a second metal line placed on both sides of the first signal line, and a third metal line and a fourth metal line placed on both sides of the second signal line; The first metal line is capacitively coupled to the first signal line, the second metal line is capacitively coupled to the first signal line, the third metal line is capacitively coupled to the second signal line, and the fourth metal line is capacitively coupled to the second signal line.

4. The circuit according to claim 3, wherein: The write assist module further includes: a third NOR logic gate and a fourth NOR logic gate; A first input terminal of the third NOR logic gate inputs a signal WDCX, a second input terminal of the third NOR logic gate inputs a signal Negcap0, an output terminal of the third NOR logic gate is connected to the first metal line after passing through an inverter, and an output terminal of the third NOR logic gate is further connected to the second metal line after passing through an inverter; The first input terminal of the fourth NOR logic gate inputs the signal WDTX, the second input terminal of the fourth NOR logic gate inputs the signal Negcap1, the output terminal of the fourth NOR logic gate is connected to the third metal line after passing through an inverter, and the output terminal of the fourth NOR logic gate is also connected to the fourth metal line after passing through an inverter.

5. The circuit according to claim 2, wherein: The write assist module includes: A fifth metal line is placed on one side of the first signal line, and a sixth metal line is placed on one side of the second signal line.

6. The circuit according to claim 5, wherein: The write assist module further includes: a fifth NOR logic gate and a sixth NOR logic gate; A first input terminal of the fifth NOR logic gate inputs a signal WDCX, a second input terminal of the fifth NOR logic gate inputs a signal Negcap0, and an output terminal of the fifth NOR logic gate is connected to the fifth metal line after passing through an inverter; A first input terminal of the sixth NOR logic gate inputs a signal WDTX, a second input terminal of the sixth NOR logic gate inputs a signal Negcap1, and an output terminal of the sixth NOR logic gate is connected to the sixth metal line after passing through an inverter.

7. The circuit according to claim 2, wherein: The trigger module includes: a trigger, a first inverter, a second inverter, and a fourth inverter; The D terminal of the trigger inputs a data signal, the Clk terminal of the trigger inputs a write clock signal, and the Q terminal of the trigger outputs a signal WDCX after passing through the first inverter and the second inverter; The Q end of the trigger also outputs a signal WDTX after passing through the fourth inverter.

8. The circuit according to claim 2, wherein: The write signal generating module includes: a first NOR logic gate, a second NOR logic gate, a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third PMOS transistor, a fourth PMOS transistor and a third inverter; The input terminal of the third inverter inputs the signal NegBl, and the output terminal of the third inverter outputs the signal NegBlEn; A first input terminal of the first NOR logic gate receives an input signal WDCX, a second input terminal of the first NOR logic gate receives an input signal NegBlEn, an output terminal of the first NOR logic gate is connected to the gate of the first PMOS transistor, and the output of the first NOR logic gate is also connected to the gate of the first NMOS transistor; a source of the first PMOS transistor is connected to a power supply VDD, a drain of the first PMOS transistor is connected to the source of the second PMOS transistor, a drain of the second PMOS transistor is connected to the drain of the first NMOS transistor, and a source of the first NMOS transistor is grounded; A first input terminal of the second NOR logic gate receives an input signal WDTX, a second input terminal of the second NOR logic gate receives an input signal NegBlEn, an output terminal of the second NOR logic gate is connected to the gate of the second PMOS transistor, and an output terminal of the second NMOS logic gate is also connected to the gate of the second NMOS transistor; a source of the second PMOS transistor is connected to a power supply VDD, a drain of the second PMOS transistor is connected to the source of the fourth PMOS transistor, a drain of the fourth PMOS transistor is connected to the drain of the second NMOS transistor, and a source of the second NMOS transistor is grounded; The gate of the third PMOS transistor is connected to the drain of the fourth PMOS transistor, the gate of the fourth PMOS transistor is connected to the drain of the third PMOS transistor, the drain of the third PMOS transistor outputs a signal WDT, and the drain of the fourth PMOS transistor outputs a signal WDC.

9. The circuit according to claim 1, wherein: Also includes: A bit line voltage clamp circuit is connected between the read / write signal line and the memory cell.

10. A static random access memory, characterized in that: The invention comprises a low-power write assist circuit as described in any one of claims 1 to 9.

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