Memory device and method of performing verification operation of memory device

Abstract

A memory device and a method of performing a verification operation of the memory device are provided herein. The memory device includes: a memory cell array including memory cells; a source line discharge transistor configured to couple a source line of the memory cell array to ground; a voltage generator configured to generate a gate voltage applied to a gate of the source line discharge transistor; and a control logic configured to determine a gate voltage according to a change in a threshold voltage of the memory cell in response to a verify operation on the memory cell performed in each of the plurality of program loops, and control the voltage generator to generate the determined gate voltage.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority from Korean Patent Application No. 10-2024-0017460, filed on February 5, 2024, the disclosure of which is hereby incorporated by reference in its entirety. Technical Field

[0003] Various embodiments of the present disclosure generally relate to a memory device, and more particularly, to a memory device and a method of performing a verification operation of the memory device. Background Art

[0004] Memory devices are categorized as volatile memory devices and non-volatile memory devices. Volatile memory devices store data only when power is supplied and lose the stored data when the power supply is interrupted. Non-volatile memory devices retain stored data even when power is interrupted.

[0005] During a verification operation of a memory device, the voltage of a source line may suddenly rise and / or fall. During a verification operation of a memory device, the voltage of a source line may vary. During a verification operation of a memory device, the voltage of a source line may fluctuate or bounce. During a verification operation of a memory device, the voltage of a source line may cause a bouncing phenomenon. As the voltage of the source line varies, the amount of current flowing through the bit line may vary. A verification operation of the memory device may be performed by sensing the bit line current. Due to variations in the bit line current, the accuracy of the verification result may be reduced. Summary of the Invention

[0006] Embodiments of the present disclosure may provide a memory device. The memory device may include: a memory cell array including memory cells; a source line discharge transistor configured to couple a source line of the memory cell array to ground; a voltage generator configured to generate a gate voltage applied to a gate of the source line discharge transistor; and control logic configured to determine a gate voltage based on a change in a threshold voltage of the memory cell in response to a verification operation performed on the memory cell in each of a plurality of programming loops, and to control the voltage generator to generate the determined gate voltage.

[0007] Embodiments of the present disclosure may provide a memory device. The memory device may include: a memory cell array including memory cells; a source line discharge transistor configured to couple a source line of the memory cell array to ground; a voltage generator configured to generate a gate voltage applied to a gate of the source line discharge transistor; and control logic configured to count the number of program-completed memory cells whose threshold voltages have reached a target threshold voltage in response to a verification operation performed on the memory cells in each of a plurality of program loops, and control logic configured to determine a gate voltage determined by the voltage generator based on the number of program-completed memory cells.

[0008] Embodiments of the present disclosure may provide a method for operating a memory device. The method may include: executing a first programming loop including a first programming pulse application operation to increase the threshold voltage of a memory cell and a first verification operation to verify whether the threshold voltage of the memory cell has reached a target threshold voltage; counting the number of program-completed memory cells whose threshold voltage has reached the target threshold voltage based on a result of the first verification operation; determining a first reduction amount of a gate voltage applied to the gate of a source line discharge transistor for coupling a source line of a memory cell array including the memory cell to ground based on the number of program-completed memory cells and the magnitude of a first voltage applied to the gate of the source line discharge transistor during the execution of the first verification operation; and applying a voltage reduced by the first reduction amount from the first voltage in response to a second verification operation included in a second programming loop executed after the first programming loop. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a diagram illustrating a memory device according to an embodiment of the present disclosure.

[0010] Figure 2 is a diagram illustrating a source line discharge transistor according to an embodiment of the present disclosure.

[0011] Figure 3 is a diagram illustrating a voltage applied to a gate of a source line discharge transistor according to an embodiment of the present disclosure.

[0012] Figure 4 is a diagram illustrating a voltage applied to a gate of a source line discharge transistor according to an embodiment of the present disclosure.

[0013] Figure 5 is a diagram illustrating the influence of a source line voltage causing a bounce phenomenon or fluctuation during a verification operation.

[0014] Figure 6 is a flowchart illustrating a method of performing a verification operation according to an embodiment of the present disclosure.

[0015] Figure 7 is a diagram illustrating an example of a data processing system including a memory device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0016] The specific structural or functional descriptions in the embodiments of the present disclosure introduced in this specification or application are provided as examples to describe the embodiments according to the concepts of the present disclosure. The embodiments according to the concepts of the present disclosure can be practiced in various forms and should not be interpreted as being limited to the embodiments described in the specification or application.

[0017] Various embodiments of the present disclosure relate to a memory device and a method of performing a verification operation of the memory device, which suppress a bouncing phenomenon in which a source line voltage varies in response to the verification operation of the memory device.

[0018] Figure 1 is a diagram illustrating a memory device according to an embodiment of the present disclosure.

[0019] Reference Figure 1 , the memory device 100 can store data. The memory device 100 may include: a memory cell array 110, which includes memory cells that store data; an address decoder 120, which decodes a column address; an input / output circuit 130, which transmits / receives data to / from an external system of the memory device 100; a control logic 140; a voltage generator 150, which generates a plurality of voltages having a plurality of voltage levels; a current sensing circuit 160, which senses a sense current flowing through a bit line during a verification operation; and a source line discharge transistor 170, which couples a source line of the memory cell array 110 to ground. The control logic 140 may be implemented as hardware, software, or a combination of hardware and software. For example, the control logic 140 may be a control logic circuit that operates according to an algorithm and / or a processor that executes control logic code.

[0020] Each memory cell included in the memory cell array 110 may be a single-level cell (SLC) storing 1-bit data or a memory cell storing multi-bit data. Depending on the number of bits in the multi-bit data, the memory cell storing the multi-bit data may be a multi-level cell (MLC) storing 2-bit data, a triple-level cell (TLC) storing 3-bit data, or a quad-level cell (QLC) storing 4-bit data.

[0021] The address decoder 120 may be coupled to the memory cell array 110 through word lines. The address decoder 120 may operate under the control of the control logic 140.

[0022] The input / output circuit 130 may include a page buffer that reads data stored in a memory cell and stores the read data for a limited amount of time. The input / output circuit 130 may output the data stored in the page buffer to an external system of the memory device 100, or may store data received from an external system in the page buffer and then store the data in the memory cell. The page buffer may provide a sense current to a bit line connected to the memory cell to sense the threshold voltage of the memory cell during a read operation and a program verification operation. The page buffer may sense a change in the amount of current flowing according to the programming state of the memory cell through a sense node and may latch the sensed change as sense data. The input / output circuit 130 may transmit the latched sense data to the control logic 140.

[0023] The control logic 140 may control the overall operation of the memory device 100. The control logic 140 may generate control signals for controlling the address decoder 120, the input / output circuit 130, the voltage generator 150, and the current sensing circuit 160 so that a read operation, a program operation, and an erase operation are performed on the memory cell array 110. The control logic 140 may determine whether the result of the program verification indicates a pass in response to a pass signal or a fail signal received from the current sensing circuit 160.

[0024] The voltage generator 150 may generate a gate voltage that is applied to the gate of the source line discharge transistor 170 during a verification operation. The voltage generator 150 may apply the generated gate voltage to the gate of the source line discharge transistor 170 at a timing determined in response to a control signal from the control logic 140.

[0025] The current sensing circuit 160 may generate a reference current or a reference voltage based on an enable bit received from the control logic 140 during a verification operation. The current sensing circuit 160 may generate a pass signal or a fail signal by comparing the generated reference voltage with a sense voltage or by comparing the generated reference current with a sense current.

[0026] Source line discharge transistor 170 can function as a switch. When source line discharge transistor 170 is turned on, the source line of memory cell array 110 can be connected to ground. In an embodiment of the present disclosure, the extent to which the source line voltage changes according to the magnitude of the sensed current during a verification operation can be reduced depending on the gate voltage applied to source line discharge transistor 170.

[0027] In an embodiment of the present disclosure, the control logic 140 may determine a gate voltage based on a change in the threshold voltage of the memory cell. The control logic 140 may control the voltage generator 150 to generate the determined gate voltage, and the voltage generator 150 may apply the generated gate voltage to the gate of the source line discharge transistor 170 in response to a verification operation.

[0028] In an embodiment of the present disclosure, control logic 140 may count the number of program-completed memory cells whose threshold voltages have reached a target threshold voltage. Control logic 140 may control voltage generator 150 to generate a gate voltage determined based on the number of program-completed memory cells, and voltage generator 150 may apply the generated gate voltage to the gate of source line discharge transistor 170 in response to a verification operation.

[0029] In an embodiment of the present disclosure, as the programming loop is executed, the number of memory cells that have passed verification may increase. Each memory cell that has passed verification may refer to a memory cell having a threshold voltage higher than the verification voltage. As the number of memory cells having a threshold voltage higher than the verification voltage increases, the magnitude of the sensing current may decrease. As the magnitude of the sensing current decreases, the degree of variation in the source line voltage may decrease. As the degree of variation in the source line voltage decreases, the control logic 140 may gradually reduce the magnitude of the gate voltage applied to the gate of the source line discharge transistor 170.

[0030] Figure 2 is a diagram illustrating a source line discharge transistor according to an embodiment of the present disclosure.

[0031] Reference Figure 2 , the cell string 210 may be coupled between the bit line and the source line, and the source line discharge transistor 170 may be coupled between the source line and the ground. Although only one cell string is shown as the cell string 210 coupled between the bit line and the source line for ease of description, a plurality of cell strings may be coupled between the bit line and the source line.

[0032] The cell string 210 may include a source select transistor SST connected in series between a source line and a bit line, n memory cells C1 to Cn, and a drain select transistor DST. The cell string 210 may include at least one source select transistor SST and at least one drain select transistor DST. The number of memory cells included in the cell string 210 may vary. In an embodiment, n may be an integer greater than zero.

[0033] A source of the source select transistor SST may be coupled to a source line, and a drain of the drain select transistor DST may be coupled to a bit line. For the cell string 210 , n memory cells C1 to Cn may be connected in series between the source select transistor SST and the drain select transistor DST.

[0034] The source line discharge transistor 170 can connect the source line to ground. When the source line discharge transistor 170 is turned on, the source line can be connected to ground. When a voltage equal to or greater than a preset threshold voltage is applied to the gate of the source line discharge transistor 170, the source line discharge transistor 170 can be turned on. In embodiments of the present disclosure, a gate voltage Vg generated by the voltage generator 150 can be applied to the gate of the source line discharge transistor 170. When the source line discharge transistor 170 is turned off, the source line can be in a floating state. The term "preset" as used herein with respect to parameters, such as preset threshold voltage, preset minimum voltage, preset time, preset first period, preset second period, preset period, preset default voltage, and preset voltage, refers to the determination of the value of the parameter before the parameter is used in a process or algorithm. In some embodiments, the value of the parameter is determined before the process or algorithm begins. In other embodiments, the value of the parameter is determined during the process or algorithm but before the parameter is used in the process or algorithm.

[0035] In an embodiment of the present disclosure, the voltage of the source line may be changed according to the gate voltage Vg applied to the gate of the source line discharge transistor 170. During a verification operation, the level of the source line voltage may become higher by the source line discharge transistor 170. As the applied gate voltage Vg increases, the level of the source line voltage may become lower.

[0036] Figure 3 is a diagram illustrating a voltage applied to a gate of a source line discharge transistor according to an embodiment of the present disclosure.

[0037] refer to Figure 3 , multiple program loops may be performed in the memory device 100. Figure 3 , the gate voltage Vg applied to the source line discharge transistor 170 when performing the verification operation included in each of the plurality of program loops may be shown. For ease of description, it may be assumed that Figure 3 1 to 5th program loops PL1 to PL5 are depicted in FIG.

[0038] Each programming loop may include a program pulse application operation to increase the threshold voltage of the memory cell and a verification operation to verify whether the threshold voltage of the memory cell has reached the target threshold voltage. During the program pulse application operation, a ground voltage GND may be applied to the gate of the source line discharge transistor 170. The memory device 100 may perform multiple programming loops. As the number of program pulse application operations performed increases, the threshold voltage of the memory cell may increase. The size of the applied programming pulse may be gradually increased in response to the increase in the number of program loops performed.

[0039] As the number of program loops executed increases, the number of program-completed memory cells whose threshold voltages have reached the target threshold voltage can increase. As the number of program-completed memory cells increases, the magnitude of the sense current flowing through the bit line can decrease. Because the increase in the potential level of the source line decreases as the magnitude of the sense current decreases, it is expected that the gate voltage Vg applied to the gate of the source line discharge transistor 170 will decrease.

[0040] In an embodiment of the present disclosure, in response to a verification operation on a memory cell performed in each of a plurality of programming loops, the control logic 140 may determine a gate voltage Vg according to a change in the threshold voltage of the memory cell. The voltage generator 150 may generate the gate voltage Vg and apply the gate voltage Vg to the gate of the source line discharge transistor 170.

[0041] The input / output circuit 130 may generate sensing data by sensing a sensing current flowing through a bit line coupled to a memory cell, and the control logic 140 may detect a change in a threshold voltage of the memory cell based on the sensing data.

[0042] In response to the magnitude of the sensed current being smaller than the magnitude of the sensed current sensed in the previous programming loop, the control logic 140 may reduce the gate voltage Vg. For example, the sensed current sensed in the second verification operation of the second programming loop PL2 may be smaller than the sensed current sensed in the first verification operation of the first programming loop PL1. The control logic 140 may control the gate voltage applied in response to the second verification operation of the second programming loop PL2 to be smaller than the gate voltage applied in response to the first verification operation of the first programming loop PL1.

[0043] Control logic 140 can determine the amount of reduction in gate voltage Vg based on the change in the sensed current. In response to executing multiple programming loops, control logic 140 can reduce the gate voltage until gate voltage Vg reaches a preset minimum voltage. In an embodiment of the present disclosure, the minimum voltage can be a limit voltage applied to the gate of source line discharge transistor 170 during a read operation. The limit voltage can be equal to or higher than the threshold voltage at which source line discharge transistor 170 turns on. Control logic 140 can gradually reduce gate voltage Vg in response to executing multiple programming loops.

[0044] For example, the control logic 140 may determine the amount of decrease in the gate voltage Vg as a first decrease amount Vstep1 based on the change in the sensed current. In response to the first verification operation, the control logic 140 may apply the first voltage V1 to the gate of the source line discharge transistor 170, and in response to the second verification operation, may apply a voltage reduced from the first voltage V1 by the first decrease amount Vstep1 to the gate of the source line discharge transistor 170. Similarly, in response to the third verification operation of the third programming loop, the control logic 140 may apply a voltage reduced from the first voltage V1 by twice the first decrease amount Vstep1 to the gate of the source line discharge transistor 170.

[0045] exist Figure 3 In the program loop executed after the third program loop PL3, the limit voltage is applied to the gate of the source line discharge transistor 170 in response to the first verification voltage PV1, and a voltage lower than the limit voltage is not applied to the gate of the source line discharge transistor 170.

[0046] One or more verification voltages may be applied during each verification operation. A gate voltage Vg corresponding to each verification voltage may be applied to the gate of source line discharge transistor 170. The gate voltage Vg applied to the gate of source line discharge transistor 170 may vary with each verification voltage. For example, in the first to third programming loops PL1 to PL3, a verification operation may be performed for a first verification voltage PV1, and in the fourth programming loop PL4 or higher, a verification operation may be performed for a second verification voltage PV2. In the first programming loop PL1, a first voltage V1 may be applied to the gate of source line discharge transistor 170 in response to the first verification voltage PV1. In the fourth programming loop PL4, a second voltage V2 may be applied to the gate of source line discharge transistor 170 in response to the second verification voltage PV2.

[0047] In response to the second verification voltage PV2, the control logic 140 may control the application of the second voltage V2 to the gate of the source line discharge transistor 170 during the fourth programming loop PL4. As with the first verification voltage PV1, the control logic 140 may determine the amount of decrease in the gate voltage Vg as a second decrease amount Vstep2 based on the change in the sensed current. In an embodiment of the present invention, the first decrease amount Vstep1 and the second decrease amount Vstep2 may be different from each other. During the fifth verification operation of the fifth programming loop PL5, a voltage reduced from the second voltage V2 by the second decrease amount Vstep2 may be applied to the gate of the source line discharge transistor 170. During verification operations performed after the fourth programming loop PL4, a voltage reduced from the second voltage V2 by a multiple of the second decrease amount Vstep2 may be applied to the gate of the source line discharge transistor 170. The gate voltage Vg applied to the gate of the source line discharge transistor 170 in response to the second verification voltage PV2 may be gradually reduced to a limit voltage.

[0048] In an embodiment of the present invention, in response to a verification operation on a memory cell performed in each of a plurality of programming loops, the control logic 140 may count the number of program-completed memory cells whose threshold voltage has reached a target threshold voltage. The control logic 140 may determine the gate voltage Vg applied to the gate of the source line discharge transistor 170 based on the number of program-completed memory cells counted. The control logic 140 may count the number of program-completed memory cells based on sensing data generated by sensing the sensing current. In response to an increase in the number of program-completed memory cells, the control logic 140 may control the gate voltage Vg to decrease. The control logic 140 may determine the amount of gate voltage reduction based on the rate of increase in the number of program-completed memory cells. The control logic 140 may gradually reduce the gate voltage Vg until the gate voltage reaches a preset minimum voltage.

[0049] Figure 4 is a diagram illustrating a voltage applied to a gate of a source line discharge transistor according to an embodiment of the present disclosure.

[0050] Reference Figure 4 , it is possible to illustrate a case 410 where the source line discharge transistor 170 is turned off for a preset time in response to a verification operation and a case 420 where a default voltage V0 is applied to the gate of the source line discharge transistor 170 during a program pulse application operation. Figure 4 In the description of Figure 3 The parts are the same as the description of the parts.

[0051] In an embodiment of the present disclosure, the control logic 140 may control the voltage generator 150 to adjust the magnitude and timing of the gate voltage Vg applied to the gate of the source line discharge transistor 170. In the case 410 where the source line discharge transistor 170 is turned off for a preset time, the gate voltage Vg may be applied during a preset first period T1, and the source line discharge transistor 170 may be turned off during a preset second period T2 after the first period T1.

[0052] In an embodiment of the present disclosure, the second period T2 during which the source line discharge transistor 170 is turned off may be shorter than the first period T1. The second period T2 during which the source line discharge transistor 170 is turned off and the first period T1 during which the gate voltage Vg is applied before the source line discharge transistor 170 is turned off may be consistent regardless of the magnitude of the verification voltage or the programming loop.

[0053] Because the source line is floating or in a floating state when the source line discharge transistor 170 is turned off, current consumption caused during a verification operation may be reduced.

[0054] In an embodiment of the present disclosure, in response to application of a programming pulse, control logic 140 may control a default voltage V0 to be applied to the gate of source line discharge transistor 170. In case 420 where default voltage V0 is applied to the gate of source line discharge transistor 170, ground voltage GND may be applied to the source line. Although ground voltage GND is applied to the source line and thus the channel-cutoff characteristics of source line discharge transistor 170 are not improved, current flowing through the source line can be reduced, thereby reducing current consumption. Default voltage V0 may be equal to or higher than a threshold voltage at which source line discharge transistor 170 turns on.

[0055] Figure 5 is a diagram illustrating the effects of source line voltage bounce, causing bounce and / or fluctuation during a verify operation.

[0056] refer to Figure 5 , shows a portion of memory device 100 in which cells are connected in series between a bit line and a source line, and a source line discharge transistor is coupled between the source line and ground. During a verify operation, the resistance of the conductive line (wire) can be represented by R1, and the resistance of the source line discharge transistor 170 can be represented by R2. In embodiments of the present disclosure, it can be assumed that R2 is greater than R1.

[0057] When multiple program loops are executed, the threshold voltage of the memory cell may increase. As the threshold voltage of the memory cell increases, the amount of the sensing current Icell flowing through the bit line may decrease. Because the amount of the sensing current decreases as the program loops are executed, the amount of the sensing current Icell flowing through the bit line during the verification operation of the program loop executed initially among the multiple program loops may be greater than the amount of the sensing current Icell flowing through the bit line during the verification operation of the program loop executed subsequently.

[0058] The source line voltage can be determined by the product of the sense current Icell and the total resistance, which is the sum of R1 and R2. Because the amount of the sense current Icell changes with the execution of the programming loop, the source line voltage can also change with the execution of the programming loop. Source line voltage bounce can refer to a phenomenon in which the voltage of the source line changes with the execution of the programming loop. Source line voltage bounce can reduce the accuracy of the verification result.

[0059] Because the magnitude of the sense current Icell decreases as the number of program loops executed increases, the source line voltage level may be high in the initial stages of the program loop and may become lower as the program loop is executed. During the verification operation of the initially executed program loop, the magnitude of the sense current Icell may be detected as being smaller than the actual sense current due to the relatively high source line voltage. In the initial stages of the program loop, the threshold voltage of the memory cell has not yet reached the target threshold voltage, so even if the programming operation is not completed, verification may pass because the sense current Icell is detected as being smaller than the actual sense current.

[0060] Furthermore, because the source line voltage decreases due to the sense current Icell (which decreases with the number of programming loops performed), the magnitude of the sense current Icell may be detected as being greater than the actual sense current. In subsequent stages of the programming loop, even if the threshold voltage of the memory cell has reached the target threshold voltage, the sense current Icell is detected as being greater than the actual sense current, and the verification result may be determined to be a verification failure. To improve the accuracy of the verification result, in some embodiments, it is necessary to reduce the impact of source line voltage bounce.

[0061] In an embodiment of the present disclosure, the equivalent resistance R2 of the source line discharge transistor may be inversely proportional to the gate voltage Vg applied to the gate of the source line discharge transistor. The control logic may apply a relatively high voltage to the gate of the source line discharge transistor to reduce the source line voltage during a verify operation of an initially executed programming loop. Furthermore, the voltage applied to the gate of the source line discharge transistor may be reduced as the number of executed programming loops increases. In other words, the gate voltage Vg may decrease as the number of executed programming loops increases.

[0062] According to embodiments of the present disclosure, during the verification operation of an initially executed programming loop, a relatively high voltage can be applied to the gate of the source line discharge transistor, thereby suppressing an increase in the source line voltage. Therefore, in embodiments, the detected sense current Icell does not decrease, thereby improving the accuracy of the verification result. Furthermore, in embodiments, the source line voltage can be increased because the voltage applied to the gate of the source line discharge transistor decreases as the number of executed programming loops increases. Therefore, in embodiments, the detected sense current Icell does not increase, thereby improving the accuracy of the verification result.

[0063] Figure 6 is a flowchart illustrating a method of performing a verification operation according to an embodiment of the present disclosure.

[0064] refer to Figure 6 In an embodiment, in response to a verification operation on a memory cell performed in each of a plurality of programming loops, the accuracy of the verification result can be improved by gradually reducing the voltage applied to the gate of the source line discharge transistor. Figure 6 In the embodiment, it is assumed that the first to third program loops are performed. Although a verification operation corresponding to a first verification voltage is described, this description is merely an embodiment, and verification operations corresponding to a plurality of verification voltages may be performed in one program loop.

[0065] At step S610, the memory device may perform a first program loop including a first program pulse application operation and a first verification operation. The first program pulse application operation may increase the threshold voltage of the memory cell. The first verification operation may be an operation to verify whether the threshold voltage of the memory cell has reached the target threshold voltage.

[0066] At step S620, the control logic may count the number of program-completed memory cells whose threshold voltages have reached the target threshold voltage among the memory cells based on the result of the first verification operation. The control logic may determine the number of program-completed memory cells based on a sense current flowing through a bit line coupled to the memory cell.

[0067] At step S630, the control logic may be configured to determine a first decrease in gate voltage applied to the gate of a source line discharge transistor, which couples a source line of a memory cell array including the memory cells to ground, based on the number of program-completed memory cells and the magnitude of a first voltage applied to the gate of the source line discharge transistor during the first verification operation. The source line discharge transistor may be configured to determine a degree of increase in the number of program-completed memory cells based on a change in the sensed current. The control logic may increase the first decrease based on the degree of increase in the number of program-completed memory cells.

[0068] In step S640, the memory device may perform a second verification operation included in a second program loop performed after the first program loop. In response to the second verification operation, the control logic may control a second voltage reduced by a first reduction amount from the first voltage to be applied to the gate of the source line discharge transistor.

[0069] At step S650, in response to the result of the second verification operation indicating a verification failure, the control logic may determine a third voltage to be applied to the gate of the source line discharge transistor when performing a third verification operation included in a third programming loop performed after the second programming loop. The control logic may determine a voltage reduced by a first reduction amount from the second voltage as the third voltage. In response to the voltage reduced by the first reduction amount from the second voltage being lower than a limit voltage applied to the gate of the source line discharge transistor during a read operation, the control logic may determine the third voltage to be the limit voltage.

[0070] At step S660 , the memory device may perform a third verification operation. The control logic may control application of a third voltage to the source line discharge transistor.

[0071] Figure 6 The description of the corresponding steps in can correspond to Figure 2 and Figure 3 Description.

[0072] Figure 7 is a diagram illustrating an example of a data processing system including a storage device according to an embodiment of the present disclosure.

[0073] refer to Figure 7 , the data processing system 2000 may include a host device 2100 and a solid state drive (SSD) 2200 .

[0074] The SSD 2200 may include a controller 2210 , a buffer memory device 2220 , nonvolatile memories 2231 to 223 n , a power supply 2240 , a signal connector 2250 , and a power connector 2260 .

[0075] The buffer memory device 2220 can store data to be stored in the nonvolatile memories 2231 to 223n for a limited time. In addition, the buffer memory device 2220 can store data read from the nonvolatile memories 2231 to 223n for a limited time. The data stored in the buffer memory device 2220 for a limited time can be transmitted to the host device 2100 or the nonvolatile memories 2231 to 223n under the control of the controller 2210.

[0076] Non-volatile memories 2231 to 223n can serve as storage media for the SSD 2200. The non-volatile memories 2231 to 223n can be connected to the controller 2210 via a plurality of channels CH1 to CHn, respectively. One or more non-volatile memories can be connected to a channel. Non-volatile memories connected to a channel can be connected to the same signal bus and the same data bus. In an embodiment of the present disclosure, each of the non-volatile memories 2231 to 223n can include memory cells connected in series between a bit line and a source line, and can include a source line discharge transistor for connecting the source line to ground.

[0077] The controller 2210 may control the overall operation of the SSD 2200. The controller 2210 may exchange signals SGL with the host device 2100 through the signal connector 2250. Here, the signal SGL may include commands, addresses, data, etc. The signal connector 2250 may be implemented as different types of connectors according to the interface scheme between the host device 2100 and the SSD 2200.

[0078] The power supply 2240 can provide the power PWR received through the power connector 2260 to the SSD 2200. The power supply 2240 may include an auxiliary power supply 2241. When a sudden power outage occurs, the auxiliary power supply 2241 can supply power so that the SSD 2200 shuts down normally. The auxiliary power supply 2241 may include a large-capacity capacitor capable of charging the power PWR.

[0079] In an embodiment of the present disclosure, SSD 2200 can perform a programming operation including multiple programming loops. In response to a verify operation performed on a memory cell in each of the multiple programming loops, SSD 2200 can determine the gate voltage of the source line discharge transistor based on a change in the threshold voltage of the memory cell. As the number of program loops executed increases, SSD 2200 can gradually reduce the voltage applied to the gate of the source line discharge transistor. SSD 2200 can count the number of programmed memory cells whose threshold voltage has reached a target threshold voltage by sensing the sense current flowing through the bit line during the verify operation. SSD 2200 can determine the amount of reduction in the voltage applied to the gate of the source line discharge transistor based on the number of programmed memory cells.

[0080] According to an embodiment of the present disclosure, a memory device and a method of performing a verification operation on the memory device may be provided, which may perform a verification operation in response to the influence of source line voltage bounce, which is reduced when a programming loop is performed by applying a gradually decreasing gate voltage to the gate of a source line discharge transistor for coupling a memory cell array to ground.

[0081] The scope of the present disclosure is defined by the appended claims, rather than the detailed description, and all modifications or variations derived from the meaning and scope of the claims and their equivalents should be construed as falling within the scope of the present disclosure.

Claims

1. A memory device comprising: a memory cell array comprising memory cells; a source line discharge transistor connecting a source line of the memory cell array to ground; a voltage generator that generates a gate voltage applied to a gate of the source line discharge transistor; as well as The control logic determines the gate voltage according to a change in a threshold voltage of the memory cell in response to a verification operation performed on the memory cell in each of a plurality of program loops, and controls the voltage generator to generate the determined gate voltage.

2. The memory device according to claim 1 , further comprising: a current sensing circuit that senses a sense current flowing through a bit line coupled to the memory cell, The control logic detects a change in a threshold voltage of the memory cell based on a result of sensing the sensing current.

3. The memory device according to claim 2, wherein In response to the magnitude of the sense current becoming smaller than the magnitude of the sense current sensed in a previous programming loop, the control logic generates a control signal that decreases the gate voltage.

4. The memory device according to claim 3, wherein The control logic determines an amount of reduction in the gate voltage based on a change in the sense current.

5. The memory device according to claim 3, wherein In response to executing the plurality of program loops, the control logic generates a control signal that decreases the gate voltage until the gate voltage reaches a preset minimum voltage.

6. The memory device according to claim 5, wherein The preset minimum voltage is a limiting voltage applied to the gate of the source line discharge transistor during a read operation, and The limit voltage is equal to or greater than a threshold voltage at which the source line discharge transistor is turned on.

7. The memory device according to claim 5, wherein In response to executing the plurality of program loops, the control logic generates a control signal that gradually decreases the gate voltage.

8. The memory device according to claim 1, wherein The voltage generator applies a programming pulse in each of the plurality of programming loops to increase a threshold voltage of the memory cell. In response to the application of the programming pulse, the control logic controls the voltage generator to apply a preset default voltage to the gate of the source line discharge transistor, and The default voltage is equal to or greater than a threshold voltage at which the source line discharge transistor is turned on.

9. The memory device according to claim 1, wherein The control logic controls the source line discharge transistor to be turned off during a second period after a first period has passed since the gate voltage was applied to the gate of the source line discharge transistor, and The second period is shorter than the first period.

10. The memory device according to claim 1, wherein The control logic generates a control signal to decrease the gate voltage based on a number of times the plurality of program loops have been performed.

11. A memory device comprising: a memory cell array comprising memory cells; a source line discharge transistor connecting a source line of the memory cell array to ground; a voltage generator that generates a gate voltage applied to a gate of the source line discharge transistor; as well as The control logic counts the number of program-completed memory cells whose threshold voltages have reached a target threshold voltage in response to a verification operation performed on the memory cells in each of a plurality of program loops, and controls the voltage generator to generate a gate voltage determined based on the number of program-completed memory cells.

12. The memory device of claim 11 , further comprising: a current sensing circuit that senses a sense current flowing through a bit line coupled to the memory cell, The control logic counts the number of the program-completed memory cells based on a result of sensing the sensing current.

13. The memory device according to claim 12, wherein: In response to the number of program-completed memory cells being greater than the number of program-completed memory cells counted in a previous program loop, the control logic controls the voltage generator to decrease the gate voltage.

14. The memory device according to claim 13, wherein: The control logic determines a reduction amount of the gate voltage based on an increase rate of the number of the program-completed memory cells.

15. The memory device according to claim 13, wherein: In response to executing the plurality of program loops, the control logic controls the voltage generator to decrease the gate voltage until the gate voltage reaches a preset minimum voltage.

16. The memory device according to claim 15, wherein In response to executing the plurality of program loops, the control logic controls the voltage generator to step-by-step decrease the gate voltage.

17. A method of operating a memory device, comprising: performing a first program loop including a first program pulse applying operation to increase a threshold voltage of a memory cell and a first verification operation to verify whether the threshold voltage of the memory cell has reached a target threshold voltage; counting, based on a result of the first verification operation, the number of program-completed memory cells whose threshold voltages have reached a target threshold voltage among the memory cells; determining a first reduction amount of a gate voltage applied to a gate of a source line discharge transistor coupling a source line of a memory cell array including the memory cell to ground based on the number of the program-completed memory cells and a magnitude of a first voltage applied to a gate of the source line discharge transistor during execution of the first verification operation; as well as In response to performing a second verification operation included in a second program loop performed after the first program loop, a voltage reduced from the first voltage by the first reduction amount is applied.

18. The method according to claim 17, wherein Counting the number includes: The number of the program-completed memory cells is determined based on a sensing current flowing through a bit line coupled to the memory cells.

19. The method according to claim 18, wherein Determining the first reduction amount includes: determining an increase degree of the number of the program-completed memory cells based on a change in the sensing current; and The first reduction amount is increased based on an increase degree of the number of the program-completed memory cells.

20. The method of claim 17, further comprising: in response to a result of the second verification operation indicating a verification failure, determining a third voltage to be applied to the gate of the source line discharge transistor during a third verification operation included in a third programming loop performed after the second programming loop; as well as The third verification operation is performed by applying the third voltage to the gate of the source line discharge transistor.

21. The method according to claim 20, wherein Determining the third voltage includes: A voltage reduced from the second voltage by the first reduction amount is determined as the third voltage.

22. The method according to claim 21, wherein Determining the third voltage further includes: In response to a voltage reduced from the second voltage by the first reduction amount being lower than a limit voltage applied to the gate of the source line discharge transistor during a read operation, the third voltage is determined as the limit voltage.

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