On-chip transformer of PCB technology and modeling method thereof

Abstract

The invention provides an on-chip transformer of a PCB technology and a modeling method thereof, and the on-chip transformer comprises a primary side coil, a surface dielectric layer is arranged outside a first layer of a PCB, and the primary side coil is electrically connected with a primary side input point and a primary side output point of the surface dielectric layer through conductive through holes; the secondary side coil is arranged on the last layer of the PCB and electrically connected with the secondary side input point and the secondary side output point of the surface dielectric layer through conductive through holes, and at least part of the primary side coil and the secondary side coil are arranged in a stacked and spaced mode; the ground shielding coil is arranged in a middle layer between the primary side coil and the secondary side coil, and the ground shielding coil is connected with an external ground wire through a conductive wire; and the middle dielectric layer is used for isolating electrical connection among the primary side coil, the secondary side coil and the ground shielding coil. The problems that in the prior art, the common-mode transient immunity of an on-chip transformer is low, and coupling of an internal coil by external electromagnetic interference easily affects the on-chip transformer are solved.

Description

Technical Field

[0001] The present invention relates to the technical field of on-chip transformers, and in particular to an on-chip transformer in a PCB process and a modeling method thereof. Background Art

[0002] An on-chip transformer is a transformer integrated on a chip. It can essentially be seen as two mutually coupled inductors. It achieves signal or power transmission through magnetic coupling and plays an important role in modern electronic systems.

[0003] Isolation driver ICs are widely used in photovoltaic inverters, energy storage systems, wind power, new energy vehicles, and industrial relays. Through their isolation and shielding capabilities, they effectively prevent voltage spikes and ground loops between low-voltage areas (such as microcontrollers) and high-voltage areas (such as gate drivers), ensuring reliable and secure communication across all voltage levels in the system. Development of isolation driver ICs focuses primarily on reducing manufacturing costs (e.g., process, area, and packaging) and improving performance (e.g., power consumption, latency, and isolation level). Magnetic induction coupling is suitable for power transmission, offering advantages such as high isolation levels, compact integration, fast transmission speeds, and low power consumption. On-chip transformers (OCTs) are key components for implementing magnetic induction coupling. Silicon-based OCTs offer a dielectric strength of up to 850 V / µm, but they occupy a large area. Self-assembly and other methods are also being researched for on-chip transformers, while the use of mature PCB processes can achieve both high isolation levels and low costs. Common-mode transient immunity (CMTI) is a key parameter for evaluating isolated driver chips. It refers to the isolator's ability to maintain correct signal output under rapid voltage changes (dV / dt). This parameter is particularly important for fast-switching power supply equipment. Related technologies do not have high CMTI, and the coupling of external electromagnetic interference (EMI) to the internal coil can easily affect the on-chip transformer. Summary of the Invention

[0004] The purpose of the present invention is to overcome the above-mentioned technical deficiencies and provide an on-chip transformer for PCB process and a modeling method thereof, so as to solve the technical problems in the prior art of low common-mode transient immunity (CMTI) of on-chip transformers and the easy influence of external electromagnetic interference (EMI) on the coupling of internal coils on the on-chip transformer.

[0005] To achieve the above technical objectives, in a first aspect, the technical solution of the present invention provides an on-chip transformer in a PCB process, comprising: A primary coil is disposed on the first layer of the PCB board. A surface dielectric layer is further disposed outside the first layer of the PCB board. The primary coil is electrically connected to a primary input point and a primary output point of the surface dielectric layer through conductive through-holes. a secondary coil disposed on the last layer of the PCB, the secondary coil being electrically connected to a secondary input point and a secondary output point of the surface dielectric layer via conductive vias, and the primary coil being at least partially stacked and spaced apart from the secondary coil; a ground shielding coil disposed in an intermediate layer between the primary coil and the secondary coil, the ground shielding coil being connected to an external ground wire via a conductive pass, the ground shielding coil being used to shield the electric field strength caused by the transient common-mode voltage and to derive eddy currents generated by the transient common-mode voltage; The intermediate dielectric layer is provided between the primary coil, the secondary coil and the ground shielding coil, and is used to isolate the electrical connection between the primary coil, the secondary coil and the ground shielding coil.

[0006] Compared with the prior art, the present invention has the following beneficial effects: In the present invention, the primary coil will excite the intersection magnetic field under the action of high-frequency alternating voltage, and the secondary coil can sense the magnetic field and generate a corresponding alternating current. The magnetic core layer will improve the magnetic field confinement, thereby improving the coupling efficiency. The dielectric layer provides a three-dimensional structure while also separating the primary coil and the secondary coil to prevent typical interconnection. The ground shielding layer can reduce the interference of common-mode signals by constructing an electric field shield. The ground shielding layer constructs a conductive and grounded shielding layer between the primary coil and the secondary coil, which can effectively intercept and reflect the electric field generated by the transient common-mode voltage of the primary coil, thereby preventing the common-mode electric field signal from propagating to the secondary coil, and does not affect the transmission of the differential-mode electric field signal. Specifically, the ground shielding layer acts as a reference surface, so that the common-mode current formed by the interfering electric field is grounded through the shielding layer, thereby reducing the coupling and interference of the common-mode signal in the system and improving the anti-interference ability of the system. The conductive through-hole provides a three-dimensional typical interconnection channel for the planar metal pattern. This structure ultimately realizes the transformer function of high-frequency operation and is used to isolate the driver chip. The present invention adds a ground shield layer to improve CMTI, which can achieve a common-mode rejection effect of 500V / ns, and the maximum common-mode rejection voltage can reach 2000V. The present invention adds a surface dielectric layer to further isolate the coil from the external environment and reduce the coupling of external electromagnetic interference (EMI) to the internal coil.

[0007] According to some embodiments of the present invention, the present invention further includes: a magnetic core layer, which is arranged on the outer surface of the PCB board corresponding to the positions of the primary coil and the secondary coil, and the magnetic core layer is used to improve coupling efficiency.

[0008] According to some embodiments of the present invention, a first conductive through-hole is provided on the outside of the primary coil, the outer wire of the primary coil is directly connected to the first conductive through-hole, a second conductive through-hole is provided in the vicinity of the first conductive through-hole, and a third conductive through-hole is provided on the inside of the primary coil, and the second conductive through-hole and the third conductive through-hole are electrically connected by a wire in a middle layer of the PCB.

[0009] According to some embodiments of the present invention, a fourth conductive via is provided on the outside of the secondary coil, the outer line of the secondary coil is directly connected to the fourth conductive via, a fifth conductive via is provided near the fourth conductive via, and a sixth conductive via is provided on the inside of the secondary coil, and the fifth conductive via and the sixth conductive via are electrically connected through a wire on a middle layer of the PCB.

[0010] According to some embodiments of the present invention, the number of the ground shielding coils is any value from 0 to 10, and the shapes of the ground shielding coils include spiral isolation type, serpentine segmented type, and ring segmented type.

[0011] According to some embodiments of the present invention, the shapes of the primary coil and the secondary coil include: spiral, serpentine, sawtooth, zigzag, and ring.

[0012] According to some embodiments of the present invention, the material of the magnetic core layer is any one of iron oxide, manganese-zinc ferrite, nickel-zinc ferrite, iron powder, and sendust.

[0013] According to some embodiments of the present invention, the inner circle areas of the primary coil and the secondary coil of the PCB board are provided with a plurality of through holes, and further include: a magnetic core layer, which is provided in the through holes.

[0014] In a second aspect, the present invention provides a modeling and simulation method for an on-chip transformer, which is applied to an on-chip transformer of a PCB process as described in any one of the first aspects, comprising the steps of: Define the two-dimensional shape and position of the primary coil, secondary coil, ground shield, conductive vias, dielectric layer, and magnetic core layer of the on-chip transformer; drawing a three-dimensional diagram based on shapes and positions of components of the on-chip transformer; Call the 3D structure in the finite element simulation tool, add corresponding material parameters for different structures, set the excitation source, boundary conditions, electrical connection relationship, meshing parameters, etc., submit the simulation, and obtain the Z parameter results of different ports; According to the value of Z parameter, calculate the corresponding self-inductance coefficient, mutual inductance coefficient, coupling efficiency, equivalent resistance and quality factor; A Spice simulation is performed using an equivalent circuit based on the self-inductance, the mutual inductance, the coupling efficiency, the equivalent resistance, and the quality factor.

[0015] According to some embodiments of the present invention, material parameter settings include dielectric constant, magnetic permeability, electrical conductivity, and loss tangent, which are used to accurately describe the electromagnetic properties of the material; the excitation source is set to any one of port excitation, surface excitation, or waveguide excitation, and the input signal type and power or voltage are defined; Boundary conditions include radiation boundaries, perfect electric conductors (PECs), and perfectly matched layers (PMLs). Boundary conditions are used to simulate actual electromagnetic environments and limitations. The electrical connection relationship ensures the correct electrical connection between different structures by setting contacts, gaps and interfaces; Meshing parameters include adaptive mesh refinement, maximum and minimum cell sizes, and segment density. Meshing parameters affect simulation accuracy and computational efficiency.

[0016] According to some embodiments of the present invention, the corresponding self-inductance coefficient, mutual inductance coefficient, coupling efficiency, equivalent resistance, and quality factor are calculated. The formula for the self-inductance coefficient L is as follows: where Z 11 is the 11 components of the Z parameter, and f is the frequency; The formula for mutual inductance M is as follows: where Z 12 is the 12-component of the Z parameter, and the formula for the coupling coefficient K is as follows: Where L1 and L2 are the self-inductance coefficients of the primary coil and the secondary coil respectively. The formula for the equivalent resistance R is as follows: The formula for the quality factor Q is as follows: .

[0017] Additional aspects and advantages of the present invention will be set forth in part in the description which follows and, in part, will be obvious from the description which follows, or may be learned by practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The above and / or additional aspects and advantages of the present invention will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, wherein the abstract drawing is identical to one of the drawings in the specification: Figure 1 A structural diagram of an on-chip transformer provided by one embodiment of the present invention; Figure 2 A structural diagram of an on-chip transformer with a dielectric layer removed provided by one embodiment of the present invention; Figure 3 A structural diagram of an on-chip transformer provided by an embodiment of the present invention with the dielectric layer removed in another direction; Figure 4 A structural diagram of an on-chip transformer including a magnetic core layer provided in one embodiment of the present invention; Figure 5 A structural diagram of an on-chip transformer provided by one embodiment of the present invention, wherein the dielectric layer is removed and the magnetic core layer is included; Figure 6 A structural diagram of an on-chip transformer provided by one embodiment of the present invention, in which the dielectric layer is removed from another direction and a magnetic core layer is included; Figure 7 A schematic diagram of the ground shielding structure of an on-chip transformer provided by one embodiment of the present invention; Figure 8 A diagram showing a ground shielding layer pattern of an on-chip transformer provided in one embodiment of the present invention; Figure 9 A spice model of an on-chip transformer provided in one embodiment of the present invention; Figure 10 A schematic diagram of magnetic flux lines of an on-chip coil of an on-chip transformer provided by one embodiment of the present invention; Figure 11 A flowchart of a modeling and simulation method for an on-chip transformer provided by one embodiment of the present invention; Figure 12 Calculation results of the physical parameters (self-inductance L, quality factor Q, coupling coefficient K, equivalent resistance R) of the on-chip transformer example in the present invention are shown in FIG.

[0019] Explanation of the accompanying drawings: magnetic core layer 11, dielectric layer 12, conductive through-hole 13, first conductive through-hole 131, second conductive through-hole 132, third conductive through-hole 133, fourth conductive through-hole 134, fifth conductive through-hole 135, sixth conductive through-hole 136, primary coil 14, ground shielding coil 15, secondary coil 16. DETAILED DESCRIPTION

[0020] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0021] It should be noted that although the system diagrams illustrate functional module divisions and the flowcharts illustrate logical sequences, in certain circumstances, the steps shown or described may be performed in a sequence that differs from the module divisions in the system or the sequence in the flowcharts. The terms "first," "second," and so on, in the specification, claims, and drawings, are used to distinguish similar items and are not necessarily used to describe a specific sequence or precedence.

[0022] Reference Figures 1 to 10 , Figure 1 A structural diagram of an on-chip transformer provided by one embodiment of the present invention; Figure 2 A structural diagram of an on-chip transformer with a dielectric layer removed provided by one embodiment of the present invention; Figure 3 A structural diagram of an on-chip transformer provided by an embodiment of the present invention with the dielectric layer removed in another direction; Figure 4 A structural diagram of an on-chip transformer including a magnetic core layer provided in one embodiment of the present invention; Figure 5 A structural diagram of an on-chip transformer provided by one embodiment of the present invention, wherein the dielectric layer is removed and the magnetic core layer is included; Figure 6 A structural diagram of an on-chip transformer provided by one embodiment of the present invention, in which the dielectric layer is removed from another direction and a magnetic core layer is included; Figure 7 A schematic diagram of the ground shielding structure of an on-chip transformer provided by one embodiment of the present invention; Figure 8 A diagram showing a ground shielding layer pattern of an on-chip transformer provided in one embodiment of the present invention; Figure 9 A spice model of an on-chip transformer provided in one embodiment of the present invention; Figure 10 A schematic diagram of magnetic flux lines of an on-chip coil of an on-chip transformer provided by one embodiment of the present invention.

[0023] In one embodiment, the on-chip transformer of the PCB process includes: a primary coil 14, which is arranged on the first layer of the PCB board, and a surface dielectric layer 12 is further arranged outside the first layer of the PCB board, and the primary coil 14 is electrically connected to the primary input point and the primary output point of the surface dielectric layer 12 through a conductive through-hole 13; a secondary coil 16, which is arranged on the last layer of the PCB board, and the secondary coil 16 is electrically connected to the secondary input point and the secondary output point of the surface dielectric layer 12 through a conductive through-hole 13, and the primary coil 14 is at least partially connected to the secondary coil 1 6 stacked and spaced apart; a ground shielding coil 15 is arranged in the middle layer between the primary coil 14 and the secondary coil 16, and the ground shielding coil 15 is connected to the external ground wire through a conductive through, and the ground shielding coil 15 is used to shield the electric field strength caused by the transient common mode voltage and derive the eddy current generated by the transient common mode voltage; an intermediate dielectric layer 12 is arranged between the primary coil 14, the secondary coil 16 and the ground shielding coil 15, and the intermediate dielectric layer 12 is used to isolate the electrical connection between the primary coil 14, the secondary coil 16 and the ground shielding coil 15.

[0024] This application adopts an on-chip transformer design using PCB technology. Through layered layout, shielding structure and dielectric isolation design, it has significant advantages in electromagnetic compatibility, parasitic parameter suppression, integration and process compatibility.

[0025] The present application improves electromagnetic compatibility and anti-interference capabilities. The electric field shielding effect of the ground shielding coil 15 suppresses common-mode interference and optimizes eddy current losses. The ground shielding coil 15 is grounded through the conductive through-hole 13, forming a low-impedance path. This effectively shields the electric field coupling between the primary and secondary sides caused by transient common-mode voltage (such as displacement current caused by parasitic capacitance), reducing the transmission of common-mode noise to the secondary circuit. The shielding layer guides the eddy currents generated by the transient common-mode voltage into the ground, preventing the eddy currents from causing additional losses or interference in unintended paths (such as the substrate or other layers). This is particularly suitable for high-frequency switching power supplies or signal transmission scenarios.

[0026] The present invention also achieves excellent results in balanced magnetic field coupling control. The primary and secondary coils 16 are partially stacked, ensuring mutual inductance while isolating unnecessary electric field coupling through the shielding layer, making magnetic field coupling the dominant path for energy transmission and improving the transformer's transmission efficiency and signal purity. The present invention also achieves excellent results in parasitic parameter suppression and performance optimization, such as reducing interlayer parasitic capacitance. The intermediate dielectric layer 12 (e.g., FR-4, PP, or a low-dielectric-constant dielectric) isolates the primary and secondary coils 16 from the ground shield coil 15, significantly reducing parasitic capacitance between the coils, lowering the capacitive shunting effect at high frequencies and broadening the transformer's operating bandwidth. The surface dielectric layer 12 further isolates the coils from the external environment, reducing the coupling of external electromagnetic interference (EMI) to the internal coils. The stacked layout design tightly couples the primary and secondary coils 16, reducing leakage inductance and increasing the proportion of magnetizing inductance, thereby minimizing leakage losses during energy transmission (such as voltage spikes caused by leakage inductance in switching power supplies). Although the ground shielding coil 15 adds a small amount of parasitic capacitance, reasonable design (such as opening or grid structure) can avoid the formation of a complete eddy current ring, prevent the shielding layer itself from generating hysteresis or eddy current loss, and balance the shielding effect and energy loss.

[0027] This application utilizes full PCB process integration, effectively reducing costs. The primary and secondary coils 16, as well as the ground shield coil 15, are all fabricated using standard PCB processes (such as multi-layer lamination and through-hole plating), eliminating the need for additional chip manufacturing processes (such as metal deposition or etching in semiconductor manufacturing). This makes it compatible with existing PCB production lines, reducing manufacturing costs and complexity. Conductive vias 13 enable electrical connections between layers, utilizing a mature and reliable process suitable for large-scale mass production. This application boasts a compact structure and is suitable for multi-layer board designs. By utilizing the multiple layers of PCB space (first, middle, and last layers) to achieve a three-dimensional layout, it saves more space than a flat spiral structure and is particularly suitable for high-density integrated modular systems (such as power modules and RF front-ends). The primary and secondary input and output points on the surface dielectric layer 12 can be directly soldered to PCB surface components (such as capacitors and chip pins), simplifying the packaging and wiring process. Connections to the primary and secondary coils 16, as well as the ground shield coil 15, can be made to external circuits using a single-sided operation on the surface dielectric layer 12, providing exceptional convenience and simple wiring. The intermediate dielectric layer 12 and surface dielectric layer 13 of this application provide physical insulation, meeting safety isolation requirements (such as high- and low-voltage circuit isolation) and preventing the risk of interlayer breakdown. This makes it particularly suitable for high-reliability applications such as industrial and automotive electronics. The shielding layer, combined with the grounding system, suppresses interference from external electromagnetic fields (such as motors and radio frequency signals) on the transformer, improving system stability in complex electromagnetic environments.

[0028] This application utilizes layered shielding, dielectric isolation, and PCB process integration to improve electromagnetic compatibility and performance while balancing cost, reliability, and process feasibility. It is particularly suitable for mid- and high-frequency applications where size, cost, and anti-interference capabilities are critical. In actual optimization, further adjustments can be made to the coil stack area, shielding layer structure (e.g., honeycomb or strip), and dielectric material parameters to balance mutual inductance, parasitic parameters, and shielding efficiency.

[0029] Furthermore, it also includes: a magnetic core layer 11, which is arranged on the outer surface of the PCB board corresponding to the position of the primary coil 14 and the secondary coil 16. The material of the magnetic core layer 11 is any one of iron oxide, manganese-zinc ferrite, nickel-zinc ferrite, iron powder, and sendust. The magnetic core layer 11 is used to improve the coupling efficiency. The magnetic core layer 11 (such as manganese-zinc ferrite, magnetic permeability can reach thousands) provides a low magnetic resistance path for the magnetic field, so that the magnetic lines of force generated by the primary coil 14 pass through the secondary coil 16 more concentratedly, significantly improving the mutual inductance coefficient ( ). Formula derivation: Mutual inductance ( is the coupling coefficient), the core reduces the leakage flux (increases ) and increase self-inductance ( ), dual effect improves , thereby enhancing energy transmission efficiency.

[0030] Furthermore, the inner circle area of the primary coil 14 and the secondary coil 16 of the PCB board is provided with a plurality of through holes, and further includes: a magnetic core layer 11, which is provided in the through holes. The through holes are located in the inner circle of the coil (magnetic flux intensive area), and after the magnetic core is filled, a closed or semi-closed magnetic circuit is formed, guiding the magnetic lines of force generated by the primary coil 14 to be directly coupled to the secondary coil 16 through the magnetic core, thereby reducing the magnetic resistance of the air gap. Compared with the surface mounted magnetic core, the magnetic core in the through hole is closer to the center of the coil, shortening the length of the magnetic circuit ( ), according to the magnetoresistance formula , the magnetic resistance is significantly reduced, and the mutual inductance coefficient ( The magnetic core in the inner coil forms a "magnetic column" structure, which confines leakage flux to the core, preventing it from spreading to other PCB layers or external circuits. This is particularly suitable for high-density layouts with multiple transformers in parallel, such as power module arrays.

[0031] The magnetic core is embedded in the through-hole, eliminating the need for PCB surface or additional layers. This makes it particularly suitable for thin PCBs with limited layer counts (such as 2-4 layer boards). For example, in a mobile phone power module, the magnetic core can be integrated into the via hole in the coil overlap area, reducing the overall thickness by over 30%.

[0032] Through holes can be achieved through existing PCB drilling and electroplating processes, and the core filling can be fixed with patch glue or hot pressing processes, without the need for new equipment. For example: first drill a through hole to form a through hole, and then insert a prefabricated magnetic core column (such as a cylindrical ferrite); or mix the magnetic core powder with the dielectric material before lamination to form an integrated magnetic core layer 11. After the magnetic core is embedded in the through hole, it is surrounded by the coil and the dielectric layer 12, forming a mechanical locking structure, which avoids the risk of traditional surface magnetic cores falling off due to vibration, and is suitable for harsh environments such as automotive electronics and industrial equipment. If the magnetic core material has thermal conductivity (such as a metal magnetic powder core), it can be connected to the heat dissipation copper layer inside the PCB through the through hole to conduct the heat generated by the core loss to the external heat sink, thereby alleviating the temperature rise problem at high frequencies.

[0033] Furthermore, a first conductive via 131 is provided on the outside of the primary coil 14, and the outer wire of the primary coil 14 is directly connected to the first conductive via 131. A second conductive via 132 is provided adjacent to the first conductive via 131. A third conductive via 133 is provided on the inside of the primary coil 14, and the second conductive via 132 and the third conductive via 133 are electrically connected via a wire on a middle layer of the PCB. A fourth conductive via 134 is provided on the outside of the secondary coil 16, and the outer wire of the secondary coil 16 is directly connected to the fourth conductive via 134. A fifth conductive via 135 is provided adjacent to the fourth conductive via 134. A sixth conductive via 136 is provided on the inside of the secondary coil 16, and the fifth conductive via 135 and the sixth conductive via 136 are electrically connected via a wire on a middle layer of the PCB. The innovative structure of multiple via interconnects and intermediate layer conductors achieves low loss, high symmetry, and strong noise immunity without significantly increasing process complexity. This is a key technology in the evolution of on-chip transformers from "functional integration" to "performance optimization." This design provides an effective solution for balancing electrical performance, reliability, and cost, particularly in high-density, high-frequency electronic systems.

[0034] In one embodiment, the primary coil 14 is located in the first layer, which is wrapped with a dielectric layer 12. The primary coil 14 has two connection points, input and output, in the layer. Each connection point is connected to the pad of the uppermost dielectric layer 12 through the metal in the customized conductive through-hole 13. The primary coil 14 is connected to the external signal input, which belongs to the electromagnetic induction generation and transmission structure; the secondary coil 16 is located in the lower layer, which has two connection points, input and output, in the layer. Each connection point is connected to the pad of the uppermost layer through the metal in the customized conductive through-hole 13. The secondary coil 16 is connected to the external signal output, which belongs to the electromagnetic induction receiving structure; the conductive through-hole 13 is a circular or directional through-hole formed by deep etching, in which a conductive material is poured; therefore, the conductive through-hole 13 is electrically connected to the primary coil 14 and the secondary coil 16 internally, and is connected to the input and output ports externally; the shape of the coil includes but is not limited to spiral (including circular, square and polygonal spirals), serpentine (sawtooth or zigzag), ring and three-dimensional structure; The ground shield (i.e., ground shield coil 15) is located in the center, shielding the electric field strength caused by transient common-mode voltage, improving the device's common-mode voltage suppression capability, achieving a maximum common-mode voltage suppression of 2000V and a common-mode voltage rise rate of 500V / ns. The ground shield has only one connection point within the layer, electrically connected internally via a custom conductive via 13. It is also connected externally to ground, dissipating eddy currents generated by transient common-mode voltage. The ground shield can be formed into various shapes, including spiral isolation, serpentine segmented, and annular segmented. The dielectric layer 12 is insulating, preventing electrical communication between the primary coil 14 and the secondary coil 16. The ground shield forms a grounded metal structure, thus creating a Faraday shield. The electric field from the primary coil 14 is primarily intercepted by the ground shield.

[0035] Therefore, during common-mode voltage transients, the displacement current caused by capacitive coupling will be directed to the ground through the ground shield, thereby reducing interference with the output signal; the magnetic core layer 11 with higher magnetic permeability can improve coupling efficiency. The primary coil 14 and the secondary coil 16 are both made of one of gold, silver, copper, iron, and an alloy. Preferably, the material is copper. The coil pattern is a periodically wound metal pattern, and the line width, line spacing, thickness, number of turns, overall length, and width of the pattern can all be adjusted. The dielectric layer 12 is one of FR4, PI, PDMS, SU8, photoresist, PET, PMMA, PVA, PEN, paper, and textile materials. Preferably, the dielectric layer 12 is FR4.

[0036] The ground shielding layer is sandwiched between the primary coil 14 and the secondary coil 16. The number of ground shielding layers can be any value from 0 to 10. Preferably, the number of ground shielding layers is 4. The distance between the ground shielding layer and the upper and lower layers can be adjusted, and the specific parameters are determined according to the values obtained by the modeling method. The pattern of the ground shielding layer is a metal pattern that is not a complete loop. Because it is necessary to reduce the eddy current effect, the line width, line spacing, thickness, number of turns, overall length and width of the pattern can be adjusted. The magnetic core layer 11 is one of iron oxide, manganese-zinc ferrite, nickel-zinc ferrite, iron powder, iron silicon aluminum, etc. Preferably, the magnetic core layer 11 is iron oxide. The magnetic core layer 11 is arranged on the surface and belongs to the post-processing process. The process is mature and simple, and no major changes to the current process are required. The conductive through hole 13 is one of gold, silver, copper, iron, and alloy. Preferably, the material is copper.

[0037] Working Principle: The primary coil 14, under the action of a high-frequency alternating voltage, excites an intersection magnetic field. The secondary coil 16 senses this field and generates a corresponding alternating current. The magnetic core layer 11 enhances magnetic field confinement, thereby improving coupling efficiency. The dielectric layer 12 provides a three-dimensional structure while also separating the primary coil 14 and the secondary coil 16, preventing typical interconnection. The ground shield layer, by providing an electric field shield, can reduce interference from common-mode signals. By creating a conductive and grounded shielding layer between the primary coil 14 and the secondary coil 16, the ground shield layer effectively intercepts and reflects the electric field generated by the transient common-mode voltage of the primary coil 14, thereby preventing the common-mode electric field signal from propagating to the secondary coil 16, while not affecting the transmission of differential-mode electric field signals. Specifically, the ground shield layer acts as a reference plane, allowing the common-mode current generated by the interfering electric field to be grounded through the shield layer, thereby reducing coupling and interference of common-mode signals in the system and improving the system's anti-interference capability. The conductive via 13 provides a three-dimensional typical interconnection channel for the planar metal pattern. This structure ultimately realizes the function of a high-frequency transformer, used to isolate the driver chip.

[0038] Reference Figure 11 、 12 , Figure 11 A flowchart of a modeling and simulation method for an on-chip transformer provided by one embodiment of the present invention; Figure 12 Calculation results of the physical parameters (self-inductance L, quality factor Q, coupling coefficient K, equivalent resistance R) of the on-chip transformer example in the present invention are shown in FIG.

[0039] In one embodiment, a modeling and simulation method for an on-chip transformer is applied to an on-chip transformer of a PCB process as described above, and is characterized in that it includes the steps of: defining the two-dimensional shape and position of a primary coil, a secondary coil, a ground shield layer, a conductive via, a dielectric layer, and a magnetic core layer of the on-chip transformer; drawing a three-dimensional diagram based on the shape and position of the components of the on-chip transformer; calling the three-dimensional structure in a finite element simulation tool, adding corresponding material parameters for different structures, setting the excitation source, boundary conditions, electrical connection relationships, meshing parameters, etc., submitting the simulation, and obtaining Z parameter results of different ports; calculating the corresponding self-inductance, mutual inductance, coupling efficiency, equivalent resistance, and quality factor based on the value of the Z parameter; and performing Spice simulation using an equivalent circuit based on the self-inductance, the mutual inductance, the coupling efficiency, the equivalent resistance, and the quality factor.

[0040] Among them, the material parameter settings include dielectric constant, magnetic permeability, electrical conductivity and loss tangent, which are used to accurately describe the electromagnetic properties of the material; the excitation source is set to any one of port excitation, surface excitation or waveguide excitation, defining the input signal type and power or voltage; boundary conditions include radiation boundary, perfect electric conductor (PEC), and perfectly matched layer (PML), and the boundary conditions are used to simulate the actual electromagnetic environment and restrictions; the electrical connection relationship ensures the correct electrical connection between different structures by setting contact, gap and interface; the meshing parameters include adaptive mesh refinement, maximum and minimum unit size and segment density, and the meshing parameters affect the simulation accuracy and computational efficiency.

[0041] The device structure is defined based on the structure described above. The structure of the present invention has the advantages of high magnetic coupling efficiency and low operating frequency, so this structure is selected. CAD software is usually used to draw multi-layer CAD drawings. The two-dimensional shape and position of the primary coil, secondary coil, ground shield layer, conductive through hole, dielectric layer, magnetic core layer, etc. are defined by layer-by-layer drawing. For example, the primary coil and secondary coil are made of copper material with a thickness of 5um, a line width of 10um, 5 turns, and a line spacing of 5um; the ground shield layer is made of Figure 4 The pattern is copper, 10µm thick, 10µm line width, 6 turns, and 10µm spacing. The dielectric layer uses FR4 material, and the core layer uses ferromagnetic concentrator material, covering the surface of the dielectric layer. The conductive vias are positioned according to the connection points of each layer to avoid overlap and improper electrical interconnection. To create a 3D structure, based on the multi-layer CAD drawing, interlayer thickness signals and interlayer relative position signals are added. For example, the spacing between the coil and the ground shield is set to 50µm, and the spacing between the primary and secondary coils is set to 300µm.

[0042] Finite element simulation Z parameters involve calling a three-dimensional structure within the finite element simulation tool, adding corresponding material parameters for each structure, setting the excitation source, boundary conditions, electrical connection relationships, meshing parameters, etc., submitting the simulation, and obtaining Z parameter results for different ports. Material parameter settings include dielectric constant, magnetic permeability, electrical conductivity, and loss tangent, which are used to accurately describe the electromagnetic properties of the material; the excitation source can be set to port excitation, surface excitation, or waveguide excitation, defining the input signal type and power or voltage; boundary conditions include radiation boundaries, perfect electric conductors (PECs), and perfectly matched layers (PMLs) to simulate actual electromagnetic environments and limitations; electrical connection relationships ensure correct electrical connections between different structures by setting contacts, gaps, and interfaces; meshing parameters include adaptive mesh refinement, maximum and minimum cell sizes, and segment density, which affect simulation accuracy and computational efficiency.

[0043] The Z parameters (impedance parameters) of the on-chip transformer are a set of complex impedances that describe the characteristics of its port network and are used to characterize the relationship between the voltage and current at each port. In a two-port network model, the Z parameters are expressed in matrix form as follows: in: 1. Definition: When port 2 is open ( ), the input impedance of port 1 is Physical meaning: The self-impedance of port 1 is composed of the DC resistance, leakage inductance, and magnetizing reactance (related to core coupling) of the primary coil.

[0044] In on-chip transformers, due to process limitations (such as silicon substrate loss and coil parasitic capacitance), The effects of parasitic parameters may also be included.

[0045] 2. Definition: When port 1 is open ( ), the reverse transfer impedance from port 2 to port 1 is Physical meaning: o It reflects the coupling effect of the current at port 2 on the voltage at port 1 and reflects the mutual inductance characteristics of the transformer.

[0046] Ideally, (reciprocity), but the actual on-chip transformer may be affected by process asymmetry (such as coil layout differences and uneven substrate loss). But not exactly equal.

[0047] Supplementary Notes Other parameters: : Forward transfer impedance from port 1 to port 2 (similar to , but in the opposite direction).

[0048] : Input impedance of port 2 (when port 1 is open).

[0049] Special features of on-chip transformer: Limited by the chip size, the number of coil turns is small, and the mutual inductance coefficient is low, resulting in Smaller than the theoretical value of an ideal transformer.

[0050] Parasitic parameters (such as inter-coil capacitance and substrate eddy current loss) will make the Z parameter frequency-dependent. At high frequencies, the changes in the real part (loss) and imaginary part (reactance) of the complex impedance need to be considered.

[0051] Deriving physical parameters means calculating the corresponding self-inductance, mutual inductance, coupling efficiency, equivalent resistance, quality factor, etc. based on the value of the Z parameter. For example, the formula for the self-inductance L is as follows: where Z 11 is the 11th component of the Z parameter, and f is the frequency. The formula for the mutual inductance coefficient M is as follows: where Z 12 is the 12-component of the Z parameter, and the formula for the coupling coefficient K is as follows: Where L1 and L2 are the self-inductance coefficients of the primary coil and the secondary coil respectively. The formula for the equivalent resistance R is as follows: The formula for the quality factor Q is as follows: Therefore, the calculation results of the example are as follows Figure 6 As shown in Figure 2, the physical parameter values under different frequency conditions can be obtained. The equivalent circuit used in Spice simulation is as follows: Figure 3 As shown, this equivalent circuit can be used to carry out circuit-level simulation.

[0052] The preparation and testing of devices is to use multi-layer CAD drawings to guide the processing of PCB boards, obtain the actual on-chip transformer, and test it. The test results are compared with the simulation results obtained by SPICE simulation, and the simulation parameters are optimized to achieve almost convergence.

[0053] Working principle: By carrying out the stages of defining device structure, drawing multi-layer CAD drawings, establishing three-dimensional structure, finite element simulation Z parameters, exporting physical parameters, spice simulation, device preparation and testing in a step-by-step manner, the on-chip transformer with corresponding physical parameters can be scientifically obtained, which is of great significance for production guidance.

[0054] The memory, as a non-transient computer-readable storage medium, can be used to store non-transient software programs and non-transient computer executable programs. In addition, the memory may include a high-speed random access memory and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some embodiments, the memory may optionally include a memory remotely located relative to the processor, and these remote memories may be connected to the processor via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0055] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate and may be located in one place or distributed across multiple network units. Some or all of the modules may be selected based on actual needs to achieve the objectives of this embodiment.

[0056] In addition, an embodiment of the present invention also provides a computer-readable storage medium, which stores computer-executable instructions. The computer-executable instructions are executed by a processor or controller, for example, by a processor in the above-mentioned terminal embodiment, so that the above-mentioned processor can execute the modeling and simulation method of the on-chip transformer in the above-mentioned embodiment.

[0057] Those skilled in the art will appreciate that all or some of the steps and systems disclosed above can be implemented as software, firmware, hardware, or any suitable combination thereof. Some or all of the physical components may be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on computer-readable media, which may include computer storage media (or non-transitory media) and communication media (or transient media). As is well known to those skilled in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information, such as computer-readable instructions, data structures, program modules, or other data. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disks (DVDs) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store the desired information and can be accessed by a computer. Furthermore, as is well known to those skilled in the art, communication media typically embodies computer-readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

[0058] The above is a specific description of the preferred implementation of the present invention, but the present invention is not limited to the above implementation. Those skilled in the art can make various equivalent modifications or substitutions without violating the spirit of the present invention. These equivalent modifications or substitutions are all included in the scope defined by the claims of the present invention.

[0059] The specific embodiments of the present invention described above do not limit the scope of protection of the present invention. Any other corresponding changes and modifications made based on the technical concept of the present invention should be included in the scope of protection of the claims of the present invention.

Claims

1. A PCB process on-chip transformer, characterized in that: include: A primary coil is disposed on the first layer of the PCB board. A surface dielectric layer is further disposed outside the first layer of the PCB board. The primary coil is electrically connected to a primary input point and a primary output point of the surface dielectric layer through conductive through-holes. a secondary coil disposed on the last layer of the PCB, the secondary coil being electrically connected to a secondary input point and a secondary output point of the surface dielectric layer via conductive vias, and the primary coil being at least partially stacked and spaced apart from the secondary coil; a ground shielding coil disposed in an intermediate layer between the primary coil and the secondary coil, the ground shielding coil being connected to an external ground wire via a conductive pass, the ground shielding coil being used to shield the electric field strength caused by the transient common-mode voltage and to derive eddy currents generated by the transient common-mode voltage; The intermediate dielectric layer is provided between the primary coil, the secondary coil and the ground shielding coil, and is used to isolate the electrical connection between the primary coil, the secondary coil and the ground shielding coil.

2. The on-chip transformer of a PCB process according to claim 1, characterized in that: It also includes: a magnetic core layer, which is arranged on the outer surface of the PCB board corresponding to the position of the primary coil and the secondary coil. The material of the magnetic core layer is any one of iron oxide, manganese-zinc ferrite, nickel-zinc ferrite, iron powder, and sendust. The magnetic core layer is used to improve the coupling efficiency.

3. The on-chip transformer of a PCB process according to claim 1, characterized in that: The inner circle areas of the primary coil and the secondary coil of the PCB board are provided with a plurality of through holes, and further include: a magnetic core layer, which is provided in the through holes.

4. The on-chip transformer of a PCB process according to claim 1, characterized in that: A first conductive through-hole is provided on the outside of the primary coil, the outer line of the primary coil is directly connected to the first conductive through-hole, a second conductive through-hole is provided adjacent to the first conductive through-hole, and a third conductive through-hole is provided on the inside of the primary coil, and the second conductive through-hole and the third conductive through-hole are electrically connected by a wire on a middle layer of the PCB.

5. The on-chip transformer of a PCB process according to claim 1, characterized in that: A fourth conductive through-hole is provided on the outside of the secondary coil, the outer line of the secondary coil is directly connected to the fourth conductive through-hole, a fifth conductive through-hole is provided near the fourth conductive through-hole, and a sixth conductive through-hole is provided on the inside of the secondary coil, and the fifth conductive through-hole and the sixth conductive through-hole are electrically connected through a wire on a middle layer of the PCB.

6. The on-chip transformer of a PCB process according to claim 1, characterized in that: The number of the ground shielding coils is any value from 0 to 10, and the shapes of the ground shielding coils include: spiral isolation type, serpentine segmented type, and ring segmented type.

7. The on-chip transformer of a PCB process according to claim 1, characterized in that: The shapes of the primary coil and the secondary coil include spiral, serpentine, sawtooth, zigzag, and ring.

8. A modeling and simulation method for an on-chip transformer, applied to an on-chip transformer of a PCB process according to any one of claims 1 to 7, characterized in that: Including steps: Define the two-dimensional shape and position of the primary coil, secondary coil, ground shield, conductive vias, dielectric layer, and magnetic core layer of the on-chip transformer; drawing a three-dimensional diagram based on shapes and positions of components of the on-chip transformer; Call the 3D structure in the finite element simulation tool, add corresponding material parameters for different structures, set the excitation source, boundary conditions, electrical connection relationship, meshing parameters, submit the simulation, and obtain the Z parameter results of different ports; According to the value of Z parameter, calculate the corresponding self-inductance coefficient, mutual inductance coefficient, coupling efficiency, equivalent resistance and quality factor; A Spice simulation is performed using an equivalent circuit based on the self-inductance, the mutual inductance, the coupling efficiency, the equivalent resistance, and the quality factor.

9. The on-chip transformer modeling and simulation method according to claim 8, characterized in that: Material parameter settings include dielectric constant, magnetic permeability, electrical conductivity, and loss tangent, which are used to accurately describe the electromagnetic properties of the material. The excitation source is set to any of port excitation, surface excitation, or waveguide excitation, and the input signal type and power or voltage are defined. Boundary conditions include radiation boundaries, perfect electric conductors (PECs), and perfectly matched layers (PMLs). Boundary conditions are used to simulate actual electromagnetic environments and limitations. The electrical connection relationship ensures the correct electrical connection between different structures by setting contacts, gaps and interfaces; Meshing parameters include adaptive mesh refinement, maximum and minimum cell sizes, and segment density. Meshing parameters affect simulation accuracy and computational efficiency.

10. The on-chip transformer modeling and simulation method according to claim 9, characterized in that: Calculate the corresponding self-inductance coefficient, mutual inductance coefficient, coupling efficiency, equivalent resistance, and quality factor. The formula for the self-inductance coefficient L is as follows: where Z 11 is the 11 components of the Z parameter, and f is the frequency; The formula for mutual inductance M is as follows: where Z 12 is the 12-component of the Z parameter, and the formula for the coupling coefficient K is as follows: Where L1 and L2 are the self-inductance coefficients of the primary coil and the secondary coil respectively. The formula for the equivalent resistance R is as follows: The formula for the quality factor Q is as follows: 。

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