Stacked bonding chip manufacturing method with function of accurately controlling silicon thickness reduction of wafer

Abstract

The invention belongs to the field of semiconductor device manufacturing, and particularly relates to a method for manufacturing a stacked and bonded chip with a function of accurately controlling silicon thickness reduction of a wafer, which comprises the following steps before wafer stacking and bonding: when a shallow trench spacer is deposited in an active region preparation process cycle of the wafer; the method comprises the following steps: firstly, micro-depositing a metal material which cannot be penetrated by infrared rays, and then depositing an insulating dielectric layer substance; and measuring the thickness of the shallow trench isolator and the thickness of an external silicon layer of the shallow trench isolator while grinding the shallow trench isolator until the silicon thickness of the wafer falls into a product design range, and stopping etching the shallow trench isolator. According to the invention, accurate silicon thickness measurement and process control can be realized only by optimizing the structure of the wafer.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor device manufacturing, and in particular relates to a method for manufacturing stacked bonded chips with the function of precisely controlling wafer silicon thickness thinning. Background Art

[0002] In addition to process factors, accurate silicon thickness measurement is also a major challenge in controlling silicon thinning thickness. Thinning equipment such as grinding and CMP adjust thinning parameters in real time based on silicon thickness feedback to ensure consistent silicon thickness across different regions. However, current silicon thickness measurement is not very accurate. This is primarily due to the fact that in existing fab processes, processing is almost entirely performed on the film layer above the silicon, requiring less measurement of silicon thickness. Consequently, overall silicon process measurement capabilities are relatively poor. Summary of the Invention

[0003] In view of the problems existing in the prior art, the present invention provides a stacked bonded chip manufacturing method with the function of precisely controlling the thinning of wafer silicon thickness. Before performing wafer stack bonding, the method includes the following steps: Step S1, when depositing shallow trench isolation in the active area preparation process cycle of the wafer, first deposit a small amount of metal material that is not penetrable by infrared rays, and then deposit an insulating dielectric layer material; Step S2, while using an infrared thickness gauge to measure the thickness of the shallow trench isolation and the thickness of the outer silicon layer of the shallow trench isolation, the shallow trench isolation is polished until the wafer silicon thickness falls within the product design range, and then the etching of the shallow trench isolation is stopped, wherein the wafer silicon thickness is the value obtained by adding the thickness of the outer silicon layer of the shallow trench isolation to the thickness of the shallow trench isolation. Preferably, the process flow involves creating the isolation trenches through photolithography and etching, at which point the thickness is measured to be T1. An impenetrable metal material is then deposited, followed by a conventional insulating dielectric layer. Finally, processes such as CMP and pickling are used to remove the surface-filling insulating dielectric material, the infrared-impenetrable metal material, and any other unnecessary layers, such as hard mask layers. Later, during the thinning process, the measured location is directly exposed to the infrared-impenetrable metal material in the STI. The silicon thickness at this point is T2, and the final silicon thickness is T1 + T2.

[0004] Furthermore, preferably, in the above-mentioned stacked bonded chip manufacturing method of the present invention, the deposition thickness of the metal material is 50 Å to 1000 Å.

[0005] Furthermore, preferably, in the above-mentioned stacked bonded chip manufacturing method of the present invention, the deposition thickness of the metal material is 100 Å to 300 Å.

[0006] Furthermore, preferably, in the stacked bonded chip manufacturing method of the present invention, after the shallow trench isolation is filled, the SiO2 and the metal material on the surface are completely ground away by a chemical mechanical polishing process to form a bowl-and-dish morphology.

[0007] In addition, preferably, in the above-mentioned stacked bonded chip manufacturing method of the present invention, it also includes: removing SiN in the shallow trench isolation to complete the active area preparation process cycle.

[0008] Furthermore, preferably, in the stacked bonded chip manufacturing method of the present invention, the material filled in the shallow trench spacer is an insulating material with low infrared absorption and high reflectivity.

[0009] In addition, preferably, in the above-mentioned stacked bonded chip manufacturing method of the present invention, the material filled in the shallow trench isolation is a ceramic material selected from one or more of aluminum oxide (Al2O3), zirconium oxide (ZrO2), and aluminum nitride (AlN).

[0010] By utilizing the present invention, accurate silicon thickness measurement and process control can be achieved by only optimizing the wafer structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 The figure is a schematic diagram of the process flow of bonding first and then TSV in a stacked bonded chip manufacturing method with the function of precisely controlling wafer silicon thickness thinning according to one embodiment of the present invention.

[0012] Figure 2 The figure is a schematic diagram of a backside removal (BVR) process flow of TSV first and bonding later in a stacked bonded chip manufacturing method with a function of precisely controlling wafer silicon thickness thinning according to an embodiment of the present invention.

[0013] Figure 3 This is a diagram showing the lateral etching defect morphology of a notch at the bottom of a TSV in a stacked bonded chip manufacturing method with precise control of wafer silicon thickness thinning according to an embodiment of the present invention. If the thickness is not accurately measured, over-etching will result in a notch at the bottom.

[0014] Figure 4 This diagram illustrates the principle of infrared silicon thickness measurement in a stacked bonded chip manufacturing method with precise control of wafer silicon thinning, according to one embodiment of the present invention. It also demonstrates that, in the original solution, due to the similar properties of light to the dielectric film and silicon, the light cannot accurately distinguish the corresponding interface, and therefore cannot accurately determine the silicon thickness.

[0015] Figure 5It is a process flow diagram of an active area preparation process cycle (shallow trench isolation preparation process cycle) in a stacked bonded chip manufacturing method with a function of precisely controlling wafer silicon thickness thinning according to an embodiment of the present invention.

[0016] Figure 6 It is a process flow diagram of an active area preparation process cycle (shallow trench isolation preparation process cycle) in a stacked bonded chip manufacturing method with a function of precisely controlling wafer silicon thickness thinning according to an embodiment of the present invention.

[0017] Figure 7 It is a schematic diagram of measuring silicon thickness in a stacked bonded chip manufacturing method with a function of precisely controlling wafer silicon thickness thinning according to an embodiment of the present invention. DETAILED DESCRIPTION

[0018] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Other embodiments or modifications derived from the embodiments of this application by ordinary technicians in this field without making any creative work are all within the scope of protection of this application.

[0019] In the advanced packaging process, wafer-level stacking is often involved. After wafer stacking, the wafers are usually thinned and then the TSV process is performed to electrically connect the stacked wafers. Other processes such as metal interconnection are then performed. This process involves bonding first and then TSV fabrication. The process flow chart is as follows: Figure 1 As shown. Or when we perform the Backside Via Reveal (BVR) backside copper exposure process, after bonding the wafers, we need to grind from the back of the wafer. After grinding to a certain thickness from the back of the TSV, we use an etching process to thin the silicon and expose the internal copper. We then proceed to other processes such as metal interconnection. This process is to make TSV first and then bond. The process flow diagram is shown as follows Figure 2 shown.

[0020] In both of the above process flows, the top wafer silicon thinning process is involved after wafer bonding. A key point of this process step is the control of the uniformity of the silicon thinning thickness, that is, the control of the total thickness variation (TTV). Figure 1In the process of bonding first and then TSV, we have very strict control requirements on the thickness of silicon thinning. Because the final thickness of silicon thinning is the thickness that needs to be etched for TSV, if the thickness uniformity of the final silicon thinning is too poor, during the TSV etching process, the thinner silicon areas have been etched completely, while the thicker silicon areas have not been etched completely. If the silicon etching is completed in the thinner areas, continuing to etch will cause side etching defects (such as Figure 3 If the thicker area is not etched completely, the TSV will eventually be disconnected. In summary, the better the uniformity of silicon thinning thickness, the more similar the time it takes to complete TSV etching in different areas, and the better the final TSV etching morphology. Figure 2 The process flow of performing TSV first and bonding later is also known as the BVR process. If the silicon thinning is not uniform, and the distance to the Cu on the back of the TSV varies greatly, the subsequent etching process will result in some areas where the copper is exposed and others where it is not. To ensure that the TSVs where the copper is not yet exposed are fully exposed, the TSVs where the copper is already exposed need to be continuously bombarded by etching ions, which will cause plasma-induced damage (PID) to them, affecting the device performance of the wafer. If we use the backside flatness reveal (BFR) process, this process directly exposes the copper inside the TSV from the back of the wafer using processes such as grinding and CMP. At this time, if the thickness uniformity of the silicon thinning process is not uniform, the copper of the TSV will be exposed in some areas and not in others. To ensure copper exposure in all areas, the copper in thinner TSVs is exposed first, and the milling time for these TSVs is the longest. This, in turn, exposes the copper in thicker TSVs. This stress is also greatest in the thicker TSVs, which can cause the copper inside to tear. Furthermore, the milling slurry and other materials remain in contact with the exposed TSVs for a longer period of time, making it more likely to contaminate the copper inside the TSVs. Simultaneously exposing copper during CMP can contaminate the silicon. Since silicon is a semiconductor, copper contamination can lead to electrical leakage. Therefore, it is best to expose the copper simultaneously, minimizing the need for simultaneous milling of both copper and silicon. Alternatively, a BVR process can be used to avoid this problem. However, the BVR process also requires accurate silicon measurement, which in turn feeds back into the process to ensure uniform thinning thickness, ensuring that copper is exposed as simultaneously as possible. Therefore, controlling the silicon thinning thickness is crucial, placing high demands on silicon thickness measurement accuracy.

[0021] At present, it is difficult to control the thickness of silicon thinning. In addition to process factors, accurate measurement of silicon thickness is also a process difficulty. Thinning machines such as grinding and CMP will adjust the thinning process parameters in real time according to the feedback results of the silicon thickness, so as to ensure the consistency of the silicon thinning thickness in different areas. However, the current measurement of silicon thickness is not very accurate. The main reason is that in the original Fab factory process, the process is almost all carried out on the film layer above the silicon, and there is less demand for measuring the thickness of silicon, so the overall measurement capability of the silicon process is poor. The current common silicon thickness measurement uses infrared (IR) measurement, which uses infrared to measure the difference in reflectivity and refractive index between silicon and other types of film layers (dielectric film layers) to measure the thickness of silicon. The schematic diagram is as follows Figure 4 However, with current technology, infrared rays can pass through both silicon and dielectric film layers, and the instrument's ability is difficult to distinguish the interface between silicon and dielectric film layers, especially difficult to distinguish Figure 4 The difference between the two circles indicates the difference between the dielectric film layer between the two silicon wafers, which is typically several microns thick. The inability of infrared light to clearly distinguish these two layers results in a deviation of several microns in the final silicon thickness measurement, making it difficult to accurately measure the silicon thickness. Without accurate silicon thickness measurement, it is impossible to accurately provide thickness feedback to the thinning grinding and CMP equipment, making it impossible to tailor the thinning recipe based on the varying thickness of the silicon and ultimately, achieving uniform silicon thickness.

[0022] Current technology still uses online measurement on a machine. Based on the measured data, the silicon wafer at the corresponding location is sliced and analyzed. The online data is compared with the actual slice data to see if there is a fixed pattern of deviation compensation differences. If there is a certain pattern, the actual silicon thickness can be calculated based on this pattern from the online measurement data. However, this solution currently has the following drawbacks.

[0023] First, online measurement data may not necessarily have a fixed pattern with the actual slicing results, so the exact thickness of silicon cannot necessarily be known through online results.

[0024] Secondly, slicing will introduce errors during the sampling and measurement process, and the sampling points are fewer than the points measured online, so relatively more sample points need to be taken. Slicing sampling and measurement requires a lot of resources.

[0025] Furthermore, the offset between online and slice measurements is closely related to the film structure (as previously mentioned, it is primarily related to the thickness and type of the dielectric film between the two silicon wafers). Therefore, each time a new wafer structure is changed, the online measurement and slice results must be re-compared to obtain the offset between the online measurement and the slice, thereby obtaining a relatively accurate silicon thickness through the online results. This overall workload is quite cumbersome.

[0026] The best way is to improve the machine's ability to identify different film layers by modifying the machine (hardware and software), so that the silicon thickness data can be easily and quickly obtained through online data, thereby assisting the thinning process. However, this involves upgrading the machine, and it may be necessary to purchase a new machine, which requires the assistance of manufacturers or dealers, and also requires a greater cost (machine upgrade purchase, etc.). The present invention still uses the existing measuring machine, adds several common process steps to the wafer, and optimizes its structure to achieve accurate measurement of silicon thickness, thereby better assisting the silicon thinning process and improving the final silicon thinning effect.

[0027] This invention utilizes existing silicon thickness measurement equipment and existing Fab process equipment, optimizes the existing wafer process flow, and creates a new process structure. This allows for accurate online measurement of silicon thickness, providing a better reference for the silicon thinning process and optimizing the silicon thinning effect.

[0028] In a stacked bonded chip manufacturing method with precise control over wafer silicon thickness reduction, according to one embodiment of the present invention, a material partially impermeable to infrared rays is deposited during the shallow trench isolation process in the initial active area preparation cycle of wafer fabrication. This is followed by the deposition of a common insulating dielectric layer to isolate different device areas. Subsequent processes are similar to conventional wafer manufacturing.

[0029] After SIT etching, the etch depth of the shallow trench isolation was measured.

[0030] After wafer bonding, silicon thickness is measured using existing equipment, using the metal deposited inside the shallow trench isolation layer as a reflective layer. Because infrared light cannot penetrate this material, the emitted infrared light is completely reflected. The added infrared light can accurately detect the interface between the top layer of air and the silicon, thus accurately determining the silicon thickness at that location.

[0031] By adding the thickness of the silicon to the etching depth of the shallow trench isolation, we can accurately know the thickness of the thinned silicon on the wafer.

[0032] Existing common silicon thickness measurement machines use the infrared measurement principle. Since infrared rays have similar optical properties such as transmittance and refractive index for silicon and dielectric films, they cannot accurately identify the two layers, nor can they identify the true interface position, thus failing to accurately measure the silicon thickness. The best way is of course to upgrade the machine and improve its performance so that it can accurately distinguish between silicon and dielectric films, thereby accurately measuring the silicon thickness. However, this involves a series of tasks such as debugging the machine's hardware and software, and even the purchase of a new machine, which requires a lot of resources and is costly.

[0033] The present invention utilizes existing machines and optimizes the structure of the wafer to achieve accurate measurement of silicon thickness. The principle is described as follows: The optical properties of infrared rays for silicon and dielectric film layers, such as transmittance and refractive index, are similar, so they are difficult to distinguish. However, infrared rays cannot penetrate certain special materials. Therefore, when they encounter such substances, the infrared signal will change significantly, so the position of the lower silicon interface can be accurately determined. In addition, the position signal changes of the upper silicon interface and the air are very obvious, which is also easy to determine the position of the upper silicon interface and the air. Through these two signals, we can calculate the exact thickness of silicon.

[0034] Next, we need to make metal structures on the surface of the silicon or near the surface. The first loop when the wafer enters the factory is the active area preparation process loop (Active Area Loop), which mainly defines the active area on the surface of the wafer and isolates different active areas. The structure that plays an isolation role is called a shallow trench isolation (STI) structure. The common process flow is to etch a trench structure (TrenchArea) between different active areas through photolithography and etching, and then fill the trench area with insulating materials such as oxide, thereby isolating different active areas. Subsequently, devices are manufactured in different active areas. The process flow diagram is as follows Figure 5 shown.

[0035] In the original process, the shallow trench isolators are filled with insulating materials (usually SiO2). In order to meet the subsequent demand for silicon thickness measurement, we first deposit a layer of infrared-impermeable material in the shallow trench isolator to play a role in the subsequent infrared reflection. This material only occupies a small part (about 200A). Later, we still fill SiO2 according to the conventional process. After the filling is completed, our shallow trench isolator CMP process will grind off all the SiO2 on the surface and the filled infrared-impermeable material. At the same time, the SiO2 inside the shallow trench isolator is similar to the original process and is ground into a bowl and dish morphology. Later, we remove the SiN on the side surface of the shallow trench isolator to complete the production of the active area preparation process cycle (shallow trench isolation preparation process cycle) of the present invention. The process flow diagram of the present invention is as follows Figure 6 shown.

[0036] In a stacked bonded chip manufacturing method with precise control of wafer silicon thickness thinning according to one embodiment of the present invention, the material filled in the shallow trench isolation needs to meet the following requirements: (1) low infrared absorption and high reflectivity. This is to reflect the infrared light used to measure the silicon thickness back, thereby determining the position of the interface and measuring the silicon thickness. (2) It must be non-conductive and insulating, thereby isolating the active area. Examples include ceramic materials such as aluminum oxide (Al2O3), zirconium oxide (ZrO2), aluminum nitride (AlN), or other materials that meet the above two requirements.

[0037] Considering that other materials different from the original ones, such as SiO2, will be added, the performance will be different from the original structure, and the design of the shallow trench isolation structure may be changed.

[0038] During the CMP process of the shallow trench isolation, both the SiO2 deposited on the surface and the material introduced by the present invention need to be removed.

[0039] The deposited material of the present invention does not need to be very thick, and a layer of filling at the bottom is sufficient to meet the subsequent function of reflecting infrared rays.

[0040] After the shallow trench isolator ETCH, the depth of the shallow trench isolator needs to be measured. The depth measurement here is a mature process. The subsequent silicon thickness measurement also selects the location of the shallow trench isolator here. The infrared light hits the special material at the bottom of the shallow trench isolator and reflects, and we measure the thickness of the silicon. These two steps measure the same position. The depth of the shallow trench isolator measured at the beginning is added to the thickness of the silicon measured later, and we get the thickness of the stacked upper wafer silicon. The schematic diagram is as follows Figure 7 shown.

[0041] In a stacked bonded chip manufacturing method with precise control of wafer silicon thickness thinning according to one embodiment of the present invention, the second measurement step can use existing equipment to accurately measure the silicon thickness of the stacked wafers. The first measurement step can be directly performed using existing process methods. In summary, this significantly reduces costs.

[0042] Only one additional step is required: the deposition of a material with low infrared absorption, high reflectivity, and insulation. All other steps can be followed from the existing process. The overall process is simple, with minimal process changes, allowing for rapid implementation into large-scale production.

[0043] The present invention is used to measure silicon thickness online, enabling multi-point, high-precision measurement, providing a more precise and accurate data reference for the silicon thinning process, significantly optimizing the final silicon thinning effect, and thus significantly improving the final effect of processes such as TSV Last Post Bonding, BFR, and BVR that require high silicon thickness thinning accuracy.

[0044] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply the existence of any such actual relationship or order between these entities or operations. Moreover, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the presence of other identical elements in the process, method, article or device comprising the element.

[0045] Each embodiment in this specification is described in a related manner. The same or similar parts between the embodiments can be referred to each other. Each embodiment focuses on the differences from other embodiments.

[0046] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present invention should be included in the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be based on the scope of protection of the claims.

[0047] The above embodiments of the present invention are merely examples for the purpose of clearly illustrating the present invention and are not intended to limit the embodiments of the present invention. Those skilled in the art will appreciate that other variations or modifications may be made based on the above description. It is not necessary and impossible to enumerate all embodiments here. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention are intended to be included within the scope of protection of the claims of the present invention.

Claims

1. A method for manufacturing stacked bonded chips with the function of precisely controlling wafer silicon thickness thinning, characterized in that: The following steps are included before wafer stack bonding: Step S1, during the shallow trench isolation deposition in the active area preparation process cycle of the wafer, a small amount of metal material that is not transparent to infrared rays is first deposited, and then an insulating dielectric layer material is deposited; In step S2, the thickness of the shallow trench isolator and the thickness of the outer silicon layer of the shallow trench isolator are measured using an infrared thickness gauge, while the shallow trench isolator is polished until the wafer silicon thickness falls within the product design range, and the etching of the shallow trench isolator is stopped, wherein the wafer silicon thickness is the value obtained by adding the thickness of the outer silicon layer of the shallow trench isolator to the thickness of the shallow trench isolator.

2. The method for manufacturing stacked bonded chips according to claim 1, wherein: The deposition thickness of the metal material is 50 Å to 1000 Å.

3. The method for manufacturing stacked bonded chips according to claim 2, wherein: The deposition thickness of the metal material is 100 Å to 300 Å.

4. The method for manufacturing stacked bonded chips according to claim 1, wherein: After the shallow trench isolation is filled, the SiO2 and the metal material on the surface are completely ground away by a chemical mechanical polishing process to form a bowl-and-dish morphology.

5. The method for manufacturing stacked bonded chips according to claim 1, wherein: Also includes: The SiN in the shallow trench isolation is removed to complete the active area preparation process cycle.

6. The method for manufacturing stacked bonded chips according to claim 1, wherein: The material filled in the shallow trench spacer is an insulating material with low infrared absorption and high reflectivity.

7. The method for manufacturing stacked bonded chips according to claim 6, wherein: The material filled in the shallow trench spacer is one or more ceramic materials selected from the group consisting of aluminum oxide, zirconium oxide, and aluminum nitride.

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