Semiconductor structure and manufacturing method thereof

Abstract

The embodiment of the invention discloses a semiconductor structure and a manufacturing method thereof, and the semiconductor structure comprises a substrate which comprises a device region and a sealing region; wherein the sealing region surrounds the device region; the device structure is positioned on the device region; a first sealing structure over the sealing region and surrounding the device structure; the second sealing structure is located on the sealing area and surrounds the first sealing structure; the second sealing structure comprises a sealing layer and a gap located in the sealing layer.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor technology, and relate to, but are not limited to, a semiconductor structure and a manufacturing method thereof. Background Art

[0002] To protect the chip's internal circuitry, prevent dicing damage, and improve chip reliability, a seal ring is typically placed between the chip and the dicing path. This seal ring not only protects against the stress of dicing, but also prevents damage to the circuitry caused by moisture and other chemical contaminants, and prevents oxidation of the internal metal.

[0003] However, with the miniaturization of semiconductor devices, higher requirements are placed on the design of the sealing ring. Summary of the Invention

[0004] According to a first aspect of an embodiment of the present disclosure, there is provided a semiconductor structure, including:

[0005] A substrate comprising: a device region and a sealing region; wherein the sealing region surrounds the device region;

[0006] a device structure located above the device region;

[0007] a first sealing structure located above the sealing area and surrounding the device structure;

[0008] The second sealing structure is located above the sealing area and surrounds the first sealing structure; wherein the second sealing structure includes a sealing layer and a gap in the sealing layer.

[0009] In some embodiments, the second sealing structure comprises:

[0010] A plurality of sub-sealing structures are arranged in sequence along a direction from the device structure to the first sealing structure; wherein at least one of the sub-sealing structures has the gap.

[0011] In some embodiments, the gap is located on at least one side of the first sealing structure.

[0012] In some embodiments, the gap surrounds the first sealing structure.

[0013] In some embodiments, the height of the gap is less than or equal to the height of the sealing layer.

[0014] In some embodiments, the cross-sectional shape of the gap includes: triangle, quadrilateral or trapezoid.

[0015] In some embodiments, the width of the second sealing structure is greater than or equal to the width of the first sealing structure.

[0016] In some embodiments, the first sealing structure is solid.

[0017] According to a second aspect of an embodiment of the present disclosure, a method for manufacturing a semiconductor structure is provided, comprising:

[0018] Providing a substrate, the substrate comprising a device region and a sealing region surrounding the device region;

[0019] forming a device structure on the device region;

[0020] forming a first sealing structure surrounding the device structure on the sealing area;

[0021] A second sealing structure is formed on the sealing area and surrounds the first sealing structure; wherein the second sealing structure includes a sealing layer and a gap located in the sealing layer.

[0022] In some embodiments, forming a second sealing structure surrounding the first sealing structure on the sealing area includes:

[0023] A plurality of sub-sealing structures are formed and arranged in sequence along a direction from the device structure to the first sealing structure; wherein at least one of the sub-sealing structures has the gap.

[0024] In the disclosed embodiment, a second sealing structure is provided, comprising a sealing layer and a gap within the sealing layer. Firstly, cracks lose their transmission medium when extending into the gap, guiding stress release there and preventing them from penetrating the first sealing structure and extending into the device structure, effectively reducing the impact of cracks generated by cutting path stress on the chip. Secondly, the gap is provided within the second sealing structure, eliminating the need to increase the number of guard rings, thereby avoiding increasing the chip area or sacrificing the area of the device region. Thirdly, the manufacturing process of the second sealing structure with a gap is simple and can be implemented using conventional equipment without requiring significant investment. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the multiple drawings represent the same or similar components or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings only depict some embodiments disclosed in this application and should not be construed as limiting the scope of this application.

[0026] Figure 1 is a schematic diagram of an electronic device according to an embodiment of the present disclosure;

[0027] Figure 2a is a schematic diagram of a memory card according to an embodiment of the present disclosure;

[0028] Figure 2b is a schematic diagram of a solid-state hard disk according to an embodiment of the present disclosure;

[0029] Figure 3a 1 is a schematic diagram showing the distribution of storage cells of a three-dimensional NAND memory according to an embodiment of the present disclosure;

[0030] Figure 3b is a schematic block diagram of a three-dimensional NAND memory according to an embodiment of the present disclosure;

[0031] Figure 4 is a cross-sectional schematic diagram of a memory according to an embodiment of the present disclosure;

[0032] Figure 5 is a schematic diagram of a memory including a memory cell array and a peripheral circuit according to an embodiment of the present disclosure;

[0033] Figure 6 is a schematic diagram of a first semiconductor structure according to an embodiment of the present disclosure;

[0034] Figure 7 is a schematic diagram of a second semiconductor structure according to an embodiment of the present disclosure;

[0035] Figure 8 is a schematic diagram of a third semiconductor structure according to an embodiment of the present disclosure;

[0036] Figure 9 is a schematic top view of various semiconductor structures according to an embodiment of the present disclosure;

[0037] Figure 10 is a schematic cross-sectional view of various semiconductor structures according to an embodiment of the present disclosure;

[0038] Figure 11 The flowchart of a method for manufacturing a semiconductor structure according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0039] To facilitate understanding of the present disclosure, exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments described herein. Instead, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0040] In the following description, numerous specific details are provided to provide a more thorough understanding of the present disclosure. However, it will be apparent to those skilled in the art that the present disclosure may be practiced without one or more of these details. In some embodiments, to avoid confusion with the present disclosure, some technical features known in the art are not described; that is, all features of an actual embodiment may not be described here, and well-known functions and structures may not be described in detail.

[0041] Generally, terms can be understood, at least in part, from their use in context. For example, depending, at least in part, on the context, as used herein, the term "one or more" can be used to describe any feature, structure, or characteristic in a singular sense, or can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, terms such as "a" or "the" can likewise be understood to convey singular usage or to convey plural usage, depending, at least in part, on the context. Additionally, the term "based on" can be understood to not necessarily be intended to convey an exclusive set of factors, and can alternatively allow for the presence of additional factors that are not necessarily explicitly described, again depending, at least in part, on the context.

[0042] Unless otherwise defined, the purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present disclosure. When used herein, the singular forms "a", "an", and "said / the" are also intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0043] In order to fully understand the present disclosure, detailed steps and detailed structures will be presented in the following description to illustrate the technical solution of the present disclosure. The preferred embodiments of the present disclosure are described in detail below. However, in addition to these detailed descriptions, the present disclosure may also have other implementation methods.

[0044] The memory in the embodiments of the present disclosure includes but is not limited to a three-dimensional NAND memory. For ease of understanding, the three-dimensional NAND memory is used as an example for description.

[0045] Figure 11 is a schematic diagram of an electronic device 100 according to an embodiment of the present disclosure. The electronic device 100 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a memory therein. Figure 1 As shown, the electronic device 100 may include a host 108 and a memory system 102, wherein the memory system 102 has one or more memories 104 and a memory controller 106. The host 108 may be a processor (e.g., a central processing unit (CPU)) or a system on chip (SoC) (e.g., an application processor (AP)) of the electronic device. The host 108 may be configured to send data to the memory 104 or receive data from the memory 104.

[0046] According to some embodiments, the memory controller 106 is coupled to the memory 104 and the host 108 and is configured to control the memory 104. The memory controller 106 can manage data stored in the memory 104 and communicate with the host 108. In some embodiments, the memory controller 106 is designed to operate in a low duty cycle environment, such as a Secure Digital (SD) card, a Compact Flash (CF) card, a Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the memory controller 106 is designed to operate in a high duty cycle environment, such as a Solid State Disk (SSD) or an embedded Multi-Media Card (eMMC), and the SSD or eMMC is used as data storage for mobile devices such as smartphones, tablet computers, laptops, etc., as well as enterprise storage arrays.

[0047] The memory controller 106 may be configured to control operations of the memory 104, such as read, erase, and program operations. The memory controller 106 may also be configured to manage various functions regarding data stored or to be stored in the memory 104, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, etc. In some embodiments, the memory controller 106 is further configured to process error checking and correction (ECC) on data read from or written to the memory 104. The memory controller 106 may also perform any other suitable functions, such as formatting the memory 104. The memory controller 106 may communicate with external devices (e.g., Figure 1 For example, the memory controller 106 may communicate with the external device through at least one of various interface protocols, such as the USB protocol, the MMC protocol, the Peripheral Component Interconnect (PCI) protocol, the PCI-E (Peripheral Component Interconnect Express) protocol, the Advanced Technology Attachment (ATA) protocol, the Serial ATA protocol, the Parallel ATA protocol, the Small Computer System Interface (SCSI) protocol, the Enhanced Small Disk Interface (ESDI) protocol, the Integrated Development Equipment (IDE) protocol, the Firewire protocol, and the like.

[0048] The memory controller 106 and the one or more memories 104 can be integrated into various types of storage devices, for example, included in the same package (e.g., Universal Flash Storage (UFS) package or eMMC package). That is, the memory system 102 can be implemented and packaged into different types of terminal electronic products. Figure 2aIn one example shown in FIG, the memory controller 106 and the single memory 104 can be integrated into a memory card 202. The memory card 202 may include a PC card (Personal Computer Memory Card), a CF card, a SmartMedia (SM) card, a memory stick, a multimedia card (MMC (Multi-Media Card), RS-MMC (Reduced-Size MMC), MMCmicro), an SD card (SD, miniSD, microSD, SDHC (Reduced-Size MMC)), UFS, etc. The memory card 202 may also include a host computer (e.g., Figure 1 The memory card connector 204 is coupled to the host 108 in FIG. Figure 2b In another example shown in , the memory controller 106 and the plurality of memories 104 can be integrated into the SSD 206. The SSD 206 can also include a processor that interfaces the SSD 206 with a host (e.g., Figure 1 In some embodiments, the storage capacity and / or operating speed of the SSD 206 is greater than the storage capacity and / or operating speed of the memory card 202.

[0049] Figure 3a FIG. 1 is a schematic diagram showing the distribution of storage cells of a three-dimensional NAND memory according to an embodiment of the present disclosure. Figure 3a As shown, the memory cell array of a three-dimensional NAND memory device consists of several parallel, staggered rows of memory cell rows parallel to the gate isolation structure. Every two rows of memory cell rows are separated by a gate isolation structure and an upper select gate isolation structure, and each memory cell row includes multiple memory cells. The gate isolation structure may include a first gate isolation structure and a second gate isolation structure. The first gate isolation structure divides the memory cell array into multiple memory blocks ("blocks" in English). The multiple second gate isolation structures can divide the memory blocks into multiple finger storage areas ("finger" in English). The upper select gate isolation structure disposed in the middle of each finger storage area can divide the finger storage area into two parts, thereby dividing the finger storage area into two memory slices ("strings" in English). Figure 3a The memory block shown in FIG includes 6 memory slices. In practical applications, the number of memory slices in a memory block is not limited thereto. The memory cells in a memory block coupled to a certain word line can be called a memory page.

[0050] It should be noted that Figure 3aThe number of memory cell rows between the gate isolation structure and the upper select gate isolation structure is provided for illustrative purposes only and is not intended to limit the number of memory cell rows within a finger storage region of the 3D NAND memory disclosed herein. In practical applications, the number of memory cell rows within a finger storage region can be adjusted to meet specific requirements, such as 2, 4, 8, or 16.

[0051] Figure 3b 3 is a schematic block diagram of a three-dimensional NAND memory 300 according to an embodiment of the present disclosure. The memory 300 may be Figure 1 3. An example of a memory 104 in FIG. Memory 300 may include a memory cell array 301 and a peripheral circuit 302 coupled to the memory cell array 301. The memory cell array 301 is described as a three-dimensional NAND memory cell array, wherein the memory cells 306 are provided in the form of an array of NAND memory strings 308, each NAND memory string 308 extending vertically above a substrate (not shown). In some embodiments, each NAND memory string 308 includes a plurality of memory cells 306 coupled in series and stacked vertically. Each memory cell 306 can hold a continuous analog value, such as a voltage or charge, which depends on the number of electrons trapped in the area of the memory cell 306. Each memory cell 306 can be a floating gate type memory cell including a floating gate transistor, or a charge trapping type memory cell including a charge trapping transistor.

[0052] In some embodiments, each memory cell 306 is a single-level cell (SLC) having two possible storage states and can therefore store one bit of data. For example, the first storage state "0" can correspond to a first voltage range, and the second storage state "1" can correspond to a second voltage range. In some embodiments, each memory cell 306 is a multi-level cell (MLC) capable of storing more than a single bit of data in more than four storage states. For example, an MLC can store two bits per cell, three bits per cell (also known as a triple level cell (TLC)), or four bits per cell (also known as a quad level cell (QLC)). Each MLC can be programmed to take a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC can be programmed by writing one of three possible nominal storage values to the cell, and a fourth nominal storage value other than the three nominal storage values can be used to represent an erased state.

[0053] like Figure 3bAs shown in FIG, each NAND memory string 308 may include a bottom select gate (BSG) 310 at its source terminal and a top select gate (TSG) 312 at its drain terminal. BSG 310 and TSG 312 may be configured to activate a selected NAND memory string 308 during read and program operations. In some embodiments, the sources of the NAND memory strings 308 in the same memory block 304 are coupled via the same source line (SL) 314 (e.g., a common SL). In other words, according to some embodiments, all NAND memory strings 308 in the same memory block 304 have an array common source (ACS). According to some embodiments, the TSG 312 of each NAND memory string 308 is coupled to a corresponding bit line (BL) 316, from which data can be read or written via an output bus (not shown). In some embodiments, each NAND memory string 308 is configured to be selected or deselected by applying a select voltage (e.g., higher than the threshold voltage of a transistor having TSG 312) or a deselect voltage (e.g., 0V) to a corresponding TSG 312 via one or more TSG lines 313 and / or by applying a select voltage (e.g., higher than the threshold voltage of a transistor having BSG 310) or a deselect voltage (e.g., 0V) to a corresponding BSG 310 via one or more BSG lines 315.

[0054] like Figure 3bAs shown in FIG, a NAND memory string 308 can be organized into a plurality of memory blocks 304, each of which can have a common source line 314 (e.g., coupled to ground). In some embodiments, each memory block 304 is a basic data unit for erase operations, i.e., all memory cells 306 on the same memory block 304 are erased simultaneously. To erase the memory cells 306 in a selected memory block, the source lines coupled to the selected memory block and unselected memory blocks in the same plane as the selected memory block can be biased with an erase voltage (Vers) (e.g., a high positive voltage (e.g., 20V or higher)). It should be understood that in some examples, erase operations can be performed at the half-memory block level, at the quarter-memory block level, or at any suitable number of memory blocks or any suitable fraction of memory blocks. The memory cells 306 of adjacent NAND memory strings 308 can be coupled by word lines 318, which select which row of memory cells 306 is affected by read and program operations. In some embodiments, each word line 318 is coupled to a page 320 of memory cells 306, which is a basic data unit for programming operations. The size of a page 320 in bits can be related to the number of NAND memory strings 308 coupled by word lines 318 in a memory block 304. Each word line 318 can include a plurality of control gates (gate electrodes) at each memory cell 306 in a corresponding page 320 and a gate line coupling the control gates. In combination with the previous Figure 3a A page 320 includes multiple memory cells 306. The memory cells are isolated from each other by an upper select gate isolation structure and a gate isolation structure. The memory cells between the upper select gate isolation structure and the gate isolation structure are arranged into multiple memory cell rows. Each memory cell row is parallel to the gate isolation structure and the upper select gate isolation structure. Memory cells in a memory slice that share the same word line form a programmable (read / write) page.

[0055] Figure 4 1 is a cross-sectional schematic diagram of a memory according to an embodiment of the present disclosure. Figure 4 As shown, NAND memory string 308 may include a stacked structure 410, which includes multiple gate layers 411 and multiple insulating layers 412 alternately stacked in sequence, and a memory string 308 vertically extending through the gate layers 411 and insulating layers 412. Gate layers 411 and insulating layers 412 may be alternately stacked, with two adjacent gate layers 411 separated by an insulating layer 412. The number of pairs of gate layers 411 and insulating layers 412 in stacked structure 410 may determine the number of memory cells included in memory cell array 301.

[0056] The constituent material of the gate layer 411 may include a conductive material. Conductive materials include, but are not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate layer 411 includes a metal layer, for example, a tungsten layer. In some embodiments, each gate layer 411 includes a doped polysilicon layer. Each gate layer 411 may include a control gate surrounding a memory cell. The gate layer 411 at the top of the stacked structure 410 may extend laterally as an upper selection gate line, the gate layer 411 at the bottom of the stacked structure 410 may extend laterally as a lower selection gate line, and the gate layer 411 extending laterally between the upper selection gate line and the lower selection gate line may serve as a word line layer.

[0057] In some embodiments, the stacked structure 410 may be disposed on a substrate 401. The substrate 401 may include silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), germanium on insulator (GOI), or any other suitable material.

[0058] In some embodiments, NAND memory string 308 includes a channel structure extending vertically through stacked structure 410. In some embodiments, the channel structure includes a channel hole filled with one or more semiconductor materials (e.g., serving as a semiconductor channel) and one or more dielectric materials (e.g., serving as a memory film). In some embodiments, the semiconductor channel comprises silicon, such as polycrystalline silicon. In some embodiments, the memory film is a composite dielectric layer comprising a tunneling layer, a storage layer (also referred to as a "charge trapping / storage layer"), and a barrier layer. The channel structure may have a cylindrical shape (e.g., a pillar). In some embodiments, the semiconductor channel, tunneling layer, storage layer, and barrier layer are arranged radially in this order from the center of the pillar toward the outer surface of the pillar. The tunneling layer may comprise silicon oxide, silicon oxynitride, or any combination thereof. The storage layer may comprise silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer may comprise silicon oxide, silicon oxynitride, a high dielectric constant (high-k) dielectric, or any combination thereof. In one example, the memory film may comprise a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0059] Return Reference Figure 3b, the peripheral circuit 302 may be coupled to the memory cell array 301 via the bit lines 316, word lines 318, source lines 314, BSG lines 315, and TSG lines 313. The peripheral circuit 302 may include any suitable analog, digital, and mixed signal circuits for facilitating the operation of the memory cell array 301 by applying a voltage signal and / or a current signal to each target memory cell 306 and sensing a voltage signal and / or a current signal from each target memory cell 306 via the bit lines 316, word lines 318, source lines 314, BSG lines 315, and TSG lines 313. The peripheral circuit 302 may include various types of peripheral circuits formed using metal-oxide-semiconductor (MOS) technology. For example, Figure 5 Some exemplary peripheral circuits are shown, and the peripheral circuit 302 includes a page buffer / sense amplifier 504, a column decoder / bit line driver 506, a row decoder / word line driver 508, a voltage generator 510, a control logic 512, a register 514, an interface 516, and a data bus 518. It should be understood that in some examples, the peripheral circuit 302 may also include Figure 5 Additional peripheral circuits not shown.

[0060] The page buffer / sense amplifier 504 can be configured to read data from the memory cell array 301 and program (write) data to the memory cell array 301 according to control signals from the control logic 512. In one example, the page buffer / sense amplifier 504 can store a page of program data (write data) to be programmed into one page 320 of the memory cell array 301. In another example, the page buffer / sense amplifier 504 can perform a program verification operation to ensure that the data has been correctly programmed into the memory cell 306 coupled to the selected word line 318. In yet another example, the page buffer / sense amplifier 504 can also sense a low-power signal from the bit line 316 representing a data bit stored in the memory cell 306 and amplify the small voltage swing to a recognizable logic level during a read operation. The column decoder / bit line driver 506 can be configured to be controlled by the control logic 512 and select one or more NAND memory strings 308 by applying a bit line voltage generated from the voltage generator 510.

[0061] The row decoder / word line driver 508 can be configured to be controlled by control logic 512 and to select / deselect memory blocks 304 of the memory cell array 301 and to select / deselect word lines 318 of the memory blocks 304. The row decoder / word line driver 508 can also be configured to drive the word lines 318 using word line voltages generated from a voltage generator 510. In some embodiments, the row decoder / word line driver 508 can also select / deselect and drive the BSG lines 315 and the TSG lines 313. As described in detail below, the row decoder / word line driver 508 is configured to perform a programming operation on the memory cells 306 coupled to the selected word line(s) 318. The voltage generator 510 can be configured to be controlled by control logic 512 and to generate word line voltages (e.g., a read voltage, a program voltage, a pass voltage, a channel boosting voltage, a verify voltage, etc.), bit line voltages, and source line voltages to be supplied to the memory cell array 301.

[0062] The control logic 512 can be coupled to each peripheral circuit described above and is configured to control the operation of each peripheral circuit. The register 514 can be coupled to the control logic 512 and includes a status register, a command register, and an address register for storing status information, command operation code (OP code), and command address for controlling the operation of each peripheral circuit. The interface 516 can be coupled to the control logic 512 and act as a control buffer to buffer control commands received from a host (not shown) and relay them to the control logic 512, as well as buffer status information received from the control logic 512 and relay it to the host. The interface 516 can also be coupled to the column decoder / bit line driver 506 via the data bus 518 and act as a data I / O interface and data buffer to buffer data and relay it to the memory cell array 301 or relay or buffer data from the memory cell array 301.

[0063] Figure 6 This is a schematic diagram of a first semiconductor structure according to an embodiment of the present disclosure, which is used to form a semiconductor device, such as the above-mentioned memory or memory controller. During the packaging process, some cracks caused by edge stress will extend from the edge of the chip to the effective area of the chip, and after passing through the sealing ring (also called the guard ring), they will cause electrical failure of the chip. Figure 6 As shown, the cracks caused by the cutting stress pass through the outer guard ring and the inner guard ring and extend to the device structure, causing electrical failure of the device structure.

[0064] Cracks are a common problem in packaging, contributing to the defective parts per million (DPPM) rate. While optimizing packaging processes to reduce crack incidence, the industry is also strengthening guard ring design to better prevent cracks. For example, using multiple guard rings can effectively prevent cracks. However, increasing the number of guard rings will occupy more area, increasing chip size or sacrificing active area without increasing chip size.

[0065] Based on one or more of the above technical problems, the embodiments of the present disclosure provide a second semiconductor structure 600 . Figure 7 is a schematic diagram of a second semiconductor structure 600 according to an embodiment of the present disclosure, wherein: Figure 7 (a) is a schematic cross-sectional view of a semiconductor structure 600. Figure 7 (b) along Figure 7 (a) is a top view of the semiconductor structure 600 obtained by the AA' dashed line. Figure 7 As shown, the semiconductor structure 600 includes a substrate 601, a device structure 610, a first sealing structure 620 and a second sealing structure 630. The semiconductor structure 600 can be a finished structure or a semi-finished structure in the semiconductor device process, used to form a semiconductor device, such as the above-mentioned memory, memory controller or other semiconductor devices known in the art.

[0066] The substrate 601 includes a device region 600a and a sealing region 600b. The sealing region 600b surrounds the device region 600a. The device region 600a is used to form a memory cell array and / or various functional circuits, while the sealing region 600b is used to form a sealing structure. The material of the substrate 601 includes a semiconductor material, such as a single-element semiconductor material (e.g., silicon (Si) or germanium (Ge)), a III-V compound semiconductor material (e.g., gallium nitride (GaN), gallium arsenide (GaAs), or indium phosphide (InP)), a II-VI compound semiconductor material (e.g., zinc sulfide (ZnS), cadmium sulfide (CdS), or cadmium telluride (CdTe)), an organic semiconductor material, or other semiconductor materials known in the art.

[0067] In some embodiments, the substrate 601 further includes a scribe line 600c. The sealing area 600b surrounds the device area 600a and is located between the device area 600a and the scribe line 600c. The scribe line 600c is used to cut the multiple chips on the wafer into individual chips. It is understood that the cut chips may include part of the scribe line or no longer include the scribe line (i.e., the scribe line is completely removed), depending on the actual cutting location.

[0068] The device structure 610 is located above the device region 600a. For example, the device structure 610 may be located in a dielectric layer covering the device region 600a. The device structure 610 includes CMOS devices, memory devices, sensor devices, capacitors, resistors, inductors, and other active and / or passive devices. The memory devices include volatile memory devices or non-volatile memory devices. The non-volatile memory devices include NOR flash memory, NAND flash memory, ferroelectric memory, phase change memory, etc. In a specific example, the device structure 610 includes a memory cell array and peripheral circuits. For details about the memory cell array and peripheral circuits, please refer to the above-mentioned Figures 3a to 5 For the sake of brevity, the description in the relevant embodiments will not be repeated.

[0069] The first sealing structure 620 and the second sealing structure 630 are both located above the sealing area 600b. The first sealing structure 620 surrounds the device structure 610, and the second sealing structure 630 surrounds the first sealing structure 620. The second sealing structure 630 includes a sealing layer 631 and a gap 632 located in the sealing layer 631. The materials of the first sealing structure 620 and the second sealing structure 630 include dielectric materials (e.g., silicon oxide, silicon nitride, silicon oxynitride, etc.) or conductive materials (e.g., copper, aluminum, tungsten, etc.). The first sealing structure 620 and the second sealing structure 630 are both used to protect the device structure 610. For example, the first sealing structure 620 and the second sealing structure 630 are both used to block stress generated by cutting, block damage to the device structure 610 caused by penetration of moisture or other chemical contaminants, and prevent oxidation of the metal inside the device structure 610.

[0070] It should be noted that cracks caused by shear stress need to propagate through a dielectric medium. If the crack propagation force is strong, it may penetrate the guard ring and continue to propagate toward the device area 600a, causing failure. If gaps 632 exist in the peripheral sealing structure, the crack will lose its propagation medium when it reaches the sealing structure with gaps 632. This effectively blocks further crack propagation and creates a stress weak point there, directing stress release there and preventing the crack from extending to the device structure 610.

[0071] Therefore, in the disclosed embodiment, a second sealing structure is provided, including a sealing layer and a gap within the sealing layer. Firstly, when cracks extend into the gap, they lose the medium through which they transmit stress, guiding the stress release there and preventing them from penetrating the first sealing structure and extending into the device structure, effectively reducing the impact of cracks generated by the cutting path stress on the chip. Secondly, the gap is provided within the second sealing structure, eliminating the need to increase the number of guard rings, thereby avoiding increasing the chip area or sacrificing the area of the device region. Thirdly, the manufacturing process of the second sealing structure with the gap is simple and can be implemented using conventional equipment without requiring a high investment of cost.

[0072] In some embodiments, reference Figure 7 As shown, the first sealing structure 620 is solid. In this embodiment, multiple sealing structures can be designed above the sealing area 600b. The first sealing structure 620 can be the sealing structure closest to the device area 600a among the multiple sealing structures. The solid first sealing structure 620 can effectively block the penetration of moisture or other chemical contamination sources and prevent the metal inside the device structure 610 from being oxidized.

[0073] In some embodiments, the width of the second sealing structure 630 is greater than or equal to the width of the first sealing structure 620. In this embodiment, by setting the width of the second sealing structure greater than or equal to the width of the first sealing structure, it is easier to form a gap in the second sealing structure.

[0074] Figure 8 is a schematic diagram of a third semiconductor structure according to an embodiment of the present disclosure. It should be noted that, Figure 8 The third semiconductor structure shown is similar to Figure 7 The second semiconductor structure 600 shown in FIG. is similar to that shown in FIG. Figure 7 The description in the corresponding embodiment is not repeated in this embodiment. Figure 7 The difference is that Figure 8 In the third semiconductor structure 600 , the height of the gap 632 ′ is equal to the height of the sealing layer 631 .

[0075] In practical applications, the gap of the chip surface protection ring can be reasonably set to be open or closed according to the reliability requirements of different chips, that is, the height of the gap is less than or equal to the height of the sealing layer. In one example, the gap of the chip surface protection ring is open, and the height of the gap 632' is equal to the height of the sealing layer 631. Figure 8 In another example, the gap of the chip surface protection ring is closed, and the height of the gap 632 is less than the height of the sealing layer 631, as shown Figure 7 As shown in (a), the gap 632 is closed by the sealing layer 631.

[0076] Figure 9 It is a schematic top view of various semiconductor structures according to the embodiment of the present disclosure. It should be noted that, Figure 9 The various semiconductor structures shown are Figure 7 The second semiconductor structure 600 shown in Figure 8 The third semiconductor structure shown in is similar to that shown in Figure 7 or Figure 8 The description in the corresponding embodiment is not repeated in this embodiment. Figure 7 or Figure 8 The difference is that Figure 9 The second sealing structure shown is Figure 7 or Figure 8 The second sealing structure 630 shown in FIG. Figure 9 An exemplary description is given.

[0077] In some embodiments, the second sealing structure 630 includes: a plurality of sub-sealing structures arranged in sequence along a direction from the device structure 610 to the first sealing structure 620 ; wherein at least one sub-sealing structure has a gap 632 .

[0078] For example, refer to Figure 9 As shown in (b), the second sealing structure 630 includes two sub-sealing structures, respectively denoted as sub-sealing structure 630a and sub-sealing structure 630b. The sub-sealing structure 630a and the sub-sealing structure 630b are arranged sequentially from the inside to the outside, with the sub-sealing structure 630a surrounding the first sealing structure 620 and the sub-sealing structure 630b surrounding the sub-sealing structure 630a. The sub-sealing structure 630a has a gap 632a, and the sub-sealing structure 630b has a gap 632b. In this way, the gap 632a and the gap 632b can form a double-layer gap, which has a stronger barrier effect on cracks caused by cutting stress and is conducive to better protection of the device structure 610. In this embodiment, from the inside to the outside can be a direction along the device structure 610 pointing to the first sealing structure 620.

[0079] It should be noted that the number of sub-sealing structures in the second sealing structure 630 is not limited to the two shown in Figure (b), and can also be more, and the present disclosure has no special restrictions on this. Of course, in other embodiments, for area considerations, the number of sub-sealing structures in the second sealing structure 630 can also be one, such as Figure 9 As shown in (a).

[0080] In some embodiments, the gap 632 is located on at least one side of the first sealing structure 620. The following description will be given exemplarily by taking the top view of the first sealing structure 620 as an annular quadrilateral.

[0081] For example, refer to Figure 9 As shown in (a), the gap 632 surrounds the first sealing structure 620, that is, the gap 632 is located on each side of the annular quadrilateral, so that a global gap can be formed to effectively block cracks from each side from extending into the device structure 610.

[0082] For example, refer to Figure 9 As shown in (b), the gap 632a in the sub-sealing structure 630a surrounds the first sealing structure 620, and the gap 632b in the sub-sealing structure 630b surrounds the sub-sealing structure 630a, so that a double-layer global gap can be formed, which strengthens the barrier effect against cracks from each side of the outside.

[0083] Of course, in other examples, the gap 632 may be provided locally, such as Figure 9 As shown in FIG. 9( c) or FIG. 9( d), the gap 632 is located on one side of the first sealing structure 620. In practical applications, gaps can be provided in specific crack risk areas of the chip where cracks are likely to occur, based on the protection requirements of different chips, to provide targeted enhanced protection. This disclosure does not impose any particular limitations on this.

[0084] Figure 10 It is a cross-sectional schematic diagram of various semiconductor structures according to the embodiment of the present disclosure. It should be noted that, Figure 10 The various semiconductor structures shown are Figure 7 The second semiconductor structure 600 shown in Figure 8 The third semiconductor structure shown in is similar to that shown in Figure 7 or Figure 8 The description in the corresponding embodiment is not repeated in this embodiment. Figure 7 or Figure 8 The difference is that Figure 10 The gap 632 shown is Figure 7 or Figure 8 The cross-sectional shape of the gap shown in is different, refer to Figure 10 As shown, the cross-sectional shape of the gap 632 includes: triangle, quadrilateral or trapezoid. It is understood that the cross-sectional shape of the gap 632 can have a variety of shapes, depending on different FAB processes and applications. Of course, the gap 632 can be designed into a regular pattern or a plurality of irregular patterns. The cross-sectional shape of the gap 632 is not limited to Figure 10 As shown, other geometric shapes are also possible.

[0085] In some embodiments, the second sealing structure 630 includes a sub-sealing structure 630a and a sub-sealing structure 630b, the sub-sealing structure 630a has a gap 632a, and the sub-sealing structure 630b has a gap 632b. The cross-sectional shapes of the gap 632a and the gap 632b can be the same or different. Figure 10 As shown in (c), the cross-sectional shape of the gap 632a is an inverted trapezoid, and the cross-sectional shape of the gap 632b is a triangle.

[0086] Table 1 shows stress test results for different regions of a semiconductor structure with three solid guard rings and a semiconductor structure with a first sealing structure and a second sealing structure. Region A may be a region where a guard ring or sealing structure is provided, and region B may be a region where a device structure is provided. As shown in Table 1, compared to the configuration with three solid guard rings, the second sealing structure with gaps provided in this embodiment exhibits reduced stress in both Regions A and B. In other words, the stress barrier capability of the second sealing structure is equivalent to that of two solid guard rings. This not only effectively blocks the extension of stress-induced cracks, but also reduces the number of guard rings, thereby saving area.

[0087] Table 1 Stress test results of two semiconductor structures

[0088]

[0089] The present disclosure provides a semiconductor structure comprising: a substrate including a device region and a sealing region; wherein the sealing region surrounds the device region; a device structure located above the device region; a first sealing structure located above the sealing region and surrounding the device structure; a second sealing structure located above the sealing region and surrounding the first sealing structure; wherein the second sealing structure comprises a sealing layer and a void located in the sealing layer. Thus, firstly, when a crack extends to the void, it loses the medium through which it transmits the crack, guiding the stress to be released there, thereby avoiding breakdown of the first sealing structure and extending into the device structure, effectively reducing the impact of cracks generated by cutting path stress on the chip; secondly, the void is provided in the second sealing structure, eliminating the need to increase the number of guard rings, thereby not increasing the chip area or sacrificing the area of the device region; thirdly, the manufacturing process of the second sealing structure with the void is simple, and can be implemented using conventional equipment without requiring a high cost investment.

[0090] Based on the above semiconductor structure, an embodiment of the present disclosure provides a method for manufacturing a semiconductor structure. The manufacturing method can be used to manufacture the semiconductor structure in any of the above embodiments. Of course, the above semiconductor structure can also be manufactured using other methods. Figure 11 is a flow chart of a method for manufacturing a semiconductor structure according to an embodiment of the present disclosure, referring to Figure 11 As shown, the production method includes:

[0091] Step S710: providing a substrate, the substrate including a device region and a sealing region surrounding the device region;

[0092] Step S720: forming a device structure on the device area;

[0093] Step S730: forming a first sealing structure surrounding the device structure on the sealing area;

[0094] Step S740: forming a second sealing structure surrounding the first sealing structure on the sealing area; wherein the second sealing structure includes a sealing layer and a gap in the sealing layer.

[0095] In step S710, the substrate material includes a semiconductor material, such as a single-element semiconductor material (e.g., silicon (Si) or germanium (Ge)), a III-V compound semiconductor material (e.g., gallium nitride (GaN), gallium arsenide (GaAs), or indium phosphide (InP), etc.), a II-VI compound semiconductor material (e.g., zinc sulfide (ZnS), cadmium sulfide (CdS), or cadmium telluride (CdTe), etc.), an organic semiconductor material, or other semiconductor materials known in the art. The substrate may also be implanted with certain dopant ions to change electrical parameters according to design requirements.

[0096] In step S720, one or more semiconductor manufacturing processes such as thin film deposition process, photolithography process, etching process, etc. can be used to form a device structure. The device structure includes CMOS devices, memory devices, sensor devices, capacitors, resistors, inductors and other active and / or passive devices. For the device structure, please refer to the relevant description in the above-mentioned device embodiment. For the sake of brevity, it will not be repeated here.

[0097] In step S730 , a first sealing trench surrounding the device structure may be formed by an etching process, and a sealing material may be filled into the first sealing trench to form a first sealing structure surrounding the device structure.

[0098] In step S740, a second sealing groove surrounding the first sealing groove can be formed by an etching process, and a sealing material can be filled into the second sealing groove to form a second sealing structure surrounding the first sealing structure. Here, the deposition rate of the sealing material filling the second sealing groove and / or the width of the second sealing groove can be regulated so that when the sealing material is filled into the second sealing groove, the top of the second sealing groove is sealed in advance, thereby forming a gap in the sealing layer. Of course, in other embodiments, the gap can also be formed by etching the sealing material.

[0099] The first sealing groove and the second sealing groove can be etched simultaneously or successively, and the first sealing structure and the second sealing structure can be filled simultaneously or successively. The embodiment of the present disclosure has no special restrictions on the order of etching the first sealing groove and the second sealing groove and the order of filling the first sealing structure and the second sealing structure.

[0100] It should be noted that Figure 11 The steps shown in the operation are not exclusive, and other steps may be performed before, after, or between any steps in the operation shown; Figure 11 The steps shown in the figure can be adjusted in sequence according to actual needs.

[0101] In some embodiments, the step S740 includes: forming a plurality of sub-sealing structures arranged in sequence along a direction from the device structure to the first sealing structure; wherein at least one sub-sealing structure has a gap.

[0102] For example, a plurality of sub-sealing grooves arranged sequentially from the inside out can be formed by etching, and a sealing material can be filled into each sub-sealing groove to form a plurality of sub-sealing structures arranged sequentially from the inside out. Here, from the inside out can be a direction along the device structure toward the first sealing structure.

[0103] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0104] The features disclosed in the several device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new device embodiments.

[0105] It should be understood that “one embodiment” or “an embodiment” mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present disclosure. Therefore, “in one embodiment” or “in an embodiment” appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present disclosure, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments.

[0106] It should be noted that, in this document, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or apparatus comprising the element.

[0107] The above description is merely an embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A semiconductor structure, characterized in that include: A substrate comprising: a device region and a sealing region; wherein the sealing region surrounds the device region; a device structure located above the device region; a first sealing structure located above the sealing area and surrounding the device structure; The second sealing structure is located above the sealing area and surrounds the first sealing structure; wherein the second sealing structure includes a sealing layer and a gap located in the sealing layer.

2. The semiconductor structure according to claim 1, wherein: The second sealing structure includes: A plurality of sub-sealing structures are arranged in sequence along a direction from the device structure to the first sealing structure; wherein at least one of the sub-sealing structures has the gap.

3. The semiconductor structure according to claim 1 or 2, characterized in that: The gap is located on at least one side of the first sealing structure.

4. The semiconductor structure according to claim 3, wherein: The gap surrounds the first sealing structure.

5. The semiconductor structure according to claim 1, wherein: The height of the gap is less than or equal to the height of the sealing layer. The semiconductor structure according to claim 1 , wherein: The cross-sectional shape of the gap includes: triangle, quadrilateral or trapezoid.

7. The semiconductor structure according to claim 1, wherein: The width of the second sealing structure is greater than or equal to the width of the first sealing structure.

8. The semiconductor structure according to claim 1, wherein: The first sealing structure is solid.

9. A method for manufacturing a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising a device region and a sealing region surrounding the device region; forming a device structure on the device region; forming a first sealing structure surrounding the device structure on the sealing area; A second sealing structure is formed on the sealing area and surrounds the first sealing structure; wherein the second sealing structure includes a sealing layer and a gap located in the sealing layer.

10. The manufacturing method according to claim 9, characterized in that: The second sealing structure formed on the sealing area and surrounding the first sealing structure includes: A plurality of sub-sealing structures are formed and arranged in sequence along a direction from the device structure to the first sealing structure; wherein at least one of the sub-sealing structures has the gap.

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