Semiconductor structure and forming method thereof
By forming a protective layer between the side wall of the interconnecting through hole structure and the dielectric layer, the problems of "flag mouth" defects and shorting during the etching process are solved, and the performance and reliability of the semiconductor structure are improved.
Patent Information
- Application Number
- CN202410162096.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-02-04
- Publication Date
- 2025-08-05
AI Technical Summary
In the prior art, the interconnected via structure of the semiconductor structure is prone to form "flare-mouth" defects during the etching process, resulting in short connection between adjacent via structures, affecting semiconductor performance, and the etching method using oxygen and fluorine will produce by-products and increase contact resistance.
A protective layer is formed between the side wall of the interconnected through-hole structure and the dielectric layer. The protective layer materials include SiN, SiON, SiC or Al2O3. By protecting the side wall of the dielectric layer during the etching process, over-etching is reduced and the formation of "flag mouth" defects are prevented.
It effectively reduces the "flag mouth" defects on the top of the interconnected via structure, reduces the probability of shorting between adjacent via structures, improves the membrane layer quality of the interconnected via structure, and thus improves the performance of the semiconductor structure.
Smart Images
Figure CN120432467A_ABST
Abstract
Description
Technical Field
[0001] Embodiments of the present invention relate to the field of semiconductor manufacturing, and particularly to a semiconductor structure and a method for forming the same. Background Art
[0002] In recent years, with the development of integrated circuit processes, the integration level of integrated circuits and semiconductor technologies have made great progress. In semiconductor manufacturing processes, as the size of integrated circuits continues to shrink, the line width of the back-end (back end of line, BEOL) metal interconnect lines also continues to decrease.
[0003] The formation of the back-end metal interconnect lines usually includes the formation of contact holes and metal lines, but currently, the yield and performance of forming the back-end metal interconnect lines with contact holes and metal lines need to be improved. Summary of the Invention
[0004] The problem solved by the embodiments of the present invention is to provide a method for forming a semiconductor structure, which is beneficial to ensuring the performance of the semiconductor structure.
[0005] To solve the above problem, embodiments of the present invention provide a semiconductor structure, including: a substrate, in which an interconnect metal layer is formed, the top surface of the interconnect metal layer is exposed on the substrate, and the interconnect metal layer includes an interconnect region for interconnection; a dielectric layer, covering the substrate; an interconnect through-hole structure, penetrating the dielectric layer on the top of the interconnect metal layer in the interconnect region and being electrically connected to the interconnect metal layer; a protective layer, located between the sidewall of the interconnect through-hole structure and the dielectric layer.
[0006] Optionally, the protective layer further extends to cover the top surface of the dielectric layer.
[0007] Optionally, the protective layer includes one or more sub-protective layers conformally covering and stacked in sequence.
[0008] Optionally, the number of sub-protective layers is less than or equal to 11 layers.
[0009] Optionally, the protective layer includes multiple sub-protective layers conformally covering and stacked in sequence, and the thickness of the sub-protective layer is 15 nm to 400 nm.
[0010] Optionally, in the protective layer, the material of the sub-protective layer in contact with the interconnect through-hole structure includes SiN, SiON, SiC or Al2O3.
[0011] Optionally, the material of the protective layer includes one or more of SiO2, SiN, SiON, SiC and Al2O3.
[0012] Optionally, the thickness of the protective layer is 45 nm to 1200 nm.
[0013] Optionally, the substrate includes a plurality of isolated interconnect metal layers; the dielectric layer includes: a first dielectric layer covering the substrate, and the first dielectric layer also fills between adjacent interconnect metal layers; a second dielectric layer located on the first dielectric layer, and the second dielectric layer exposes the top surface of the through-hole interconnect structure.
[0014] Correspondingly, an embodiment of the present invention further provides a method for forming a semiconductor structure, including: providing a substrate in which an interconnect metal layer is formed, the top surface of the interconnect metal layer is exposed on the substrate, and the interconnect metal layer includes an interconnect region for interconnection; forming a dielectric layer covering the substrate; patterning the dielectric layer to form a first opening in the dielectric layer on the interconnect metal layer in the interconnect region; forming a protective layer on the sidewall of the first opening; patterning through the dielectric layer along the first opening to form a second opening; and forming a through-hole interconnect structure in the second opening.
[0015] Optionally, the step of patterning the dielectric layer to form a first opening in the dielectric layer on the interconnect metal layer in the interconnect region includes: forming a mask layer on the dielectric layer, a mask opening located above the interconnect region is formed in the mask layer, and the mask opening exposes the top surface of the dielectric layer; patterning the dielectric layer along the mask opening to remove a part of the thickness of the dielectric layer to form a first opening; after forming the first opening, it further includes: removing the mask layer.
[0016] Optionally, in the step of patterning the dielectric layer to form a first opening in the dielectric layer on the interconnect metal layer in the interconnect region, the difference between the opening size of the first opening and the width size of the through-hole interconnect structure is 45 nm to 1200 nm.
[0017] Optionally, in the step of forming a protective layer on the sidewall of the first opening, the protective layer further extends to cover the top surface of the dielectric layer.
[0018] Optionally, in the step of forming a protective layer on the sidewall of the first opening, the protective layer includes one or more sub-protective layers conformally covering and stacked in sequence.
[0019] Optionally, in the step of forming a protective layer on the sidewall of the first opening, the number of sub-protective layers is less than or equal to 11 layers.
[0020] Optionally, in the step of forming a protective layer on the sidewall of the first opening, the thickness of the sub-protective layer is 15 nm to 400 nm.
[0021] Optionally, in the step of forming a protective layer on the sidewall of the first opening, in the protective layer, the material of the sub-protective layer exposed by the first opening includes SiN, SiON, SiC or Al2O3.
[0022] Optionally, in the step of forming a protective layer on the sidewall of the first opening, the material of the protective layer includes one or more of SiO2, SiN, SiON, SiC and Al2O3.
[0023] Optionally, the step of forming a protective layer on the sidewall of the first opening includes: forming one or more layers of protective material layers stacked in sequence to cover the sidewall and bottom of the first opening and the top surface of the dielectric layer; removing the protective material layer at the bottom of the first opening and retaining the remaining protective material layer as the protective layer.
[0024] Optionally, in the step of providing a substrate, the substrate includes a plurality of spaced interconnecting metal layers; the step of forming a dielectric layer covering the substrate includes: forming a first dielectric layer covering the substrate, and the first dielectric layer also fills between adjacent interconnecting metal layers; forming a second dielectric layer covering the first dielectric layer; in the step of patterning the dielectric layer to form a first opening in the dielectric layer on the interconnecting metal layer in the interconnect region, the first opening penetrates through the second dielectric layer and is located in the first dielectric layer with a partial thickness.
[0025] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:
[0026] In the semiconductor structure provided by the embodiment of the present invention, the interconnect via structure penetrates through the dielectric layer on the top of the interconnecting metal layer in the interconnect region and is electrically connected to the interconnecting metal layer, and the protective layer is located between the sidewall of the interconnect via structure and the dielectric layer; in the embodiment of the present invention, the protective layer is located between the sidewall of the interconnect via structure and the dielectric layer, which can protect the dielectric layer on the sidewall of the interconnect via structure during the process of etching the dielectric layer to form the interconnect via structure, which is beneficial to reducing the probability that the dielectric layer on the top of the interconnect via structure is over-etched, resulting in the formation of a "flare" defect at the top of the interconnect via structure, thereby being beneficial to reducing the probability of short circuit between adjacent interconnect via structures, being beneficial to ensuring the film quality of the interconnect via structure, and further being beneficial to ensuring the performance of the semiconductor structure.
[0027] In the method for forming a semiconductor structure provided by the embodiment of the present invention, patterning the dielectric layer to form a first opening in the dielectric layer on the interconnecting metal layer in the interconnect region, forming a protective layer on the sidewall of the first opening, patterning through the dielectric layer along the first opening to form a second opening, and forming an interconnect via structure in the second opening; in the embodiment of the present invention, forming a protective layer on the sidewall of the first opening can protect the dielectric layer on the sidewall of the first opening during the process of patterning through the dielectric layer along the first opening to form a second opening, which is beneficial to reducing the probability that the dielectric layer on the top of the first opening is over-etched, resulting in the formation of a "flare" defect at the top of the first opening, correspondingly being beneficial to reducing the probability of forming a "flare" defect at the top of the formed interconnect via structure, thereby being beneficial to reducing the probability of short circuit between adjacent interconnect via structures, being beneficial to ensuring the film quality of the interconnect via structure, and further being beneficial to ensuring the performance of the semiconductor structure. Description of the Drawings
[0028] Figures 1 to 4 is a schematic structural diagram corresponding to each step in a method for forming a semiconductor structure;
[0029] Figure 5 is a schematic structural diagram corresponding to an embodiment of the semiconductor structure of the present invention;
[0030] Figures 6 to 14 is a schematic structural diagram corresponding to each step in an embodiment of the method for forming the semiconductor structure of the present invention. Detailed implementation manners
[0031] Currently, it is difficult to guarantee the performance of the semiconductor structure. Now, in combination with a method for forming a semiconductor structure, the reasons why it is difficult to guarantee the semiconductor structure will be analyzed.
[0032] Refer to Figures 1 to 4 , which shows a schematic structural diagram corresponding to each step in a method for forming a semiconductor structure.
[0033] Refer to Figure 1 , provide a substrate 10, form an interconnect metal layer 20 in the substrate 10, expose the top surface of the interconnect metal layer 20 on the substrate 10, and form a dielectric layer on the substrate 10. The dielectric layer includes a first dielectric layer 31 and a second dielectric layer 50 located on the first dielectric layer 31.
[0034] Refer to Figure 2 , pattern the dielectric layer to form a first opening 52 in the dielectric layer.
[0035] Refer to Figure 3 , pattern the remaining dielectric layer along the first opening 52 to form a second opening 53 penetrating through the dielectric layer.
[0036] Refer to Figure 4 , form an interconnect via structure 54 electrically connected to the interconnect metal layer 20 in the second opening 53.
[0037] In the step of patterning the remaining dielectric layer along the first opening 52 to form a second opening 53 penetrating through the dielectric layer, it is easy to cause over-etching of the dielectric layer at the top of the first opening 52, resulting in a defect of "flare" at the top of the formed second opening 53. Correspondingly, a defect of "flare" is formed at the top of the interconnect via structure 54 formed in the second opening 53, thus easily causing a problem of short-circuit between the tops of adjacent interconnect via structures 54, affecting the performance of the semiconductor structure.
[0038] Currently, usually, in the step of patterning the remaining dielectric layer along the first opening 52, the content of oxygen and fluorine is increased during the etching process to improve the control ability for over-etching (OE). However, the introduction of oxygen and fluorine will generate Al m O n and Al y F xBy-products, and these by-products are difficult to clean thoroughly, thus easily leading to an increase in contact resistance and affecting the performance of the semiconductor structure.
[0039] To solve the above technical problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, in which an interconnect metal layer is formed, the top surface of the interconnect metal layer is exposed on the substrate, and the interconnect metal layer includes an interconnect region for interconnection; forming a dielectric layer covering the substrate; patterning the dielectric layer to form a first opening in the dielectric layer on the interconnect metal layer in the interconnect region; forming a protective layer on the sidewall of the first opening; patterning through the dielectric layer along the first opening to form a second opening; and forming an interconnection via structure in the second opening.
[0040] In an embodiment of the present invention, forming a protective layer on the sidewall of the first opening can protect the dielectric layer on the sidewall of the first opening during the process of patterning through the dielectric layer along the first opening to form a second opening, which is beneficial to reducing the probability that the dielectric layer at the top of the first opening is over-etched, resulting in the formation of a "flare" defect at the top of the first opening. Correspondingly, it is beneficial to reducing the probability that a "flare" defect is formed at the top of the formed interconnection via structure, thereby being beneficial to reducing the probability of short circuit between adjacent interconnection via structures, being beneficial to ensuring the film quality of the interconnection via structure, and further being beneficial to ensuring the performance of the semiconductor structure.
[0041] To make the above objects, features, and advantages of the embodiments of the present invention more obvious and understandable, the following detailed description of the specific embodiments of the present invention will be given in conjunction with the accompanying drawings.
[0042] Figure 5 It is a schematic structural diagram corresponding to an embodiment of the semiconductor structure of the present invention.
[0043] Refer to Figure 5 , the semiconductor structure includes: a substrate 100, in which an interconnect metal layer 200 is formed, the top surface of the interconnect metal layer 200 is exposed on the substrate 100, and the interconnect metal layer 200 includes an interconnect region 100A for interconnection; a dielectric layer (not labeled), covering the substrate 100; an interconnection via structure 530, passing through the dielectric layer on the top of the interconnect metal layer 200 in the interconnect region 100A and electrically connected to the interconnect metal layer 200; and a protective layer 720, located between the sidewall of the interconnection via structure 530 and the dielectric layer.
[0044] The substrate 100 is used to provide an operation basis for the process of forming the interconnection via structure 530.
[0045] In this embodiment, according to the actual process conditions, functional structures may be formed in the substrate 100. For example: semiconductor devices such as MOS field effect transistors may be formed in the substrate 100, and a resistance structure or the like may also be formed.
[0046] The interconnecting metal layer 200 is used to achieve electrical connection with the interconnecting via structure 530 to realize basic circuit functions.
[0047] Specifically, in this embodiment, the interconnecting metal layer 200 includes an interconnecting region 100A, which is the region for interconnecting with the interconnecting via structure 530.
[0048] In this embodiment, the material of the interconnecting metal layer 200 includes aluminum.
[0049] Aluminum has the advantages of low cost, good diffusion stability, good conductivity, and a process that can form a thick aluminum layer. In this embodiment, if the interconnecting metal layer 200 is a top metal layer, using aluminum can form a relatively stable and thick enough top metal layer.
[0050] Specifically, in this embodiment, the substrate 100 includes multiple isolated interconnecting metal layers 200.
[0051] The multiple isolated interconnecting metal layers 200 are respectively used to form different circuit structures.
[0052] The dielectric layer is used to provide a process operation platform for the formation of the interconnecting via structure 530.
[0053] In this embodiment, the dielectric layer includes: a first dielectric layer 310, which covers the substrate 100, and the first dielectric layer 310 also fills between adjacent interconnecting metal layers 200.
[0054] The first dielectric layer 310 is used to electrically isolate adjacent interconnecting metal layers 200.
[0055] In this embodiment, the material of the first dielectric layer 310 is an insulating material, including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxide, silicon carbon nitride, and silicon carbon oxynitride.
[0056] In this embodiment, the dielectric layer further includes: a second dielectric layer 500, which is located on the first dielectric layer 310, and the second dielectric layer 500 exposes the top surface of the interconnecting via structure 530.
[0057] The second dielectric layer 500 is used to provide a process operation platform for the formation of the interconnecting via structure 530 and also to electrically isolate adjacent interconnecting via structures 530.
[0058] In this embodiment, the material of the second dielectric layer 500 is an insulating material, including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxide, silicon carbon nitride, and silicon carbon oxynitride.
[0059] The interconnecting via structure 530 is used to achieve electrical connection with the interconnecting metal layer 200.
[0060] In this embodiment, the material of the interconnection via structure 530 includes copper.
[0061] Copper has good metallic conductivity and small resistance, which is beneficial to obtaining an interconnection via structure 530 with better conductivity.
[0062] The protective layer 720 is used to protect the dielectric layer on the sidewall of the interconnection via structure 530 during the manufacturing process of the interconnection via structure 530.
[0063] In this embodiment, the protective layer 720 is located between the sidewall of the interconnection via structure 530 and the dielectric layer, and can protect the dielectric layer on the sidewall of the interconnection via structure 530 during the process of etching the dielectric layer to form the interconnection via structure 530. This is beneficial to reducing the probability that the dielectric layer at the top of the interconnection via structure 530 is over-etched, resulting in the formation of a "flare" defect at the top of the interconnection via structure 530. Thus, it is beneficial to reduce the probability of short circuit between adjacent interconnection via structures 530, beneficial to ensuring the film quality of the interconnection via structure 530, and further beneficial to ensuring the performance of the semiconductor structure.
[0064] In this embodiment, the protective layer 720 also extends to cover the top surface of the dielectric layer.
[0065] The protective layer 720 also extends to cover the top surface of the dielectric layer, and can also protect the dielectric layer on the side part of the top surface of the interconnection via structure 530 during the process of etching the dielectric layer to form the interconnection via structure 530. That is to say, the protective layer 720 protects the corners of the dielectric layer on both sides of the top of the interconnection via structure 530, so that during the etching process of the dielectric layer, the corners of the dielectric layer on both sides of the top of the interconnection via structure 530 will not be over-etched to produce a "flare" morphological defect. Thus, it is further beneficial to reduce the probability of short circuit between adjacent interconnection via structures 530, further beneficial to ensuring the film quality of the interconnection via structure 530, and further beneficial to ensuring the performance of the semiconductor structure. Moreover, the protective layer 720 also extends to cover the top surface of the dielectric layer, increasing the dielectric depth on the side of the interconnection via structure 530. Thus, during the process of forming the pseudo-interconnection structure in the dielectric on the side of the interconnection via structure 530, it is beneficial to reduce the probability of miscontact between the pseudo-interconnection structure and the underlying circuit structure, thereby being beneficial to ensuring the performance of the semiconductor structure.
[0066] It should be noted that in this embodiment, the thickness of the protective layer 720 should not be too large or too small. If the thickness of the protective layer 720 is too large, it is likely to cause the problem that the space occupied by the protective layer 720 on both sides of the through-interconnection hole structure 530 is too large, correspondingly resulting in too small space for the through-interconnection hole structure 530, thus easily affecting the formation of the through-interconnection hole structure 530 and further easily affecting the electrical connection performance between the through-interconnection hole structure 530 and the interconnection metal layer 200; if the thickness of the protective layer 720 is too small, it is likely to cause greater difficulty in forming the protective layer 720 and also likely to result in poor protection effect of the protective layer 720 on the dielectric layers on both sides of the through-interconnection hole structure 530, making it difficult to guarantee the performance of the semiconductor structure. Therefore, in this embodiment, the thickness of the protective layer 720 is 45 nm to 1200 nm.
[0067] In this embodiment, the material of the protective layer 720 includes one or more of SiO2, SiN, SiON, SiC, and Al2O3.
[0068] The materials of SiO2, SiN, SiON, SiC, and Al2O3 are all easily obtainable materials and can play a good protective role.
[0069] In this embodiment, the protective layer 720 includes one or more sub-protective layers 710 that are conformally covered and stacked in sequence.
[0070] The multi-layer sub-protective layers 710 that are conformally covered and stacked in sequence mean that among the multi-layer sub-protective layers 710, the upper sub-protective layer 710 conformally covers the lower sub-protective layer 710, and the multi-layers are stacked in sequence to form the protective layer 720.
[0071] In this embodiment, the protective layer 720 includes multi-layer sub-protective layers 710 that are conformally covered and stacked in sequence.
[0072] The protective layer 720 is composed of multi-layer sub-protective layers 710 that are conformally covered and stacked in sequence, so that the stress of the protective layer 720 is relieved, which is beneficial to reducing the stress generated on the semiconductor structure when forming the protective layer 720.
[0073] It should be noted that in this embodiment, the number of layers of the sub-protective layer 720 should not be too many. If the number of layers of the sub-protective layer 720 is too many, it is likely to cause difficulties in forming the protective layer 720 and it is difficult to guarantee the film quality of the multi-layer sub-protective layers 710. Therefore, in this embodiment, the number of layers of the sub-protective layer 720 is less than or equal to 11 layers.
[0074] As an example, in this embodiment, the protective layer 720 is composed of 3 sub-protective layers 710. The number of sub-protective layers 710 is appropriate, the film layer structure is simple, and it is easy to form the protective layer 720.
[0075] It should be noted that in this embodiment, the protective layer 720 includes multiple sub-protective layers 710 that are conformally covered and stacked in sequence. The thickness of the sub-protective layer 710 should not be too large nor too small. If the thickness of the sub-protective layer 710 is too large, it is easy to cause the thickness of the formed protective layer 710 to be too large, which may easily lead to the problem that the space occupied by the protective layer 720 on both sides of the through-interconnection hole structure 530 is too large, correspondingly resulting in the space of the through-interconnection hole structure 530 being too small, thus easily affecting the formation of the through-interconnection hole structure 530 and further easily affecting the electrical connection performance between the through-interconnection hole structure 530 and the interconnection metal layer 200. If the thickness of the sub-protective layer 710 is too small, it is easy to cause the formation of the sub-protective layer 710 to be difficult, affecting the formation quality of the sub-protective layer 710, and thus affecting the formation quality of the protective layer 720. For this reason, in this embodiment, the protective layer 720 includes multiple sub-protective layers 710 that are conformally covered and stacked in sequence, and the thickness of the sub-protective layer 710 is 15 nm to 400 nm.
[0076] In this embodiment, the material of the sub-protective layer 710 in contact with the through-interconnection hole structure 530 includes SiN, SiON, SiC, or Al2O3. That is to say, when forming the second opening for forming the through-interconnection hole structure 530, the material of the sub-protective layer 710 exposed by the second opening includes SiN, SiON, SiC, or Al2O3. These materials have relatively high hardness and can have less damage during the formation of the second opening, which is beneficial to keeping the top of the second opening at the original opening size without forming a "flare" morphological defect.
[0077] As an example, in this embodiment, the protective layer 720 is composed of 3 sub-protective layers 710. The materials of the sub-protective layer 710 farthest from the through-interconnection hole structure 530 to the sub-protective layer 710 closest to the through-interconnection hole structure 530 are SiN, SiO2, and SiN respectively.
[0078] It should be noted that in the manufacturing process of the semiconductor structure, a first opening is first formed in the dielectric layer, and a part of the dielectric layer with a certain thickness is reserved at the bottom of the first opening. After forming the protective layer on the sidewall of the first opening, a second opening is formed by patterning through the dielectric layer along the first opening, and finally the through-interconnection hole structure 530 is formed in the second opening. Therefore, in this embodiment, the bottom through-interconnection hole structure 530 is in contact with the dielectric layer.
[0079] In this embodiment, the semiconductor structure further includes: a barrier layer 210, covering the top of the interconnection metal layer 200 exposed on the substrate 100.
[0080] The barrier layer 210 is used to block the diffusion of metal ions in the interconnection metal layer 200.
[0081] In other embodiments, it is also possible to retain a barrier layer between the interconnection metal layer and the protective layer.
[0082] In this embodiment, the material of the barrier layer 210 includes one or more of TiN and TaN.
[0083] The TiN and TaN materials can play a good role in blocking the diffusion of ions.
[0084] Figures 6 to 14 It is a schematic diagram corresponding to each step in an embodiment of the method for forming a semiconductor structure of the present invention.
[0085] Refer to Figure 6 , a substrate 100 is provided. An interconnect metal layer 200 is formed in the substrate 100. The top surface of the interconnect metal layer 200 is exposed on the substrate 100. The interconnect metal layer 200 includes an interconnect region 100A for interconnection.
[0086] The substrate 100 is used to provide an operation basis for the subsequent process of forming the through-hole interconnect structure.
[0087] In this embodiment, according to the actual process conditions, functional structures may be formed in the substrate 100. For example, semiconductor devices such as MOS field effect transistors may be formed in the substrate 100, and a resistance structure may also be formed.
[0088] The interconnect metal layer 200 is used to achieve electrical connection with the through-hole interconnect structure subsequently to realize basic circuit functions.
[0089] Specifically, in this embodiment, the interconnect metal layer 200 includes an interconnect region 100A, which is a region for subsequent interconnection with the through-hole interconnect structure.
[0090] In this embodiment, the material of the interconnect metal layer 200 includes aluminum.
[0091] Aluminum has advantages such as low cost, good diffusion stability, good conductivity, and a process that can form a thick aluminum layer. In this embodiment, if the interconnect metal layer 200 is a top metal layer, using aluminum can form a relatively stable and thick enough top metal layer.
[0092] In this embodiment, in the step of providing the substrate 100, the substrate 100 includes a plurality of spaced interconnect metal layers 200, constituting different circuit structures.
[0093] In this embodiment, in the step of providing the substrate 100, a barrier layer 210 is formed on the top of the interconnect metal layer 200.
[0094] The barrier layer 210 is used to play a role in blocking the diffusion of metal ions in the interconnect metal layer 200.
[0095] In this embodiment, the material of the barrier layer 210 includes one or more of TiN and TaN.
[0096] TiN and TaN materials can play a good role in blocking ion diffusion.
[0097] Combined with reference Figure 6 and Figure 7 , a dielectric layer covering the substrate 100 is formed.
[0098] The dielectric layer is used to provide a process operation platform for the formation of the interconnection via structure 530.
[0099] Specifically, in this embodiment, the steps of forming the dielectric layer covering the substrate 100 include: referring to Figure 6 , a first dielectric layer 310 covering the substrate 100 is formed, and the first dielectric layer 310 also fills between adjacent interconnect metal layers 200; referring to Figure 7 , a second dielectric layer 500 covering the first dielectric layer 310 is formed.
[0100] The first dielectric layer 310 is used to electrically isolate adjacent interconnect metal layers 200.
[0101] In this embodiment, the material of the first dielectric layer 310 is an insulating material, including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxide, silicon carbon nitride, and silicon carbon oxynitride.
[0102] Specifically, in this embodiment, the steps of forming the first dielectric layer 310 covering the substrate 100 include: forming a dielectric material layer covering the interconnect metal layer 200 and filling the gaps between the interconnect metal layers 200.
[0103] The dielectric material layer is used to form the first dielectric layer 310.
[0104] In this embodiment, the dielectric material layer is planarized, and a part of the thickness of the dielectric material layer is removed, and the remaining dielectric material layer located on the interconnect metal layer 200 is retained as the first dielectric layer 310.
[0105] The planarization of the dielectric material layer provides a better process platform for subsequent processes on the first dielectric layer 310.
[0106] The second dielectric layer 500 is used to provide a process operation platform for the subsequent formation of the interconnection via structure and also to electrically isolate adjacent interconnection via structures.
[0107] In this embodiment, the material of the second dielectric layer 500 is an insulating material, including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxide, silicon carbon nitride, and silicon carbon oxynitride.
[0108] Combined with reference Figure 8 and Figure 9, patterning the dielectric layer, and forming a first opening 510 in the dielectric layer on the interconnection metal layer 200 in the interconnection region 100A.
[0109] The first opening 510 is used as an initial opening for subsequently forming a second opening.
[0110] In this embodiment, in the step of patterning the dielectric layer and forming a first opening 510 in the dielectric layer on the interconnect metal layer 200 in the interconnect region 100A, the difference between the opening size of the first opening 510 and the width size of the subsequently formed interconnect via structure should not be too large or too small. The difference between the opening size of the first opening 510 and the width size of the subsequently formed interconnect via structure is the space for the subsequent formation of the protective layer. If the difference between the opening size of the first opening 510 and the width size of the subsequently formed interconnect via structure is too large, the protective layer on both sides of the interconnect via structure may occupy too much space, resulting in too little space for the formation of the interconnect via structure, thereby easily affecting the formation of the interconnect via structure and the electrical connection performance between the interconnect via structure and the interconnect metal layer 200. If the difference between the opening size of the first opening 510 and the width size of the subsequently formed interconnect via structure is too small, the formation of the protective layer may be difficult, and the protective layer may not be effective in protecting the dielectric layer on both sides of the interconnect via structure, thereby making it difficult to ensure the performance of the semiconductor structure. To this end, in this embodiment, in the step of forming the first opening 510 in the dielectric layer on the interconnection metal layer 200 in the interconnection region 100A, the difference between the opening size of the first opening 510 and the width size of the subsequently formed interconnection via structure is 45 nm to 1200 nm.
[0111] It should be noted that during the fabrication process of the semiconductor structure, a first opening 510 is formed in a partially thick dielectric layer, with a partially thick dielectric layer remaining at the bottom of the first opening 510. Specifically, in this embodiment, during the step of patterning the dielectric layer to form the first opening 510 in the dielectric layer on the interconnect metal layer 200 in the interconnect region 100A, the first opening 510 penetrates the second dielectric layer 500 and is located in the partially thick first dielectric layer 310. Since the etching depth of the first opening 510 is relatively large, the over-etching (OE) control capability is poor. Therefore, retaining a partially thick dielectric layer 310 can protect the interconnect metal layer 200 and minimize damage to the interconnect metal layer 200 due to the poor over-etching control capability. Furthermore, removing a partially thick first dielectric layer 310 helps reduce the height difference on the surface of the first dielectric layer 310, thereby reducing the height difference on the surface of the remaining first dielectric layer 310. This improves the over-etching control capability when the remaining first dielectric layer 310 is subsequently etched along the first opening 510.
[0112] In other embodiments, a first opening exposing the top surface of the barrier layer may also be formed.
[0113] Referring Figure 8 , for the patterned dielectric layer, the step of forming the first opening 510 in the dielectric layer on the interconnect metal layer 200 in the interconnect region 100A includes: forming a mask layer 600 on the dielectric layer, with a mask opening 610 formed in the mask layer 600 and located above the interconnect region 100A, and the mask opening 610 exposing the top surface of the dielectric layer.
[0114] The mask layer 600 is used as a mask for patterning the dielectric layer.
[0115] In this embodiment, the mask layer 600 is a photoresist.
[0116] Referring Figure 9 , patterning the dielectric layer along the mask opening 610, removing a part of the thickness of the dielectric layer, and forming the first opening 510.
[0117] Patterning the dielectric layer along the mask opening 610 can play a better protective role for the top of the dielectric layer during the etching process of the dielectric layer.
[0118] Referring Figure 10 , after forming the first opening 510, it further includes: removing the mask layer 600.
[0119] Removing the mask layer 600 prepares for the subsequent formation of the protective layer.
[0120] Combined with reference Figures 11 to 13 , a protective layer 720 is formed on the sidewall of the first opening 510.
[0121] The protective layer 720 is used to protect the dielectric layer on the sidewall of the interconnection via structure 530 during the manufacturing process of the interconnection via structure 530.
[0122] In this embodiment, forming the protective layer 720 on the sidewall of the first opening 510 can protect the dielectric layer on the sidewall of the first opening 510 during the subsequent process of patterning through the dielectric layer along the first opening 510 to form the second opening, which is beneficial to reducing the probability that the dielectric layer at the top of the first opening 510 is over-etched and causing a "flare" defect at the top of the first opening 510. Correspondingly, it is beneficial to reducing the probability of forming a "flare" defect at the top of the subsequent formed interconnection via structure, thereby being beneficial to reducing the probability of short-circuit between adjacent interconnection via structures, being beneficial to ensuring the film quality of the interconnection via structure, and further being beneficial to ensuring the performance of the semiconductor structure.
[0123] In this embodiment, in the step of forming the protective layer 720 on the sidewall of the first opening 510, the protective layer 720 also extends to cover the top surface of the dielectric layer.
[0124] The protective layer 720 also extends to cover the top surface of the dielectric layer, and can protect the dielectric layer on the side of the top surface of the first opening 510 during the subsequent patterning of the second opening through the dielectric layer along the first opening 510. That is to say, the protective layer 720 protects the corners of the dielectric layer on both sides of the top of the first opening 510, so that during the etching process of the dielectric layer, the corners of the dielectric layer on both sides of the top of the first opening 510 will not be over-etched to produce the morphological defect of "flare", which further helps to reduce the probability of short circuit between adjacent interconnected via structures formed subsequently, further helps to ensure the film quality of the interconnected via structure, and further helps to ensure the performance of the semiconductor structure. Moreover, the protective layer 720 also extends to cover the top surface of the dielectric layer, increasing the dielectric depth on the side of the interconnected via structure 530, so that during the formation of the pseudo-interconnect structure in the dielectric on the side of the interconnected via structure 530, it is beneficial to reduce the probability of miscontact between the pseudo-interconnect structure and the underlying circuit structure, thus helping to ensure the performance of the semiconductor structure.
[0125] In this embodiment, in the step of forming the protective layer 720 on the sidewall of the first opening 510, the material of the protective layer 720 includes one or more of SiO2, SiN, SiON, SiC and Al2O3.
[0126] The materials of SiO2, SiN, SiON, SiC and Al2O3 are all easily obtainable materials and can play a good protective role.
[0127] In this embodiment, in the step of forming the protective layer 720 on the sidewall of the first opening 510, the protective layer 720 includes one or more sub-protective layers 710 that are conformally covered and stacked in sequence.
[0128] The multi-layer sub-protective layers 710 that are conformally covered and stacked in sequence means that in the multi-layer sub-protective layers 710, the upper sub-protective layer 710 conformally covers the lower sub-protective layer 710, and the multi-layers are stacked in sequence to form the protective layer 720.
[0129] In this embodiment, the protective layer 720 includes multi-layer sub-protective layers 710 that are conformally covered and stacked in sequence.
[0130] The protective layer 720 is composed of multi-layer sub-protective layers 710 that are conformally covered and stacked in sequence, so that the stress of the protective layer 720 is relieved, which is beneficial to reducing the stress generated by the formation of the protective layer 720 on the semiconductor structure.
[0131] It should be noted that in this embodiment, in the step of forming the protective layer 720 on the sidewall of the first opening 510, the number of sub-protective layers 720 should not be too large. If the number of sub-protective layers 720 is too large, it is likely to cause difficulties in forming the protective layer 720, and it is difficult to ensure the film quality of the multi-layer sub-protective layers 710. Therefore, in this embodiment, the number of sub-protective layers 720 is less than or equal to 11 layers.
[0132] As an example, in this embodiment, in the step of forming the protective layer 720 on the sidewall of the first opening 510, the protective layer 720 is composed of 3 sub-protective layers 710. The number of sub-protective layers 710 is appropriate, the film structure is simple, and it is easy to form the protective layer 720.
[0133] It should be noted that in this embodiment, in the step of forming the protective layer 720 on the sidewall of the first opening 510, the protective layer 720 includes multiple sub-protective layers 710 that are conformally covered and stacked in sequence. The thickness of the sub-protective layer 710 should not be too large or too small. If the thickness of the sub-protective layer 710 is too large, it is likely to cause the thickness of the formed protective layer 710 to be too large, which may lead to the problem that the space occupied by the protective layer 720 on both sides of the interconnection through-hole structure is too large, correspondingly resulting in too small space for the interconnection through-hole structure, thus easily affecting the formation of the interconnection through-hole structure and further easily affecting the electrical connection performance between the interconnection through-hole structure and the interconnection metal layer 200; if the thickness of the sub-protective layer 710 is too small, it is likely to cause greater difficulty in forming the sub-protective layer 710, affecting the formation quality of the sub-protective layer 710, and thus affecting the formation quality of the protective layer 720. For this reason, in this embodiment, the protective layer 720 includes multiple sub-protective layers 710 that are conformally covered and stacked in sequence, and the thickness of the sub-protective layer 710 is 15 nm to 400 nm.
[0134] In this embodiment, in the step of forming the protective layer 720 on the sidewall of the first opening 510, in the protective layer 720, the materials of the sub-protective layers 710 exposed by the first opening 510 include SiN, SiON, SiC or Al2O3. That is to say, these materials have relatively high hardness and can cause less damage during the formation of the second opening, which is beneficial to keeping the top of the second opening at the original opening size without forming a "flare" morphology defect.
[0135] As an example, in this embodiment, in the step of forming the protective layer 720 on the sidewall of the first opening 510, the protective layer 720 is composed of 3 sub-protective layers 710. The materials of the sub-protective layers 710 from the one closest to the sidewall of the first opening 510 to the one farthest from the sidewall of the first opening 510 are SiN, SiO2, and SiN respectively.
[0136] Reference Figure 11, the step of forming the protective layer 720 on the sidewall of the first opening 510 includes: forming one or more layers of protective material layers 700 stacked in sequence to cover the sidewall and bottom of the first opening 510 and the top surface of the dielectric layer.
[0137] The protective material layer 700 is used to form the sub-protective layer 710.
[0138] With reference to Figure 12 and Figure 13 , the protective material layer 700 at the bottom of the first opening 510 is removed, and the remaining protective material layer 700 is retained as the sub-protective layer 710, and one or more sub-protective layers 710 constitute the protective layer 720.
[0139] Removing the protective material layer 700 at the bottom of the first opening 510 to form the protective layer 720 is also used to prepare for exposing the top of the interconnect metal layer 200.
[0140] Specifically, in this embodiment, the step of removing the protective material layer 700 at the bottom of the first opening 510 includes: referring to Figure 12 , a discrete photoresist layer 800 is formed on the protective material layer 700 located on the top of the dielectric layer; referring to Figure 13 , the protective material layer 700 is patterned along the photoresist layer 800, the protective material layer 700 at the bottom of the first opening 510 and the protective material layer 700 at the position for forming other openings on the top of the dielectric layer are removed, and the protective layer 720 is formed.
[0141] In this embodiment, patterning the protective material layer 700 along the photoresist layer 800 is beneficial to further strengthen the protection of the dielectric layer on both sides of the top of the first opening 510 and the protective material layer 700, thereby further reducing the probability that the dielectric layer at the top of the first opening 510 is over-etched, resulting in the formation of a "flare" defect at the top of the first opening 510. It is further beneficial to reduce the probability of forming a "flare" defect at the top of the subsequent formed interconnect via structure, thereby further reducing the probability of short circuit between adjacent interconnect via structures, which is beneficial to ensuring the film quality of the interconnect via structure and further beneficial to ensuring the performance of the semiconductor structure.
[0142] Moreover, in this embodiment, processes such as BARC coating and Etch back are also omitted, which is beneficial to simplifying the process flow and improving the process efficiency.
[0143] In this embodiment, after forming the protective layer 720, it further includes: removing the photoresist layer 800.
[0144] Continuing to refer to Figure 13 , the dielectric layer is patterned along the first opening 510 to form the second opening 520.
[0145] The second opening 520 is used to provide a spatial position for subsequently forming an interconnected via structure.
[0146] In this embodiment, the barrier layer 210 exposed by the second opening 520 is also removed to expose the top of the interconnect metal layer 200.
[0147] In other embodiments, the barrier layer exposed by the second opening may also be retained, or part of the thickness of the barrier layer exposed by the second opening may be removed.
[0148] It should be noted that the thickness of the first dielectric layer 310 at the bottom of the first opening 510 is small, and the height difference of the top surface of the first dielectric layer 310 is small. During the process of removing the first dielectric layer 310 at the bottom along the first opening 510, the etching aspect ratio is small, and the control ability for over-etching is strong, which is beneficial to reducing the over-etching of the interconnect metal layer 200, and thus is beneficial to avoiding the problem of side etching in the interconnect metal layer 200.
[0149] In this embodiment, in the step of forming the second opening 520, the dielectric layer at the position for forming other openings is also patterned to form other openings.
[0150] Reference Figure 14 , an interconnected via structure 530 is formed in the second opening 520.
[0151] The interconnected via structure 530 is used to achieve electrical connection with the interconnect metal layer 200.
[0152] In this embodiment, the material of the interconnected via structure 530 includes copper.
[0153] Copper has good metal conductivity and small resistance, which is beneficial to obtaining an interconnected via structure 530 with better conductivity.
[0154] In this embodiment, in the step of forming the interconnected via structure 530 in the second opening 520, a pseudo-interconnect structure is also formed in other openings.
[0155] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be determined by the scope defined by the claims.
Claims
1. A semiconductor structure, characterized in that include: A substrate, wherein an interconnection metal layer is formed in the substrate, the substrate exposes a top surface of the interconnection metal layer, and the interconnection metal layer includes an interconnection area for interconnection; a dielectric layer covering the substrate; an interconnection through-hole structure, penetrating the dielectric layer on top of the interconnection metal layer in the interconnection region and electrically connected to the interconnection metal layer; The protection layer is located between the sidewall of the interconnection through-hole structure and the dielectric layer.
2. The semiconductor structure according to claim 1, wherein The protection layer also extends to cover the top surface of the dielectric layer.
3. The semiconductor structure according to claim 1, wherein: The protective layer includes one or more sub-protective layers sequentially and conformally covering the stacked layers.
4. The semiconductor structure according to claim 3, wherein: The number of the sub-protective layers is less than or equal to 11 layers.
5. The semiconductor structure according to claim 3, wherein: The protective layer includes multiple sub-protective layers sequentially stacked in a conformal manner, and the thickness of the sub-protective layers is 15 nm to 400 nm.
6. The semiconductor structure according to claim 3, wherein: In the protection layer, the material of the sub-protection layer in contact with the interconnection through-hole structure includes SiN, SiON, SiC or Al2O3.
7. The semiconductor structure according to claim 1 or 6, wherein: The material of the protective layer includes one or more of SiO2, SiN, SiON, SiC and Al2O3.
8. The semiconductor structure according to any one of claims 1 to 6, wherein: The thickness of the protective layer is 45 nm to 1200 nm.
9. The semiconductor structure according to claim 1, wherein: The substrate includes a plurality of isolated interconnected metal layers; The dielectric layer includes: a first dielectric layer covering the substrate, the first dielectric layer also filling between adjacent interconnect metal layers; The second dielectric layer is located on the first dielectric layer, and the second dielectric layer exposes the top surface of the interconnection through-hole structure.
10. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, wherein an interconnection metal layer is formed in the substrate, wherein a top surface of the interconnection metal layer is exposed by the substrate, and the interconnection metal layer includes an interconnection region for interconnection; forming a dielectric layer covering the substrate; patterning the dielectric layer to form a first opening in the dielectric layer on the interconnect metal layer in the interconnect region; forming a protective layer on a sidewall of the first opening; Patterning the dielectric layer along the first opening to form a second opening; An interconnect via structure is formed in the second opening.
11. The method for forming a semiconductor structure according to claim 10, wherein: The step of patterning the dielectric layer to form a first opening in the dielectric layer on the interconnect metal layer in the interconnect area comprises: forming a mask layer on the dielectric layer, wherein the mask layer has a mask opening located above the interconnect area, the mask opening exposing the top surface of the dielectric layer; patterning the dielectric layer along the mask opening, removing a portion of the dielectric layer to form the first opening; After forming the first opening, the method further includes: removing the mask layer.
12. The method for forming a semiconductor structure according to claim 10, wherein: In the step of patterning the dielectric layer and forming a first opening in the dielectric layer on the interconnection metal layer in the interconnection area, the difference between the opening size of the first opening and the width size of the interconnection through-hole structure is 45 nm to 1200 nm.
13. The method for forming a semiconductor structure according to claim 10, wherein: In the step of forming a protection layer on the sidewall of the first opening, the protection layer also extends to cover the top surface of the dielectric layer.
14. The method for forming a semiconductor structure according to claim 10, wherein: In the step of forming a protection layer on the sidewall of the first opening, the protection layer includes one or more sub-protection layers sequentially and conformally covered and stacked.
15. The method for forming a semiconductor structure according to claim 14, wherein: In the step of forming a protective layer on the sidewall of the first opening, the number of layers of the sub-protective layer is less than or equal to 11 layers.
16. The method for forming a semiconductor structure according to claim 14, wherein: In the step of forming a protective layer on the sidewall of the first opening, the thickness of the sub-protective layer is 15 nm to 400 nm.
17. The method for forming a semiconductor structure according to claim 14, wherein: In the step of forming a protective layer on the sidewall of the first opening, the material of the sub-protective layer exposed by the first opening in the protective layer includes SiN, SiON, SiC or Al2O3.
18. The method for forming a semiconductor structure according to claim 10 or 17, wherein: In the step of forming a protection layer on the sidewall of the first opening, a material of the protection layer includes one or more of SiO 2 , SiN, SiON, SiC and Al 2 O 3 .
19. The method for forming a semiconductor structure according to claim 14, wherein: The step of forming a protective layer on the sidewall of the first opening includes: forming one or more layers of protective material layers stacked in sequence to cover the sidewall and bottom of the first opening and the top surface of the dielectric layer; The protective material layer at the bottom of the first opening is removed, and the remaining protective material layer is retained as the sub-protective layer. One or more sub-protective layers constitute the protective layer.
20. The method for forming a semiconductor structure according to claim 10, wherein: In the step of providing the substrate, the substrate includes a plurality of spaced-apart interconnected metal layers; The step of forming a dielectric layer covering the substrate includes: forming a first dielectric layer covering the substrate, wherein the first dielectric layer is also filled between adjacent interconnect metal layers; forming a second dielectric layer covering the first dielectric layer; The dielectric layer is patterned, and in the step of forming a first opening in the dielectric layer on the interconnection metal layer in the interconnection region, the first opening penetrates the second dielectric layer and is located in a partial thickness of the first dielectric layer.