Dynamic Balance Control Method for Midpoint Voltage of Multilevel Converter

Abstract

The present application relates to the field of power electronics technology, and in particular to a method for dynamic balancing control of the midpoint voltage of a multi-level converter, comprising collecting the positive bus voltage and the negative bus voltage, and calculating the deviation voltage of the DC side midpoint based on the positive bus voltage and the negative bus voltage; calculating the duty cycle in the current switching cycle based on the positive bus voltage, the negative bus voltage and the calculated deviation voltage of the DC side midpoint, combined with the acquired balance bridge current, the balance bridge inductance value and the switching cycle; determining the duty cycle of the upper and lower tubes of the balance bridge according to the comparison result of the deviation voltage with the preset positive and negative threshold values; performing carrier comparison based on the determined duty cycle of the upper and lower tubes of the balance bridge, generating a PWM signal and driving the upper and lower tubes of the balance bridge. The present application can meet the high responsiveness and high precision requirements of the multi-level converter for the midpoint voltage balancing performance under dynamic operating conditions.

Description

Technical Field

[0001] The present application relates to the field of power electronics technology, and in particular to a method for dynamically balancing the midpoint voltage of a multi-level converter. Background Art

[0002] With the rapid development of power electronics technology, multilevel converters have been widely used in medium-, high-voltage, and high-power applications. Compared with traditional two-level converters, multilevel converters, by introducing multiple levels, offer significant advantages such as low output voltage harmonics, reduced switching device voltage stress, and high efficiency. As a result, they have become an important topology in various scenarios, including industrial drives, renewable energy generation, and grid access.

[0003] In a typical three-level converter topology, the DC side typically contains multiple capacitors to provide an intermediate potential, enabling multi-level output. Because capacitors are affected by factors such as load current variations and system asymmetry, the DC side midpoint voltage is prone to fluctuations, leading to midpoint offset. To maintain the normal operation of the converter, a "balanced bridge" structure has been introduced in engineering practice. This structure adjusts the balanced bridge current by controlling the conduction state of the upper and lower tubes in the bridge arm, so that the midpoint voltage tends to be balanced, thereby stabilizing the voltage distribution across the entire DC side. Existing balanced bridge control strategies are typically based on the deviation of the midpoint voltage, using fixed control parameters or linear adjustment methods to calculate the duty cycle of the upper and lower tubes and combine them with PWM control.

[0004] However, existing balanced bridge control methods are often only suitable for static or weakly dynamic response scenarios. They struggle to achieve fast and accurate control when the midpoint voltage fluctuates rapidly or the load changes dramatically. On the one hand, duty cycle regulation fails to fully account for multi-dimensional factors such as the balanced bridge current, inductor parameters, and bus voltage, resulting in a slow control response. On the other hand, the control strategy fails to effectively avoid the risk of overcurrent in the bridge arms, posing a potential risk to system stability. Therefore, existing technologies are unable to meet the high responsiveness and high precision requirements for midpoint voltage balancing performance in multilevel converters under dynamic operating conditions. Developing a balanced bridge control strategy with fast response, high control accuracy, and excellent anti-interference capabilities has become a key issue that urgently needs to be addressed in the current technology. Summary of the Invention

[0005] This application provides a method for dynamically balancing the midpoint voltage of a multilevel converter, which can meet the high responsiveness and high precision requirements of the midpoint voltage balancing performance of the multilevel converter under dynamic operating conditions. This application provides the following technical solutions:

[0006] In a first aspect, the present application provides a method for dynamically balancing the midpoint voltage of a multi-level converter, the method comprising:

[0007] Collecting a positive bus voltage and a negative bus voltage, and calculating a deviation voltage at a DC side midpoint based on the positive bus voltage and the negative bus voltage;

[0008] The duty cycle in the current switching cycle is calculated based on the positive bus voltage, the negative bus voltage, and the calculated deviation voltage at the DC side midpoint, combined with the obtained balancing bridge current, balancing bridge inductance, and switching cycle;

[0009] Determining the duty cycle of the upper and lower tubes of the balancing bridge according to the comparison result of the deviation voltage and the preset positive and negative thresholds;

[0010] Carrier comparison is performed based on the determined duty cycle of the upper and lower tubes of the balancing bridge, and a PWM signal is generated to drive the upper and lower tubes of the balancing bridge.

[0011] In a specific embodiment, the topology of the balancing bridge includes:

[0012] Two switching tubes are connected in series between the positive and negative busbars S p and S n , connect the inductor to the midpoint of the two switching tubes and the midpoint of the DC bus;

[0013] Among them, when the balance bridge tube S p When conducting, the balanced bridge current i bb Flowing into the busbar midpoint, when the balance bridge pipe S n When conducting, the balanced bridge current i bb Outflow busbar midpoint.

[0014] In a specific implementation scheme, collecting the positive bus voltage and the negative bus voltage, and calculating the deviation voltage of the DC side midpoint based on the positive bus voltage and the negative bus voltage includes:

[0015] Collect positive bus voltage and negative bus voltage The real-time value of the DC side midpoint deviation voltage is calculated according to the following formula :

[0016] .

[0017] In a specific implementation scheme, the duty cycle in the current switching cycle is calculated based on the positive bus voltage, the negative bus voltage, and the calculated DC side midpoint deviation voltage, in combination with the acquired balancing bridge current, the balancing bridge inductance, and the switching cycle, including:

[0018] Duty cycle The calculation formula is as follows:

[0019] ;

[0020] in, and are all adjustable coefficients. is the balance bridge inductance value, is the switching period, is the balanced bridge current.

[0021] In a specific implementation scheme, determining the duty cycle of the upper and lower tubes of the balancing bridge according to the comparison result of the deviation voltage with the preset positive and negative thresholds includes:

[0022] If the deviation voltage Greater than the positive threshold When the balance bridge tube S p Duty cycle for , balance bridge undertube S n Duty cycle is 0;

[0023] If the deviation voltage Less than the negative threshold When the balance bridge tube S p Duty cycle 0, balance the bridge down tube S n Duty cycle for ;

[0024] If the deviation voltage At the positive threshold and negative threshold When the balance bridge is between S p Duty cycle 0, balance the bridge down tube S n Duty cycle is 0;

[0025] The formula for determining the duty cycle of the upper and lower tubes of the balance bridge is as follows:

[0026] .

[0027] In a specific implementation scheme, performing carrier comparison based on the determined duty cycles of the upper and lower tubes of the balancing bridge, generating a PWM signal, and driving the upper and lower tubes of the balancing bridge includes:

[0028] The duty cycles of the upper and lower tubes of the determined balance bridge are compared with the high-frequency triangle wave carrier in real time;

[0029] When the triangle wave amplitude is lower than the balance bridge upper tube S p Duty cycle When the output balance bridge tube S p The PWM driving signal is high level, otherwise it is low level;

[0030] When the triangle wave amplitude is lower than the balance bridge tube S n Duty cycle When the output balance bridge tube S n The PWM driving signal is high level, otherwise it is low level.

[0031] In a second aspect, the present application provides a multi-level converter midpoint voltage dynamic balance control system, which adopts the following technical solution:

[0032] A multi-level converter midpoint voltage dynamic balance control system, comprising:

[0033] a deviation voltage calculation module, configured to collect the positive bus voltage and the negative bus voltage, and calculate the deviation voltage of the DC side midpoint based on the positive bus voltage and the negative bus voltage;

[0034] A duty cycle calculation module is used to calculate the duty cycle in the current switching cycle based on the positive bus voltage, the negative bus voltage and the calculated deviation voltage of the DC side midpoint, combined with the obtained balancing bridge current, the balancing bridge inductance value and the switching cycle;

[0035] A duty cycle determination module for upper and lower tubes, configured to determine the duty cycles of the upper and lower tubes of the balancing bridge according to a comparison result between the deviation voltage and a preset positive and negative threshold value;

[0036] The driving signal generation module is used to perform carrier comparison based on the determined duty cycle of the upper and lower tubes of the balancing bridge, generate a PWM signal and drive the upper and lower tubes of the balancing bridge.

[0037] In a third aspect, the present application provides an electronic device comprising a processor and a memory; the memory stores a program, which is loaded and executed by the processor to implement a dynamic balancing control method for the midpoint voltage of a multi-level converter as described in the first aspect.

[0038] In a fourth aspect, the present application provides a computer-readable storage medium, wherein the storage medium stores a program, and when the program is executed by a processor, it is used to implement a multi-level converter midpoint voltage dynamic balance control method as described in the first aspect.

[0039] In summary, the beneficial effects of this application include at least:

[0040] (1) It can intervene quickly when the midpoint voltage deviates significantly. Through closed-loop regulation with dual voltage and current feedback, it can accurately generate the required current compensation in a very short time, allowing the midpoint voltage to quickly return to balance. This high-response, high-precision control capability significantly shortens the balance recovery time. Even in the case of sudden load changes or bus fluctuations, it can ensure that the DC side midpoint potential is always maintained in a safe and symmetrical operating range, thereby improving the stability and reliability of the converter in dynamic operating environments.

[0041] (2) After the balancing action is completed, it can automatically enter the idle state to avoid invalid switching actions, greatly reducing device switching losses and electromagnetic interference. At the same time, through the organic combination of current feedback and the inductor volt-second balance principle, it effectively suppresses the risk of overcurrent and oscillation. This intelligent threshold dead zone and overcurrent protection mechanism not only improves system efficiency, but also extends the life of power devices and enhances the anti-interference and self-protection capabilities of the entire machine under complex working conditions.

[0042] By collecting the DC-side positive and negative bus voltages and the balanced bridge current in real time, the midpoint potential deviation is quantified and mapped to a reference current. This is then combined with the actual current and the bridge arm inductance characteristics to dynamically adjust the current injection or withdrawal using a pre-set response gain. Finally, the required current regulation is converted into a precise PWM drive signal to control the on and off of the upper and lower transistors. When the midpoint deviation exceeds the set threshold, the corresponding bridge arm is specifically turned on to quickly correct the voltage imbalance. When the deviation falls back to an acceptable range, the upper and lower transistors are automatically turned off to reduce ineffective switching and power loss. At the same time, through the organic combination of current feedback and the principle of inductive volt-second balance, as well as adjustable gain parameters, a rapid response to transient disturbances and high-precision suppression of steady-state errors are achieved. The risks of overcurrent and oscillation are effectively avoided throughout the entire process, thus meeting the high responsiveness and high precision requirements of the multilevel converter for DC-side midpoint voltage balance under dynamic operating conditions.

[0043] The above description is only an overview of the technical solution of the present application. In order to more clearly understand the technical means of the present application and to implement it in accordance with the contents of the specification, the following is a detailed description of the preferred embodiments of the present application in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 This is a topological diagram of a balanced bridge in an embodiment of the present application.

[0045] Figure 2 This is a schematic diagram of the overall flow of a method for dynamically balancing the midpoint voltage of a multi-level converter in an embodiment of the present application.

[0046] Figure 3 This is a topological diagram of a balanced bridge applied to a diode-clamped three-level converter in an embodiment of the present application.

[0047] Figure 4 It is a verification effect diagram of the technical effect in the embodiment of this application.

[0048] Figure 5 This is a structural block diagram of a multi-level converter midpoint voltage dynamic balance control system in an embodiment of the present application.

[0049] Figure 6 It is a block diagram of an electronic device for dynamic balancing control of the midpoint voltage of a multi-level converter in an embodiment of the present application. DETAILED DESCRIPTION

[0050] The following embodiments are used to illustrate the present invention, but are not intended to limit the scope of the present invention.

[0051] Optionally, the present application uses the multi-level converter midpoint voltage dynamic balancing control method provided in each embodiment as an example for description in an electronic device, where the electronic device is a terminal or a server. The terminal can be a mobile phone, a computer, a tablet computer, etc. This embodiment does not limit the type of electronic device.

[0052] Reference Figure 1 , is a balanced bridge topology diagram in the embodiment of the present application, where two switching tubes are connected in series between the positive and negative busbars. S p and S n , and then an inductor L bb Connected to the midpoint of the two switching tubes and the midpoint of the DC bus. S p When conducting, the balanced bridge current i bb Flows into the bus midpoint, positive bus voltage u p Reduce, negative bus voltage u n Raise; when the balance bridge under the pipe S n When conducting, the balanced bridge current i bb Outgoing bus midpoint, positive bus voltage u p Increase, negative bus voltage u n Therefore, the DC side midpoint voltage can be adjusted by controlling the upper and lower tubes of the balance bridge.

[0053] Reference Figure 2, is a schematic diagram of the overall flow of a method for dynamically balancing the midpoint voltage of a multi-level converter according to an embodiment of the present application. The method includes at least the following steps:

[0054] Step S101 : collecting the positive bus voltage and the negative bus voltage, and calculating the deviation voltage of the DC side midpoint based on the positive bus voltage and the negative bus voltage.

[0055] In step S101, first collect the positive bus voltage and negative bus voltage Real-time value of positive bus voltage and negative bus voltage The potential conditions at both ends of the DC busbar are reflected respectively, and then the deviation voltage at the DC midpoint is calculated according to the following formula :

[0056] ;

[0057] It should be noted that, under ideal equilibrium conditions, the DC side midpoint potential should be located in the middle of the positive and negative bus voltages, that is, half of the sum of the voltages at both ends.

[0058] Step S102 : Calculate the duty cycle in the current switching cycle based on the positive bus voltage, the negative bus voltage, and the calculated DC side midpoint deviation voltage, the obtained balancing bridge current, the balancing bridge inductance, and the switching cycle.

[0059] In step S102, the balancing bridge current is first collected, and then the duty cycle in the current switching cycle is calculated based on the positive bus voltage, the negative bus voltage and the calculated deviation voltage of the DC side midpoint, combined with the obtained balancing bridge current, the balancing bridge inductance and the switching cycle. The calculation formula is as follows:

[0060] ;

[0061] in, and are all adjustable coefficients. Map the deviation voltage to the balanced bridge reference current, Used to adjust the gain of the current error term in the duty cycle calculation, is the balance bridge inductance value, is the switching period, To balance the bridge current, the duty cycle It quantifies the average conduction ratio that needs to be applied to the upper and lower tubes of the balancing bridge under the current bus voltage and current conditions.

[0062] In the above formula, the calculation formula is derived from the improved principle of inductor volt-second balance. In order to make the current of the balanced bridge inductor close to the reference value at the end of a switching cycle, the controller needs to apply a suitable average voltage between the upper and lower tubes. The first term in the formula is the average inductor voltage increment required based on the current error. After adding the negative bus voltage and dividing it by the total voltage, the average voltage requirement is converted into the actual duty cycle. Unlike traditional duty cycle calculations based only on voltage deviation or simple proportional control, this method introduces current feedback and combines the dynamic characteristics of the inductor with the bidirectional feed of the bus voltage. This allows the required average voltage to be generated quickly and accurately during dynamic load changes or bus fluctuations, effectively improving the response speed and control accuracy of the midpoint voltage balance, while suppressing overcurrent risks and system oscillations.

[0063] Step S103: determining the duty ratios of the upper and lower transistors of the balancing bridge according to the comparison result between the deviation voltage and the preset positive and negative thresholds.

[0064] In step S103, the calculated DC side midpoint deviation voltage is converted to With the preset positive and negative thresholds as well as Compare to determine the duty cycle of the upper and lower tubes of the balance bridge.

[0065] Specifically, if the deviation voltage Greater than the positive threshold When the positive bus voltage is lowered and the negative bus voltage is raised, the positive bus voltage is lowered and the negative bus voltage is raised by injecting negative current into the bus midpoint. S p To achieve this, the balanced bridge tube S p Duty cycle for , balance bridge undertube S n Duty cycle 0. That is, the balance bridge tube S p In each switching cycle, the At the same time, to ensure that there is no current action in the opposite direction during the current cycle, the bridge tube under the balance S n Completely shut down, Through such a configuration, the average current from the positive bus to the midpoint is finely controlled with an adjustable duty cycle, thereby achieving smooth and rapid correction of the midpoint potential.

[0066] If the deviation voltage Less than the negative threshold When the midpoint potential is low, it is necessary to extract the midpoint current to increase the positive bus voltage and reduce the negative bus voltage. In this balanced bridge topology, by turning on the lower tube S n To achieve this, the balanced bridge tube S p Duty cycle 0, balance the bridge down tube S n Duty cycle for . That is, keep the top tube S p Completely shut down, the reason for using Rather than directly using As the duty cycle of the lower tube, it is because in the PWM generation, the calculated Essentially, this is a reference value for the high-side transistor conduction ratio. To achieve current injection of equivalent magnitude but opposite direction, the conduction window must be complementary to the carrier waveform, so that the low-side transistor conduction period overlaps with the high-side transistor blanking period. This provides the required average voltage drop within the same switching cycle. This complementary duty cycle design ensures the required reverse current while preventing short circuits caused by simultaneous conduction of the upper and lower transistors, thereby improving system switching safety.

[0067] If the deviation voltage At the positive threshold and negative threshold When the midpoint offset is between 0 and 1, it means that the midpoint offset is within the acceptable range and no balance bridge action is required. S p Duty cycle 0, balance the bridge down tube S n Duty cycle When both upper and lower transistors are off, the bridge circuit is isolated from the main converter bus capacitor, preventing any ineffective current flow. Furthermore, this idle zone strategy significantly reduces the number of switching cycles and voltage stress at the switching frequency, thereby reducing losses and heat generation in the switching devices. Finally, by maintaining a static state within a small deviation range, the system avoids control jitter caused by deviation noise, improving the robustness and efficiency of the overall control loop.

[0068] In practice, the duty cycle of the upper and lower tubes of the balance bridge is determined as follows:

[0069] ;

[0070] Step S104: Carrier comparison is performed based on the determined duty cycles of the upper and lower tubes of the balancing bridge, and a PWM signal is generated to drive the upper and lower tubes of the balancing bridge.

[0071] In step S104, the duty cycle of the upper and lower tubes of the balanced bridge is compared with the high-frequency triangle wave carrier in real time. When the amplitude of the triangle wave is lower than that of the upper tube of the balanced bridge, the duty cycle of the upper and lower tubes of the balanced bridge is compared with the high-frequency triangle wave carrier in real time. S p Duty cycle When the output balance bridge tube S p The PWM drive signal is high level, otherwise it is low level. Similarly, when the triangle wave amplitude is lower than the balance bridge tube S n Duty cycle When the output balance bridge tube S n The PWM drive signal is high when the duty cycle is set, and low otherwise. Through this duty cycle-carrier comparison method, the conduction period of the upper and lower transistors of the balance bridge is accurately divided within each switching cycle, realizing digital control of the average conduction ratio.

[0072] In summary, the present application collects the DC side positive and negative bus voltages and balanced bridge currents in real time, quantifies the midpoint potential deviation and maps it to a reference current, and then combines the actual current with the bridge arm inductance characteristics to dynamically adjust the current injection or extraction amount through a pre-set response gain, and finally converts the required current regulation into a precise PWM drive signal to control the conduction and shutdown of the upper and lower tubes. When the midpoint deviation exceeds the set threshold, the corresponding bridge arm will be turned on in a targeted manner to quickly correct the voltage imbalance, and when the deviation falls back to an acceptable range, the upper and lower tubes will be automatically stopped to reduce invalid switching and power loss; at the same time, through the organic combination of current feedback and the inductor volt-second balance principle, as well as adjustable gain parameters, a rapid response to transient disturbances and high-precision suppression of steady-state errors are achieved, and the risks of overcurrent and oscillation are effectively avoided throughout the process, thereby meeting the high responsiveness and high precision requirements of the multi-level converter for DC side midpoint voltage balance under dynamic operating conditions.

[0073] In addition, as a preferred embodiment, in order to verify the effective effect of the control strategy of the present application, the balanced bridge topology is as follows: Figure 3 As shown, it is integrated into a diode-clamped three-level converter. The main parameters are set as follows: DC bus voltage is 750V, load voltage RMS is 230V, balance bridge inductance is 750uH, switching period is 62.5us, and They are 0.1 and 2 respectively.

[0074] In the initial operation, that is, before time t, since the balancing bridge is not enabled, the upper and lower DC bus capacitors are unbalanced, and the negative bus voltage is significantly higher than the positive bus voltage. When time t arrives, the balancing bridge control strategy is officially started, and the closed-loop process of steps S101-S104 is entered. Figure 4As shown, after time t, the positive and negative bus voltages converge rapidly, reaching symmetrical balance within several switching cycles. The system operates stably with no additional power loss. This embodiment intuitively verifies that the control strategy of this application can both quickly respond to midpoint offsets and automatically stabilize after balancing under dynamic load and switch control, thereby significantly improving the dynamic balance performance of the DC side midpoint voltage of the multilevel converter and system efficiency.

[0075] Figure 5 This is a structural block diagram of a multi-level converter midpoint voltage dynamic balance control system provided by an embodiment of the present application. The system includes at least the following modules:

[0076] A deviation voltage calculation module is used to collect the positive bus voltage and the negative bus voltage, and calculate the deviation voltage of the DC side midpoint based on the positive bus voltage and the negative bus voltage;

[0077] A duty cycle calculation module is used to calculate the duty cycle in the current switching cycle based on the positive bus voltage, the negative bus voltage and the calculated deviation voltage of the DC side midpoint, combined with the obtained balancing bridge current, the balancing bridge inductance value and the switching cycle;

[0078] The upper and lower tube duty cycle determination module is used to determine the duty cycle of the upper and lower tubes of the balance bridge according to the comparison result of the deviation voltage and the preset positive and negative thresholds;

[0079] The driving signal generation module is used to perform carrier comparison based on the determined duty cycle of the upper and lower tubes of the balancing bridge, generate a PWM signal and drive the upper and lower tubes of the balancing bridge.

[0080] For relevant details, please refer to the above method embodiment.

[0081] Figure 6 4 is a block diagram of an electronic device provided in one embodiment of the present application. The device includes at least a processor 401 and a memory 402.

[0082] Processor 401 may include one or more processing cores, such as a quad-core processor or an octa-core processor. Processor 401 may be implemented in hardware using at least one of the following: a DSP (Digital Signal Processing), an FPGA (Field-Programmable Gate Array), or a PLA (Programmable Logic Array). Processor 401 may also include a main processor and a coprocessor. The main processor is used to process data in the awake state, also known as a CPU (Central Processing Unit); the coprocessor is a low-power processor used to process data in the standby state. In some embodiments, processor 401 may be integrated with a GPU (Graphics Processing Unit), which is responsible for rendering and drawing content displayed on the display screen. In some embodiments, processor 401 may also include an AI (Artificial Intelligence) processor, which is used to handle computational operations related to machine learning.

[0083] The memory 402 may include one or more computer-readable storage media, which may be non-transitory. The memory 402 may also include high-speed random access memory and non-volatile memory, such as one or more disk storage devices and flash memory storage devices. In some embodiments, the non-transitory computer-readable storage medium in the memory 402 is used to store at least one instruction, which is executed by the processor 401 to implement the multi-level converter midpoint voltage dynamic balancing control method provided in the method embodiment of the present application.

[0084] In some embodiments, the electronic device may optionally include a peripheral device interface and at least one peripheral device. The processor 401, memory 402, and peripheral device interface may be connected via a bus or signal lines. Each peripheral device may be connected to the peripheral device interface via a bus, signal lines, or circuit boards. Illustratively, the peripheral devices include, but are not limited to, radio frequency circuitry, a touchscreen display, audio circuitry, and a power supply.

[0085] Of course, the electronic device may also include fewer or more components, which is not limited in this embodiment.

[0086] Optionally, the present application also provides a computer-readable storage medium, in which a program is stored. The program is loaded and executed by a processor to implement the multi-level converter neutral point voltage dynamic balancing control method of the above method embodiment.

[0087] Optionally, the present application also provides a computer product, which includes a computer-readable storage medium, in which a program is stored. The program is loaded and executed by a processor to implement the multi-level converter midpoint voltage dynamic balance control method of the above method embodiment.

[0088] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0089] The above embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that a person skilled in the art could make various modifications and improvements without departing from the spirit of the present application, all of which fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. A method for dynamically balancing the midpoint voltage of a multi-level converter, characterized in that: The method comprises: Collecting the positive bus voltage and the negative bus voltage, and calculating the deviation voltage of the DC side midpoint based on the positive bus voltage and the negative bus voltage, including: collecting the positive bus voltage and negative bus voltage The real-time value of the DC side midpoint deviation voltage is calculated according to the following formula : ; A balancing bridge is provided between the positive bus and the negative bus of the multilevel converter. The topology of the balancing bridge includes: two switching tubes connected in series between the positive and negative bus. S p and S n , connect the inductor to the midpoint of the two switching tubes and the midpoint of the DC bus; when the balance bridge tube S p When conducting, the balanced bridge current i bb Flowing into the busbar midpoint, when the balance bridge pipe S n When conducting, the balanced bridge current i bb Outflow busbar midpoint; Based on the positive bus voltage, the negative bus voltage, and the calculated DC side midpoint deviation voltage, combined with the obtained balance bridge current, balance bridge inductance, and switching period, the duty cycle in the current switching period is calculated, including: Duty cycle The calculation formula is as follows: ； in, and are all adjustable coefficients. is the balance bridge inductance value, is the switching period, is the balanced bridge current; The duty cycle of the upper and lower tubes of the balance bridge is determined according to the comparison result of the deviation voltage and the preset positive and negative thresholds, including: if the deviation voltage is Greater than the positive threshold When the balance bridge tube S p Duty cycle for , balance bridge undertube S n Duty cycle Is 0; if the deviation voltage Less than the negative threshold When the balance bridge tube S p Duty cycle 0, balance the bridge down tube S n Duty cycle for ; If the deviation voltage At the positive threshold and negative threshold When the balance bridge is between S p Duty cycle 0, balance the bridge down tube S n Duty cycle is 0; the duty cycle of the upper and lower tubes of the balance bridge is determined as follows: ； Carrier comparison is performed based on the determined duty cycle of the upper and lower tubes of the balancing bridge, and a PWM signal is generated to drive the upper and lower tubes of the balancing bridge.

2. The method for dynamic balancing control of midpoint voltage of a multilevel converter according to claim 1, wherein: The carrier comparison based on the determined duty cycle of the upper and lower tubes of the balancing bridge, generating a PWM signal and driving the upper and lower tubes of the balancing bridge includes: The duty cycles of the upper and lower tubes of the balanced bridge are respectively compared with the high-frequency triangle wave carrier in real time; When the triangle wave amplitude is lower than the balance bridge upper tube S p Duty cycle When the output balance bridge tube S p The PWM drive signal is high level, otherwise it is low level; When the triangle wave amplitude is lower than the balance bridge tube S n Duty cycle When the output balance bridge tube S n The PWM driving signal is high level, otherwise it is low level.

3. A multi-level converter midpoint voltage dynamic balance control system, characterized in that: include: Deviation voltage calculation module, used for collecting positive bus voltage and negative bus voltage, and calculating the deviation voltage of DC side midpoint based on the positive bus voltage and negative bus voltage, including: collecting positive bus voltage and negative bus voltage The real-time value of the DC side midpoint deviation voltage is calculated according to the following formula : ; A balancing bridge is provided between the positive bus and the negative bus of the multilevel converter. The topology of the balancing bridge includes: two switching tubes connected in series between the positive and negative bus. S p and S n , connect the inductor to the midpoint of the two switching tubes and the midpoint of the DC bus; when the balance bridge tube S p When conducting, the balanced bridge current i bb Flowing into the busbar midpoint, when the balance bridge pipe S n When conducting, the balanced bridge current i bb Outflow busbar midpoint The duty cycle calculation module is used to calculate the duty cycle of the current switching cycle based on the positive bus voltage, negative bus voltage, and the calculated DC side midpoint deviation voltage, combined with the obtained balance bridge current, balance bridge inductance, and switching cycle, including: Duty cycle The calculation formula is as follows: ； in, and are all adjustable coefficients. is the balance bridge inductance value, is the switching period, is the balanced bridge current; The upper and lower tube duty cycle determination module is used to determine the duty cycle of the upper and lower tubes of the balance bridge according to the comparison result of the deviation voltage and the preset positive and negative thresholds, including: if the deviation voltage Greater than the positive threshold When the balance bridge tube S p Duty cycle for , balance bridge undertube S n Duty cycle Is 0; if the deviation voltage Less than the negative threshold When the balance bridge tube S p Duty cycle 0, balance the bridge down tube S n Duty cycle for ; If the deviation voltage At the positive threshold and negative threshold When the balance bridge is between S p Duty cycle 0, balance the bridge down tube S n Duty cycle is 0; the duty cycle of the upper and lower tubes of the balance bridge is determined as follows: ； The driving signal generation module is used to perform carrier comparison based on the determined duty cycle of the upper and lower tubes of the balancing bridge, generate a PWM signal and drive the upper and lower tubes of the balancing bridge.

4. An electronic device, characterized in that: The device includes a processor and a memory; the memory stores a program, and the program is loaded and executed by the processor to implement a multi-level converter neutral point voltage dynamic balance control method according to any one of claims 1 to 2.

5. A computer-readable storage medium, characterized in that The storage medium stores a program, and when the program is executed by the processor, it is used to implement the multi-level converter midpoint voltage dynamic balance control method according to any one of claims 1 to 2.

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