A novel switched capacitor current-type quasi-Z-source inverter and its modulation method

Abstract

The present invention discloses a novel switched capacitor current-type quasi-Z-source inverter and a modulation method thereof. The positive and negative electrodes of the voltage source are connected to endpoints 1 and 2 of a Z-source impedance network via a third inductor and an eighth inductor, respectively. The Z-source impedance network includes a first switched capacitor, wherein endpoint 1 of the first switched capacitor is endpoint 1 of the Z-source impedance network, and endpoint 2 of the first switched capacitor is connected to endpoint 2 of the Z-source impedance network via a second inductor. Endpoint 2 of the second switched capacitor is connected to endpoint 1 of the Z-source impedance network via a first inductor. Endpoint 2 of the first switched capacitor is connected to endpoint 2 of the second switched capacitor via a first diode. In the first switched capacitor, endpoint 1 is connected to endpoint 2 sequentially via a third capacitor and a fourth inductor. Endpoint 1 is connected to endpoint 2 sequentially via a fifth inductor and a fourth capacitor. The second switched capacitor has the same structure as the first switched capacitor. The Z-source inverter of the present invention can improve the current-raising capability.

Description

Technical Field

[0001] The present invention relates to a novel switched capacitor current-type quasi-Z-source inverter topology and a modulation method thereof, and belongs to the technical field of current-type quasi-Z-source inverters. Background Art

[0002] To overcome the shortcomings of traditional voltage- and current-source inverters, a new inverter topology, the Z-source inverter, was proposed in 2002. Compared to traditional voltage- and current-source inverters, the Z-source inverter offers greater flexibility. Its DC input can be either a voltage source or a current source, and the connected AC load can be either inductive or capacitive. The Z-source inverter enables flexible buck-boost switching, allowing the upper and lower switches of the same arm of the inverter bridge to be turned on and off simultaneously without requiring dead time or commutation overlap, thus improving inverter reliability. Compared to voltage-source Z-source inverters, current-source Z-source inverters offer advantages such as fast dynamic response, strong current limiting capability, and the ability of the inductor in series on the DC side to effectively buffer reactive energy generated on the AC side. Consequently, they hold broad prospects for development in renewable energy generation, electric vehicles, microgrids, and other fields.

[0003] In recent years, to address the shortcomings of traditional current-source inverters, such as limited current-rate capability, high inductor current stress, and bulky inverters, numerous researchers at home and abroad have proposed various improved current-source Z-source / quasi-Z-source inverter topologies, including the current-source quasi-Z-source inverter, the switched-capacitor current-source quasi-Z-source inverter, the current-source Trans-Z-source inverter, and the Trans-quasi-Z-source inverter. Current-source quasi-Z-source inverters provide continuous input current, reducing inductor current stress and capacitor voltage stress, but do not improve current-rate capability. While the switched-capacitor current-source quasi-Z-source inverter offers higher current-rate capability and lower capacitor voltage stress, it also suffers from the disadvantages of increased passive component count, resulting in a larger inverter size and weight. Current-source Trans-Z-source and Trans-quasi-Z-source inverters improve current gain while reducing component count. However, their current gain is directly related to the transformer's turns ratio. Higher current gain requires a larger turns ratio, which increases the inverter size and cost. How to improve the inverter's current-raising capability, reduce the inductive current stress of the impedance network, and reduce the inverter's size and cost are key areas for improving the Z-source / quasi-Z-source topology and are technical issues that need to be further explored.

[0004] Leakage current not only increases the harmonic content of the system's output current, increasing system operating losses, but also causes high-frequency electromagnetic interference and, in severe cases, even poses a safety hazard. While existing topology improvements such as H5 and HERIC can suppress leakage current, they do so at the expense of increased component count. Therefore, developing new, efficient, and cost-effective leakage current suppression strategies is crucial. Summary of the Invention

[0005] The technical problem to be solved by the present invention is: how to further improve the current-rising capability of the switched capacitor current-type quasi-Z-source inverter and how to effectively suppress the system leakage current.

[0006] In order to further improve the current-raising capability of a switched capacitor current-mode quasi-Z-source inverter, the present invention provides a novel switched capacitor current-mode quasi-Z-source inverter, comprising a voltage source, wherein the positive electrode and the negative electrode of the voltage source are connected to terminal 1 and terminal 2 of a Z-source impedance network via a third inductor and an eighth inductor, respectively;

[0007] The Z source impedance network includes a first switched capacitor, wherein terminal 1 of the first switched capacitor is terminal 1 of the Z source impedance network, and terminal 2 of the first switched capacitor is connected to terminal 2 of the Z source impedance network via a second inductor L2;

[0008] End point 1 of the second switched capacitor is end point 2 of the Z source impedance network, and end point 2 of the second switched capacitor is connected to end point 1 of the Z source impedance network through the first inductor L1;

[0009] The second terminal of the first switch capacitor is connected to the second terminal of the second switch capacitor via the first diode D1;

[0010] In the first switching capacitor, terminal one is connected to terminal two via the third capacitor C3 and the fourth inductor L4 in sequence; terminal one is connected to terminal two via the third capacitor C3, the second diode D2, and the fourth capacitor C4 in sequence; terminal one is connected to terminal two via the fifth inductor L5 and the fourth capacitor C4 in sequence.

[0011] In the second switched capacitor, terminal one is connected to terminal two via the first capacitor C1 and the sixth inductor L6 in sequence; terminal one is connected to terminal two via the seventh inductor L7, the third diode D3, and the sixth inductor L6 in sequence; terminal one is connected to terminal two via the seventh inductor L7 and the second capacitor C2 in sequence.

[0012] In the aforementioned novel switched capacitor current-type quasi-Z-source inverter, a filter capacitor and a load are connected between terminal 1 and terminal 2 of the Z-source impedance network via an inverter bridge.

[0013] In the aforementioned novel switched capacitor current-type quasi-Z-source inverter, all inductance values ​​in the Z-source impedance network are L, and all capacitance values ​​are C.

[0014] A novel current boosting method for a switched capacitor current type quasi-Z source inverter, comprising: when the switched capacitor current type quasi-Z source inverter is working in an effective state, the inverter bridge is equivalent to a voltage source, and the DC link voltage U out Equal to the AC line voltage in the corresponding switch state;

[0015] When the inverter works in the direct-through state, the inverter bridge is equivalent to a zero-value voltage source, that is, short-circuited, U out =0;

[0016] When the inverter is in a non-open circuit state, including an effective state and a through state, the first diode D1, the second diode D2, and the third diode D3 are disconnected, and the first capacitor C1, the second capacitor C2, the third capacitor C3, and the fourth capacitor C4 are in a discharge state, then:

[0017] (1-1)

[0018] Where, I L1 , I L2 , I L4 , I L5 , I L6 , I L7 are the currents flowing through the first inductor L1, the second inductor L2, the fourth inductor L4, the fifth inductor L5, the sixth inductor L6, and the seventh inductor L7, respectively. C1 、i C2 、i C3 、i C4 are the currents flowing through the first capacitor C1, the second capacitor C2, the third capacitor C3, and the fourth capacitor C4, respectively. pn is the DC link output current flowing into the inverter bridge, I in is the input current.

[0019] In the aforementioned novel current boosting method of the switched capacitor current-type quasi-Z-source inverter, when the inverter is in an open-circuit state, the inverter bridge is equivalent to an open circuit. At this time, the first diode D1, the second diode D2, and the third diode D3 are turned on, and the first capacitor C1, the second capacitor C2, the third capacitor C3, and the fourth capacitor C4 are in a charging state. Then:

[0020] (1-2)

[0021] In steady state, one carrier cycle T s The average current value of the internal capacitor is zero, and the inductor current remains unchanged. According to formula (1-1) and formula (1-2), the inductor current I is calculated L1 , I L2 , I L4 , I L5 , I L6 , I L7 and DC link output current peak They are:

[0022] (1-3)

[0023] (1-4)

[0024] (1-5)

[0025] Where D op is the open circuit duty cycle, B is the current boost factor. op When the flow rate is less than 1 / 4, the flow-raising factor B>1, thus realizing the flow-raising function.

[0026] The aforementioned new switching capacitor current type quasi-Z source inverter current boost method, DC link output peak current is the equivalent DC input current of the inverter, the peak value of the inverter output phase current I omax Expressed as:

[0027] (1-6)

[0028] Where m is the modulation factor and G is the current gain. By setting the boost factor B and the modulation factor m, the inverter output current greater than or less than the input current can be obtained.

[0029] The aforementioned new type of switched capacitor current-type quasi-Z-source inverter current boost method can be seen from equations (1-1) to (1-4). If the currents flowing through the first capacitor C1, the second capacitor C2, the third capacitor C3, and the fourth capacitor C4 are equal, then:

[0030] (1-7)

[0031] Assume D a and D sh are the duty ratios of the effective state and the through state in one carrier cycle, respectively. The DC power supply voltage is U in In steady state, one carrier cycle T s The average voltage value of the internal inductor is zero, then:

[0032] (1-8)

[0033] (1-9)

[0034] Solving equations (1-8) and (1-9), we can calculate the voltages of each capacitor and the DC link voltage in the effective state:

[0035] (1-10)

[0036] (1-11).

[0037] A novel optimized SVPWM method for a switched capacitor current-mode quasi-Z-source inverter is proposed, comprising:

[0038] Step 1: Define the common-mode voltage U cmv for:

[0039] (1-12)

[0040] Where U PO 、U NO They are the voltage drops between points PO and NO in the inverter topology, point P is the endpoint one of the Z source impedance network, point N is the endpoint two of the Z source impedance network, and point O is the load neutral point;

[0041] According to the working principle of the new switched capacitor current-type quasi-Z source inverter, the bridge arm states Q of phases a, b, and c are k Expressed as:

[0042] (1-13)

[0043] The working states of the switched capacitor current-type quasi-Z-source inverter include 6 valid states, 3 direct-through zero states and 7 open-circuit zero states. When the switch device in the upper arm is turned on, U PO is the corresponding phase voltage; when all the switches in the upper arm are turned off, U PO =4U in +U NO Similarly, when the switch device in the lower bridge arm is turned on, U NO is the corresponding phase voltage; when all the switching devices in the lower bridge arm are turned off, U NO =-4U in +U PO ; When both upper and lower bridge arms are turned off, U PO =U NO =0;

[0044] Based on the analysis of common mode voltage in different switching states, the open circuit zero vector is selected as I 10 , and eliminate the direct zero vector, select the three non-zero vectors closest to the reference vector to synthesize I ref ;

[0045] Step 2: Based on the analysis of the vector synthesis scheme, the sectors are redistributed. The judgment of the sectors only requires comparing the three-phase current i a 、i b 、i c Assuming the reference current vector I ref In sector 1, we can get:

[0046] (1-14)

[0047] Simplifying, we can get i a ≥ib ≥i c , similarly, the judgment conditions for the remaining sectors are obtained;

[0048] Step 3: Calculate the effective vector action time, assuming that the reference current vector I ref In sector 1, I ref The effective vectors I6, I1, I2 and the open circuit zero vector I 10 Perform synthesis and list equations on the α and β axes to obtain:

[0049] (1-15)

[0050] Wherein, T1, T2, and T6 are the action times of the first effective current vector I1, the second effective current vector I2, and the sixth effective current vector I6 respectively; I α , I β They are the reference current vector I ref Components on the α and β axes;

[0051] Substitution According to formula (1-15), the action times of three adjacent effective vectors are:

[0052] (1-16)

[0053] Similarly, the action time T of three adjacent effective vectors in other different sectors can be calculated: x 、T y 、T z Expressions of

[0054] Step 4: Calculate the vector switching point, generate the PWM signal, and convert the carrier period T s Press T op / 4-T x / 2-T y / 2-T z / 2-T op / 2-T z / 2-T y / 2-T x / 2-T op / 4 switching sequence is distributed, when the reference current vector I ref When in sector 1, the first time point T corresponding to the switch state switching c1 , the second time point T c2 , the third time point T c3 , the fourth time point T c4 The expressions are:

[0055] (1-17).

[0056] The present invention achieves the following beneficial effects: Compared with current-source and switched-capacitor current-source quasi-Z-source inverters, the new switched-capacitor current-source quasi-Z-source inverter has a higher current-rise capability and, under the same input current and current gain conditions, achieves relatively low diode and switch current stress. The optimized SVPWM modulation strategy simplifies the calculation of sector determination, effectively reduces the common-mode voltage, and achieves relatively low diode and switch current stress. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] Figure 1 Schematic diagram of the topology structure of the novel switched capacitor current-type quasi-Z-source inverter in Example 1 of the present invention;

[0058] Figure 2 1 is an equivalent circuit diagram of different states of the novel switched capacitor current-type quasi-Z-source inverter in Example 1 of the present invention;

[0059] Figure 3 : is a current space vector distribution diagram of the optimized SVPWM modulation strategy in Example 1 of the present invention;

[0060] Figure 4 The optimized SVPWM modulation strategy I in embodiment 1 of the present invention ref Switching timing diagram when in sector 1;

[0061] Figure 5 This is a comparison chart of the current-raising capabilities of three inverters with different topologies;

[0062] Figure 6 This is a comparison chart of the DC link output peak current of three different inverter topologies;

[0063] Figure 7 Here are the output line voltage waveforms of three inverters with different topologies;

[0064] Figure 8 The output line current, DC link output current and common mode voltage waveforms of different SVPWM modulation strategies are shown;

[0065] Figure 9 It is a current-type quasi-Z-source inverter topology in the prior art;

[0066] Figure 10 It is an equivalent circuit diagram of a current-type quasi-Z-source inverter in different states in the prior art;

[0067] Figure 11 It is a switched capacitor current type quasi-Z source inverter topology in the prior art;

[0068] Figure 12 It is an equivalent circuit diagram of a switched capacitor current-type quasi-Z-source inverter in different states in the prior art;

[0069] Figure 13 It is the current space vector distribution diagram of the SVPWM modulation strategy in the prior art;

[0070] Figure 14 This is the SVPWM algorithm flow in the prior art. DETAILED DESCRIPTION

[0071] The technical solution of the present invention will be further described below with reference to the accompanying drawings.

[0072] Example 1

[0073] This embodiment provides a novel switched capacitor current-type quasi-Z-source inverter, the topology of which is as follows: Figure 1 As shown, it includes voltage source, DC side series inductor, Z source impedance network, inverter bridge, filter circuit and load:

[0074] Voltage source U in The positive terminal is connected to the terminal 1 of the Z source impedance network through the third inductor L3, and the voltage source U in The negative electrode is connected to the second terminal of the Z source impedance network through the eighth inductor L8;

[0075] The Z source impedance network includes a first switched capacitor, wherein terminal 1 of the first switched capacitor is terminal 1 of the Z source impedance network, and terminal 2 of the first switched capacitor is connected to terminal 2 of the Z source impedance network via a second inductor L2;

[0076] End point 1 of the second switched capacitor is end point 2 of the Z source impedance network, and end point 2 of the second switched capacitor is connected to end point 1 of the Z source impedance network through the first inductor L1;

[0077] A filter capacitor and a load are connected between terminal 1 of the Z source impedance network and terminal 2 of the Z source impedance network via an inverter bridge;

[0078] The second terminal of the first switch capacitor is connected to the second terminal of the second switch capacitor through the first diode D1.

[0079] In the first switching capacitor, terminal one is connected to terminal two via the third capacitor C3 and the fourth inductor L4 in sequence; terminal one is connected to terminal two via the third capacitor C3, the second diode D2, and the fourth capacitor C4 in sequence; terminal one is connected to terminal two via the fifth inductor L5 and the fourth capacitor C4 in sequence.

[0080] In the second switched capacitor, terminal one is connected to terminal two via the first capacitor C1 and the sixth inductor L6 in sequence; terminal one is connected to terminal two via the seventh inductor L7, the third diode D3, and the sixth inductor L6 in sequence; terminal one is connected to terminal two via the seventh inductor L7 and the second capacitor C2 in sequence.

[0081] In this embodiment, the two diodes of the switch capacitor in the prior art are replaced by inductors, thereby significantly improving the current-raising capacity of the impedance network without changing the complexity of the topological structure.

[0082] At the same time, a new current boosting method for a switched capacitor current-type quasi-Z-source inverter is provided, including:

[0083] Step 1: Assume that all devices are in ideal state, and all inductance values ​​in the Z source impedance network are L, and all capacitance values ​​are C. The new switched capacitor current-mode quasi-Z source inverter can operate in three states: active state, direct-through state, and open-circuit state.

[0084] Step 2: When the new switched capacitor current-type quasi-Z-source inverter is working in an effective state, the inverter bridge is equivalent to a voltage source, and the DC link voltage U out Equal to the AC line voltage in the corresponding switching state, the equivalent circuit is as follows Figure 2 As shown in (a) in .

[0085] When the inverter works in the direct-through state, the inverter bridge is equivalent to a zero-value voltage source, that is, short-circuited, U out =0, the equivalent circuit is Figure 2 As shown in (b) in .

[0086] When the inverter is in a non-open circuit state, including an effective state and a through state, the first diode D1, the second diode D2, and the third diode D3 are disconnected, and the first capacitor C1, the second capacitor C2, the third capacitor C3, and the fourth capacitor C4 are in a discharge state, then:

[0087] (1-1)

[0088] Where, I L1 , I L2 , I L4 , I L5 , I L6 , I L7 are the currents flowing through the first inductor L1, the second inductor L2, the fourth inductor L4, the fifth inductor L5, the sixth inductor L6, and the seventh inductor L7, respectively. C1 、i C2 、i C3 、i C4 are the currents flowing through the first capacitor C1, the second capacitor C2, the third capacitor C3, and the fourth capacitor C4, respectively. pn is the DC link output current flowing into the inverter bridge, I in is the input current.

[0089] When the inverter is in the open circuit state, the inverter bridge is equivalent to an open circuit, and the equivalent circuit is as follows: Figure 2(c) As shown. At this time, the first diode D1, the second diode D2, and the third diode D3 are turned on, and the first capacitor C1, the second capacitor C2, the third capacitor C3, and the fourth capacitor C4 are in a charging state, then:

[0090] (1-2)

[0091] In steady state, one carrier cycle T s The average current value of the internal capacitor is zero, and the inductor current remains unchanged. According to formula (1-1) and formula (1-2), the inductor current I is calculated L1 , I L2 , I L4 , I L5 , I L6 , I L7 and DC link output current peak They are:

[0092] (1-3)

[0093] (1-4)

[0094] (1-5)

[0095] Where D op is the open circuit duty cycle, B is the current boost factor. op When the flow rate is less than 1 / 4, the flow-raising factor B>1, thus realizing the flow-raising function.

[0096] DC link output peak current is the equivalent DC input current of the inverter, the peak value of the inverter output phase current I omax It can be expressed as:

[0097] (1-6)

[0098] Where m is the modulation factor and G is the current gain. By properly setting the boost factor B and the modulation factor m, you can achieve an inverter output current that is greater or less than the input current.

[0099] From equations (1-1) to (1-4), we can see that the currents flowing through the first capacitor C1, the second capacitor C2, the third capacitor C3, and the fourth capacitor C4 are equal, so:

[0100] (1-7)

[0101] Assume D a and D sh are the duty ratios of the effective state and the through state in one carrier cycle, respectively. The DC power supply voltage is Uin In steady state, one carrier cycle T s The average voltage value of the internal inductor is zero, then:

[0102] (1-8)

[0103] (1-9)

[0104] Solving equations (1-8) and (1-9), we can calculate the voltages of each capacitor and the DC link voltage in the effective state:

[0105] (1-10)

[0106] (1-11).

[0107] This embodiment also provides a novel optimized SVPWM modulation method for a switched capacitor current-mode quasi-Z-source inverter, including:

[0108] Step 1: Define the common-mode voltage U cmv for:

[0109] (1-12)

[0110] Where U PO 、U NO They are the voltage drops between PO and NO in the inverter topology, respectively. Figure 1 As shown, point P is the endpoint one of the Z source impedance network, point N is the endpoint two of the Z source impedance network, and point O is the load neutral point.

[0111] According to the working principle of the new switched capacitor current-type quasi-Z source inverter, the bridge arm states Q of phases a, b, and c are k It can be expressed as:

[0112] (1-13)

[0113] The working states of the new switched capacitor current-type quasi-Z-source inverter include 6 valid states, 3 direct-through zero states and 7 open-circuit zero states. PO is the corresponding phase voltage; when all the switches in the upper arm are turned off, U PO =4U in +U NO Similarly, when a switch device in the lower bridge arm is turned on, U NO is the corresponding phase voltage; when all the switching devices in the lower bridge arm are turned off, U NO =-4U in +U POWhen both upper and lower bridge arms are turned off, U PO =U NO =0.

[0114] The current vectors and corresponding common-mode voltages in different switching states are shown in Table 1. Based on the analysis of common-mode voltages in different switching states, the open-circuit zero vector is selected as I 10 , and eliminate the direct zero vector, select the three non-zero vectors closest to the reference vector to synthesize I ref .

[0115] Table 1: Current vectors and common-mode voltages in different switching states

[0116]

[0117] Step 2: Based on the analysis of the vector synthesis scheme, the sectors are redistributed as follows Figure 3 As shown, the judgment of the sector only requires comparing the three-phase current i a 、i b 、i c Assuming the reference current vector I ref In sector 1, we can get:

[0118] (1-14)

[0119] Simplifying, we can get i a ≥i b ≥i c Similarly, the judgment conditions for the remaining sectors are obtained, such as shown.

[0120] Table 2: Sector judgment conditions

[0121]

[0122] Step 3: Calculate the effective vector action time, assuming that the reference current vector I ref In sector 1, I ref The effective vectors I6, I1, I2 and the open circuit zero vector I 10 Perform synthesis and list equations on the α and β axes to obtain:

[0123] (1-15)

[0124] Wherein, T1, T2, and T6 are the action times of the first effective current vector I1, the second effective current vector I2, and the sixth effective current vector I6 respectively; I α , I β They are the reference current vector I ref In the components of the α and β axes, Table 1 lists 16 current vectors I1-I in each switching state. 16, Figure 3 The middle sector is distributed with the first to sixth effective current vectors I1-I6;

[0125] Substitution According to formula (1-15), the action times of three adjacent effective vectors are:

[0126] (1-16)

[0127] Similarly, the action time T of three adjacent effective vectors in other different sectors can be calculated: x 、T y 、T z The expression of , the results are shown in Table 3. x 、T y 、T z They correspond respectively to the action times of the three adjacent effective current vectors that are closest to the reference current vector and are arranged in increasing counterclockwise order according to the spatial angle.

[0128] Table 3: T in different sectors x 、T y and T z expression

[0129]

[0130] Step 4: Calculate the vector switching point, generate the PWM signal, and convert the carrier period T s Press T op / 4-T x / 2-T y / 2-T z / 2-T op / 2-T z / 2-T y / 2-T x / 2-T op / 4 switching sequence is distributed, when the reference current vector I ref When in sector 1, the switching sequence is as follows: As shown, the first time point T corresponding to the switch state switching c1 , the second time point T c2 , the third time point T c3 , the fourth time point T c4 The expressions are:

[0131] (1-17).

[0132] In the prior art, the current-type quasi-Z-source inverter topology is as follows: Figure 9As shown. Assume that all components are in ideal state, and L1=L2=L, C1=C2=C. According to the symmetry of the circuit, we can get:

[0133] (2-1)

[0134] Where, I L1 , I L2 are the currents flowing through the first inductor L1 and the second inductor L2, i C1 、i C2 are the currents flowing through the first capacitor C1 and the second capacitor C2, U C1 、U C2 are the voltages across the first capacitor C1 and the second capacitor C2 respectively.

[0135] The current-type quasi-Z-source inverter in the prior art can work in three states: active state, direct-through state and open-circuit state. When the inverter works in the active state, the inverter bridge can be equivalent to a voltage source, and the DC link voltage U out Equal to the AC line voltage in the corresponding switching state, the equivalent circuit is as follows Figure 10 When the inverter is working in the direct-through state, the inverter bridge can be equivalent to a zero-value voltage source, that is, short-circuited, U out =0, the equivalent circuit is 10 (b). When the inverter is in a non-open circuit state (including the effective state and the through state), the first diode D1 is disconnected, and the first capacitor C1 and the second capacitor C2 are in a discharge state, and:

[0136] (2-2)

[0137] Where, I pn is the DC link output current flowing into the inverter bridge, I in is the input current.

[0138] When the inverter is in the open circuit state, the inverter bridge is equivalent to an open circuit, and the equivalent circuit is as follows: 10 (c). At this time, the first diode D1 is turned on, and the first capacitor C1 and the second capacitor C2 are in the charging state, then:

[0139] (2-3)

[0140] In steady state, one carrier cycle T s The average current value of the internal capacitor is zero. According to formula (2-2) and formula (2-3), the inductor current I L and DC link output current peak They are:

[0141] (2-4)

[0142] (2-5)

[0143] Where D op is the open circuit duty cycle, B is the current boost factor. op When <0.5, the flow-raising factor B>1, thus realizing the flow-raising function.

[0144] Assume D a and D sh are the duty ratios of the effective state and the through state in one carrier cycle, respectively. The DC power supply voltage is U in Considering the steady state, a carrier cycle T s The average voltage value of the internal inductor is zero, so:

[0145] (2-6)

[0146] (2-7)

[0147] Solving equations (2-6) and (2-7), we can calculate the capacitor voltage and the DC link voltage in the effective state as follows:

[0148] (2-8)

[0149] (2-9)

[0150] In the prior art, the topology of the switched capacitor current-type quasi-Z-source inverter is as follows: Figure 11 Assume that all components are in ideal state, L1=L2=L, C1=C2=C3=C4=C. Figure 12 (a) and Figure 12 (b) shows the equivalent circuits of the inverter in the active and direct-through states, respectively. When the inverter is in a non-open-circuit state (including the active and direct-through states), the first diode D1, the third diode D3, and the sixth diode D6 are disconnected, the second diode D2, the fourth diode D4, the fifth diode D5, and the seventh diode D7 are conductive, and the first capacitor C1, the second capacitor C2, the third capacitor C3, and the fourth capacitor C4 are in a discharged state. Thus,

[0151] (3-1)

[0152] Where, I L1 , I L2 are the currents flowing through the first inductor L1 and the second inductor L2, i C1 、i C2 、iC3 、i C4 are the currents flowing through the first capacitor C1, the second capacitor C2, the third capacitor C3, and the fourth capacitor C4 respectively. pn is the DC link output current flowing into the inverter bridge, I in is the input current.

[0153] When the inverter is in the open circuit state, the inverter bridge is equivalent to an open circuit, and the equivalent circuit is as follows: Figure 12 (c) As shown. At this time, the first diode D1, the third diode D3, and the sixth diode D6 are turned on, the second diode D2, the fourth diode D4, the fifth diode D5, and the seventh diode D7 are turned off, and the first capacitor C1, the second capacitor C2, the third capacitor C3, and the fourth capacitor C4 are in a charging state, and:

[0154] (3-2)

[0155] In steady state, one carrier cycle T s The average current value of the internal capacitor is zero. According to formula (3-1) and formula (3-2), the inductor current I L1 , I L2 and DC link output current peak They are:

[0156] (3-3)

[0157] (3-4)

[0158] Where D op is the open circuit duty cycle, and B is the current boost factor. When the flow rate is increased, the flow rate factor B>1, thus realizing the flow rate increase function.

[0159] Let U C1 、U C2 、U C3 、U C4 They are the voltages across the first capacitor C1, the second capacitor C2, the third capacitor C3, and the fourth capacitor C4, respectively. In steady state, one carrier cycle T s The voltage across the internal capacitor remains unchanged, so:

[0160] (3-5)

[0161] (3-6)

[0162] Assume D a and D sh are the duty ratios of the effective state and the through state in one carrier cycle, respectively. The DC power supply voltage is Uin In steady state, one carrier cycle T s The average voltage value of the internal inductor is zero, so:

[0163] (3-7)

[0164] (3-8)

[0165] (3-9)

[0166] Solve equations (3-7) to (3-9) to calculate the voltage of each capacitor and the DC link voltage in the effective state:

[0167] (3-10)

[0168] (3-11)

[0169] The working state of the current-type quasi-Z-source inverter includes 6 valid states, 3 direct-through zero states and 7 open-circuit zero states. The current vectors in different switching states are shown in Table 1 above. In the prior art, the current space vector distribution in the valid state of the SVPWM modulation strategy is as follows: Figure 13 As shown, the sector determination method is as follows:

[0170] make:

[0171] (4-1)

[0172] Four variables, A, B, C, and N, are defined. When i1 > 0, A is 1; otherwise, A is 0. When i2 > 0, B is 1; otherwise, B is 0. When i3 > 0, C is 1; otherwise, C is 0. Let N = 4A + 2B + C. Different N values ​​correspond to different sectors. The corresponding relationship between N values ​​and the sectors where the reference current vector is located is shown in Table 4.

[0173] Table 4: N and sector correspondence table

[0174]

[0175] Figure 13 In the example, the six effective current vectors divide the space into six sectors. ref To transform the three-phase symmetrical sinusoidal current signal to be synthesized into the reference current vector in the αβ coordinate system, in each different sector, two valid vectors and a zero vector adjacent to the sector are usually selected to synthesize I ref .

[0176] Taking sector II as an example, the equations on the α and β axes are:

[0177] (4-2)

[0178] Where, T1 and T2 are the action time of the first effective current vector I1 and the second effective current vector I2 respectively; I α , I β They are the reference current vector I ref Components on the α and β axes.

[0179] Substitution According to formula (4-2), the action time of two adjacent effective vectors can be obtained as follows:

[0180] (4-3)

[0181] Similarly, the action time of the effective vector, open-circuit zero vector and straight-through zero vector in other different sectors can be calculated. The results are shown in Table 5.

[0182] Table 5: Expression of the action time of effective vector, open circuit zero vector and through zero vector in different sectors

[0183]

[0184] when When, take , .

[0185] For the current-type quasi-Z-source inverter SVPWM modulation method in the prior art, in order to minimize the number of switching times of the switching device in one carrier cycle, the results of selecting the through-zero vector and the open-circuit zero vector are shown in Table 6.

[0186] Table 6: Zero vector corresponding to each sector

[0187]

[0188] The carrier period T s Press T op / 4-T1 / 2-T sh / 2-T2 / 2-T op / 2-T2 / 2-T sh / 2-T1 / 2-T op The specific steps of the SVPWM modulation method in the prior art are as follows: Figure 14 shown.

[0189] A comparative analysis of the current-raising capabilities of different inverter topologies is conducted. Figure 5The figure shows a comparison of the current-raising capabilities of the current-mode quasi-Z-source topology, the switched-capacitor current-mode quasi-Z-source topology, and the novel switched-capacitor current-mode quasi-Z-source topology. As can be seen from the figure, when the open-circuit duty cycle is the same, the novel switched-capacitor current-mode quasi-Z-source topology has significantly higher current-raising capabilities than the other two topologies.

[0190] In the three different current-type quasi-Z-source inverter topologies, the maximum current flowing through the diode and the switch tube is the DC link peak current of the impedance network, that is, BI in When the system current gain G is determined, in order to reduce the current stress of the diode and the switch tube, the current boost factor B should be reduced as much as possible and the modulation factor m should be increased.

[0191] In current-source quasi-Z-source inverters, commonly used modulation strategies include simple SPWM modulation and SVPWM modulation. Assuming that different topologies have the same current gain G, and that the modulation factor and open-circuit duty cycle are set to minimize the current stress on the switch tube and diode, the peak DC link output current of the current-source quasi-Z-source topology, the switched capacitor current-source quasi-Z-source topology, and the new switched capacitor current-source quasi-Z-source topology under the simple SPWM control strategy is as follows: 、 、 It can be expressed as:

[0192] (5-1)

[0193] (5-2)

[0194] (5-3)

[0195] Peak DC link output current of the current-type quasi-Z source topology, the switched capacitor current-type quasi-Z source topology, and the new switched capacitor current-type quasi-Z source topology under the SVPWM modulation strategy 、 、 It can be expressed as:

[0196] (5-4)

[0197] (5-5)

[0198] (5-6).

[0199] The comparison of the ratio of DC link output peak current to input current under the simple SPWM modulation strategy and SVPWM modulation strategy at the same current gain G for three different topologies is shown in Figure 2. Figure 6 As shown. It can be seen that at the same input current I inand current gain G, the new switched capacitor quasi-Z source topology can obtain a relatively low DC link output peak current, that is, the current stress of the diode and switch tube is relatively small.

[0200] To sum up, compared with the current-type quasi-Z-source inverter and the switched capacitor current-type quasi-Z-source inverter, the new switched capacitor current-type quasi-Z-source inverter has a high current-rising capability and can obtain relatively low diode and switch tube current stress under the same input current and current gain conditions.

[0201] In order to verify that the new switched capacitor current-type quasi-Z-source inverter has a high current-rising capability compared to the current-type quasi-Z-source inverter and the switched capacitor current-type quasi-Z-source inverter, the current-type quasi-Z-source inverter, the switched capacitor current-type quasi-Z-source inverter and the new switched capacitor current-type quasi-Z-source inverter models were built in the MATLAB / Simulink environment. in The voltage is 100 V; the DC side inductance is 3 mH; the inductance L in the impedance network is 4 mH; the capacitance C in the impedance network is 100 μF; the AC side filter capacitor C f is 47 μF; the load resistance R is 10 Ω; the carrier frequency f s is 10 kHz.

[0202] Ignoring the power loss of the inverter, the energy conservation law yields:

[0203] (5-7)

[0204] Where, is the peak value of the inverter output line voltage, The output power factor of the inverter.

[0205] Under the same SVPWM modulation strategy, when D op =0.15, m=0.85, Figure 7 The output line voltage waveforms of the current-type quasi-Z-source inverter, the switched capacitor current-type quasi-Z-source inverter, and the new switched capacitor current-type quasi-Z-source inverter are shown from top to bottom. It can be seen that the new switched capacitor current-type quasi-Z-source inverter has the smallest output line voltage peak. Equation (5-7) shows that the new switched capacitor current-type quasi-Z-source inverter has the highest current-raising capability.

[0206] In order to verify that the new switched capacitor current-type quasi-Z-source inverter can obtain relatively lower diode and switch tube current stress under the same input current and current gain conditions compared with the current-type quasi-Z-source inverter and the switched capacitor current-type quasi-Z-source inverter, the DC power supply and DC-side inductor in the simulation model are replaced with a 10 A current source.

[0207] Under the same SVPWM modulation strategy, when the current gain G=mB=3, the peak current flowing through the diode and switch tube of the current-type quasi-Z source inverter is 、 The peak currents of the switched capacitor current-type quasi-Z-source inverter flowing through the diode and the switch are 47.35A and 47.52A respectively. 、 41.67 A and 42.13 A respectively; the peak current flowing through the diode and switch tube of the new switched capacitor current-type quasi-Z source inverter 、 They are 41.01 A and 41.66 A respectively. It can be seen that under the same input current and current gain conditions, the new switched capacitor current-mode quasi-Z-source inverter can achieve relatively low diode and switch tube current stress.

[0208] When D op =0.15, m=0.85, for the new switched capacitor current type quasi-Z source inverter, using the existing SVPWM strategy and the optimized SVPWM strategy, the output line current i abc , DC link output current i pn and common mode voltage u cmv The simulation waveforms are as follows Figure 8 (a) and Figure 8 As shown in (b) of the figure. The peak DC link output current for the existing SVPWM strategy is 5.94 A, while the peak DC link output current for the optimized SVPWM strategy is 5.79 A. The common-mode voltage range for the existing SVPWM strategy is (-175.18 V, 176.18 V), while the common-mode voltage range for the optimized SVPWM strategy is (-19.16 V, 19.19 V). It can be seen that compared to the existing SVPWM strategy, the optimized SVPWM strategy significantly reduces the common-mode voltage, and the switch and diode current stress under the optimized SVPWM strategy is relatively low.

[0209] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the technical principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A novel switched capacitor current-type quasi-Z-source inverter, characterized in that: A voltage source is included, wherein the positive electrode and the negative electrode of the voltage source are connected to the terminal 1 and the terminal 2 of the Z source impedance network through the third inductor and the eighth inductor respectively; The Z source impedance network includes a first switched capacitor unit, wherein terminal 1 of the first switched capacitor unit is terminal 1 of the Z source impedance network, and terminal 2 of the first switched capacitor unit is connected to terminal 2 of the Z source impedance network via a second inductor L2; End point 1 of the second switched capacitor unit is end point 2 of the Z source impedance network, and end point 2 of the second switched capacitor unit is connected to end point 1 of the Z source impedance network through the first inductor L1; The second terminal of the first switch capacitor unit is connected to the second terminal of the second switch capacitor unit through the first diode D1; The first switched capacitor unit includes a third capacitor C3, a fourth capacitor C4, a fourth inductor L4, a fifth inductor L5, and a second diode D2. In the first switched capacitor unit, terminal 1 is connected to terminal 2 of the first switched capacitor unit via the third capacitor C3 and the fourth inductor L4 in sequence; terminal 1 is connected to terminal 2 via the third capacitor C3, the second diode D2, and the fourth capacitor C4 in sequence; and terminal 1 is connected to terminal 2 via the fifth inductor L5 and the fourth capacitor C4 in sequence. The second switched capacitor unit includes a first capacitor C1, a second capacitor C2, a sixth inductor L6, a seventh inductor L7 and a third diode D3. In the second switched capacitor unit, terminal one is connected to terminal two of the second switched capacitor unit through the first capacitor C1 and the sixth inductor L6 in sequence; terminal one is connected to terminal two through the seventh inductor L7, the third diode D3 and the sixth inductor L6 in sequence; and terminal one is connected to terminal two through the seventh inductor L7 and the second capacitor C2 in sequence.

2. A novel switched capacitor current-mode quasi-Z-source inverter according to claim 1, characterized in that: A filter capacitor and a load are connected between terminal 1 and terminal 2 of the Z source impedance network via an inverter bridge.

3. The novel switched capacitor current-mode quasi-Z-source inverter according to claim 1, characterized in that: All inductance values ​​in the Z source impedance network are L, and all capacitance values ​​are C.

4. The method for increasing current of a novel switched capacitor current-mode quasi-Z-source inverter according to claim 3, characterized in that: include: When the switched capacitor current-type quasi-Z-source inverter works in an effective state, the inverter bridge is equivalent to a voltage source, and the DC link voltage U out Equal to the AC line voltage in the corresponding switch state; When the inverter works in the direct-through state, the inverter bridge is equivalent to a zero-value voltage source, that is, short-circuited, U out =0; When the inverter is in a non-open circuit state, including an effective state and a through state, the first diode D1, the second diode D2, and the third diode D3 are disconnected, and the first capacitor C1, the second capacitor C2, the third capacitor C3, and the fourth capacitor C4 are in a discharge state, then: （1-1） Where, I L1 , I L2 , I L4 , I L5 , I L6 , I L7 are the currents flowing through the first inductor L1, the second inductor L2, the fourth inductor L4, the fifth inductor L5, the sixth inductor L6, and the seventh inductor L7, respectively. C1 、i C2 、i C3 、i C4 are the currents flowing through the first capacitor C1, the second capacitor C2, the third capacitor C3, and the fourth capacitor C4, respectively. pn is the DC link output current flowing into the inverter bridge, I in is the input current.

5. The method for increasing current of a novel switched capacitor current-mode quasi-Z-source inverter according to claim 4, characterized in that: When the inverter is in an open circuit state, the inverter bridge is equivalent to an open circuit. At this time, the first diode D1, the second diode D2, and the third diode D3 are turned on, and the first capacitor C1, the second capacitor C2, the third capacitor C3, and the fourth capacitor C4 are in a charging state. Then: （1-2） In steady state, one carrier cycle T s The average current value of the internal capacitor is zero, and the inductor current remains unchanged; according to formula (1-1) and formula (1-2), the inductor current I is calculated L1 , I L2 , I L4 , I L5 , I L6 , I L7 and DC link output current peak They are: （1-3） （1-4） （1-5） Where D op is the open circuit duty cycle, B is the rising current factor; when the open circuit duty cycle D op When the flow rate is less than 1 / 4, the flow-raising factor B>1, thus realizing the flow-raising function.

6. The method for increasing current of a novel switched capacitor current-mode quasi-Z-source inverter according to claim 5, characterized in that: DC link output peak current is the equivalent DC input current of the inverter, the peak value of the inverter output phase current I omax Expressed as: （1-6） Where m is the modulation factor and G is the current gain. By setting the boost factor B and the modulation factor m, the inverter output current greater than or less than the input current can be obtained.

7. The method for increasing current of a novel switched capacitor current-mode quasi-Z-source inverter according to claim 6, characterized in that: From equations (1-1) to (1-4), we can see that the currents flowing through the first capacitor C1, the second capacitor C2, the third capacitor C3, and the fourth capacitor C4 are equal, so: （1-7） Assume D a and D sh are the duty ratios of the effective state and the through state in one carrier cycle, respectively. The DC power supply voltage is U in ; In steady state, one carrier cycle T s The average voltage value of the internal inductor is zero, then: （1-8） （1-9） Solving equations (1-8) and (1-9), we can calculate the voltages of each capacitor and the DC link voltage in the effective state: （1-10） （1-11）。 8. The optimized SVPWM method for a novel switched capacitor current-mode quasi-Z-source inverter according to claim 3, characterized in that: include: Step 1: Define the common-mode voltage U cmv for: （1-12） Where U PO 、U NO They are the voltage drops between points PO and NO in the inverter topology, point P is the endpoint one of the Z source impedance network, point N is the endpoint two of the Z source impedance network, and point O is the load neutral point; According to the working principle of the new switched capacitor current-type quasi-Z source inverter, the bridge arm states Q of phases a, b, and c are k Expressed as: （1-13） The working states of the switched capacitor current-type quasi-Z-source inverter include 6 valid states, 3 direct-through zero states and 7 open-circuit zero states. When the switch device in the upper arm is turned on, U PO is the corresponding phase voltage; when all the switches in the upper arm are turned off, U PO =4U in +U NO Similarly, when the switch device in the lower bridge arm is turned on, U NO is the corresponding phase voltage; when all the switching devices in the lower bridge arm are turned off, U NO =-4U in +U PO ; When both upper and lower bridge arms are turned off, U PO =U NO =0; Based on the analysis of common mode voltage in different switching states, the open circuit zero vector is selected as I 10 , and eliminate the direct zero vector, select the three non-zero vectors closest to the reference vector to synthesize I ref ; Step 2: Assume that the reference current vector I ref In sector 1, we can get: （1-14） Simplifying, we can get i a ≥i b ≥i c , similarly, the judgment conditions for the remaining sectors are obtained; Step 3: Assume that the reference current vector I ref In sector 1, I ref The effective vectors I6, I1, I2 and the open circuit zero vector I 10 Perform synthesis and list equations on the α and β axes to obtain: （1-15） Wherein, T1, T2, and T6 are the action times of the first effective current vector I1, the second effective current vector I2, and the sixth effective current vector I6 respectively; I α , I β They are the reference current vector I ref Components on the α and β axes; Substitution According to formula (1-15), the action times of three adjacent effective vectors are: （1-16） Similarly, the action time T of three adjacent effective vectors in other different sectors can be calculated: x 、T y 、T z Expressions of Step 4: Change the carrier period T s Press T op / 4-T x / 2-T y / 2-T z / 2-T op / 2-T z / 2-T y / 2-T x / 2-T op / 4 switching sequence is distributed, when the reference current vector I ref When in sector 1, the first time point T corresponding to the switch state switching c1 , the second time point T c2 , the third time point T c3 , the fourth time point T c4 The expressions are: （1-17）。

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