A timing control, logic circuit, chip and digital-to-analog converter

Abstract

The present application provides a timing control, logic circuit, chip, and digital-to-analog converter. A signal receiving module receives a divided clock signal and a digital signal. A signal processing module divides the digital signal into N parallel input sub-signals arranged in chronological order. Under the control of a sampling clock signal, a logic control module generates a virtual differential compensation signal pair and inputs it to the virtual latch when it detects that the level values ​​of two consecutive adjacent groups of input sub-signals are the same. Furthermore, a differential control signal pair is generated based on the input sub-signals and inputs it to the actual latch. The divided clock signal is equal to one-Nth of the sampling clock signal, where N ≥ 2 and N is a positive integer. The present application operates under a divided clock of the sampling clock, greatly reducing timing requirements and improving linearity.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and in particular to a timing control, logic circuit, chip and digital-to-analog converter. Background Art

[0002] In the field of high-speed, high-precision DACs (Digital to Analog Converters), current-steering DACs are a common and important implementation method. They primarily consist of a digital interface, decoding circuitry, latches, switching circuitry, a voltage source, a voltage-to-current converter, and a current source array.

[0003] For an N-bit binary coded DAC, 2 N -1 current source unit constitutes a current source array, and each current source unit needs to be equipped with a corresponding switch and latch for precise control. However, how to improve the linearity of DAC is a technical problem that needs to be solved urgently by those skilled in the art. Summary of the Invention

[0004] The present application provides a timing control, logic circuit, chip and digital-to-analog converter that reduce timing requirements while improving linearity.

[0005] In a first aspect, the present application provides a timing control circuit, wherein the timing control circuit is connected to a virtual latch and an actual latch, and the timing control circuit includes:

[0006] A signal receiving module, used for receiving a frequency-divided clock signal and a digital signal;

[0007] a signal processing module, configured to divide the digital signal into N parallel input sub-signals arranged in chronological order in K beats; wherein the N-1th input sub-signal of the N input sub-signals in the Kth beat is adjacent to the Nth input sub-signal of the N input sub-signals in the Kth beat, and the last input sub-signal of the N input sub-signals in the K-1th beat is adjacent to the first input sub-signal of the N input sub-signals in the Kth beat; N ≥ 2 and N is a positive integer, and K ≥ 2 and K is a positive integer;

[0008] A logic control module is configured to generate a virtual differential compensation signal pair and input the virtual latch when it is detected that the level values ​​of two consecutive adjacent groups of input sub-signals are the same, and to generate a differential control signal pair based on the input sub-signals and input the differential control signal pair to the actual latch under the control of a sampling clock signal; the divided clock signal is equal to one-Nth of the sampling clock signal.

[0009] In some embodiments, the logic control module includes:

[0010] a signal detection unit, configured to detect whether the level values ​​of two consecutive adjacent groups of input sub-signals are the same, and if so, to generate a selection control signal;

[0011] a signal generating unit, configured to generate a corresponding flip control signal according to the selection control signal, and generate the virtual differential compensation signal pair according to the flip control signal;

[0012] The signal generating unit is configured to output a corresponding output sub-signal according to the input sub-signal, and to generate the differential control signal pair according to the multiple output sub-signals.

[0013] In some embodiments, the signal detection unit includes a primary trigger and a primary XNOR gate module; the signal generation unit includes a secondary XNOR gate module, a primary multiplexer module, a buffer, a NOT gate, a secondary trigger module and a secondary multiplexer; the signal generation unit includes a multiplexer;

[0014] The signal output interface of the primary trigger is connected to the input end of the primary XNOR gate module, and the signal output interface of the primary trigger is used to output the next input sub-signal adjacent to the current input sub-signal connected to the signal input interface of the primary trigger;

[0015] The primary XNOR gate module includes N primary XNOR gates, which are cascaded in sequence to detect whether two consecutive adjacent groups of input sub-signals are the same;

[0016] The secondary XNOR gate module includes N-1 secondary XNOR gates, and the input end of the secondary XNOR gate module is connected to the output end of the primary XNOR gate module;

[0017] The primary multiplexer module includes N primary multiplexers, which are cascaded in sequence. The input pin of the primary multiplexer module is connected to the output end of the secondary XNOR gate module, the output end of the buffer, and the output end of the NOT gate, and is used to implement a flipping function when it is detected that two consecutive adjacent groups of input sub-signals are the same;

[0018] The secondary trigger module includes N secondary triggers, the input end of the secondary trigger module is connected to the output pin of the primary multiplexer module, the output end of the secondary trigger module is connected to the input end of the buffer and the input end of the NOT gate, the clock input end of each secondary trigger is connected to the divided clock signal, and the N secondary triggers are used to realize the latched output of N channels of the divided clock signals;

[0019] The input pin of the secondary multiplexer is connected to the output end of the secondary trigger module, the selection pin of the secondary multiplexer is connected to the sampling clock signal, and the input end of the virtual latch is connected to the output pin of the secondary multiplexer to receive the virtual differential compensation signal pair;

[0020] An input pin of the multiplexer receives the output sub-signal and outputs the differential control signal pair, and an input terminal of the actual latch is connected to the output pin of the multiplexer to receive the differential control signal pair.

[0021] In some embodiments, the first input terminal of the first primary XOR gate among the N primary XOR gates is connected to the signal output interface of the primary flip-flop, the clock input interface of the primary flip-flop is connected to the divided clock signal, the signal input interface of the primary flip-flop is connected to the second input terminal of the last primary XOR gate among the N primary XOR gates, and the second input terminal of the last primary XOR gate is connected to the last input sub-signal;

[0022] Among the N primary XNOR gates, except the first primary XNOR gate, the second input terminal of the previous primary XNOR gate is connected to the first input terminal of the next primary XNOR gate to access the same input sub-signal, and the previous primary XNOR gate is adjacent to the next primary XNOR gate.

[0023] In some embodiments, the first input terminal of the Mth secondary XNOR gate among the N-1 secondary XNOR gates is connected to the output terminal of the first primary XNOR gate; M≥1 and M is a positive integer, M=N-1;

[0024] The Nth input terminal of the Mth secondary XNOR gate is connected to the output terminal of the Nth primary XNOR gate;

[0025] The selection pin of the first primary multiplexer among the N primary multiplexers is connected to the output end of the first primary XNOR gate;

[0026] The selection pin of the Nth primary multiplexer except the first primary multiplexer among the N primary multiplexers is connected to the output end of the Mth secondary XNOR gate, the first input pin of each primary multiplexer is connected to the output end of the buffer, and the first input pin of each primary multiplexer is connected to the output end of the NOT gate;

[0027] The output pin of the Nth primary multiplexer is connected to the signal input interface of the Nth secondary flip-flop, and the signal output interface of the first secondary flip-flop of the N secondary flip-flops is also connected to the input end of the NOT gate and the input end of the buffer;

[0028] The clock input interface of the Nth secondary trigger is connected to the divided clock signal, and the signal output interfaces of the plurality of secondary triggers are respectively connected to the input pins of the secondary multiplexer in a one-to-one correspondence.

[0029] In some embodiments, the selection control signal is triggered to be generated by the second clock edge of two consecutive clocks with the same level value.

[0030] In some embodiments, when there are two consecutive 11s or 00s in the input sub-signal, the level value of the virtual differential compensation signal pair is flipped;

[0031] When two consecutive adjacent level values ​​of the input sub-signal change alternately, the output maintains the original state.

[0032] In a second aspect, the present application further provides a sequential logic circuit, comprising: a virtual latch, an actual latch, a switch module, a current source array, and the sequential control circuit according to the first aspect, wherein the logic control module is connected to the virtual latch and the actual latch, the switch module is connected to the actual latch, and the current source array is connected to the switch module;

[0033] The virtual latch is configured to generate a signal flip according to the received virtual differential compensation signal pair to balance the change of the power supply load;

[0034] The actual latch is configured to generate a switch control signal according to the differential control signal pair;

[0035] The switch module is used to control the switch state according to the switch control signal;

[0036] The current source array is used to switch the current direction of the current source array according to the switch state

[0037] In a third aspect, the present application further provides a digital-to-analog converter, which includes the sequential logic circuit described in the first aspect.

[0038] In a fourth aspect, the present application further provides a chip, comprising the digital-to-analog converter described in the third aspect.

[0039] The timing control, logic circuit, chip, and digital-to-analog converter provided by the present application receive a divided-frequency clock signal and a digital signal through a signal receiving module. The signal processing module divides the digital signal into N parallel input sub-signals arranged in chronological order. Under the control of the sampling clock signal, the logic control module generates a virtual differential compensation signal pair and inputs it to the virtual latch when it detects that the level values ​​of two consecutive adjacent groups of the input sub-signals are the same. The logic control module also generates a differential control signal pair based on the input sub-signals and inputs it to the actual latch. The divided-frequency clock signal is equal to one-Nth of the sampling clock signal, where N ≥ 2 and N is a positive integer. The present application operates under the divided-frequency clock of the sampling clock, greatly reducing the timing requirements and improving linearity. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0041] Figures 1 to 2 This is a structural diagram of a current-steering DAC.

[0042] Figure 3 This is another structural diagram of the current steering DAC.

[0043] Figure 4 This is a structural diagram of a timing control circuit provided in an embodiment of the present application.

[0044] Figure 5 This is a circuit diagram of a timing control circuit provided in an embodiment of the present application.

[0045] Figure 6 This is an embodiment of the present application Figure 5 Provides a timing diagram of the corresponding input and output sub-signals.

[0046] Figure 7 This is an embodiment of the present application Figure 5 The timing change diagram corresponding to the timing control circuit provided. DETAILED DESCRIPTION

[0047] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without making creative efforts are within the scope of protection of this application.

[0048] In the description of the embodiments of the present application, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0049] In order to enable any person skilled in the art to implement and use the present application, the following description is provided. In the following description, details are listed for the purpose of explanation. It should be understood that one of ordinary skill in the art will recognize that the present application can be implemented without using these specific details. In other examples, well-known processes will not be elaborated in detail to avoid obscuring the description of the embodiments of the present application with unnecessary details. Therefore, the present application is not intended to be limited to the embodiments shown, but is consistent with the widest range of principles and features disclosed in accordance with the embodiments of the present application.

[0050] The basic operating principle of a current-steering DAC is as follows: In the peripheral circuitry, a clock circuit provides clock signals to each module, ensuring synchronized operation. A low-dropout regulator (LDO) circuit, or voltage source, provides stable power to each module. The input digital signal first enters the digital interface and is then transmitted to the decoding circuit. The decoding circuit aggregates the multiple digital signals into a single digital signal using a multiplexer (MUX) and outputs it to a latch. The latch latches the received aggregated digital signal and then outputs it to the switch circuit and current source array. The current source array is a collection of multiple current source units arranged and organized in an array within the circuit. The latch signal controls the opening and closing of the corresponding switch, thereby changing the direction of the current in the corresponding current source array, achieving the critical conversion from digital to analog.

[0051] There are some problems with current-steering DACs in practical applications. Specifically, if there is a mismatch in the steering time of the current source units in the current source array, it will directly affect the linearity of the DAC. Although the random mismatch in latch time can be reduced by using larger latches, when multiple switches work simultaneously, their switching times will differ, resulting in switching time mismatch, which will have a significant impact on the performance of the DAC. In addition, due to the limited power supply impedance, when a large number of latches work to drive the current source units, power supply ripple will be caused. This ripple will affect the signal time output by the latch to the switch, thereby causing a correlation between the steering time and signal of the DAC current unit, ultimately leading to a decrease in DAC linearity. In a high-frequency operating environment, the parasitic inductance caused by the connection lines between the components inside the chip will also generate a large amount of on-chip power supply impedance, further exacerbating the degradation of DAC linearity. This poses many challenges to the design and performance improvement of high-speed and high-precision DACs.

[0052] In order to avoid the impact of latch flipping on LDO, a possible solution is to configure a small LDO to power each latch, as follows Figure 1 and Figure 2 As shown, Solution 1 uses an error amplifier and multiple source followers with decoupling capacitors to power each latch to avoid interference with the power supply due to latch flipping. Solution 1 has multiple latches, and each unit requires a source follower for power supply, consuming a large amount of area. There are differences in matching between multiple source followers, resulting in random mismatch in the DAC. Moreover, for advanced processes, the gate of the MOS tube may have leakage, and the trace impedance from the error amplifier to the source follower may cause a fixed mismatch between the source followers. Even if the active follower is isolated, there will still be signal-related components on the power supply at high frequencies, and the improvement effect is limited.

[0053] Another possible solution is to build a set of latches based on the original one, such as Figure 3 As shown, a set of dummy latches is added to compensate for power supply load variations. When the signal is continuously 0 or 1, the latches do not flip, and accordingly, the power supply ripple does not change. When the signal is 0, 1, 0, 1, the latches flip continuously, and the power supply follows the latch flips, generating ripple. In both cases, the power supply load follows the signal variation, causing signal energy to appear in the power supply ripple. Solution 2 detects digital signals. When two consecutive 1s appear, the dummy latch input is 0, and when two consecutive 0s appear, the dummy latch input is 1. When two consecutive digital inputs are 01 or 10, the dummy latch input remains unchanged. The dummy latch output is left floating, serving only to eliminate correlation between power supply ripple and the signal. The truth table is shown in Table 1 below.

[0054]

[0055] like Figure 3 As shown, the digital signal of Solution 2 passes through a D flip-flop 5. After a delay of one beat, DATA-1 passes through an XNOR gate 6. The output of XNOR gate 6 is the selection signal of the two-way selector 3. The input of the two-way selector 3 is DATA-1 and the inverted signal of DATA-1. When the two digital signals are the same, the inverted signal of DATA-1 is output. When the two digital signals are different, DATA-1 is output, that is, the output remains unchanged. Solution 2 uses a D flip-flop 5 to sample the signal at the frequency of signal Fs. In high-speed DACs, the frequency of signal Fs is relatively high. Implementing this timing logic at this frequency has strict requirements on the setup and hold time, which will limit the operating frequency of the DAC. In addition, each latch needs to be added. Figure 3 The circuit logic shown results in a large waste of power consumption and area.

[0056] In order to make the objectives, technical solutions and advantages of this application clearer, the implementation methods of this application will be further described in detail below with reference to the accompanying drawings.

[0057] Reference Figure 4 As shown, Figure 4 This is a structural diagram of a timing control circuit provided by an embodiment of the present application. Figure 4 As shown, the timing control circuit is connected to the virtual latch 20 and the actual latch 30, and the timing control circuit includes:

[0058] The signal receiving module 11 is used to receive the divided clock signal and the digital signal DATA_IN;

[0059] a signal processing module 12 configured to divide the digital signal DATA_IN into N parallel input sub-signals arranged in chronological order in K beats; wherein the N-1th input sub-signal of the N input sub-signals in the K-th beat is adjacent to the Nth input sub-signal of the N input sub-signals in the K-th beat, and the last input sub-signal of the N input sub-signals in the K-1th beat is adjacent to the first input sub-signal of the N input sub-signals in the K-th beat; K ≥ 2 and K is a positive integer;

[0060] The logic control module 13 is configured to generate a virtual differential compensation signal pair and input the virtual latch 20 when it is detected that the level values ​​of two consecutive adjacent groups of the input sub-signals are the same, and to generate a differential control signal pair based on the input sub-signals and input the differential control signal pair to the actual latch 30 under the control of the sampling clock signal fs; the divided clock signal is equal to one-Nth of the sampling clock signal fs.

[0061] Specifically, some digital circuits are speed-limited and cannot process and transmit high-frequency signals. This application utilizes a digital interface (such as a frequency divider or demultiplexer) to split the input high-speed digital signal DATA_IN into multiple, lower-speed input sub-signals. Based on the timing and logical relationships of the signals, this application decomposes the original high-frequency digital signal DATA_IN into multiple, lower-frequency input sub-signals in a time-interleaved manner. This allows the subsequent DAC to temporally or logically splice the output sub-signals obtained from the multiplexed input sub-signals to form a complete output signal. For example, in a high-speed digital-to-analog conversion scenario below 1 GHz, after the digital signal DATA_IN is split, the signal processing frequency of each branch is relatively low. For example, if the original signal is split into four channels, the frequency of each channel can be reduced to 1 / 4 of the original signal frequency. This reduces timing requirements during subsequent processing, making digital timing convergence easier and meeting the requirements of high-speed digital-to-analog conversion. Therefore, the present application uses a lower-frequency divided clock signal derived from the high-frequency sampling clock signal fs to divide the original digital signal DATA_IN into multiple input sub-signals, reducing the frequency of each input sub-signal. This solves the timing convergence and transmission issues of the high-speed digital signal DATA_IN. Because the rate of the divided input sub-signals is reduced, it is easier to meet timing constraints, which also helps to increase the maximum operating frequency of the DAC. In addition, the present application triggers the generation of a virtual differential compensation signal pair by detecting whether the level values ​​of two consecutive adjacent groups of input sub-signals are the same, balancing transient changes in the power supply load, suppressing signal-related ripple, and significantly improving the linearity of the DAC.

[0062] Assuming N=4, the digital signal DATA_IN is divided into N parallel input sub-signals arranged in chronological order. The 4 input sub-signals are DATA <n-3>、DATA <n-2>、DATA <n-1>、DATA <n>, and, since each digital signal DATA_IN is divided into N parallel input sub-signals arranged in time sequence, multiple digital signals DATA_IN are divided multiple times and arranged according to the time interleaving rule so that the input sub-signal corresponding to the K-1th beat is DATA <n-3>、DATA <n-2>、DATA <n-1>、DATA <n>; The input sub-signal corresponding to the Kth beat is DATA <n-3>、DATA <n-2>、DATA <n-1>、DATA <n>; Thus, the input sub-signal DATA corresponding to the K-1th beat <n-3>Input sub-signal DATA corresponding to the K-1th beat <n-2>Adjacent, the input sub-signal DATA corresponding to the K-1th beat <n-2>Input sub-signal DATA corresponding to the K-1th beat <n-1>Adjacent, the input sub-signal DATA corresponding to the K-1th beat <n-1>The input sub-signal corresponding to the Kth beat is DATA <n>Adjacent, the input sub-signal DATA corresponding to the K-1th beat <n>The input sub-signal corresponding to the Kth beat is DATA <n-3>adjacent.

[0063] In some embodiments, the logic control module 13 includes:

[0064] a signal detection unit, configured to detect whether the level values ​​of two consecutive adjacent groups of input sub-signals are the same, and if so, to generate a selection control signal;

[0065] a signal generating unit, configured to generate a corresponding flip control signal according to the selection control signal, and generate the virtual differential compensation signal pair according to the flip control signal;

[0066] The signal generating unit is configured to output a corresponding output sub-signal according to the input sub-signal, and to generate the differential control signal pair according to the multiple output sub-signals.

[0067] In some embodiments, the signal detection unit includes a primary trigger D1 and a primary XNOR gate module; the signal generation unit includes a secondary XNOR gate module, a primary multiplexer module, a buffer, a NOT gate, a secondary trigger module and a secondary multiplexer; the signal generation unit includes a multiplexer;

[0068] The signal output interface of the primary trigger D1 is connected to the input end of the primary XNOR gate module, and the signal output interface of the primary trigger D1 is used to output the next input sub-signal adjacent to the current input sub-signal connected to the signal input interface of the primary trigger D1; for example, assuming N=4, the signal output interface of the primary trigger D1 outputs the last input sub-signal DATA of the four input sub-signals in the K-1th beat. <3> , then the current input sub-signal connected to the signal input interface of the primary trigger D1 is the last input sub-signal DATA of the 4 input sub-signals in the K-1th beat. <3> The first input sub-signal DATA of the four input sub-signals in the adjacent K-1th beat <0> ;

[0069] The primary XNOR gate module includes N primary XNOR gates, which are cascaded in sequence to detect whether two consecutive adjacent groups of input sub-signals are the same;

[0070] The secondary XNOR gate module includes N-1 secondary XNOR gates, and the input end of the secondary XNOR gate module is connected to the output end of the primary XNOR gate module;

[0071] The primary multiplexer module includes N primary multiplexers, which are cascaded in sequence. The input pin of the primary multiplexer module is connected to the output end of the secondary XNOR gate module, the output end of the buffer, and the output end of the NOT gate, and is used to implement a flipping function when it is detected that two consecutive adjacent groups of input sub-signals are the same;

[0072] The secondary trigger module includes N secondary triggers, the input end of the secondary trigger module is connected to the output pin of the primary multiplexer module, the output end of the secondary trigger module is connected to the input end of the buffer and the input end of the NOT gate, and the clock input end of each secondary trigger is connected to the divided clock signal; the N secondary triggers are used to realize the latched output of N channels of the divided clock signals;

[0073] The input pin of the secondary multiplexer is connected to the output end of the secondary trigger module, the selection pin of the secondary multiplexer is connected to the sampling clock signal fs, and the input end of the virtual latch 20 is connected to the output pin of the secondary multiplexer to receive the virtual differential compensation signal pair; the secondary multiplexer is used to merge the N-way divided clock signals into one way and output it to the virtual latch.

[0074] The input pin of the multiplexer receives the output sub-signal and outputs the differential control signal pair. The input terminal of the actual latch 30 is connected to the output pin of the multiplexer to receive the differential control signal pair.

[0075] In some embodiments, the first input terminal of the first primary XENOR gate among the N primary XENOR gates is connected to the signal output interface of the primary trigger D1, the clock input interface of the primary trigger D1 is connected to the divided clock signal, the signal input interface of the primary trigger D1 is connected to the second input terminal of the last primary XENOR gate among the N primary XENOR gates, and the second input terminal of the last primary XENOR gate is connected to the last input sub-signal; the primary trigger D1 obtains the next beat signal after the divided clock is beaten, and the next beat signal is adjacent to the last signal of the previous beat in the original signal. This function is used to realize continuous detection of the signal.

[0076] Among the N primary XOR gates, excluding the first primary XOR gate, the second input terminal of the preceding primary XOR gate is connected to the first input terminal of the succeeding primary XOR gate to receive the same input sub-signal, and the preceding primary XOR gate is adjacent to the succeeding primary XOR gate, thereby realizing detection of N input sub-signals in the same beat.

[0077] In some embodiments, the first input terminal of the Mth secondary XNOR gate among the N-1 secondary XNOR gates is connected to the output terminal of the first primary XNOR gate; M≥1 and M is a positive integer, M=N-1; used to realize the detection of multiple consecutive input sub-signals of K consecutive beats and N paths.

[0078] The Nth input terminal of the Mth secondary XNOR gate is connected to the output terminal of the Nth primary XNOR gate;

[0079] The selection pin of the first primary multiplexer among the N primary multiplexers is connected to the output end of the first primary XNOR gate;

[0080] The selection pin of the Nth primary multiplexer except the first primary multiplexer among the N primary multiplexers is connected to the output end of the Mth secondary XNOR gate, the first input pin of each primary multiplexer is connected to the output end of the buffer, and the first input pin of each primary multiplexer is connected to the output end of the NOT gate;

[0081] The output pin of the Nth primary multiplexer is connected to the signal input interface of the Nth secondary flip-flop, and the signal output interface of the first secondary flip-flop of the N secondary flip-flops is also connected to the input end of the NOT gate and the input end of the buffer;

[0082] The clock input interface of the Nth secondary trigger is connected to the divided clock signal, and the signal output interfaces of the plurality of secondary triggers are respectively connected to the input pins of the secondary multiplexer in a one-to-one correspondence.

[0083] Specifically, this application detects the continuity of the input signal (continuous 0 / 1 or alternating) and utilizes an exclusive-OR gate and control logic driven by a divided clock to trigger a compensatory flip of the virtual latch 20 when the same signal is present continuously. This forces the power supply load to remain constant, thereby eliminating signal correlation and improving DAC linearity. This solution, implemented using a divided clock, balances high-speed performance with area and power optimization. The primary trigger and all secondary triggers (D21-D24) operate at the divided clock signal frequency, reducing timing requirements while ensuring synchronization between the compensation signal output by the virtual latch 20 and the operation of the actual latch 30.

[0084] Since the digital circuit rate in high-speed DAC is limited, generally below 1GHz, in order to meet the needs of high-speed digital-to-analog conversion, the digital signal DATA_IN needs to be divided into multiple channels first, and then combined into a single channel signal by the MUX unit in the decoding circuit in the DAC. Take the MUX unit that combines 4 channels into 1 as an example, Figure 5 and Figure 6 As shown, for the four groups of input sub-signals DATA<3:0> provided, they are sequentially spliced ​​into output signals along the time sequence (the four groups of output sub-signals DATA_OUT<3:0> are sequentially spliced), DATA<N+1> It is DATA <n>The sequential logic circuit of the present application includes a logic control module 13, a virtual latch 20, an actual latch 30, a switch module (not shown), and a current source array 40. The circuit structure of the logic control module 13 is as follows: the signal input interface D of the primary trigger D1 inputs DATA<3>, the clock input interface CLK of the primary trigger D1 inputs the CK_DIV4 signal, and the signal output interface Q of the primary trigger D1 is connected to the first input terminal of the first primary XNOR gate XN11.

[0085] The second input terminal of the first primary XNOR gate XN11 is connected to the first input terminal of the second primary XNOR gate XN12 and receives the DATA<0> signal. The output terminal of the first primary XN11 is respectively connected to the first input terminal of the first secondary XNOR gate XN21, the first input terminal of the second secondary XNOR gate XN22, the first input terminal of the third secondary XN23, and the selection pin of the first primary multiplexer P11 to output the signal DIFF<0>. The first input pin of the first primary multiplexer P11 is connected to the output terminal of the buffer H1. The second input pin of the multiplexer P11 is connected to the output end of the NOT gate NP1, the input end of the buffer H1 and the input end of the NOT gate NP1 are both connected to the signal output interface Q of the first secondary trigger D21, the output pin of the first primary multiplexer P11 is connected to the signal input interface D of the first secondary trigger D21, the clock input interface CLK of the first secondary trigger D21 inputs the CK_DIV4 signal, and the signal output interface Q of the first secondary trigger D21 is also connected to the first input pin of the secondary multiplexer P21 to access DUM<3>.

[0086] The second input terminal of the second primary XNOR gate XN12 is connected to the first input terminal of the third primary XNOR gate XN13 and receives the DATA<1> signal. The output terminal of the second primary XNOR gate XN12 is connected to the second input terminal of the first secondary XNOR gate XN21, the second input terminal of the second secondary XNOR gate XN22 and the second input terminal of the third secondary XNOR gate XN23 respectively. The output terminal of the first secondary XNOR gate XN21 is connected to the selection pin of the second primary multiplexer P12 to output the signal DIFF<1>. The first input terminal of the second primary multiplexer P12 is connected to the selection pin of the second primary multiplexer P12 to output the signal DIFF<1>. An input pin is connected to the output end of the buffer H1, the output end of the second input pin of the second primary multiplexer P12 is connected to the output end of the NOT gate NP1, the output pin of the second primary multiplexer P12 is connected to the signal input interface D of the second secondary flip-flop D22, the clock input interface CLK of the second secondary flip-flop D22 is connected to the clock input interface CLK of the first secondary flip-flop D21, and the signal output interface Q of the second secondary flip-flop D22 is also connected to the second input pin of the secondary multiplexer P21 to access DUM<2>.

[0087] The second input terminal of the third primary XNOR gate XN13 is connected to the first input terminal of the fourth primary XNOR gate XN14 and receives the DATA<2> signal. The output terminal of the third primary XN13 is connected to the third input terminal of the second secondary XNOR gate XN22, the third input terminal of the third secondary XNOR gate XN23, and the second input terminal of the third secondary XNOR gate XN23, respectively. The output terminal of the second secondary XN22 is connected to the selection pin of the third primary multiplexer P13 to output the signal DIFF<2>. The third primary multiplexer P13 An input pin is connected to the output end of the buffer H1, the output end of the second input pin of the third primary multiplexer P13 is connected to the output end of the NOT gate NP1, the output pin of the third primary multiplexer P13 is connected to the signal input interface D of the third secondary flip-flop D23, the clock input interface CLK of the third secondary flip-flop D23 is connected to the clock input interface CLK of the second secondary flip-flop D22, and the signal output interface Q of the third secondary flip-flop D23 is also connected to the third input pin of the secondary multiplexer P21 to access DUM<1>.

[0088] A second input terminal of the fourth primary X-OR gate XN14 is connected to the DATA<3> signal, an output terminal of the fourth primary X-OR gate XN14 is connected to the fourth input terminal of the third secondary X-OR gate XN23, an output terminal of the third secondary X-OR gate XN23 is connected to the select pin of the fourth primary multiplexer P14 to output the signal DIFF<3>, a first input pin of the fourth primary multiplexer P14 is connected to the output terminal of the buffer H1, an output terminal of the second input pin of the fourth primary multiplexer P14 is connected to the output terminal of the inverter NP1, an output pin of the fourth primary multiplexer P14 is connected to the signal input interface D of the fourth secondary flip-flop D24, a clock input interface CLK of the fourth secondary flip-flop D24 is connected to the clock input interface CLK of the third secondary flip-flop D23, and a signal output interface Q of the fourth secondary flip-flop D24 is also connected to the fourth input pin of the secondary multiplexer P21 to receive DUM<0>.

[0089] The first output pin of the secondary multiplexer P21 is connected to the first terminal of the dummy latch 20 to output the first positive-phase compensation signal DOUTP_DUM. The second output pin of the secondary multiplexer P21 is connected to the second terminal of the dummy latch 20 to output the first negative-phase compensation signal DOUTN_DUM. The clock input pin of the dummy latch 20 receives the CK signal, and the output terminal of the dummy latch 20 is left floating. When the input sub-signals are consecutively identical (such as 00 or 11), the actual latch 30 does not flip, but the dummy latch 20 actively flips (by inputting the opposite value of 0 or 1), resulting in current consumption similar to that during signal changes. For example, when two consecutive 1s appear in the input, the dummy latch 20 receives an input 0, triggering a flip; when two consecutive 0s appear in the input, the dummy latch 20 receives an input 1, triggering a flip. When the input sub-signals alternate (such as 01 or 10), the dummy latch 20 remains in its original state. When the virtual latch 20 actively flips, its internal circuit will generate a transient current (such as charging and discharging current) similar to that of the actual latch 30, thereby offsetting the load difference when the actual latch 30 is not flipped. This makes the total load current of the LDO independent of the input signal change, thereby eliminating the impact of signal correlation on power supply ripple and improving linearity.

[0090] The signal input interface D of the signal trigger D3 inputs DATA<3:0>, the clock input interface CLK of the signal trigger D3 inputs the CK_DIV4 signal, and the signal output interface Q of the signal trigger D3 outputs the sub-signal DATA_OUT<3:0> (including DATA_OUT<3>, DATA_OUT<2>, DATA_OUT<1> and DATA_OUT<0>).

[0091] The first input pin of the actual latch 30 inputs the first sub-signal DATA_OUT<0>, the second input pin of the actual latch 30 inputs the second sub-signal DATA_OUT<1>, the third input pin of the actual latch 30 inputs the third sub-signal DATA_OUT<2>, the fourth input pin of the actual latch 30 inputs the fourth sub-signal DATA_OUT<3>, and the clock input pin of the actual latch 30 inputs the CK signal.

[0092] A first output pin of the multiplexer P22 is connected to a first end of the actual latch 30 to output a second positive phase compensation signal DOUTP, and a second output pin of the multiplexer P22 is connected to a second end of the actual latch 30 to output a second negative phase compensation signal DOUTN.

[0093] The working principle of this application is: through the primary XNOR gate chain structure, the adjacent level values ​​of two adjacent groups of input sub-signals are detected step by step to see if they are the same, that is, XN11 compares the DATA in the K-1th beat <3> (Q end of D1) and DATA in the Kth beat <0> , namely DIFF <0> =XNOR(DATA in K-1th shot <3> , DATA in the Kth shot <0> ); XN12 compares the DATA in the Kth beat <0> and DATA in the Kth shot <1> , namely DIFF <1> =XNOR(DATA in Kth shot <0> , DATA in the Kth shot <1> ); XN13 compares the DATA in the Kth shot <1> and DATA in the Kth shot <2> , namely DIFF <2> =XNOR(DATA in Kth shot <1> , DATA in the Kth shot <2> ); XN14 compares the DATA in the Kth shot <2> and DATA in the Kth shot <3> , namely DIFF <3> =XNOR(DATA in Kth shot <2> , DATA in the Kth shot <3> When two adjacent bits are the same (00 or 11), the corresponding DIFF<n> outputs a high level; when two adjacent bits are the same but different (01 or 10), the corresponding DIFF<n> outputs a low level.

[0094] The implementation logic of the present application is that the input sub-signal DATA is delayed by one beat through the primary trigger D1 to obtain DATA-1 (the previous beat signal, i.e., the signal output by the signal output interface Q of the primary trigger, not shown in the figure). That is, the primary trigger D1 is used to delay the current input sub-signal connected to the signal input interface of the primary trigger D1 by one beat. For example, when the current input sub-signal connected to the signal input interface of the primary trigger D1 is the last input sub-signal of the N input sub-signals in the K-1th beat, the next input sub-signal output by the signal output port of the primary trigger D1, which is adjacent to the current input sub-signal, is the first input sub-signal of the N input sub-signals in the Kth beat. Among them, DIFF <0> to DIFF <3> , synchronized with the edge of the divided clock CK_DIV4, usually triggered by the rising edge of CK_DIV4. <0> to DIFF <3> The signals connected to the selection pins of the first to fourth primary multiplexers (P11-P14) respectively determine whether the primary multiplexer selects the signal input from the first input pin (0 terminal, connected to the output of buffer H1) or the second input pin (1 terminal, connected to the output of inverter NP1). For example, when DIFF <0> When the DIFF is low, the first primary multiplexer P11 selects the signal output by the buffer H1; <0> When it is high, the signal output by the inverter NP1 is selected. The signal input interface D of the signal trigger D3 inputs DATA<3:0>, the CLK input pin inputs the CK_DIV4 signal, and the signal output interface Q outputs the sub-signal DATA_OUT<3:0>, including DATA_OUT <3> DATA_OUT <2> DATA_OUT <1> and DATA_OUT <0> These four signals are processed digital signals DATA_IN, which are used to update the status of the actual latch 30. In each CK_DIV4 clock cycle, the actual latch 30 updates the status of the actual latch 30 according to DATA_OUT. <0> to DATA_OUT <3> To update the output, the current source array 40 is controlled to switch, completing the digital-to-analog conversion. In short, the current path of the virtual latch 20 and the actual latch 30 share the same power network (LDO output terminal), and its dynamic current is complementary to the current of the actual latch 30 in the time domain.

[0095] Even if the digital signal DATA_IN itself does not change, if the input sub-signal DATA shows consecutive 0s or 1s, resulting in the actual latch 30 not flipping, the introduction of DOUTP_DUM and DOUTN_DUM as a compensation flipping signal can provide a load current similar to that during a normal flipping, thereby balancing the LDO load variation. This means that the LDO load does not change with the digital signal DATA_IN. Instead, the virtual differential compensation signal pair (DOUTP_DUM and DOUTN_DUM) maintains a constant frequency and amplitude of change, severing the direct connection between latch voltage fluctuations and the input signal. This reduces the adverse effects of latch voltage fluctuations and the input signal correlation on DAC performance, helping to improve DAC linearity. When the actual latch 30 does not flip, such as when the signal shows consecutive 0s or 1s, the output signals of the two virtual latches 20, DOUTP_DUM and DOUTN_DUM, flip. In this way, although the circuit portion corresponding to the actual latch 30 does not change, the change in the output of the virtual latch 20 compensates for the overall LDO load variation. Because the load change is jointly determined by the flipping of all actual latches 30, the flipping of the virtual latch 20 compensates for the overall load change that may be caused by the actual latch 30 not flipping, making the load current change of the LDO independent of the signal frequency, thereby reducing the power supply ripple and signal correlation caused by the latch flipping, and improving the linearity of the DAC. The present application eliminates the connection between the latch voltage fluctuation and the input signal through the virtual latch 20 and its control logic. When the actual latch 30 does not flip due to the continuous and identical input signal, the virtual latch 20 can force a compensating flip to decouple the AC component of the power supply load current from the data pattern, thereby effectively improving the linearity of the DAC.

[0096] The present application divides the digital signal DATA_IN into multiple channels, each with a relatively low frequency. This allows the sequential logic circuit to operate at a lower clock frequency, thereby reducing the timing requirements and increasing the maximum frequency of the DAC. For example, by utilizing a four-way multiplexing mechanism, the operating frequency of the virtual signal generation circuit is reduced to 1 / 4 of the original sampling clock signal fs, significantly improving the timing margin from 1GHz to 250MHz, thereby alleviating the problem of high-speed timing closure. The control logic added in the present application is relatively simple and does not increase power consumption excessively. Multiple latch units can share a set of logic circuits, further reducing power consumption. Furthermore, the present application only requires adding a set of virtual latches 20 and related logic control modules 13 to the original latches. Using a splitting and combining scheme, four latches share a set of logic control modules 13. Compared to configuring a separate circuit for each latch, through reasonable splitting and combining, and with the compensation of the virtual latch 20, the impact of latch flipping on the LDO power supply can be effectively reduced, thereby significantly reducing power consumption and area while improving linearity. Furthermore, the design of the timing control circuit of the present application offers a degree of flexibility, allowing for expansion and adjustment based on different DAC bit counts and performance requirements. For example, for multiplexing structures with varying numbers of branch paths, the scale and connection method of the logic control module 13 can be adjusted accordingly to accommodate different application scenarios. In summary, the present application reduces timing requirements, improves the linearity of high-speed DACs, and reduces power consumption and area.

[0097] In some embodiments, the selection control signal is triggered to be generated by the second clock edge of two consecutive clocks with the same level value.

[0098] In some embodiments, when there are two consecutive 11s or 00s in the input sub-signal, the level value of the virtual differential compensation signal pair is flipped;

[0099] When two consecutive adjacent level values ​​of the input sub-signal change alternately, the output maintains the original state.

[0100] Specifically, taking the first primary XNOR gate XN11 as an example, its first input terminal is connected to the signal output interface Q of the first primary trigger D1 to receive DATA <3> Signal, the second input terminal is connected to the first input terminal of the second primary XNOR gate XN12 and is connected to DATA <0> signal, the output signal is DIFF <0> Similarly, the other primary XNOR gates compare DATA <1> ,DATA <2> ,DATA <3> Adjacent signals, output DIFF <1> DIFF <2> DIFF <3> . Detect whether two consecutive adjacent groups of input sub-signals are the same. When the two consecutive adjacent groups of input sub-signals are the same, the virtual latch 20 will be triggered to generate DIFF <0> Taking the first primary multiplexer P11 as an example, its selection pin is connected to the output of the first primary XNOR gate XN11 to receive the signal DIFF <0> , the first input pin is connected to the output end of the buffer H1, the output end of the second input pin is connected to the output end of the inverter NP1, and the input ends of the buffer H1 and the inverter NP1 are both connected to the signal output interface Q of the first secondary trigger D21. <0> Different values ​​of P11 select the signal output from the first input pin or the second input pin to the signal input interface D of the first secondary trigger D21, and the first secondary trigger D21 outputs DOUT_DUM under the control of the CK_DIV4 signal. <3> Similarly, other primary multiplexers and secondary triggers cooperate according to DIFF <1> DIFF <2> DIFF <3> Generate DOUT_DUM <2> 、DOUT_DUM <1> 、DOUT_DUM <0> When DIFF<n> = 1, the corresponding DOUT_DUM signal will toggle during the second CK_DIV4 divided clock cycle. The inverted DOUT_DUM<3:0> signal is input to the secondary multiplexer P21. P21's first output pin outputs the first positive-phase compensation signal, DOUTP_DUM, and its second output pin outputs the first negative-phase compensation signal, DOUTN_DUM. DOUTP_DUM and DOUTN_DUM are a simultaneously generated differential signal pair, their levels always complementary, and their generation timing is strictly synchronized with the edges of the divided clock signal, CK_DIV4. When two consecutive identical values ​​(00 or 11) appear in the input data stream, a set of toggle signals is generated on the second CK_DIV4 clock edge of the same value. When the input data alternates (01 or 10), DOUTP_DUM and DOUTN_DUM maintain their previous outputs, with no valid toggle. The first output pin of multiplexer P22 outputs the second positive-phase compensation signal DOUTP, while the second output pin outputs the second negative-phase compensation signal DOUTN. DOUTP and DOUTN are also a differential signal pair generated simultaneously, with complementary levels, and generated synchronously with the clock edge of the actual latch 30 (synchronized with CK_DIV4).The actual latch 30 updates its output based on the input data DATA_OUT<3:0> during every CK_DIV4 clock cycle. When the input data transitions from low to high (0→1), a rising edge on DOUTP and a falling edge on DOUTN occur simultaneously. When the input data transitions from high to low (1→0), a falling edge on DOUTP and a rising edge on DOUTN occur simultaneously. When the input data is held (0→0 or 1→1), the output remains unchanged, with no active edge. DOUTP_DUM and DOUTN_DUM, the differential positive and negative compensation signals, are output from the secondary multiplexer P21 to the dummy latch 20. The CK signal is fed into the clock input pin of the dummy latch 20, and its output is left floating. If the actual latch 30 does not flip due to consecutive identical data, the dummy latch 20 forces a flip, decoupling the AC component of the power supply load current from the data pattern, thereby improving DAC linearity. DOUTP and DOUTN are the differential positive and negative physical output signals, respectively, output from multiplexer P22 to physical latch 30. The clock input pin of physical latch 30 receives the CK signal. Physical latch 30 updates its output based on the DOUTP and DOUTN signal states, controlling the switching of current source array 40 to convert the digital signal DATA_IN into an analog signal. Continue. Figure 6 From the corresponding timing, we can see that CK_P is the original sampling clock signal fs, CK_DIV4 is the fourth divided clock signal obtained by dividing the signal CK_P by four. DATA_IN is the original input digital signal DATA_IN, and DATA<3:0> is the four input sub-signals obtained by sampling DATA_IN with the four-divided clock. The final timing is as follows Figure 7 As shown, when two consecutive identical values ​​(00 or 11) appear in the input data stream, resulting in the actual latch 30 not flipping, a flip signal is compensated through DOUTP_DUM\DOUTN_DUM, so that the load of the LDO does not change with the signal.

[0101] When DIFF<n> = 0 is detected, the multiplexer output remains unchanged to avoid redundant compensation. The number of virtual latch 20 flips is dynamically adjusted using DIFF<n>, ensuring that the total number of switching events (real + virtual) remains constant regardless of the data pattern. For example, when the actual latch 30's current decreases due to data quiescence (i.e., when the input sub-signals are consecutively identical (e.g., 00 or 11), the DIFF signal marks the consecutively identical bits (i.e., DIFF<n> = 1). The primary multiplexer selects the inverted data output by the NOT gate, triggering the virtual latch 20 to generate compensating flips in the second and fourth bits, injecting additional current. When the actual latch 30's current surges due to data transitions (i.e., when the input sub-signals alternate (e.g., 01 or 10), the DIFF signal is unmarked (i.e., DIFF<n> = 0). The primary multiplexer selects the original data output by the buffer, causing only the actual latch 30 to flip normally, while the virtual latch 20 reduces current injection. Ultimately, the load current fluctuation at the LDO output is decoupled from the data pattern, and the signal-related components in the ripple are significantly suppressed.

[0102] This application is applicable to the scenario where the original digital signal DATA_IN is split into 2 interleaved input sub-signals, and is also applicable to the scenario where the original digital signal DATA_IN is split into a total of 4 interleaved input sub-signals. Based on this principle, if the original digital signal DATA_IN is split into 8 interleaved input sub-signals, the 16-way signal can be merged into 4 4-way signals through 4 4-to-1 selectors, or the 8-way input sub-signals can be merged into 2 4-way signals through 2 4-to-1 selectors. Then it is connected to the timing control circuit described in this article to generate a differential control signal pair and a virtual differential compensation signal pair.

[0103] The design of this application is based on the principle of splitting the original digital signal DATA_IN into 4 interleaved input sub-signals, which also applies to the case of splitting into 2 interleaved input sub-signals. Based on this principle, if the original signal needs to be split into 16 or 8 channels, it needs to be processed separately: for 16 channels, 4 4-to-1 selectors are used to merge it into 4 groups of 4-channel signals; for 8 channels, 2 4-to-1 selectors are used to merge it into 2 groups of 4-channel signals. Subsequently, these merged signal groups are input into the timing control circuit described in this article to generate differential control signal pairs and virtual differential compensation signal pairs.

[0104] In a second aspect, the present application further provides a sequential logic circuit, comprising: a virtual latch 20, an actual latch 30, a switch module, a current source array 40, and the sequential control circuit according to the first aspect, wherein the logic control module 13 is connected to the virtual latch 20 and the actual latch 30, the switch module is connected to the actual latch 30, and the current source array 40 is connected to the switch module;

[0105] The virtual latch 20 is configured to generate a signal flip according to the received virtual differential compensation signal pair to balance the change of the power supply load;

[0106] The actual latch 30 is used to generate a switch control signal according to the differential control signal pair;

[0107] The switch module is used to control the switch state according to the switch control signal;

[0108] The current source array 40 is configured to switch the current direction of the current source array 40 according to the switch state.

[0109] Specifically, the number of virtual latches 20 and actual latches 30 can be at least two or one. The present application adjusts the structure of the logic control module in the above embodiment according to the number of virtual latches 20 and actual latches 30, which can also increase the maximum operating frequency of the DAC, reduce the area and power consumption, effectively suppress signal correlation ripple, and significantly improve the linearity of the DAC.

[0110] In a third aspect, the present application further provides a digital-to-analog converter, which includes the sequential logic circuit described in the first aspect.

[0111] In a fourth aspect, the present application further provides a chip, comprising the digital-to-analog converter described in the third aspect.

[0112] In specific implementation, the above units or modules can be implemented as independent entities, or they can be arbitrarily combined and implemented as the same or several entities. The above units or modules can refer to the previous method embodiments to implement data collection for supply chain management projects, which will not be repeated here.

[0113] Those skilled in the art will appreciate that all or part of the steps in the various methods of the above embodiments can be accomplished by instructions, or by controlling related hardware through instructions. The instructions can be stored in a computer-readable storage medium and loaded and executed by a processor to implement the above method embodiments. The computer-readable storage medium may include a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0114] In the above embodiments, the description of each embodiment has its own focus. For parts not described in detail in one embodiment, reference can be made to the relevant description of other embodiments. Those skilled in the art will clearly understand that for the convenience and brevity of description, the specific working process and beneficial effects of the data acquisition system and its corresponding units described above can be referred to the description of the timing control method in the above embodiments, and the details will not be repeated here.

[0115] The above is a detailed introduction to a timing control method and system provided in an embodiment of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for technical personnel in this field, based on the ideas of the present application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.< / n> < / n> < / n> < / n> < / n> < / n>

Claims

1. A timing control circuit, characterized in that: The timing control circuit is connected to the virtual latch and the actual latch, and the timing control circuit includes: A signal receiving module, used for receiving a frequency-divided clock signal and a digital signal; a signal processing module, configured to divide the digital signal into N parallel input sub-signals arranged in chronological order in K beats; wherein the N-1th input sub-signal of the N input sub-signals in the Kth beat is adjacent to the Nth input sub-signal of the N input sub-signals in the Kth beat, and the last input sub-signal of the N input sub-signals in the K-1th beat is adjacent to the first input sub-signal of the N input sub-signals in the Kth beat; N ≥ 2 and N is a positive integer, K ≥ 2 and K is a positive integer; a logic control module, configured to, under the control of a sampling clock signal, generate a virtual differential compensation signal pair and input the pair to the virtual latch when it is detected that the level values ​​of two consecutive adjacent groups of the input sub-signals are the same, and generate a differential control signal pair based on the input sub-signals and input the pair to the actual latch; The frequency-divided clock signal is equal to one-Nth of the sampling clock signal; The logic control module includes: a signal detection unit, configured to detect whether the level values ​​of two consecutive adjacent groups of input sub-signals are the same, and if so, to generate a selection control signal; a signal generating unit, configured to generate a corresponding flip control signal according to the selection control signal, and generate the virtual differential compensation signal pair according to the flip control signal; a signal generating unit, configured to output corresponding output sub-signals according to the input sub-signals, and generate the differential control signal pair according to the multiple output sub-signals; The signal detection unit includes a primary trigger and a primary XNOR gate module; the signal generation unit includes a secondary XNOR gate module, a primary multiplexer module, a buffer, a NOT gate, a secondary trigger module and a secondary multiplexer; the signal generation unit includes a multiplexer; The signal output interface of the primary trigger is connected to the input end of the primary XNOR gate module, and the signal output interface of the primary trigger is used to output the next input sub-signal adjacent to the current input sub-signal connected to the signal input interface of the primary trigger; The primary XNOR gate module includes N primary XNOR gates, which are cascaded in sequence to detect whether two consecutive adjacent groups of input sub-signals are the same; The secondary XNOR gate module includes N-1 secondary XNOR gates, and the input end of the secondary XNOR gate module is connected to the output end of the primary XNOR gate module; The primary multiplexer module includes N primary multiplexers, which are cascaded in sequence. The input pin of the primary multiplexer module is connected to the output end of the secondary XNOR gate module, the output end of the buffer, and the output end of the NOT gate, and is used to implement a flipping function when it is detected that two consecutive adjacent groups of input sub-signals are the same; The secondary trigger module includes N secondary triggers, the input end of the secondary trigger module is connected to the output pin of the primary multiplexer module, the output end of the secondary trigger module is connected to the input end of the buffer and the input end of the NOT gate, the clock input end of each secondary trigger is connected to the divided clock signal, and the N secondary triggers are used to realize the latched output of N channels of the divided clock signals; The input pin of the secondary multiplexer is connected to the output end of the secondary trigger module, the selection pin of the secondary multiplexer is connected to the sampling clock signal, and the input end of the virtual latch is connected to the output pin of the secondary multiplexer to receive the virtual differential compensation signal pair; An input pin of the multiplexer receives the output sub-signal and outputs the differential control signal pair, and an input terminal of the actual latch is connected to the output pin of the multiplexer to receive the differential control signal pair.

2. The timing control circuit according to claim 1, wherein: The first input terminal of the first primary XOR gate among the N primary XOR gates is connected to the signal output interface of the primary flip-flop, the clock input interface of the primary flip-flop is connected to the divided clock signal, the signal input interface of the primary flip-flop is connected to the second input terminal of the last primary XOR gate among the N primary XOR gates, and the second input terminal of the last primary XOR gate is connected to the last input sub-signal; Among the N primary XNOR gates, except the first primary XNOR gate, the second input terminal of the previous primary XNOR gate is connected to the first input terminal of the next primary XNOR gate to access the same input sub-signal, and the previous primary XNOR gate is adjacent to the next primary XNOR gate.

3. The timing control circuit according to claim 2, wherein: The first input terminal of the Mth secondary XOR gate among the N-1 secondary XOR gates is connected to the output terminal of the first primary XOR gate; M≥1 and M is a positive integer, M=N-1; The Nth input terminal of the Mth secondary XNOR gate is connected to the output terminal of the Nth primary XNOR gate; The selection pin of the first primary multiplexer among the N primary multiplexers is connected to the output end of the first primary XNOR gate; The selection pin of the Nth primary multiplexer except the first primary multiplexer among the N primary multiplexers is connected to the output end of the Mth secondary XNOR gate, the first input pin of each primary multiplexer is connected to the output end of the buffer, and the first input pin of each primary multiplexer is connected to the output end of the NOT gate; The output pin of the Nth primary multiplexer is connected to the signal input interface of the Nth secondary flip-flop, and the signal output interface of the first secondary flip-flop of the N secondary flip-flops is also connected to the input end of the NOT gate and the input end of the buffer; The clock input interface of the Nth secondary trigger is connected to the divided clock signal, and the signal output interfaces of the plurality of secondary triggers are respectively connected to the input pins of the secondary multiplexer in a one-to-one correspondence.

4. The timing control circuit according to claim 1, wherein: The selection control signal is generated by triggering the second clock edge of two consecutive clocks with the same level value.

5. The timing control circuit according to any one of claims 1 to 4, characterized in that: When there are two consecutive 11s or 00s in the input sub-signal, the level value of the virtual differential compensation signal pair is flipped; When two consecutive adjacent level values ​​of the input sub-signal change alternately, the output maintains the original state.

6. A sequential logic circuit, characterized in that: The sequential logic circuit comprises: a virtual latch, an actual latch, a switch module, a current source array, and the sequential control circuit according to any one of claims 1 to 5, wherein the logic control module is connected to the virtual latch and the actual latch, the switch module is connected to the actual latch, and the current source array is connected to the switch module; The virtual latch is configured to generate a signal flip according to the received virtual differential compensation signal pair to balance the change of the power supply load; The actual latch is configured to generate a switch control signal according to the differential control signal pair; The switch module is used to control the switch state according to the switch control signal; The current source array is used to switch the current direction of the current source array according to the switch state.

7. A digital-to-analog converter, characterized in that: The digital-to-analog converter includes the sequential logic circuit according to claim 6.

8. A chip, characterized in that: The chip includes the digital-to-analog converter according to claim 7.

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