LDPC (Low Density Parity Check) decoder and decoding method supporting multiple code rates and multiple code lengths

Abstract

The invention provides an LDPC (Low Density Parity Check) decoder and a decoding method supporting multiple code rates and multiple code lengths, which are suitable for data channel decoding in a wireless communication system. The decoder comprises a decoding control module, a variable information storage module, a cyclic shift module, a subtraction module, a reverse cyclic shift module, a verification information updating module, a verification information storage module, a variable information updating module and a decoding judgment module. The decoding method adopts a hierarchical scheduling block parallel minimum sum algorithm, supports dynamic configuration of various code rates and code lengths, comprehensively adapts to 51 expansion factors Z (2-384) defined in the 5G standard, and the code rate range covers 1 / 3-8 / 9 of BG1 and 1 / 5-2 / 3 of BG2. The method has the advantages of high flexibility, low complexity and optimized resource utilization rate, and is suitable for terminal equipment with limited resources.

Description

Technical Field

[0001] The present application relates to the field of wireless communication and channel coding technology, and in particular to an LDPC decoder and decoding method supporting multiple code rates and multiple code lengths. Background Art

[0002] LDPC codes are linear error-correcting codes that approach the Shannon limit and are widely used in modern communication systems. The 3GPP TS 38.212 standard selects quasi-cyclic LDPC codes (QC-LDPC) as the coding scheme for 5G data channels. It defines the basic matrices BG1 and BG2, supports 51 expansion factors Z (2 to 384), and covers a code rate range of 1 / 3 to 8 / 9 for BG1 and 1 / 5 to 2 / 3 for BG2. This standard places high demands on decoder flexibility. However, existing LDPC decoding technologies typically use fixed code rates and code lengths and are unable to dynamically adapt to various parameter combinations. This results in poor resource utilization or limited performance when dealing with different expansion factors or code rates, making it difficult to meet the requirements of the standard. Therefore, a flexible and efficient LDPC decoding scheme is urgently needed to meet the practical needs of 5G multi-scenario applications. Summary of the Invention

[0003] This application aims to provide an LDPC decoder and decoding method that supports multiple code rates and multiple code lengths, so as to solve the problems of insufficient flexibility and high complexity of decoders in the prior art and meet the demand for efficient LDPC decoding in 5G multi-scenario communication systems.

[0004] The technical solutions for achieving the purpose of the present invention are:

[0005] An LDPC decoder supporting multiple code rates and multiple code lengths, comprising:

[0006] The decoding control module is used to control and coordinate the decoding process. It adapts to the corresponding base matrix type and size by receiving the external input base matrix signal, code rate signal, and expansion factor signal, and schedules the variable information storage module, cyclic shift module, reverse cyclic shift module, check information update module, check information storage module, and variable information update module respectively by outputting corresponding control signals;

[0007] The variable information storage module is used to store the initial confidence information and the variable information during the iterative process. When the initial data to be decoded is stored, it outputs a feedback signal to the decoding control module to start the iterative decoding process, and outputs the corresponding variable information to the cyclic shift module according to the signal returned by the control module. When the final iteration is completed, it outputs all the variable information to the decoding decision module.

[0008] The circular shift module is used to perform circular shift processing on the variable information and output the shifted information to the subtraction module;

[0009] A subtraction module, used for performing subtraction operation on the variable information after circular shift;

[0010] The reverse cyclic shift module is used to restore the processed variable information to its original order and output it to the variable information update module;

[0011] A verification information updating module is used to update the verification information according to the variable information and output the verification information to the verification information storage module and the variable information updating module;

[0012] A verification information storage module is used to store verification information and output corresponding verification information to the subtraction module according to the signal of the decoding control module;

[0013] A variable information updating module, configured to update the variable information according to the verification information and output the updated variable information to the variable information storage module;

[0014] The decoding decision module is used to receive the final variable information when the maximum number of iterations is reached, extract and decide the sign bit of the final variable information, and output a binary hard decision result as the final output of the LDPC decoding.

[0015] Furthermore, the main input signals of the decoding control module include the base matrix signal enabg, the code rate signal rate_flag, the expansion factor signal z_factor, the variable information storage module feedback signal flag_control, and the check information update module feedback signal flag_wr_row. The main output signals include the variable information storage module RAM read enable signal reg_h_rom_rd_en, the cyclic shift module enable signal reg_ver_rd_en, the check information update module enable signal flag_CNU, the check information storage module enable signal flag_row, the row weight signal degree, the shift value position signal control_addr, the shift value signal shift, and the layer signal cnt_row. The module integrates multiple read-only memory (ROM) units for storing the positions and values of the shift values of the basic matrices BG1 and BG2. Driven by a clock signal, the module determines the base matrix type and the corresponding shift value ROM for the expansion factor based on the base matrix signal enabg and the expansion factor signal z_factor. The expansion factor size corresponds to the code length, supporting dynamic selection of the expansion factor Z from 2 to 384. The module determines the base matrix size based on the code rate signal rate_flag. This means that the ROM only reads data from the addresses corresponding to the base matrix rows 0 to rate_flag. Different code rates correspond to different base matrix sizes, supporting code rates ranging from 1 / 3 to 8 / 9 for BG1 and 1 / 5 to 2 / 3 for BG2. The control module coordinates the decoding process of each module through these control signals.

[0016] Furthermore, the variable information storage module's primary input signals include the data to be decoded, the base matrix signal enabg, the code rate signal rate_flag, the expansion factor signal z_factor, and variable information update data. Its primary output signals include flag_control and intermediate data from variable information iterations. The module sequentially distributes the decoded information to Z RAMs based on the enabg, rate_flag, and z_factor signals. When the variable information storage module completes storage of all decoded data, it feeds back to the control module via the flag_control signal, initiating decoding. The control module outputs the reg_h_rom_rd_en and control_addr signals to control the enable and address signals for the variable information storage module's RAMs, extracting Z variable information and outputting them to the cyclic shift module.

[0017] Furthermore, the main input signals of the cyclic shift module include Z variable information data to be shifted, a shift value signal shift, and a cyclic shift enable signal reg_ver_rd_en, and the main output signals include Z shifted variable information data.

[0018] The cyclic shift module cyclically shifts the Z variable information to be shifted by shift positions through the reg_ver_rd_en and shift signals output by the control module, and then outputs the shifted information to the subtraction module.

[0019] Furthermore, the subtraction module primarily receives the Z shifted variable information data and the Z old verification information data as its input signals, and primarily outputs the difference between the two. The subtraction module performs a subtraction operation on the Z variable information data and the Z old verification information data, performs saturation processing, and then outputs the Z subtraction data to the inverse cyclic shift module and the verification information update module.

[0020] Furthermore, the reverse cyclic shift module mainly inputs Z subtraction data, an expansion factor signal z_factor, and a shift value signal shift, and mainly outputs inversely shifted data of the Z subtraction data. The reverse cyclic shift module cyclically shifts the Z subtraction data to be shifted by z_factor-shift positions based on the expansion factor signal z_factor and the shift signal output by the decoding control module, and then outputs the result to the variable information update module.

[0021] Furthermore, the verification information update module contains Z independent verification information update units, and each verification unit updates the value of a row of the check matrix. The main input signals include Z subtraction data, the verification information update module enable signal flag_CNU, and the row weight signal degree. The main output signals include the minimum value, the second minimum value, the minimum value position, the sign bit sequence, and the verification information update module feedback signal flag_wr_row. When the enable signal flag_CNU is valid, the verification information update module calculates the Z rows of data at the same time, independently calculates the minimum value and the second minimum value of the data in each row, and records the minimum value position and the sign bit sequence according to the row weight signal degree. After the calculation is completed, it is fed back to the control module through the signal flag_wr_row, and fed back to the verification information storage module through the signal flag_row, and the minimum value, the second minimum value, the minimum value position, the sign bit sequence, that is, the new verification information data are output to the verification information storage module and the variable information update module.

[0022] Furthermore, the verification information storage module's main input signals include Z groups of minimum values, sub-minimum values, minimum value positions, sign bit sequences, and row weight signal degree, as well as a storage enable signal flag_compress and a read enable signal flag_row. Its main output signals include Z old verification information data. When the enable signal flag_compress is valid, the module begins storing the Z groups of minimum values, sub-minimum values, minimum value positions, and sign bit sequences. When the enable signal flag_row is valid, the module begins reading the minimum value, sub-minimum value, minimum value position, and sign bit sequence from the RAM, and outputs Z old verification information data per clock according to the row weight signal degree, outputting degree times to the subtraction module.

[0023] Furthermore, the main input signals of the variable information update module include Z new verification information data and Z inverse shifted data, the row weight signal degree, the shift value signal shift, the expansion factor signal z_factor, and the enable signal flag_compress. The main output signals include the variable information update data. Since the verification information update module requires degree clocks to complete the calculation to obtain the new verification information data, the inverse shifted data must be stored in the FIFO first, waiting for the new verification information data to be input. When the enable signal flag_compress is valid, it means that the new verification information data has been calculated and input. The new verification information data is compressed data and needs to be decompressed into degree data according to the row weight signal degree. Because the verification data is shifted data, it needs to be reversely shifted according to the shift value signal shift and the expansion factor z_factor signal before it can correspond one-to-one with the data in the FIFO. The two are then added together to obtain new variable information data, which is then saturated and output to the variable information storage module, completing a cycle of the variable information data flow. At this point, the first layer operation is completed, the layer signal cnt_row of the control module is incremented by one, and the above steps are repeated. When the maximum layer of the bit rate parsing is reached, it indicates that one iteration is complete. Iteration continues until the maximum number of iterations is reached.

[0024] Furthermore, the decoding decision module is used to receive the final variable information when the maximum number of iterations is reached, extract and judge the sign bit of the final variable information, and output a binary hard decision result as the final output of the LDPC decoding. The module adopts a distributed parallel design, and the decision operations of each channel are performed independently and synchronously, ensuring efficient processing of multi-channel data and reducing overall decision delay.

[0025] A decoding method for an LDPC decoder supporting multiple code rates and multiple code lengths, based on the decoder implementation provided in this application, employing a hierarchically scheduled, block-wise, parallel minimum-sum decoding algorithm, the decoding method comprising the following steps:

[0026] Step 1: After the decoder is globally reset, the variable information storage module begins receiving externally input data to be decoded and stores it into Z channels in Z RAMs based on the externally input expansion factor signal parameter Z. The decoding control module selects the appropriate parity check matrix type and the number of layers for this hierarchical scheduling based on the externally input base matrix signal parameter and code rate parameter. It then waits for the variable information storage module to complete the storage of the data to be decoded before proceeding to Step 2.

[0027] Step 2: Initialize the check matrix. The initialization work is done by the decoding control module, variable information storage module, and cyclic shift module to dynamically generate a single-layer check matrix. The decoding control module outputs the shift value information of the base matrix to the cyclic shift module and the position information of the base matrix to the variable information storage module. The variable information storage module outputs the variable information data of this position to the cyclic shift module according to the position information of the base matrix. The cyclic shift module completes the initialization and enters step 3 after performing cyclic shift processing on the variable information according to the shift value information of the base matrix.

[0028] Step 3: A hierarchically scheduled, block-parallel minimum-sum decoding algorithm with a degree of parallelism of Z is used. The decoding control module divides the parity check matrix into F layers based on the bit rate information, with each layer containing Z rows of parity check equations. The decoding control module coordinates the iterative decoding operation, performing each module sequentially on a layer-by-layer basis. It monitors the decoding progress and the number of iterations. Completion of the Fth layer completes an iteration. When the maximum number of iterations is reached, the process proceeds to Step 4.

[0029] Step 4: After reaching the final number of iterations, the decoding decision module performs hard decision processing on the a posteriori information of the variable nodes in the variable information storage module. Specifically, the decoding decision module extracts the sign bit from the a posteriori information data, generates a multi-bit wide binary hard decision result, and outputs it to the decoder to complete the decoding.

[0030] Furthermore, the operations in each layer of step 3 include the following sub-steps:

[0031] (1) Update verification information:

[0032] The subtraction module reads the variable node posterior information Q corresponding to the current layer n , Q n Input by the cyclic shift module. Combined with the check information R passed in the previous iteration m,n , R m,n Input from the verification information storage module, calculate the input information from the variable node to the verification node:

[0033] L m,n =Q n -R m,n

[0034] Among them L m,n The information passed from variable node n to check node m.

[0035] For each check node m, based on the minimum sum algorithm, the check information update module calculates the input information L of all connected variable nodes m,nThe minimum and second minimum values of the check node are obtained and the position of the minimum value is recorded. The calculation result is output as the update information from the check node to the variable node. The check information storage module receives the calculation result and temporarily stores it through the distributed storage structure. The update information R from the check node to the variable node is m,n The calculation is as follows:

[0036]

[0037] in:

[0038] N(m) represents the set of variable nodes connected to the check node m;

[0039] N(m)\n represents the set excluding variable node n;

[0040] sign(L m,n′ ) is L m,n′ The sign function (+1 or -1);

[0041] |L m,n′ | for L m,n′ The absolute value of

[0042] The update information is compressed by the verification information storage module according to quantization rules to reduce storage and computing overhead while retaining decoding accuracy.

[0043] (2) Variable information update:

[0044] The variable information update module verifies the updated information R of the node in the current layer. m,n , combined with the old variable information data L input from the reverse cycle shift module n Update the posterior information of the corresponding variable node:

[0045]

[0046] Where M(n) represents the set of check nodes connected to variable node n.

[0047] For the updated posterior information Q n Store it back into RAM for use in the next layer iteration.

[0048] Compared with the prior art, the present invention has the following advantages:

[0049] 1. High flexibility: By integrating dynamic configuration of read-only memory (ROM) and random access memory (RAM), it supports LDPC codes with 51 expansion factors and a wide range of code rates. It can adapt to diverse needs without modifying the hardware structure, significantly improving versatility compared to existing fixed designs.

[0050] 2. Low complexity: The hierarchical parallel minimum sum algorithm is used, which reduces the complexity of the algorithm compared to the traditional belief propagation algorithm, accelerates the decoding convergence speed, reduces the number of iterations, and increases the throughput.

[0051] 3. Efficient resource utilization: Confidence information and iterative variable information are stored and reused, and initial data and intermediate results are efficiently integrated through a single RAM array, reducing storage resource usage by approximately 35%. The introduction of sequential logic comparison technology allows dynamic solution of minimum and second-minimum values using only two data locations. Compared with the traditional method of storing the entire group and then comparing, the use of registers and comparators is reduced. In addition, by compressing the check information into a sequence of minimum value, second-minimum value, minimum value position, and sign bit for storage, rather than a single data point, further saving resources. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] Figure 1 This is a schematic diagram of the overall structure of the LDPC decoder supporting multiple code rates and multiple code lengths provided in this application.

[0053] Figure 2 This is a flow chart of the LDPC decoding algorithm based on the decoder provided in this application.

[0054] Figure 3 This is a schematic diagram of the multi-rate and multi-code length support structure of the decoding control module provided in this application.

[0055] Figure 4 This is a schematic diagram of the calculation principle of the multi-code length support structure of the cyclic shift module provided in this application. DETAILED DESCRIPTION

[0056] In order to make the technical solutions and advantages of the present application clearer, the implementation methods of the present application are described in detail below with reference to the accompanying drawings.

[0057] See also Figure 1 , Figure 1 The overall structure diagram of the LDPC decoder supporting multiple code rates and code lengths provided in this application is a detailed description of the decoder structure and decoding process using the BG1 matrix, expansion factor 384, and code rate 0.85 as an example. The decoder includes: a decoding control module, a variable information storage module, a cyclic shift module, a subtraction module, a reverse cyclic shift module, a check information update module, a check information storage module, a variable information update module, and a decoding decision module; wherein,

[0058] The decoding control module is used to control and coordinate module calls at each decoding stage. It adapts to the corresponding base matrix type and size by receiving external input base matrix signals, code rate signals, and expansion factor signals, and schedules the variable information storage module, cyclic shift module, reverse cyclic shift module, check information update module, check information storage module, and variable information update module by outputting corresponding control signals, so that the decoder can complete the decoding operation normally and orderly.

[0059] The variable information storage module is used to receive and store the initially input data to be decoded and the iteratively updated variable information. When the initial data to be decoded is stored, it outputs a feedback signal to the decoding control module to start the iterative decoding process, and outputs the corresponding variable information to the cyclic shift module according to the signal returned by the control module. When the final iteration is completed, all the variable information is output to the decoding decision module.

[0060] The cyclic shift module is used to perform cyclic shift on the input variable information according to the shift value input by the control module and then output the shifted variable information to the subtraction module.

[0061] The subtraction module is used to subtract the old verification information of the previous iteration input by the verification information storage module from the input variable information after cyclic shift, and then output the result to the reverse cyclic shift module and the verification information update module.

[0062] The reverse cyclic shift module is used to perform a reverse shift operation on the input variable information that has undergone subtraction processing according to the shift value input by the decoding control module, and output it to the variable information update module after restoring it to the original order.

[0063] The verification information update module is used to calculate the input variable information that has undergone subtraction processing according to the control signal input by the decoding control module to obtain the minimum value, second minimum value, minimum value position, and sign bit of this row of information, and then output it to the verification information storage module and the variable information update module.

[0064] The verification information storage module is used to store the input updated verification information and output the corresponding verification information to the subtraction module according to the signal of the control module.

[0065] The variable information updating module is used to perform an operation on the input minimum value, the second minimum value, the minimum value position, the sign bit information and the variable information input through the reverse cyclic shift module, perform an addition calculation and output the result to the variable information storage module.

[0066] The decoding decision module is used to perform a hard decision operation on the variable information input after the final iteration and output the decoding result to the decoder.

[0067] Furthermore, the main input signals of the decoding control module include the base matrix signal enabg = 0 (corresponding to BG1), the code rate signal rate_flag = 5 (corresponding to a code rate of 0.85), the expansion factor signal z_factor = 384, the variable information storage module feedback signal flag_control, and the check information update module feedback signal flag_wr_row. The main output signals include the variable information storage module RAM read enable signal reg_h_rom_rd_en, the cyclic shift module enable signal reg_ver_rd_en, the check information update module enable signal flag_CNU, the check information storage module enable signal flag_row, the row weight signal degree, the shift value position signal control_addr, the shift value signal shift, and the layer signal cnt_row. The module integrates multiple read-only memory (ROM) units for storing the positions and values of the shift values of the base matrices BG1 and BG2. Driven by the clock signal, the module determines that the base matrix type is BG1 and the shift value ROM corresponding to the expansion factor is 384 based on the base matrix signal enabg = 0 and the expansion factor signal z_factor = 384. Based on the code rate signal rate_flag = 5, the module determines that the base matrix size is 5 rows, meaning that the ROM only reads the data corresponding to the addresses of rows 0 to 5 of the base matrix (the address signal is counted starting from row 0, so there are actually 6 rows). The control module coordinates the decoding process of each module through the above control signals.

[0068] Furthermore, the variable information storage module's primary input signals include the data to be decoded, the base matrix signal enabg = 0, the code rate signal rate_flag = 5, the expansion factor signal z_factor = 384, and variable information update data. Its primary output signals include flag_control and intermediate data from variable information iterations. Based on the signals enabg = 0, rate_flag = 5, and z_factor = 384, the module sequentially distributes the decoded information to 384 RAMs, each containing 68 data items. When the variable information storage module completes storage of all decoded data, it feeds back to the control module via the flag_control signal, initiating decoding. The control module outputs the reg_h_rom_rd_en and control_addr signals to control the enable and address signals of the variable information storage module's RAMs, extracting 384 variable information items and outputting them to the cyclic shift module.

[0069] Furthermore, the cyclic shift module's main input signals include the 384 variable information data to be shifted, the shift value signal "shift," and the cyclic shift enable signal "reg_ver_rd_en." Its main output signal includes the 384 shifted variable information data. The cyclic shift module uses the reg_ver_rd_en and shift signals output by the control module to cyclically shift the 384 variable information data by shift positions, and then outputs the shift position to the subtraction module.

[0070] Furthermore, the subtraction module's primary input signals include the shifted 384 variable information data and the 384 old verification information data, and its primary output signal is the difference between the two. The subtraction module performs a subtraction operation on the 384 variable information data and the 384 old verification information data, performs saturation processing, and then outputs the 384 subtraction data to the de-cyclic shift module and the verification information update module.

[0071] Furthermore, the reverse cyclic shift module mainly inputs 384 subtraction data, an expansion factor signal z_factor=384, and a shift value signal shift, and mainly outputs inversely shifted data of the 384 subtraction data. The reverse cyclic shift module cyclically shifts the 384 subtraction data to be shifted by 384-shift positions based on the expansion factor signal 384 and the shift signal output by the decoding control module, and then outputs the result to the variable information update module.

[0072] Furthermore, the check information update module contains 384 independent check information update units, and each check unit updates the value of a row of the check matrix. The main input signals include 384 subtraction data, the check information update module enable signal flag_CNU, and the row weight signal degree. The main output signals include the minimum value, the second minimum value, the minimum value position, the sign bit sequence, and the check information update module feedback signal flag_wr_row. When the enable signal flag_CNU is valid, the check information update module calculates the 384 rows of data at the same time, independently calculates the minimum value and the second minimum value of the data in each row, and records the minimum value position and the sign bit sequence according to the row weight signal degree (such as the first row weight is 19). After the calculation is completed, it is fed back to the control module through the signal flag_wr_row, and fed back to the check information storage module through the signal flag_row, and the minimum value, the second minimum value, the minimum value position, the sign bit sequence, that is, the new check information data are output to the check information storage module and the variable information update module.

[0073] Furthermore, the verification information storage module's main input signals include 384 sets of minimum values, sub-minimum values, minimum value positions, sign bit sequences, and a row weight signal (degree), a storage enable signal (flag_compress), and a read enable signal (flag_row). Its main output signals include 384 sets of old verification information data. When the flag_compress enable signal is valid, storage of the 384 sets of minimum values, sub-minimum values, minimum value positions, and sign bit sequences begins. When the flag_row enable signal is valid, reading of the minimum value, sub-minimum value, minimum value position, and sign bit sequence from the RAM begins. Based on the row weight signal (degree), in the first row, the row weight (degree) = 19, 384 sets of old verification information data are output per clock cycle, 19 times to the subtraction module.

[0074] Furthermore, the main input signals of the variable information update module include 384 new verification information data and 384 reverse shifted data, the row weight signal degree, the shift value signal shift, the expansion factor signal z_factor, and the enable signal flag_compress. The main output signals include the variable information update data. Since the verification information update module requires degree = 19 clocks to complete the calculation to obtain the new verification information data, the reverse shifted data must first be stored in the FIFO and wait for the new verification information data to be input. When the enable signal flag_compress is valid, it means that the new verification information data has been calculated and input. The new verification information data is compressed data and needs to be decompressed into 19 data according to the row weight signal degree. Because the verification data is shifted data, it needs to be reversely shifted according to the shift value signal shift and the expansion factor z_factor = 384 signal before it can correspond one-to-one with the data in the FIFO. The two are then added together to obtain new variable information data. After saturation processing, the data is output to the variable information storage module, completing a cycle of the variable information data flow. At this point, the first layer operation is completed, the layer signal cnt_row of the control module is incremented by one, and the above steps are repeated. When the maximum layer of the bit rate parsing is reached, 5, it indicates that one iteration is complete. Iteration continues until the maximum number of iterations (e.g., 10) is reached.

[0075] Furthermore, the decoding decision module is used to receive the final variable information when the maximum number of iterations is reached, extract and judge the sign bit of the final variable information, and output a binary hard decision result as the final output of the LDPC decoding. The module adopts a distributed parallel design, and the decision operations of each channel are performed independently and synchronously, ensuring efficient processing of multi-channel data and reducing overall decision delay.

[0076] Decoding method:

[0077] See also Figure 2 ,like Figure 2 The LDPC decoding algorithm flow chart based on the above decoder provided in this application uses a hierarchical scheduling block parallel minimum sum algorithm to achieve efficient decoding by iteratively processing quantized data. When using BG1, an expansion factor of 384, and a code rate of 0.85, the specific decoding steps are as follows:

[0078] Step 1: After the decoder is globally reset, the variable information storage module begins receiving externally input data to be decoded and stores it in 384 RAMs, divided into 384 channels based on the externally input expansion factor signal parameter Z = 384. The decoding control module selects the appropriate parity check matrix type and the number of layers F = 5 for this hierarchical scheduling based on the externally input base matrix signal parameter BG1 and the code rate parameter 5. It then waits for the variable information storage module to complete storage of the data to be decoded before proceeding to Step 2.

[0079] Step 2: Initialize the check matrix. The initialization work is performed by the decoding control module, the variable information storage module, and the cyclic shift module to dynamically generate a single-layer check matrix. The decoding control module outputs the shift value information when the adaptation expansion factor signal parameter is Z=384 and the base matrix is BG1 to the cyclic shift module, and outputs the position information of the base matrix BG1 to the variable information storage module. The variable information storage module outputs the 384 variable information data at this position to the cyclic shift module according to the position information of the base matrix BG1. The cyclic shift module completes the initialization and enters step 3 after performing cyclic shift processing on the 384 variable information according to the shift value information of the base matrix.

[0080] Step 3: Iterative decoding uses a layered, block-parallel minimum-sum decoding algorithm with a degree of parallelism of 384. The decoding control module divides the parity check matrix into five layers based on the bit rate information, with each layer containing 384 rows of parity check equations. The decoding control module coordinates the iterative decoding operations of each module, performing them sequentially on a layer-by-layer basis. It monitors the decoding progress of each layer and the number of iterations. Completion of the fifth layer completes one iteration. When the maximum number of iterations is reached, the process proceeds to step 4.

[0081] Step 4: After reaching the final number of iterations, the decoding decision module performs hard decision processing on the a posteriori information of the variable nodes in the variable information storage module. Specifically, the decoding decision module extracts the sign bit from the a posteriori information data, generates a multi-bit wide binary hard decision result, and outputs it to the decoder to complete the decoding.

[0082] Furthermore, the operations in each layer of step 3 include the following sub-steps:

[0083] Verification information update:

[0084] The subtraction module reads the posterior information Q of the 384 variable nodes corresponding to the current layer n , Q nInput by the cyclic shift module. Combined with the 384 check information R passed in the previous iteration m,n , R m,n Input from the verification information storage module, calculate the input information from the variable node to the verification node:

[0085] L m,n =Q n -R m,n

[0086] Among them L m,n The information passed from variable node n to check node m.

[0087] For each check node m, based on the minimum sum algorithm, 384 check information update modules calculate the input information L of all connected variable nodes. m,n The minimum and second minimum values of the check node are obtained and the position of the minimum value is recorded. The calculation result is output as the update information from the check node to the variable node. The check information storage module receives 384 sets of calculation results at a time and temporarily stores them through the distributed storage structure. The update information R from the check node to the variable node is m,n The calculation is as follows:

[0088]

[0089] in:

[0090] N(m) represents the set of variable nodes connected to the check node m;

[0091] N(m)\n represents the set excluding variable node n;

[0092] sign(L m,n′ ) is L m,n′ The sign function (+1 or -1);

[0093] |L m,n′ | for L m,n′ The absolute value of

[0094] The update information is compressed by the verification information storage module according to quantization rules to reduce storage and computational overhead while maintaining decoding accuracy. For example, in this decoding, the first complete row of data consists of 19 5-bit signed data, occupying a total of 95 bits. This is compressed into a 4-bit minimum absolute value, a 4-bit next-to-minimum absolute value, a 19-bit sign bit sequence, and a 5-bit minimum position, occupying a total of 32 bits, reducing storage overhead.

[0095] Variable information update:

[0096] The variable information update module updates the information R of the 384 check nodes in the current layer. m,n, combined with the 384 old variable information data L input from the reverse cycle shift module n Update the posterior information of the corresponding variable node:

[0097]

[0098] Where M(n) represents the set of check nodes connected to variable node n.

[0099] The variable information storage module updates the 384 posterior information Q n Store it back into RAM for use in the next layer iteration.

[0100] Implementation of key modules:

[0101] See also Figure 3 , Figure 3 This is a schematic diagram of the decoder control module provided by the present application, which is used to implement a multi-rate, multi-code length support structure. The decoding control module receives the expansion factor and base matrix signal and adapts the shift value storage ROM for BG1 or BG2. The ROM group contains 18 ROM blocks, two of which are used to store the non-negative 1 value positions of BG1 and BG2, and 16 blocks are used to store the non-negative 1 values of BG1 and BG2, corresponding to eight sets of shift values for the two matrices, supporting Z = 2 to 384. For example, when Z = 384 and the BG signal is 0, the BG1 non-1 value position storage ROM and the BG1 non-1 value storage ROM 2 are selected. The output is controlled according to the ROM read enable signal, and the check matrix is dynamically generated. For example, when the code rate is 0.85, based on the code rate flag information of 5, the ROM read address range is adjusted to the data address of layers 0 to 5, supporting 1 / 3 to 8 / 9 (BG1) or 1 / 5 to 2 / 3 (BG2).

[0102] See also Figure 4 , Figure 4 The decoder cyclic shift module provided in this application is used to implement the calculation principle diagram of the multi-code length support structure; the cyclic shift module includes a register group that can accommodate 384 confidence information and supports the maximum expansion factor. When Z = 384, the register is full of 384 data, and the intermediate value A is obtained by left shifting by shift bits, and B is obtained by right shifting by (384-shift) bits. The result Q = A|B completes the shift. When Z < 384 (such as Z = 128), 128 data are stored, and after shifting, the valid bits are retained through the mask Q = Q&[(1 < < 128) - 1].

[0103] In the FPGA implementation, taking BG1, Z=384, and bit rate 0.85 as an example, the decoder iterates 10 times. At a clock frequency of 100 MHz, the core decoding delay is about 21.84 μs and the throughput is about 386.81 Mbps.

[0104] In summary, the LDPC decoder and method of this application dynamically supports 51 expansion factors Z (2 to 384) and multiple code rates (BG11 / 3 to 8 / 9, BG21 / 5 to 2 / 3) in the 5G standard, with high flexibility, low complexity, and optimized resource utilization, making it suitable for 5G terminal devices. This embodiment does not limit the scope of protection, and equivalent variations of the technical solution remain within the scope of protection of this application.

Claims

1. An LDPC decoder supporting multiple code rates and multiple code lengths, characterized in that: include: The decoding control module is used to control and coordinate the decoding process. It adapts to the corresponding base matrix type and size by receiving the external input base matrix signal, code rate signal, and expansion factor signal, and schedules the variable information storage module, cyclic shift module, reverse cyclic shift module, check information update module, check information storage module, and variable information update module respectively by outputting corresponding control signals; The variable information storage module is used to store the initial confidence information and the variable information during the iterative process. When the initial data to be decoded is stored, it outputs a feedback signal to the decoding control module to start the iterative decoding process, and outputs the corresponding variable information to the cyclic shift module according to the signal returned by the control module. When the final iteration is completed, it outputs all the variable information to the decoding decision module. The circular shift module is used to perform circular shift processing on the variable information and output the shifted information to the subtraction module; A subtraction module, used for performing subtraction operation on the variable information after circular shift; The reverse cyclic shift module is used to restore the processed variable information to its original order and output it to the variable information update module; A verification information updating module is used to update the verification information according to the variable information and output the verification information to the verification information storage module and the variable information updating module; A verification information storage module is used to store verification information and output corresponding verification information to the subtraction module according to the signal of the decoding control module; A variable information updating module, configured to update the variable information according to the verification information and output the updated variable information to the variable information storage module; The decoding decision module is used to receive the final variable information when the maximum number of iterations is reached, extract and decide the sign bit of the final variable information, and output a binary hard decision result as the final output of the LDPC decoding.

2. The LDPC decoder according to claim 1, wherein: The input signals of the decoding control module include base matrix signal enabg, code rate signal rate_flag, expansion factor signal z_factor, variable information storage module feedback signal flag_control, and check information update module feedback signal flag_wr_row. The output signals include variable information storage module RAM read enable signal reg_h_rom_rd_en, cyclic shift module enable signal reg_ver_rd_en, check information update module enable signal flag_CNU, check information storage module enable signal flag_row, row weight signal degree, shift value position signal control_addr, shift value signal shift, layer signal Number cnt_row, this module integrates multiple read-only memory units for storing the positions and values of the shift values of the basic matrices BG1 and BG2. Driven by the clock signal, the base matrix type and the shift value ROM corresponding to the expansion factor are determined according to the base matrix signal enabg and the expansion factor signal z_factor. The size of the expansion factor corresponds to the length of the code length, and supports dynamic selection of the expansion factor Z from 2 to 384. The base matrix size is determined according to the code rate signal rate_flag, that is, the ROM only reads the data in the address corresponding to the 0th row to the rate_flag row of the base matrix. Different code rates correspond to different base matrix sizes, and the supported code rate range covers 1 / 3 to 8 / 9 of BG1 and 1 / 5 to 2 / 3 of BG2.

3. The LDPC decoder according to claim 1, wherein: The input signals of the variable information storage module include data information to be decoded, base matrix signal enabg, code rate signal rate_flag, expansion factor signal z_factor, and variable information update data; the output signals include feedback signal flag_control and intermediate data of variable information iteration; the module distributes the decoding information to Z RAMs in sequence according to the enabg, rate_flag, and z_factor signals; when the variable information storage module completes the storage of all decoded data, it feeds back to the control module through the flag_control signal to start decoding; the control module outputs the RAM read enable signal reg_h_rom_rd_en and the shift value position signal control_addr, and controls the enable signal and address signal of the variable information storage module RAM to extract Z variable information and output them to the cyclic shift module.

4. The LDPC decoder according to claim 1, wherein: The input signal of the subtraction module includes the shifted Z variable information data and the Z old verification information data. The output signal is the difference between the two input signals. The subtraction module performs a subtraction operation on the Z variable information data and the Z old verification information data, performs saturation processing, and then outputs Z subtraction data to the reverse cyclic shift module and the verification information update module.

5. The LDPC decoder according to claim 1, wherein: The check information update module contains Z independent check information update units, each of which updates the value of a row of the check matrix. The input signals of the module include Z subtraction data, the check information update module enable signal flag_CNU, and the row weight signal degree. The output signals include the minimum value, the second minimum value, the minimum value position, the sign bit sequence, and the check information update module feedback signal flag_wr_row. When the enable signal flag_CNU is valid, the check information update module calculates the Z rows of data at the same time, independently calculates the minimum value and the second minimum value of the data in each row, and records the minimum value position and the sign bit sequence according to the row weight signal degree. After the calculation is completed, the signal flag_wr_row is fed back to the control module, and then to the check information storage module through the signal flag_row. The minimum value, the second minimum value, the minimum value position, and the sign bit sequence, i.e., the new check information data, are output to the check information storage module and the variable information update module.

6. The LDPC decoder according to claim 1, wherein: The input signals of the verification information storage module include Z groups of minimum values, second minimum values, minimum value positions, sign bit sequences, and row weight signals degree, storage enable signals flag_compress, and reading enable signals flag_row. The output signals include Z old verification information data. When the enable signal flag_compress is valid, the module starts storing the Z groups of minimum values, second minimum values, minimum value positions, and sign bit sequences. When the enable signal flag_row is valid, the module starts reading the minimum value, second minimum value, minimum value position, and sign bit sequence in the RAM. According to the row weight signal degree, the module outputs Z old verification information data per clock, and outputs degree times to the subtraction module.

7. The LDPC decoder according to claim 1, wherein: The input signals of the variable information update module include Z new check information data and Z inverse shifted data, a row weight signal degree, a shift value signal shift, an expansion factor signal z_factor, and an enable signal flag_compress. The output signal includes variable information update data. When calculating, the check information update module first stores the inverse shifted data in the FIFO and waits for new check information data to be input. When the enable signal flag_compress is valid, it indicates that the new check information data calculation is completed and input, and the new check information data is decompressed into degree data according to the row weight signal degree; the check data is reversely shifted according to the shift value signal shift and the expansion factor z_factor signal and corresponds one-to-one to the data in the FIFO. Then, the new check information data and the inverse shifted data are added to obtain new variable information data, which is output to the variable information storage module after saturation processing, completing a cycle of the variable information data flow. At this time, the first-layer operation is completed, the layer signal cnt_row of the control module is increased by one, and the above steps are repeated. When the maximum layer of the code rate analysis is reached, it indicates that one iteration is completed, and the iteration is continued to reach the maximum number of iterations.

8. The LDPC decoder according to claim 1, wherein: The decoding decision module adopts a distributed parallel design, and the decision operation of each channel is performed independently and synchronously.

9. An LDPC decoding method based on the decoder according to any one of claims 1 to 8, characterized in that: Including steps: Step 1: After the decoder is globally reset, the variable information storage module begins receiving externally input data to be decoded and stores it into Z channels in Z RAMs based on the externally input expansion factor signal parameter Z. The decoding control module selects the appropriate check matrix type and the number of layers for this hierarchical scheduling based on the externally input base matrix signal parameter and code rate parameter, and waits for the variable information storage module to complete the storage of the data to be decoded before proceeding to Step 2. Step 2: Initialize the parity check matrix. The decoding control module, variable information storage module, and cyclic shift module collaborate to dynamically generate a single-layer parity check matrix. The decoding control module outputs the shift value information of the base matrix to the cyclic shift module, and outputs the position information of the base matrix to the variable information storage module. The variable information storage module outputs the variable information data at this position to the cyclic shift module based on the position information of the base matrix. The cyclic shift module performs cyclic shift processing on the variable information based on the shift value information of the base matrix, completing the initialization and entering step 3. Step 3: Adopt the minimum sum decoding algorithm with hierarchical scheduling and block parallelism, with a parallelism of Z. The decoding control module divides the check matrix into F layers according to the bit rate information. Each layer contains Z rows of check equations. The iterative decoding operation is coordinated by the decoding control module to perform each module in sequence according to each layer, and the layer decoding progress and number of iterations are monitored. When the Fth layer is completed, it indicates that one iteration is completed. When the maximum number of iterations is reached, enter step 4. Step 4: After reaching the final number of iterations, the decoding decision module extracts the sign bit from the posterior information data, generates a multi-bit wide binary hard decision result and outputs it to the decoder to complete the decoding.

10. The LDPC decoding method according to claim 9, wherein: The operations in each layer of step 3 include updating verification information and updating variable information. The verification information update includes: The subtraction module reads the variable node posterior information Q corresponding to the current layer n , Q n Input by the cyclic shift module, combined with the check information R passed in the previous iteration m,n , R m,n Input from the verification information storage module, calculate the input information from the variable node to the verification node: L m,n =Q n -R m,n Among them L m,n The information passed from variable node n to check node m; For each check node m, based on the minimum sum algorithm, the check information update module calculates the input information L of all connected variable nodes m,n The minimum and second minimum values of the check node are output as the update information from the check node to the variable node; the check information storage module receives the calculation results and temporarily stores them through the distributed storage structure, and the update information R from the check node to the variable node is output as the update information R from the check node to the variable node. m,n The calculation is as follows: in: N(m) represents the set of variable nodes connected to the check node m; N(m)\n represents the set excluding variable node n; sign(L m,n′ ) is L m,n′ The symbolic function of |L m,n′ | for L m,n′ The absolute value of The update information is compressed by the verification information storage module according to the quantization rules; The variable information update includes: The variable information update module verifies the updated information R of the node in the current layer. m,n , combined with the old variable information data L input from the reverse cycle shift module n Update the posterior information of the corresponding variable node: Where M(n) represents the set of check nodes connected to variable node n; The variable information storage module updates the posterior information Q n Store it back into RAM for use in the next layer iteration.

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