Semiconductor device, manufacturing method thereof and electronic equipment

Abstract

A semiconductor device, a manufacturing method thereof, and an electronic apparatus, the semiconductor device comprising: a multilayer memory cell array stacked in a direction perpendicular to a substrate; a plurality of layers of bit lines, wherein each layer of bit lines comprises a plurality of bit lines; the adjacent bit lines are insulated through an insulating layer; a plurality of shielding layers, wherein each shielding layer is at least located between the adjacent layers of memory cell arrays; the shielding layer is at least located between the bit lines of the adjacent layers; the shielding layer is configured to have a constant potential. According to the semiconductor device, the capacitance coupling effect between two adjacent bit lines can be reduced, and the performance of the device is improved.

Description

Technical Field

[0001] Embodiments of the present application relate to the field of semiconductor technology, and more particularly to a semiconductor device, a manufacturing method thereof, and an electronic device. Background Art

[0002] With the development of integrated circuit technology, the critical dimensions of devices are increasingly reduced, and the types and quantities of devices included in a single chip increase accordingly. As a result, minor differences in the process production may affect the device performance.

[0003] In order to reduce the cost of products as much as possible, people hope to fabricate as many device units as possible on a limited substrate. Since the advent of Moore's Law, various semiconductor structure designs and process optimizations have been proposed in the industry to meet the requirements of current products. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail in this document. This overview is not intended to limit the scope of protection of the present application.

[0005] Embodiments of the present application provide a semiconductor device, a manufacturing method thereof, and an electronic device. The semiconductor device can reduce the capacitive coupling effect between two adjacent bit lines and improve the device performance.

[0006] Embodiments of the present application provide a semiconductor device, including:

[0007] A multi-layer memory cell array stacked in a direction perpendicular to the substrate;

[0008] A multi-layer bit line, each layer of the bit line including multiple bit lines;

[0009] The adjacent bit lines are insulated from each other by an insulating layer;

[0010] A multi-layer shielding layer, each layer of the shielding layer being at least located between adjacent layers of the memory cell array;

[0011] The shielding layer is at least located between the bit lines of adjacent layers;

[0012] The shielding layer is configured to have a constant potential.

[0013] In some embodiments of the present application, there is the shielding layer between any two adjacent bit lines located in different layers.

[0014] In some embodiments of the present application, there is the shielding layer between at least some adjacent bit lines located on the same layer.

[0015] In some embodiments of the present application, the shielding layer is at least located in the insulating layer between the bit lines of adjacent layers.

[0016] In some embodiments of the present application, the shielding layer is also located in the insulating layer between two adjacent bit lines on the same layer.

[0017] In some embodiments of the present application, the shielding layer extends in a first direction and a second direction, the bit line extends in the second direction, and the first direction and the second direction intersect and are both horizontal directions.

[0018] In some embodiments of the present application, the orthographic projection of the bit line on the substrate falls within the range of the orthographic projection of the shielding layer on the substrate.

[0019] In some embodiments of the present application, the shielding layers between the bit lines of adjacent layers are connected to each other.

[0020] In some embodiments of the present application, the shielding layer between the bit lines of adjacent layers is connected to the shielding layer between two adjacent bit lines on the same layer.

[0021] In some embodiments of the present application, the shielding layers of different layers are connected by a wire in a through hole extending towards the substrate; or,

[0022] In the same layer of the memory cell array, two adjacent bit lines of each adjacent two columns of the memory cells are adjacent, and there is a trench extending towards the substrate between the two adjacent bit lines, and a shielding layer located between the two bit lines is provided in the trench, and the shielding layer is located between the two adjacent bit lines of each layer.

[0023] In some embodiments of the present application, the shielding layer is a conductive layer containing metal.

[0024] In some embodiments of the present application, the memory cells in the memory cell array include transistors, and the transistors include a semiconductor layer, a gate electrode, and a gate insulating layer located between the semiconductor layer and the gate electrode; the semiconductor layer extends in a direction towards the substrate and at least partially surrounds the gate electrode; the source and drain of the transistor are spaced apart horizontally on the outer sidewall of the semiconductor layer;

[0025] The bit line extends horizontally and is cross-connected to the drain.

[0026] In some embodiments of the present application, the memory cell includes a read transistor and a write transistor, the bit line includes a read bit line and a write bit line, the read transistor is connected to the read bit line, and the write transistor is connected to the write bit line;

[0027] There is the shielding layer between two adjacent read bit lines of different layers.

[0028] The embodiment of the present application further provides an electronic device, and the electronic device includes the semiconductor device provided by the embodiment of the present application.

[0029] In the semiconductor device of the embodiment of the present application, a shielding layer with a constant potential is provided between at least two adjacent bit lines stacked at least partially in the vertical direction, which can shield the coupling charges between the adjacent bit lines in the adjacent layers, thereby reducing or even eliminating the coupling capacitance between the adjacent bit lines, avoiding the influence of the coupling capacitance or charges on the signals on the bit lines, making the signals on the bit lines not easily affected by the coupling capacitance when reading out the signals, and further improving the accuracy of data reading.

[0030] Other features and advantages of the present application will be described in the subsequent specification, and part of them will become clearer from the specification or be understood by implementing the present application. Other advantages of the present application can be realized and obtained through the solutions described in the specification and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The drawings are used to provide an understanding of the technical solutions of the present application and constitute a part of the specification. They are used together with the embodiments of the present application to explain the technical solutions of the present application and do not constitute a limitation to the technical solutions of the present application.

[0032] Figure 1 It is a schematic diagram of the coupling capacitance C between adjacent bit lines in the current 3D semiconductor device;

[0033] Figure 2 It is a schematic diagram of the signal curve in the data sensing and amplifying stage read from the bit line;

[0034] Figure 3 It is a schematic diagram of the distribution of the coupling capacitance formed by the interaction of multiple bit lines and multiple shielding layers of a semiconductor device according to an exemplary embodiment of the present application;

[0035] Figure 4 It is a schematic longitudinal sectional view of multiple bit lines stacked in the vertical substrate direction of a semiconductor device according to an exemplary embodiment of the present application;

[0036] Figure 5A It is a schematic sectional view of a semiconductor device according to an exemplary embodiment of the present application in a section parallel to the substrate;

[0037] Figure 5B For Figure 5A It is a schematic sectional view of the semiconductor device shown in a section perpendicular to the substrate;

[0038] Figure 6A It is a schematic sectional view of another semiconductor device according to an exemplary embodiment of the present application in a section parallel to the substrate;

[0039] Figure 6B is Figure 6A a schematic cross-sectional view of the semiconductor device shown in a cross-section perpendicular to the substrate. Detailed implementation manners

[0040] To make the objectives, technical solutions, and advantages of this application clearer and more understandable, the embodiments of this application will be described in detail below with reference to the accompanying drawings. It should be noted that, without conflict, the embodiments and features in the embodiments of this application can be arbitrarily combined with each other.

[0041] To make the objectives, technical solutions, and advantages of this application clearer and more understandable, the embodiments of this application will be described in detail below with reference to the accompanying drawings. It should be noted that, without conflict, the embodiments and features in the embodiments of this application can be arbitrarily combined with each other.

[0042] The implementation manners of this application do not necessarily limit the sizes shown in the accompanying drawings. The shapes and sizes of the components in the drawings are preferred implementation schemes and can also be other shapes and sizes. In addition, the drawings schematically show ideal examples, and the implementation manners of this application are not limited to the shapes or values shown in the drawings.

[0043] The size and proportional relationships between the various film layers or components in the accompanying drawings of this application can be used as a reference in actual processes, which are implementation manners with better technical effects, but are not limited thereto. For example: the aspect ratio of the semiconductor layer, the thickness and spacing of each film layer, can be adjusted according to actual needs.

[0044] The ordinal numbers such as "first" and "second" in this application are set to avoid confusion of the components and do not represent any order, quantity, or importance.

[0045] In this application, for convenience, words and phrases indicating the orientation or positional relationship, such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., are used to describe the positional relationship of the components with reference to the accompanying drawings. This is only for the convenience of describing this specification and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation to this application. The positional relationship of the components changes appropriately according to the directions describing each component. Therefore, it is not limited to the words and phrases described in the disclosure and can be appropriately replaced according to the situation.

[0046] In this application, unless otherwise clearly specified or limited, the terms "installed", "connected", and "linked" shall be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected, or indirectly connected through an intermediate member, or the internal communication of two components. For those of ordinary skill in the art, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0047] In this application, a transistor refers to an element that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In this application, the channel region refers to the region where current mainly flows.

[0048] In this application, it can be that the first electrode is the drain electrode and the second electrode is the source electrode, or it can be that the first electrode is the source electrode and the second electrode is the drain electrode. In cases such as using transistors with opposite polarities or changes in the current direction during circuit operation, the functions of the "source electrode" and "drain electrode" sometimes swap with each other. Therefore, in this application, unless otherwise specified, the "source electrode" and "drain electrode" can swap with each other.

[0049] In this application, "electrically connected" or "connected" includes cases where components are connected together through an element with a certain electrical effect. For example, an electrical signal connection (coupled connection, such as coupled to), or a physical direct connection. There are no particular restrictions on the "element with a certain electrical effect" as long as it can transfer electrical signals between the components to be connected. Examples of the "element with a certain electrical effect" include not only electrodes and wirings, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.

[0050] In this application, "parallel" means approximately parallel or almost parallel. For example, the state where the angle formed by two straight lines is -10° or more and 10° or less, and thus also includes the state where the angle is -5° or more and 5° or less. Additionally, "perpendicular" means approximately perpendicular. For example, the state where the angle formed by two straight lines is 80° or more and 100° or less, and thus also includes the state where the angle is 85° or more and 95° or less.

[0051] In this application, "film" and "layer" can be swapped with each other. For example, sometimes the "shielding layer" can be replaced with a "conductive film". Similarly, sometimes the "insulating film" can be replaced with an "insulating layer".

[0052] As used in this application, "A and B are arranged on the same layer" means that A and B are distributed on the same horizontal plane, or although they are not on the same horizontal plane, they are in different regions on the same supporting surface. In one embodiment, A and B are simultaneously formed by patterning the same film layer through the same patterning process.

[0053] "A and B are of an integral structure" in the embodiments of this application may mean that there is no obvious fault or gap or other obvious boundary interface in the microscopic structure. Generally, a connected film layer patterned on a film layer is of an integral structure. For example, A and B are formed of the same material to form a film layer and simultaneously form a connected structure through the same patterning process, or B is directly grown on A by epitaxy, and the materials of the two may not be completely the same.

[0054] The substrate in the embodiments of this application may be a supporting structure. For example, a silicon substrate, or a supporting structure on which other film layers or functions or circuits have been distributed on the silicon substrate. The device involved in the inventive configuration of the embodiments of this application is arranged on the main surface of the supporting structure.

[0055] In this application, spaced-apart distribution can be understood as separated and independent distribution. It can be achieved by physical disconnection in the physical structure, or by electrical disconnection in electrical characteristics. For example, the semiconductor layer between the effective channels corresponding to two transistors is modified to achieve insulation to realize the electrical spacing between the two channels.

[0056] In a 3D three-dimensional structure, the distance between adjacent bit lines is small, and / or there is a large overlap between the bit lines. Therefore, it is easy to form a coupling effect between adjacent bit lines, which will pose a huge challenge to signal sensing and amplification operations. Because when adjacent bit lines sense opposite signals from the storage unit, the sensed signals will be significantly weakened.

[0057] Figure 1 FIG. shows a schematic diagram of the coupling capacitance C between adjacent bit lines in a current 3D semiconductor device. The 3D semiconductor device includes multiple bit lines BL00, BL01, BL02,... BL0n. The multiple bit lines extend along the direction parallel to the substrate. Each layer of the memory array includes multiple bit lines arranged at intervals in the horizontal direction. The memory cell arrays of each layer are periodically distributed in the direction perpendicular to the substrate. Because the distance between the bit lines of adjacent layers, especially the stacked bit lines, is relatively close, there is a coupling capacitance C. The two ends of the coupling capacitance are the bit lines. Each end serves as a charge storage node SN of a capacitor. The charge stored by the storage node affects the accuracy of reading the signal through the bit line. Especially for the bit line at one end of the coupling capacitance, its signal is not fixed. The coupling capacitance is sometimes large and sometimes small, resulting in a large impact on the read signal, and even the read information is incorrect. Therefore, the smaller the coupling capacitance between the bit lines, the better.

[0058] Figure 2 It is a schematic diagram of signal curves in the data sensing and amplifying stages for data read from bit lines. It can be seen that in the data sensing stage, when there is a coupling effect and when there is no coupling effect between adjacent bit lines, the data signals sensed on the bit lines are different, and this difference is even more obvious in the signal amplifying stage, which may even lead to incorrect read signals.

[0059] The embodiments of the present application provide a semiconductor device. Figure 3 It is a schematic diagram of the distribution of coupling capacitors formed by the interaction and stacking of multiple bit lines and multiple shielding layers of a semiconductor device according to an exemplary embodiment of the present application; Figure 4 It is a longitudinal sectional view of multiple bit lines stacked in the vertical substrate direction of a semiconductor device according to an exemplary embodiment of the present application. This structure enables no coupling capacitance between adjacent bit lines, and even if there is signal interference, it can be conducted away by the shielding layer.

[0060] As Figure 3 and Figure 4 shown, the semiconductor device of the embodiments of the present application includes: a multi-layer memory cell array located on a substrate 10, multiple layers of bit lines (including Figure 3 BL00, BL01, BL02,... BL0n in

[0061] ), an insulating layer 11, and a shielding layer 20;

[0062] The multi-layer memory cell array is stacked in a direction perpendicular to the substrate 10;

[0063] Each layer of bit lines includes multiple bit lines BL; one bit line BL is connected to a column of memory cells in a two-dimensional memory cell array parallel to the substrate;

[0064] The memory cells distributed in an array and the bit lines BL are located in the same layer;

[0065] The insulating layer 11 described in the embodiments of the present application can be a single layer, or a double layer or multiple layers;

[0066] Each layer of shielding layer 12 is at least located between adjacent layers of memory cell arrays;

[0067] The shielding layer 12 is at least located between adjacent layers of bit lines; the shielding layer 20 is configured to have a constant potential.

[0068] In the semiconductor device according to an embodiment of the present application, a shielding layer with a constant potential is provided between at least two adjacent bit lines stacked at least partially in the vertical direction, which can shield the coupling charges between the adjacent bit lines in different layers, thereby reducing or even eliminating the coupling capacitance between the adjacent bit lines, avoiding the influence of the coupling capacitance or charges on the signals on the bit lines, making it difficult for the signals on the read bit lines to be affected by the coupling capacitance, and further improving the accuracy of data reading.

[0069] In the present application, "having a constant potential" for the shielding layer 20 means that the shielding layer 20 has a constant voltage or current, which can be understood as a constant potential relative to a reference potential. The reference potential can be a ground voltage. The constant potential can be a zero potential provided by the ground terminal or a non-zero potential provided by a constant voltage terminal.

[0070] In some embodiments of the present application, the material of the shielding layer 20 can be a conductive material containing metal, such as tungsten, molybdenum, cobalt, titanium, titanium nitride and their alloys, etc., or can also be a conductive material such as polysilicon.

[0071] In some embodiments of the present application, as Figure 3 and Figure 4 shown, the semiconductor device includes a plurality of bit lines BL distributed in different layers and stacked in a direction perpendicular to the substrate 10. The adjacent two bit lines in different layers are stacked periodically, and the bit lines almost overlap in the vertical projection. A shielding layer 20 is provided between any two adjacent bit lines BL in different layers. The projection of the shielding layer 20 on the substrate 10 includes the projection of the bit line BL on the substrate 10, or the shielding layer 20 has the same shape as the bit line BL and the projections overlap on the substrate 10.

[0072] Figure 5A is a schematic cross-sectional view of a semiconductor device according to an exemplary embodiment of the present application in a cross-section parallel to the substrate; Figure 5B is Figure 5A shown in the schematic cross-sectional view of the semiconductor device in a cross-section perpendicular to the substrate; Figure 6A is a schematic cross-sectional view of another semiconductor device according to an exemplary embodiment of the present application in a cross-section parallel to the substrate; Figure 6B is Figure 6A shown in the schematic cross-sectional view of the semiconductor device in a cross-section perpendicular to the substrate.

[0073] In some embodiments of the present application, as Figure 5B and Figure 6B shown, a shielding layer 20 is provided between any two adjacent bit lines BL in different layers. For example, Figure 5B the lateral extension portion of the shielding layer 20 shown shields the coupling capacitance between the adjacent bit lines BL stacked vertically. In some embodiments of the present application, as Figures 5A to 6BAs shown, there is a shielding layer 20 between at least some adjacent two bit lines BL on the same layer. For example, Figure 5B the longitudinal extension part of the shown shielding layer 20 shields the coupling capacitance between two horizontally spaced bit lines. Figure 5B As shown, in the two-dimensional memory cell array, two adjacent bit lines are provided between every two columns of memory cells, and these two bit lines are distributed in a vertically circular stacked manner.

[0074] In some embodiments of the present application, such as Figure 6B shown, the shielding layer 20 is at least located in the insulating layer 11 between the bit lines BL of adjacent layers; in some embodiments, the shielding layer 20 is also located in the insulating layer 11 between two adjacent bit lines on the same layer.

[0075] In some embodiments of the present application, such as Figure 5A (top view) to Figure 6B shown, the shielding layer 20 extends in the first direction and the second direction, the bit line BL extends in the second direction, and the first direction and the second direction intersect and are both horizontal directions;

[0076] The shielding layer 20 covers two adjacent bit lines at the same time, and the length in the first direction is greater than the sum of the lengths of the two bit lines BL in the first direction.

[0077] In some embodiments of the present application, the first direction may be the X direction as shown in Figure 5A and Figure 6A shown, and the second direction may be the Y direction as shown in Figure 5B and Figure 6B shown; the first direction and the second direction may be perpendicular to each other, or may both be parallel to the substrate 10.

[0078] In some embodiments of the present application, such as Figure 5B and Figure 6B shown, the positive projection of the bit line BL on the substrate 10 falls within the range of the positive projection of the shielding layer 20 on the substrate 10. This is beneficial to shielding the coupling capacitance between adjacent bit lines BL to a greater extent.

[0079] In some embodiments of the present application, such as Figure 5B and Figure 6B shown, the horizontally extending shielding layers 20 between adjacent layer bit lines BL are connected by the longitudinally extending parts. For example, the shielding layers 20 between adjacent layer bit lines BL are connected by the longitudinally extending parts to form an integral structure.

[0080] In some embodiments of the present application, such as Figure 5B and Figure 6BAs shown, the shielding layer 20 between adjacent layer lines BL is connected to the shielding layer 20 between two adjacent bit lines on the same layer. For example, the shielding layer 20 between adjacent layer lines BL and the shielding layer 20 between two adjacent bit lines on the same layer may be of an integral structure.

[0081] When multiple shielding layers 20 are of an integral structure, a film layer can be deposited through a single film-forming process, and then multiple shielding layers 20 can be formed through a patterning process, simplifying the formation process of the multiple shielding layers 20.

[0082] In some embodiments of the present application, if the memory cells periodically distributed in the vertical direction in adjacent two columns share bit lines and the shielding layer is located between the bit lines of adjacent layers, the shielding layers of different layers can be connected through wires in through holes extending towards the substrate.

[0083] In some embodiments of the present application, as Figure 5B and Figure 6B shown, the memory cells in two adjacent columns on the same layer are respectively connected to different bit lines BL, that is, they do not share bit lines, and the bit lines BL of the two adjacent columns of memory cells are mirror-distributed and adjacent to each other. There is a trench 50 extending towards the substrate 10 between the two adjacent columns of memory cells. The trench 50 isolates the two adjacent columns of memory cells. The bit lines BL of the two adjacent columns of memory cells extend in the trench 50 along the second direction. A shielding layer 20 insulated from the bit line BL is provided in the trench 50. In some embodiments of the present application, as Figure 5B and Figure 6B shown, the semiconductor device may include at least two adjacent groups of bit lines BL distributed in different layers and stacked along a direction perpendicular to the substrate 10 (two adjacent groups of bit lines are shown in Figure 5B , and each group of bit lines BL includes 4 bit lines BL stacked along a direction perpendicular to the substrate 10), and each layer includes multiple bit lines (two bit lines are shown in each layer in Figure 5B );

[0084] As Figure 6B shown, multiple shielding layers 20 in one trench 50 are all connected together to form a shielding structure. The multiple shielding layers 20 forming the shielding structure may be of an integral structure; the shielding structure composed of multiple shielding layers includes a main body 21 and multiple extension parts 22 connected to the main body 21. The main body 21 is located between the adjacent bit lines BL from two columns of memory cells and extends along a direction perpendicular to the substrate 10. The extension parts 22 extend to between at least some adjacent two bit lines of different layers. The main body 21 and the multiple extension parts 22 connected to the main body 21 may form a shielding structure with a “rich” character-shaped cross-section (intercepted along the first direction and the direction perpendicular to the substrate).

[0085] In Figure 5Band Figure 6B In Figure 6B , the main body 21 with a shielding structure is provided between two adjacent bit lines BL in a direction perpendicular to the substrate 10. An extension 22 is provided between each two adjacent bit lines BL in the same layer, so that a shielding layer 20 is provided between any two adjacent bit lines BL. Moreover, each extension 22 and the main body 21 connected thereto are of an integral structure, which is beneficial to simplifying the formation process of the shielding layer 20.

[0086] In some embodiments of the present application, as Figure 5B and Figure 6B shown, the main body 21 of the shielding structure is a film layer extending in a direction perpendicular to the substrate 10, and the extension 22 is a film layer extending in a direction parallel to the substrate 10.

[0087] In some embodiments of the present application, as Figures 5A to 6B shown, the semiconductor device includes a plurality of memory cells distributed in different layers and stacked in a direction perpendicular to the substrate 10; the memory cell includes a transistor 30, and the transistor 30 includes a semiconductor layer 31, a gate electrode 32, and a gate insulating layer 33 located between the semiconductor layer 31 and the gate electrode 32; the semiconductor layer 31 extends in a direction perpendicular to the substrate 10 and at least partially surrounds the gate electrode 32; the channel region of the transistor 30 extends along a first direction parallel to the substrate 10, that is, the channel region of the transistor 30 is a horizontal channel; the source and drain of the transistor 30 are spaced apart horizontally on the outer sidewalls of the semiconductor layer 31;

[0088] The bit line BL extends along a second direction (Y direction) parallel to the substrate 10, and the first direction (X direction) intersects with the second direction.

[0089] The semiconductor layer 31 at least partially surrounds the gate electrode 32. Here, "surrounds" can be understood as partial surround or full surround. In some embodiments, the surround can be full surround, that is, at least the entire sidewall of the gate electrode 32 is surrounded by the semiconductor layer 31, and the cross-section of the surrounded semiconductor layer 31 is a closed ring shape, where the cross-section is a section parallel to the substrate 10. In some embodiments, the surround can be partial surround, that is, a part of the sidewall of the gate electrode 32 is surrounded by the semiconductor layer 31, and the cross-section after surround is not closed but presents a ring shape. For example, a ring with an opening or two independent semiconductor layers 31. For example, the opposite side surfaces of the gate electrode 32 are surrounded by the semiconductor layer 31, and at this time, the cross-section of the semiconductor layer 31 is a ring with two openings.

[0090] The horizontal channel is such that the carrier transmission direction in the channel is within the plane parallel to the substrate 10, but the carrier transmission direction is not restricted to be in one direction. In practical applications, the carrier transmission direction extends along one direction as a whole, but locally, it is related to the shape of the semiconductor layer 31. In other words, the horizontal channel does not mean that it must extend along one direction within the horizontal plane. It may extend in different directions. For example, when the semiconductor layer 31 is annular, the source contact region and the drain contact region on the annular semiconductor layer 31 are part of the annulus. At this time, the carriers extend along one direction as a whole from the source contact region to the drain contact region, but may not be in one direction locally. Of course, the carrier transmission direction within the plane parallel to the substrate 10 is also a macroscopic concept and is not limited to being absolutely parallel to the substrate 10. This application protects the channel between the first electrode and the second electrode as a channel that is not perpendicular to the substrate 10.

[0091] In some embodiments of the present application, as Figures 5A to 6B shown, the semiconductor device further includes a word line WL, the word line WL extends in a direction perpendicular to the substrate 10, and penetrates through the memory cells of different layers; the semiconductor layer 31 at least partially surrounds the word line WL.

[0092] In some embodiments of the present application, as Figure 5A and Figure 5B shown, the memory cell includes a transistor 30, and the gate electrode 32 of the transistor 30 is connected to the word line WL.

[0093] In some embodiments of the present application, as Figure 6A and Figure 6B shown, the memory cell includes two transistors 30, namely a read transistor and a write transistor. The bit line BL includes a read bit line RBL and a write bit line WBL. The semiconductor layer of the read transistor is connected to the read bit line RBL, and the semiconductor layer of the write transistor is connected to the write bit line WBL;

[0094] There is a shielding layer 20 between two adjacent read bit lines RBL located in different layers.

[0095] In some embodiments of the present application, the word line WL includes a read word line RWL and a write word line WWL;

[0096] The read word line RWL is connected to the gate electrode 32 of the read transistor, and the semiconductor layer 31 of the read transistor at least partially surrounds the read word line RWL;

[0097] The write word line WWL is connected to the gate electrode 32 of the write transistor, and the semiconductor layer 31 of the write transistor at least partially surrounds the write word line WWL.

[0098] In some embodiments of the present application, as Figure 5B andFigure 6B As shown, the semiconductor layers 31 of the transistors 30 of the memory cells in at least some adjacent layers are spaced apart in a direction perpendicular to the substrate 10.

[0099] In some embodiments of the present application, as Figure 5B and Figure 6B shown, the semiconductor layers 31 of the transistors 30 of the memory cells in different layers are spaced apart in a direction perpendicular to the substrate 10, that is, the semiconductor layers 31 of the transistors of the memory cells in all adjacent layers are spaced apart in a direction perpendicular to the substrate 10, thereby eliminating parasitic MOS between all adjacent layers and improving device stability.

[0100] In some embodiments of the present application, as Figure 5B shown, the semiconductor layer 31 can extend on the sidewalls of the gate electrode 32 to form an annular semiconductor layer extending in a direction perpendicular to the substrate 10, including the overall extension of the semiconductor layer 31 in the direction towards the substrate 10. In some embodiments, the cross-sectional shape and size of the semiconductor layer 31 can be the same. In some embodiments, both ends of the semiconductor layer in the direction perpendicular to the substrate can extend towards the gate or away from the gate, forming an annular curved surface.

[0101] In some embodiments of the present application, as Figure 5B shown, the gate electrode 32 of the transistor 30 is a part of the word line WL, and the word line WL includes the gate electrode 32 and a word line body 34 extending in a direction perpendicular to the substrate 10;

[0102] The orthographic projection of the word line body 34 on the substrate 10 falls within the range of the orthographic projection of the gate electrode 32 on the substrate 10.

[0103] In other embodiments, the orthographic projection of the gate electrode 32 on the substrate 10 can fall within the range of the orthographic projection of the word line body 34 on the substrate 10, or the two exactly overlap.

[0104] In some embodiments of the present application, as Figure 5B shown, the gate insulating layers 33 of the transistors of a column of memory cells stacked in a direction perpendicular to the substrate 10 can be of an integral structure.

[0105] In some embodiments of the present application, as Figure 5A and Figure 5B shown, the transistor 30 can include a first electrode 35 and a second electrode 36. The first electrode 35 is connected to the bit line BL or is of an integral structure.

[0106] In some embodiments of the present application, as Figure 5A and Figure 5BAs shown, the storage unit may further include a capacitor 40, which includes a first capacitive electrode 41, a second capacitive electrode 42, and a dielectric layer 43 located between the first capacitive electrode 41 and the second capacitive electrode 42. The first capacitive electrode 41 is connected to the second electrode 36 of the transistor in the same storage unit or is an integral structure.

[0107] In the present application, the semiconductor layer can be understood as a semiconductor material, where its shape and structure are not emphasized, only its function is emphasized.

[0108] Exemplarily, the material of the semiconductor layer can be silicon, polysilicon, etc. with a bandgap less than 1.65 eV, or it can also be a wide-bandgap material, such as a metal oxide material with a bandgap greater than 1.65 eV.

[0109] For example, the material of the metal oxide semiconductor layer or the channel may include metal oxides of at least one of the following metals: indium, gallium, zinc, tin, tungsten, magnesium, zirconium, aluminum, hafnium, etc. Of course, compounds containing other elements are not excluded in the metal oxide, such as elements N, Si, etc.; and the inclusion of other minor doping elements is not excluded either.

[0110] In some embodiments, the material of the metal oxide semiconductor layer or the channel may include any one or more of the following: indium gallium zinc oxide (InGaZnO), indium zinc oxide (InZnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), indium gallium tin oxide (InGaSnO), indium gallium zinc tin oxide (InGaZnSnO), indium oxide (InO), tin oxide (SnO), zinc tin oxide (ZnSnO, ZTO), indium aluminum zinc gold oxide (InAlZnO), zinc oxide (ZnO), indium gallium silicon oxide (InGaSiO), indium tungsten oxide (InWO, IWO), titanium oxide (TiO), zinc oxide nitride (ZnON), magnesium zinc oxide (MgZnO), zirconium indium zinc oxide (ZrInZnO), hafnium indium zinc oxide (HfInZnO), tin indium zinc oxide (SnInZnO), aluminum tin indium zinc oxide (AlSnInZnO), silicon indium zinc oxide (SiInZnO), aluminum zinc tin oxide (AlZnSnO), gallium zinc tin oxide (GaZnSnO), zirconium zinc tin oxide (ZrZnSnO), etc. As long as the leakage current of the transistor can meet the requirements, it can be specifically adjusted according to the actual situation.

[0111] These materials have a wide bandgap and low leakage current. For example, when the metal oxide material is IGZO, the leakage current of the transistor is less than or equal to 10 -15 A to 10 -18 A, thereby improving the operating performance of the dynamic memory.

[0112] The material of the above metal oxide semiconductor layer or channel only emphasizes the elemental type of the material, and does not emphasize the atomic ratio in the material and the film quality of the material.

[0113] Exemplarily, the material of the bit line can be selected from any one or more of other metal materials with similar properties such as tungsten, molybdenum, cobalt, etc. The bit line can be a single-layer or multi-layer structure. For example, it can be a multi-layer structure formed by titanium (Ti), titanium nitride (TiN), and tungsten (W).

[0114] In some embodiments of the present application, the electrode material of the gate electrode can be any one or more of the following different types of materials:

[0115] For example, metals such as tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, cobalt, etc.; it can be a metal alloy containing the aforementioned metals;

[0116] It can also be metal oxides, metal nitrides, metal silicides, metal carbides, etc., such as indium tin oxide ITO, indium zinc oxide IZO, indium oxide InO and other metal oxide materials with relatively high conductivity; for example, metal nitride materials such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN), etc.;

[0117] Of course, it can also be polysilicon material; it can also be a conductive material doped with a semiconductor material, for example, silicon after conductive doping, germanium after conductive doping, silicon-germanium after conductive doping, etc.; other materials showing conductivity, etc.

[0118] In some embodiments of the present application, the material of the gate insulating layer can include one or more layers of Low-K and / or High-K dielectric materials, or include two or more regions with different dielectric constants K. The characteristics of the gate insulating layer of the present application will be exemplarily described below.

[0119] Low-K material, such as silicon oxide.

[0120] High-K material, such as a dielectric material with a dielectric constant K≥3.9. In some embodiments, it can include one or more oxides of hafnium, aluminum, lanthanum, zirconium, etc. Exemplarily, it can include, but is not limited to, at least one of the following: hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), zirconium oxide (ZrO2) and other high-K materials.

[0121] In some embodiments of the present application, the semiconductor device can be a 3D memory, for example, a memory such as 3D DRAM, etc. The 3D memory can be a 1T1C, 2T1C structure, and can also be a 1T0C or 2T0C structure.

[0122] The embodiment of the present application further provides an electronic device, which includes the semiconductor device provided by the embodiment of the present application.

[0123] In some embodiments of the present application, the electronic device may be: a storage device, a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a mobile power supply, etc. The storage device may include the memory in a computer, etc., which is not limited herein.

[0124] Although the disclosed embodiments of the present application are as above, the described content is only an embodiment adopted for the convenience of understanding the present application, and is not used to limit the present application. Any person skilled in the art within the scope of the present application can make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed by the present application. However, the protection scope of the present application shall still be subject to the scope defined by the appended claims.

Claims

1. A semiconductor device, characterized in that: include: Multi-layer memory cell array, stacked in a direction perpendicular to the substrate; Multi-layer bit line, each bit line layer contains multiple bit lines; Adjacent bit lines are insulated by an insulating layer; Multiple shielding layers, each shielding layer is located at least between adjacent layers of memory cell arrays; The shielding layer is at least located between the bit lines of adjacent layers; The shielding layer is configured to have a constant electric potential.

2. The semiconductor device according to claim 1, wherein The shielding layer is provided between any two adjacent bit lines located in different layers; and / or the shielding layer is provided between at least some of the adjacent bit lines located in the same layer.

3. The semiconductor device according to claim 2, wherein The shielding layer is located at least within the insulating layer between the bit lines of adjacent layers.

4. The semiconductor device according to claim 3, wherein The shielding layer is further located in the insulating layer between two adjacent bit lines in the same layer.

5. The semiconductor device according to claim 2, wherein The shielding layer extends along a first direction and a second direction, the bit line extends along the second direction, and the first direction and the second direction intersect and are both horizontal directions.

6. The semiconductor device according to claim 5, wherein The orthographic projection of the bit line on the substrate falls within the range of the orthographic projection of the shielding layer on the substrate.

7. The semiconductor device according to claim 5, wherein The shielding layers between the bit lines of adjacent layers are connected.

8. The semiconductor device according to claim 7, wherein: The shielding layer between the bit lines in adjacent layers is connected to the shielding layer between two adjacent bit lines on the same layer.

9. The semiconductor device according to claim 8, wherein Shielding layers of different layers are connected by wires in through holes extending toward the substrate; or, In the same layer of memory cell array, the two bit lines of each two adjacent columns of memory cells are adjacent, and there is a trench extending toward the substrate between the two adjacent bit lines. A shielding layer located between the two bit lines is provided in the trench, and the shielding layer is located between the two adjacent bit lines in each layer.

10. The semiconductor device according to any one of claims 1 to 9, wherein: The shielding layer is a conductive layer comprising metal.

11. The semiconductor device according to any one of claims 1 to 9, wherein: The memory cell in the memory cell array includes a transistor, wherein the transistor includes a semiconductor layer, a gate electrode, and a gate insulating layer located between the semiconductor layer and the gate electrode; The semiconductor layer extends in a direction toward the substrate and at least partially surrounds the gate electrode; the source and drain of the transistor are spaced apart and distributed in a horizontal direction on an outer sidewall of the semiconductor layer; The bit line extends in a horizontal direction and is connected to the drain.

12. The semiconductor device according to any one of claims 1 to 9, wherein: The memory cell includes a read transistor and a write transistor, the bit line includes a read bit line and a write bit line, the read transistor is connected to the read bit line, and the write transistor is connected to the write bit line; The shielding layer is located between two adjacent read bit lines located in different layers.

13. An electronic device, characterized in that: Comprising the semiconductor device according to any one of claims 1 to 12.

Images