Semiconductor memory device

Abstract

A semiconductor memory device includes: a substrate; the bit line extends on the substrate along a first direction; the first channel pattern is arranged on the bit line, and the first channel pattern is arranged on the bit line; a second channel pattern disposed on the bit line and spaced apart from the first channel pattern in the first direction; a first word line disposed between the first channel pattern and the second channel pattern and extending in a second direction; a second word line disposed between the first channel pattern and the second channel pattern, extending in the second direction, and spaced apart from the first word line in the first direction; and a first capacitor and a second capacitor, the first capacitor and the second capacitor being connected to the first channel pattern and the second channel pattern, respectively, on the first channel pattern and the second channel pattern.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor memory device. Background Art

[0002] In order to meet consumer demand for excellent performance and affordable prices, the integration density of semiconductor memory devices needs to be increased, especially because the integration density of semiconductor memory devices is a key factor determining product prices.

[0003] For two-dimensional (2D) or planar semiconductor memory devices, their integration density is mainly determined by the area occupied by each unit memory cell and is greatly affected by the level of fine pattern formation technology. However, since the miniaturization and refinement of patterns require very expensive equipment, the integration density of 2D semiconductor memory devices is improving but still limited. Therefore, a semiconductor memory device including a vertical channel transistor (VCT) with a channel extending in the vertical direction has been proposed. Summary of the Invention

[0004] In general, in some aspects, the present disclosure relates to a semiconductor memory device having increased integration density and improved electrical characteristics.

[0005] According to some implementations, the present disclosure relates to a semiconductor memory device, comprising: a substrate; a bit line extending in a first direction on the substrate; a first channel pattern disposed on the bit line; a second channel pattern disposed on the bit line and spaced apart from the first channel pattern in the first direction; a first word line disposed between the first and second channel patterns and extending in a second direction; a second word line disposed between the first and second channel patterns, extending in the second direction, and spaced apart from the first word line in the first direction; and a first capacitor and a second capacitor connected to the first and second channel patterns on the first and second channel patterns, respectively, wherein each of the first and second channel patterns includes a first metal oxide pattern containing indium (In), gallium (Ga), and tin (Sn), and in a composition distribution of the first metal oxide pattern, a position of an In peak is different from a position of a Ga peak, and the number of the In peaks is different from the number of the Ga peaks.

[0006] According to some implementations, the present disclosure relates to a semiconductor memory device, comprising: a substrate; a bit line extending along a first direction on the substrate; a protruding insulating pattern disposed on the bit line and including a channel trench extending in a second direction intersecting the first direction; a channel structure disposed on the bit line within the channel trench; a first word line disposed on the channel structure and extending in the second direction; a second word line disposed on the channel structure, extending in the second direction, and spaced apart from the first word line in the first direction; and a capacitor disposed on the channel structure and connected to the channel structure, wherein the channel structure includes a first metal oxide pattern having a plurality of oxide semiconductor regions, each of the plurality of oxide semiconductor regions including indium (In), gallium (Ga), and tin (Sn), each of the plurality of oxide semiconductor regions extending along sidewalls and a bottom surface of the channel trench, and each of the plurality of oxide semiconductor regions including a plurality of In peaks in a composition distribution of the first metal oxide pattern.

[0007] According to some implementations, the present disclosure relates to a semiconductor memory device, comprising: a substrate; a peripheral gate structure located on the substrate; a bit line disposed on the peripheral gate structure and extending in a first direction; a channel structure disposed on the bit line and comprising a horizontal portion and a first vertical portion and a second vertical portion protruding from the horizontal portion; a first word line disposed on the channel structure and extending in a second direction; a second word line disposed on the channel structure, extending in the second direction, and spaced apart from the first word line in the first direction; a gate a separation pattern, the gate separation pattern being arranged on the horizontal portion of the channel structure and separating the first word line and the second word line; a landing pad, the landing pad being arranged on the channel structure and connected to the channel structure; and a data storage pattern, the data storage pattern being arranged on the landing pad, wherein the channel structure includes a first metal oxide pattern containing indium (In), gallium (Ga) and tin (Sn), a ratio of Sn among the metal elements included in the first metal oxide pattern is 10at% to 30at%, and in the composition distribution of the first metal oxide pattern, a ratio of the number of In peaks to the number of Ga peaks is 2 or greater. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Example implementations will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0009] Figure 1 is a layout diagram illustrating an example of a semiconductor memory device according to some implementations.

[0010] Figure 2 It is based on some implementation along Figure 1 A cross-sectional view taken along lines AA and BB.

[0011] Figure 3 It is based on some implementation along Figure 1 A cross-sectional view taken along lines CC and DD.

[0012] Figure 4 According to some implementation methods Figure 2 An enlarged cross-sectional view of an example of a portion P.

[0013] Figure 5 According to some implementation methods Figure 4 FIG. 1 is an enlarged cross-sectional view of an example of a portion of a first metal oxide pattern.

[0014] Figure 6 FIG. 1 is a diagram showing a metal oxide pattern included in the first metal oxide pattern according to some implementations. Figure 5 A graph showing an example of the composition distribution of a “SCAN LINE”.

[0015] Figures 7 to 10 is a diagram illustrating an example of a semiconductor memory device according to some implementations.

[0016] Figure 11 and Figure 12 is a diagram illustrating an example of a semiconductor memory device according to some implementations.

[0017] Figures 13 to 16 is a diagram illustrating an example of a semiconductor memory device according to some implementations.

[0018] Figures 17 to 20 is a diagram illustrating an example of a semiconductor memory device according to some implementations.

[0019] Figure 21 is a flowchart illustrating an example of a method of manufacturing a semiconductor memory device according to some implementations.

[0020] Figure 22 is a flowchart illustrating an example of a method of manufacturing a semiconductor memory device according to some implementations.

[0021] Figure 23 is a diagram illustrating a method for forming a Figure 21 and Figure 22 Figure 2 shows an example timing diagram of each metal oxide film deposition cycle.

[0022] Figure 24 is a graph illustrating example compositions of thin films analyzed by X-ray fluorescence spectroscopy (XRF), according to some implementations.

[0023] Figure 25 is a graph illustrating example compositions of thin films analyzed by X-ray photoelectron spectroscopy (XPS), according to some implementations.

[0024] Figure 26 is a graph illustrating an example of XPS analysis results for metal oxide thin films according to some implementations.

[0025] Figure 27 is a graph illustrating an example of spectroscopic ellipsometry (SE) analysis results for metal oxide thin films according to some implementations.

[0026] Figure 28 and Figure 29 is a graph illustrating example results of an optical reliability evaluation for a transistor according to some implementations.

[0027] Figure 30 is a graph illustrating example electrical characteristic evaluation results for thin films according to some implementations.

[0028] Figure 31 is a graph illustrating example electrical characteristic evaluation results for a transistor according to some implementations. DETAILED DESCRIPTION

[0029] Hereinafter, example implementations will be described in detail with reference to the accompanying drawings. It should be understood that although the terms "first," "second," "third," etc. may be used herein to describe various elements, components, regions, layers, and / or sections, these elements, components, regions, layers, and / or sections should not be limited by these terms. These terms are used to distinguish one element, component, region, layer, or section from another element, component, region, layer, or section. Therefore, without departing from the spirit and scope of the present disclosure, the first element, component, region, layer, or section described below may be referred to as a second element, component, region, layer, or section.

[0030] The terms used herein are to describe some implementations and are not intended to limit the present disclosure. As used herein, unless the context clearly indicates otherwise, the singular forms "one" and "an" are also intended to include plural forms. It should be further understood that when the terms "comprise", "including", "comprising" and "comprising" are used in this specification, it is specified that there are stated features, integers, operations, elements and / or parts, but it is not excluded that there are or add one or more other features, integers, operations, elements, parts and / or a part thereof. As used herein, the term "and / or" includes any and all combinations of one or more of the relevant listed items. When a statement such as "at least one of ... " is before a list of elements, the entirety of the list of elements can be modified without modifying the individual elements of the list. When mentioning "C to D", unless otherwise specified, this refers to C (including C) to D (including D).

[0031] Figure 1 is a layout diagram illustrating an example of a semiconductor memory device according to some implementations. Figure 2 It is based on some implementation along Figure 1 A cross-sectional view taken along lines AA and BB. Figure 3 It is based on some implementation along Figure 1 A cross-sectional view taken along lines CC and DD. Figure 4 According to some implementation methods Figure 2 An enlarged cross-sectional view of an example of a portion P. Figure 5 According to some implementation methods Figure 4 FIG. 1 is an enlarged cross-sectional view of an example of a portion of a first metal oxide pattern. Figure 6 FIG. 1 is a diagram showing a metal oxide pattern included in the first metal oxide pattern according to some implementations. Figure 5 FIG. 1 is a graph showing an example of a composition distribution of a “scan line” of FIG. 1 . In some implementations, a semiconductor memory device may include a memory cell having a vertical channel transistor (VCT).

[0032] exist Figures 1 to 6 , the semiconductor memory device may include a peripheral gate structure PG, a bit line BL, word lines (WL1 and WL2), a channel structure AP_ST, a protruding insulating pattern 175, and a data storage pattern DSP. The substrate 100 may be a silicon substrate or may include other materials such as silicon germanium, indium antimonide, lead telluride compound, indium arsenide, indium phosphide, gallium arsenide, or aluminum antimonide, but the present disclosure is not limited thereto.

[0033] The peripheral gate structure PG may be provided on the substrate 100. The substrate 100 may include a cell array region and a peripheral circuit region. The peripheral gate structure PG may be provided across the cell array region and the peripheral circuit region. In other words, a portion of the peripheral gate structure PG may be provided in the cell array region of the substrate 100, and the remaining portion of the peripheral gate structure PG may be provided in the peripheral circuit region of the substrate 100.

[0034] The peripheral gate structure PG may be included in a sensing transistor, a transfer transistor, and a driving transistor. The types of transistors provided in the cell array region and the peripheral circuit region may vary depending on the design layout of the semiconductor memory device according to some implementations of the present disclosure.

[0035] The peripheral gate structure PG may include a peripheral gate insulating film 215, a peripheral lower conductive pattern 223, and a peripheral upper conductive pattern 225. The peripheral gate insulating film 215 may include a silicon oxide film, a silicon oxynitride film, a high-k insulating film having a larger dielectric constant than silicon oxide, or a combination thereof. The high-k insulating film may include, for example, at least one of a metal oxide, a metal oxynitride, a metal silicon oxide, and a metal silicon oxynitride, but the present disclosure is not limited thereto.

[0036] The peripheral lower conductive pattern 223 and the peripheral upper conductive pattern 225 may include a conductive material. For example, the peripheral lower conductive pattern 223 and the peripheral upper conductive pattern 225 may include at least one of a doped semiconductor material, a conductive metal nitride, a conductive metal silicon nitride, a metal carbon nitride, a conductive metal silicide, a conductive metal oxide, a two-dimensional (2D) material, a metal, and a metal alloy. The peripheral gate structure PG is illustrated as including a plurality of conductive patterns, but the present disclosure is not limited thereto.

[0037] In semiconductor memory devices, 2D materials can be metal materials and / or semiconductor materials. 2D materials can include 2D allotropes or compounds, such as at least one of graphene, molybdenum disulfide (MoS2), molybdenum diselenide (MoSe2), tungsten diselenide (WSe2), and tungsten disulfide (WS2), but the present disclosure is not limited thereto. That is, the foregoing examples of 2D materials are merely illustrative and not restrictive.

[0038] The first and second lower peripheral insulating films 227 and 228 are disposed on the substrate 100. The first and second lower peripheral insulating films 227 and 228 may be formed of an insulating material.

[0039] The second lower peripheral insulating film 228 is shown as contacting the sidewalls of the lower peripheral conductive pattern 223 and the sidewalls of the upper peripheral conductive pattern 225, but the disclosure is not limited thereto. The peripheral gate structure PG may include a peripheral gate spacer disposed on the sidewalls of the lower peripheral conductive pattern 223 and the sidewalls of the upper peripheral conductive pattern 225.

[0040] The first peripheral wiring line 241a and the peripheral contact plug 241b can be disposed within the first peripheral lower insulating film 227 and the second peripheral lower insulating film 228. The first peripheral wiring line 241a and the peripheral contact plug 241b are illustrated as belonging to different films, but the present disclosure is not limited thereto. In some implementations, the boundary between the first peripheral wiring line 241a and the peripheral contact plug 241b can be indistinct. The first peripheral wiring line 241a and the peripheral contact plug 241b can include a conductive material.

[0041] A first peripheral upper insulating film 261 and a second peripheral upper insulating film 262 may be provided on the first peripheral wiring line 241a and the peripheral contact plug 241b. The first peripheral upper insulating film 261 and the second peripheral upper insulating film 262 may be formed of an insulating material.

[0042] The second peripheral wiring line 243 and the peripheral via plug 242 may be provided on the first peripheral wiring line 241a. The peripheral via plug 242 may be provided in the first peripheral upper insulating film 261. The second peripheral wiring line 243 may be provided in the second peripheral upper insulating film 262.

[0043] The second peripheral wiring line 243 and the peripheral via plug 242 can be connected to the first peripheral wiring line 241a. The peripheral via plug 242 can connect the first peripheral wiring line 241a and the second peripheral wiring line 243. The second peripheral wiring line 243 and the peripheral via plug 242 may include a conductive material. The second peripheral wiring line 243 and the peripheral via plug 242 are illustrated as belonging to different films, but the present disclosure is not limited to this. In some implementations, the boundary between the second peripheral wiring line 243 and the peripheral via plug 242 may be unclear.

[0044] The third, fourth, and fifth peripheral upper insulating films 263, 264, and 265 may be sequentially disposed on the second peripheral wiring line 243. The third, fourth, and fifth peripheral upper insulating films 263, 264, and 265 may be formed of an insulating material.

[0045] The fourth outer insulating film 264 may be formed of an insulating material different from that of the third outer insulating film 263 and the fifth outer insulating film 265. For example, the fourth outer insulating film 264 may be formed of an oxide-based insulating material, while the third outer insulating film 263 and the fifth outer insulating film 265 may be formed of a nitride-based insulating material. However, the present disclosure is not limited thereto.

[0046] The cell connection plugs 244 may be disposed within the third peripheral upper insulating film 263, the fourth peripheral upper insulating film 264, and the fifth peripheral upper insulating film 265. The cell connection plugs 244 may be connected to the second peripheral wiring line 243. The cell connection plugs 244 may include a conductive material. In some implementations, the cell connection plugs 244 may be disposed within a single peripheral upper insulating film. That is, the third peripheral upper insulating film 263, the fourth peripheral upper insulating film 264, and the fifth peripheral upper insulating film 265 may be integrally formed as a single insulating film.

[0047] The bit line BL may be disposed on the peripheral gate structure PG. Specifically, the bit line BL may be disposed on the fifth peripheral upper insulating film 265. For example, the bit line BL may contact the fifth peripheral upper insulating film 265.

[0048] The bit lines BL may extend longitudinally in the second direction D2. Each pair of adjacent bit lines BL may be spaced apart from each other in the first direction D1. Each bit line BL includes a long sidewall extending in the second direction D2 and a short sidewall extending in the first direction D1.

[0049] Each bit line BL may extend from the cell array region to the peripheral circuit region, and an end portion of each bit line BL may be disposed on the peripheral circuit region of the substrate 100 .

[0050] The bit line BL may be disposed on the cell connection plug 244. The bit line BL may be connected to the cell connection plug 244. The bit line BL may include, for example, at least one of a doped semiconductor material, a conductive metal nitride, a conductive metal silicon nitride, a metal carbonitride, a conductive metal silicide, a conductive metal oxide, a 2D material, a metal, and a metal alloy. The bit line BL is illustrated as a single film, but the present disclosure is not limited thereto.

[0051] The cell lower insulating film 171 may be disposed on the fifth peripheral upper insulating film 265. The cell lower insulating film 171 is disposed between the bit lines BL spaced apart from each other in the first direction D1. The cell lower insulating film 171 may be formed of an insulating material.

[0052] A protruding insulating pattern 175 may be disposed on the bit line BL and the lower cell insulating film 171 . A lower cell etch stopper film 173 may be disposed between the protruding insulating pattern 175 and the lower cell insulating film 171 .

[0053] The protruding insulating pattern 175 and the lower cell etch stop film 173 may include an insulating material. The lower cell etch stop film 173 may include a material having an etching selectivity relative to the protruding insulating pattern 175. For example, the protruding insulating pattern 175 may be formed of an oxide-based insulating material containing silicon, but the present disclosure is not limited thereto. For example, the protruding insulating pattern 175 may include silicon oxide.

[0054] In some implementations, the lower cell etch stop film 173 may not be disposed between the protruding insulating pattern 175 and the lower cell insulating film 171. In some implementations, each protruding insulating pattern 175 may include a plurality of insulating layers stacked along the third direction D3. For example, each protruding insulating pattern 175 may include a silicon oxide film and a silicon nitride film stacked along the third direction D3.

[0055] The protruding insulating pattern 175 may include a plurality of channel trenches CH_T. The channel trenches CH_T may be elongated in the first direction D1. Each pair of adjacent channel trenches CH_T may be spaced apart from each other in the second direction D2.

[0056] The channel trench CH_T may intersect the bit lines BL. A single channel trench CH_T may expose a plurality of bit lines BL adjacent to each other in the first direction D1.

[0057] The bottom surface of the channel trench CH_T may be defined by the bit line BL and the lower cell insulating film 171. The sidewall of each channel trench CH_T may be defined by the protruding insulating pattern 175 and the lower cell etch stop film 173. At least a portion of the sidewall of each channel trench CH_T may be a sidewall 175SW of each protruding insulating pattern 175. If the lower cell etch stop film 173 is not provided, the sidewall of each channel trench CH_T may be defined by the protruding insulating pattern 175.

[0058] The channel structure AP_ST may be disposed on the bit line BL. A plurality of channel structures AP_ST may be connected to a single bit line BL. The plurality of channel structures AP_ST disposed on the single bit line BL are spaced apart from each other in the second direction D2.

[0059] The channel structure AP_ST may be disposed in a channel trench CH_T extending in the first direction D1. A plurality of channel structures AP_ST may be disposed in a single channel trench CH_T. The channel structures AP_ST disposed in the channel trench CH_T are spaced apart in the first direction D1.

[0060] For example, the channel structures AP_ST may be two-dimensionally arranged along a first direction D1 and a second direction D2 crossing each other.

[0061] The channel structure AP_ST may extend along sidewalls and a bottom surface of the channel trench CH_T. In a cross-sectional view taken along the second direction D2, the channel structure AP_ST may have a “U” shape.

[0062] The channel structure AP_ST may include a horizontal portion AP_STH, a first vertical portion AP_STV1, and a second vertical portion AP_STV2. The first vertical portion AP_STV1 and the second vertical portion AP_STV2 of the channel structure AP_ST may protrude from the horizontal portion AP_STH of the channel structure AP_ST in a third direction D3.

[0063] The horizontal portion AP_STH of the channel structure AP_ST may extend along the bottom surface of the channel trench CH_T. In a cross section taken along the second direction D2, the horizontal portion AP_STH of the channel structure AP_ST may extend along the upper surface of the bit line BL. The horizontal portion AP_STH of the channel structure AP_ST is connected to the bit line BL. For example, the horizontal portion AP_STH of the channel structure AP_ST may contact the upper surface of the bit line BL.

[0064] The first and second vertical portions AP_STV1 and AP_STV2 of the channel structure AP_ST may extend along sidewalls of the channel trench CH_T. In a cross section taken along the second direction D2, the first and second vertical portions AP_STV1 and AP_STV2 of the channel structure AP_ST may extend along sidewalls 175SW of the protruding insulating pattern 175.

[0065] The channel structure AP_ST may include a first channel pattern AP1, a second channel pattern AP2, and a connection channel pattern AP_CP. The connection channel pattern AP_CP connects the first channel pattern AP1 and the second channel pattern AP2. The first channel pattern AP1 and the second channel pattern AP2 are spaced apart from each other in the second direction D2.

[0066] The first channel pattern AP1, the second channel pattern AP2, and the connection channel pattern AP_CP may be disposed on the bit line BL. The first channel pattern AP1 and the second channel pattern AP2 are connected to the bit line BL. The first channel pattern AP1 and the second channel pattern AP2 may contact an upper surface of the bit line BL.

[0067] The first channel pattern AP1 may include a first vertical portion AP_STV1 of the channel structure AP_ST and a portion of the horizontal portion AP_STH of the channel structure AP_ST. A portion of the horizontal portion AP_STH of the channel structure AP_ST may be a horizontal portion of the first channel pattern AP1. The first vertical portion AP_STV1 of the channel structure AP_ST may be a vertical portion of the first channel pattern AP1.

[0068] The second channel pattern AP2 may include a second vertical portion AP_STV2 of the channel structure AP_ST and other portions of the horizontal portion AP_STH of the channel structure AP_ST. The other portions of the horizontal portion AP_STH of the channel structure AP_ST may be the horizontal portion of the second channel pattern AP2. The second vertical portion AP_STV2 of the channel structure AP_ST may be the vertical portion of the second channel pattern AP2.

[0069] The connection channel pattern AP_CP includes a portion of the horizontal portion AP_STH of the channel structure AP_ST.

[0070] The first channel pattern AP1, the second channel pattern AP2, and the connection channel pattern AP_CP can be distinguished from each other by a first word line WL1 and a second word line WL2 described below. Figure 4 In the embodiment, the first word line WL1 may include an inner sidewall facing the sidewall 175SW of the protruding insulating pattern 175 and an outer sidewall opposite to the inner sidewall in the second direction D2. The boundary between the first channel pattern AP1 and the connection channel pattern AP_CP may be an extension of the outer sidewall of the first word line WL1 extending in the third direction D3.

[0071] The channel structure AP_ST may include an oxide semiconductor material. For example, the channel structure AP_ST may include a first metal oxide pattern 110 disposed on the bit line BL.

[0072] The first metal oxide pattern 110 may extend along a bottom surface and sidewalls of the channel trench CH_T. The first metal oxide pattern 110 may contact the bit line BL.

[0073] The first metal oxide pattern 110 may include a metal oxide. The first metal oxide pattern 110 may include an oxide semiconductor material containing indium (In), gallium (Ga), and tin (Sn). For example, the first metal oxide pattern 110 may include indium tin gallium oxide (ITGO).

[0074] The first metal oxide pattern 110 may include a plurality of oxide semiconductor regions 110SR. The oxide semiconductor regions 110SR may extend along the bottom surface and sidewalls of the channel trench CH_T.

[0075] The oxide semiconductor region 110SR may include an oxide semiconductor material containing In, Ga, and Sn. The oxide semiconductor regions 110SR extending along the bottom surface and sidewalls of the channel trench CH_T may be stacked to form a first metal oxide pattern 110. Each first metal oxide pattern 110 is illustrated as being stacked with three oxide semiconductor regions 110SR, but the present disclosure is not limited thereto.

[0076] Figure 6 An example of composition distribution of the first metal oxide pattern 110 is shown. Figure 6 The composition distribution of the metal component in one oxide semiconductor region 110SR is shown.

[0077] exist Figure 6 In the embodiment, the position of the In peak In_PK may be different from the position of the Ga peak Ga_PK. In one oxide semiconductor region 110SR, the number of In peaks In_PK may be different from the number of Ga peaks Ga_PK. For example, the number of In peaks In_PK may be greater than the number of Ga peaks Ga_PK.

[0078] Multiple In peaks In_PK may appear within one oxide semiconductor region 110SR. One Ga peak Ga_PK may appear within one oxide semiconductor region 110SR. An Sn peak Sn_PK may appear between the In peaks In_PK. In some implementations, one oxide semiconductor region 110SR may include multiple In peaks In_PK and one Ga peak Ga_PK. In the composition distribution of the first metal oxide pattern 110, the ratio of the number of In peaks In_PK to the number of Ga peaks Ga_PK may be 2 or greater.

[0079] Since the number of In peaks In_PK and Ga peaks Ga_PK appearing in one oxide semiconductor region 110SR varies, the number of In peaks In_PK may be different from the number of Ga peaks Ga_PK in the composition distribution of the first metal oxide pattern 110. For example, the number of In peaks In_PK may be greater than the number of Ga peaks Ga_PK.

[0080] In other words, the first metal oxide pattern 110 may include an In-rich region In_RR and a Ga-rich region Ga_RR. Each oxide semiconductor region 110SR may include an In-rich region In_RR and a Ga-rich region Ga_RR. The In-rich region In_RR and the Ga-rich region Ga_RR may extend along the sidewalls and bottom surface of the channel trench CH_T.

[0081] Since the Sn peak Sn_PK may appear between the In peaks In_PK, the In-rich region In_RR includes Sn. A plurality of In peaks In_PK may appear in each In-rich region In_RR. Each In-rich region In_RR may include a plurality of In peaks In_PK.

[0082] For example, the Ga-rich region Ga_RR may be a region containing more Ga than In and Sn. The Ga-rich region Ga_RR may include a Ga peak Ga_PK.

[0083] For example, the content of Sn included in the first metal oxide pattern 110 may be less than the content of In included in the first metal oxide pattern 110. Alternatively, the content of In included in the first metal oxide pattern 110 may be greater than the sum of the contents of Sn and Ga included in the first metal oxide pattern 110.

[0084] The ratio of Sn to all metal elements included in the first metal oxide pattern 110 (ie, Sn / (In+Sn+Ga)) may be, for example, 10 (atomic percent, at%) to 30 at%. The ratio of Sn included in the first metal oxide pattern 110 will be described in further detail later.

[0085] The Sn peak Sn_PK is illustrated as being lower than the In peak In_PK and the Ga peak Ga_PK, but the present disclosure is not limited thereto.

[0086] In the semiconductor memory device, the first channel pattern AP1 , the second channel pattern AP2 , and the connection channel pattern AP_CP may include a first metal oxide pattern 110 .

[0087] When the first metal oxide pattern 110 is formed by, for example, a physical vapor deposition (PVD) method using a target material containing ITGO, In, Ga, and Sn can be uniformly distributed throughout the first metal oxide pattern 110. Furthermore, the composition ratio of In, Ga, and Sn included in the deposited ITGO film can be determined based on the ratio of In, Ga, and Sn contained in the target material. That is, in order to change the composition ratio of In, Ga, and Sb in the ITGO film, it is necessary to change the target material used in the PVD method.

[0088] In semiconductor memory devices, indium oxide, tin oxide, and gallium oxide can be formed by atomic layer deposition (ALD) to produce an ITGO film. In this case, the position of the In peak In_PK can be different from the position of the Ga peak Ga_PK. Alternatively, the Sn peak Sn_PK can be located between adjacent In peaks In_PK. By adjusting the number of deposition cycles used to form indium oxide, tin oxide, and gallium oxide, the composition ratio of In, Ga, and Sn in the deposited ITGO film can be easily controlled.

[0089] exist Figure 2 and Figure 3 , the memory cell including the channel structure AP_ST is disposed on the peripheral gate structure PG, but the present disclosure is not limited thereto. In some implementations, the memory cell including the channel structure AP_ST may be spaced apart from the peripheral gate structure PG in the horizontal direction (i.e., the first direction D1 and / or the second direction D2) rather than in the vertical direction (i.e., the third direction D3).

[0090] The first word line WL1 and the second word line WL2 may be disposed on the channel structure AP_ST. The first word line WL1 and the second word line WL2 may be disposed within the channel trench CH_T.

[0091] The first word line WL1 and the second word line WL2 may extend in the first direction D1. The first word line WL1 and the second word line WL2 may be alternately arranged along the second direction D2. The first word line WL1 is spaced apart from the second word line WL2 in the second direction D2.

[0092] The first word line WL1 and the second word line WL2 are spaced apart from the bit line BL in the third direction D3. The first word line WL1 and the second word line WL2 intersect the bit line BL.

[0093] The first and second word lines WL1 and WL2 may be disposed on the horizontal portion AP_STH of the channel structure AP_ST. The first and second word lines WL1 and WL2 are disposed between the first and second vertical portions AP_STV1 and AP_STV2 of the channel structure AP_ST.

[0094] A first word line WL1 is disposed on the first channel pattern AP1. A second word line WL2 is disposed on the second channel pattern AP2. The first word line WL1 and the second word line WL2 are disposed between the first channel pattern AP1 and the second channel pattern AP2. The first channel pattern AP1 is closer to the first word line WL1 than to the second word line WL2. The second channel pattern AP2 is closer to the second word line WL2 than to the first word line WL1.

[0095] The first word line WL1 and the second word line WL2 may have a width in the second direction D2. The width of the portion of the first word line WL1 overlapping with the channel structure AP_ST in the third direction D3 may be different from the width of the portion of the first word line WL that does not overlap with the channel structure AP_ST. Similarly, the width of the portion of the second word line WL2 overlapping with the channel structure AP_ST in the third direction D3 may be different from the width of the portion of the second word line WL2 that does not overlap with the channel structure AP_ST.

[0096] For example, each of the first word line WL1 and the second word line WL2 may include a first portion WLa and a second portion WLb. The width of the first portion WLa of the word line in the second direction D2 may be smaller than the width of the second portion WLb of the word line in the second direction D2. As an example, the first portion WLa of the word line may be disposed on the channel structure AP_ST. The first portion WLa of the word line may be disposed on the first channel pattern AP1 and the second channel pattern AP2.

[0097] Each of the first word line WL1 and the second word line WL2 may include first portions WLa and second portions WLb alternately arranged along the first direction D1. A channel structure AP_ST may be provided between pairs of second portions WLb of the word lines that are adjacent in the first direction D1. In each first word line WL1, each first channel pattern AP1 may be provided between pairs of second portions WLb of the first word line WL1 that are adjacent in the first direction D1. In each second word line WL2, each second channel pattern AP2 may be provided between pairs of second portions WLb of the second word line WL2 that are adjacent in the first direction D1.

[0098] The channel structure AP_ST is not disposed below the second portion WLb of the word line. The height of the first portion WLa of the word line may be less than the height of the second portion WLb of the word line. For example, the difference between the height of the first portion WLa of the word line and the height of the second portion WLb of the word line may be the same as the thickness of the channel structure AP_ST.

[0099] The first and second word lines WL1 and WL2 may include a conductive material, such as at least one of doped polysilicon, conductive metal nitride, conductive metal silicon nitride, metal carbonitride, conductive metal silicide, conductive metal oxide, 2D material, metal, and metal alloy.

[0100] Each of the first word line WL1 and the second word line WL2 may include an upper surface WL_US and a bottom surface opposite to each other in the third direction D3. The bottom surfaces of the first word line WL1 and the second word line WL2 face the bit line BL. For example, the upper surfaces WL_US of the first word line WL1 and the second word line WL2 may be flat.

[0101] With the upper surface of the bit line BL as a reference, the upper surface WL_US of the first word line WL1 and the second word line WL2 may be higher than the uppermost portion AP_UUS of the vertical portion (AP_STV1 and AP_STV2) of the channel structure AP_ST. The uppermost portions of the first channel pattern AP1 and the second channel pattern AP2 may be the uppermost portion AP_UUS of the vertical portion (AP_STV1 and AP_STV2) of the channel structure AP_ST. For example, the uppermost portion AP_UUS of the vertical portion (AP_STV1 and AP_STV2) of the channel structure AP_ST may include the first metal oxide pattern 110. A height H1 from the upper surface of the bit line BL to the uppermost portion AP_UUS of the vertical portion (AP_STV1 and AP_STV2) of the channel structure AP_ST may be less than a height H2 from the upper surface of the bit line BL to the upper surface WL_US of the first word line WL1 and the second word line WL1.

[0102] The gate insulating film GOX may be disposed between the first word line WL1 and the channel structure AP_ST and between the second word line WL2 and the channel structure AP_ST. The gate insulating film GOX may be disposed between the first word line WL1 and the first channel pattern AP1 and between the second word line WL2 and the second channel pattern AP2. The gate insulating film GOX may extend parallel to the first word line WL1 and the second word line WL2 along the first direction D1.

[0103] The gate insulating film GOX may extend along the first vertical portion AP_STV1 of the channel structure AP_ST. The gate insulating film GOX may extend along the second vertical portion AP_STV2 of the channel structure AP_ST. In the semiconductor memory device, the gate insulating film GOX may not be provided on the horizontal portion AP_STH of the channel structure AP_ST that does not overlap with the first word line WL1 and the second word line WL2 in the third direction D3. From a cross-sectional perspective, the portion of the gate insulating film GOX between the first word line WL1 and the channel structure AP_ST may be separated from the portion of the gate insulating film GOX between the second word line WL2 and the channel structure AP_ST.

[0104] The gate insulating film GOX may include silicon oxide, silicon oxynitride, a high-k insulating film having a larger dielectric constant than silicon oxide, or a combination thereof.

[0105] A portion of the gate insulating film GOX may protrude beyond the upper surfaces WL_US of the first and second word lines WL1 and WL2 in the third direction D3. A portion of the gate insulating film GOX may also protrude beyond the uppermost portion AP_UUS of the vertical portions (AP_STV1 and AP_STV2) of the channel structure AP_ST in the third direction D3.

[0106] A height H4 from the upper surface of the bit line BL to the uppermost portion GOX_UUS of the gate insulating film GOX may be greater than a height H1 from the upper surface of the bit line BL to the uppermost portion AP_UUS of the vertical portions (AP_STV1 and AP_STV2) of the channel structure AP_ST. The height H4 from the upper surface of the bit line BL to the uppermost portion GOX_UUS of the gate insulating film GOX may also be greater than a height H2 from the upper surface of the bit line BL to the upper surfaces WL_US of the word lines (WL1 and WL2).

[0107] The gate separation pattern GSS may be disposed on the bit line BL and the cell lower insulating film 171. The gate separation pattern GSS may be disposed within the channel trench CH_T. The gate separation pattern GSS may be disposed on the channel structure AP_ST, the first word line WL1, and the second word line WL2.

[0108] In the semiconductor memory device, the gate separation pattern GSS may contact the channel structure AP_ST. The gate separation pattern GSS may be disposed on the connection channel pattern AP_CP. The gate separation pattern GSS may contact the horizontal portion AP_STH of the channel structure AP_ST. The gate separation pattern GSS may be spaced apart from the bit line BL in the third direction D3.

[0109] Each gate separation pattern GSS may be disposed between a pair of adjacent first and second word lines WL1 and WL2 along the second direction D2. The first and second word lines WL1 and WL2 may be separated by the gate separation pattern GSS. The gate separation pattern GSS may extend along the first direction D1 between the first and second word lines WL1 and WL2.

[0110] The first word line WL1 may be disposed between the gate separation pattern GSS and the channel structure AP_ST. Similarly, the second word line WL2 may be disposed between the gate separation pattern GSS and the channel structure AP_ST. The first word line WL1 may be disposed between the gate separation pattern GSS and the first channel pattern AP1. The second word line WL2 may be disposed between the gate separation pattern GSS and the second channel pattern AP2.

[0111] The gate separation pattern GSS may include a horizontal portion and a protruding portion. The protruding portion of the gate separation pattern GSS may protrude from the horizontal portion of the gate separation pattern GSS toward the bit line BL along a third direction D3. The protruding portion of the gate separation pattern GSS may be closer to the bit line BL than the horizontal portion of the gate separation pattern GSS. The horizontal portion of the gate separation pattern GSS may be disposed on the upper surface WL_US of the first word line WL1 and the second word line WL2. In a cross-sectional view, the gate separation pattern GSS may have a "T" shape.

[0112] The gate separation pattern GSS may include a gate separation liner 151, a gate separation filling film 153, and a gate separation capping film 155. The gate separation liner 151 may extend along the upper surface WL_US and outer walls of the first and second word lines WL1 and WL2. The gate separation liner 151 may also extend along the horizontal portion AP_STH of the channel structure AP_ST. The gate separation liner 151 may contact the connection channel pattern AP_CP. The gate separation liner 151 may extend along a portion of the gate insulation film GOX that protrudes beyond the upper surface WL_US of the first and second word lines WL1 and WL2. The gate separation liner 151 may contact the sidewalls of the gate insulation film GOX. In some implementations, the gate separation liner 151 may not extend along the portion of the gate insulation film GOX that protrudes beyond the upper surface WL_US of the first and second word lines WL1 and WL2.

[0113] The gate separation filling film 153 may be disposed on the gate separation liner 151. The gate separation capping film 155 may be disposed on the gate separation filling film 153. The gate separation liner 151, the gate separation filling film 153, and the gate separation capping film 155 may be formed of an insulating material. In some implementations, the gate separation pattern GSS may be formed as a single film.

[0114] With the upper surface of the bit line BL as a reference, the upper surface GSS_US of the gate separation pattern GSS and the upper surface of the protruding insulating pattern 175 may be at the same height, but the present disclosure is not limited thereto.

[0115] A height H3 from the upper surface of the bit line BL to the upper surface GSS_US of the gate separation pattern GSS may be greater than a height H1 from the upper surface of the bit line BL to the uppermost portion AP_UUS of the vertical portions (AP_STV1 and AP_STV2) of the channel structure AP_ST. The height H3 from the upper surface of the bit line BL to the upper surface GSS_US of the gate separation pattern GSS may also be greater than a height H2 from the upper surface of the bit line BL to the upper surfaces WL_US of the word lines (WL1 and WL2).

[0116] A height H3 from the upper surface of the bit line BL to the upper surface GSS_US of the gate separation pattern GSS is illustrated as being the same as a height H4 from the upper surface of the bit line BL to the uppermost portion GOX_UUS of the gate insulation film GOX, but the present disclosure is not limited thereto.

[0117] The landing pad LP may be disposed on the channel structure AP_ST. The landing pad LP is connected to the first vertical portion AP_STV1 and the second vertical portion AP_STV2 of the channel structure AP_ST.

[0118] The landing pad LP may be disposed on the first and second channel patterns AP1 and AP2. The landing pad LP is connected to the first and second channel patterns AP1 and AP2.

[0119] From a planar perspective, the landing pad LP may have various shapes such as a circle, an ellipse, a rectangle, a square, a diamond, or a hexagon.

[0120] The landing pad LP may include a horizontal portion LP_H and a protruding portion LP_P. The horizontal portion LP_H of the landing pad LP may be disposed on the upper surface of the protruding insulating pattern 175 and the upper surface GSS_US of the gate separation pattern GSS. The protruding portion LP_P of the landing pad LP may protrude from the horizontal portion LP_H of the landing pad LP toward the bit line BL along the third direction D3.

[0121] With the upper surface of the bit line BL as a reference, the lowermost portion of the landing pad LP may be lower than the upper surface GSS_US of the gate separation pattern GSS. In other words, the protruding portion LP_P of the landing pad LP is disposed between the protruding insulating pattern 175 and the gate separation pattern GSS. The height from the upper surface of the bit line BL to the lowermost portion of the landing pad LP may be less than the height H4 from the upper surface of the bit line BL to the uppermost portion GOX_UUS of the gate insulation film GOX.

[0122] The pad separation insulating pattern 235 may be disposed between the landing pads LP. From a planar perspective, the landing pads LP may be arranged in a matrix along the first direction D1 and the second direction D2. The upper surface of the landing pads LP and the upper surface of the pad separation insulating pattern 235 may be located on the same plane, but the present disclosure is not limited thereto.

[0123] The landing pad LP includes a conductive material. For example, the landing pad LP may include at least one of doped polysilicon, a conductive metal nitride, a conductive metal silicon nitride, a metal carbonitride, a conductive metal silicide, a conductive metal oxide, a 2D material, a metal, and a metal alloy. The pad separation insulating pattern 235 may include a nitride-based insulating material containing silicon, such as silicon nitride, but the present disclosure is not limited thereto.

[0124] The cell top etch stop film 257 may be disposed on the landing pad LP and the pad separation insulating pattern 235. The cell top etch stop film 257 may extend along a portion of an upper surface of the landing pad LP and an upper surface of the pad separation insulating pattern 235.

[0125] The cell top etch stop film 257 may include, for example, a nitride-based insulating material containing silicon. The cell top etch stop film 257 may include, for example, at least one of silicon nitride (SiN), silicon carbonitride (SiCN), silicon boronitride (SiBN), and silicon oxynitride (SiON), but the present disclosure is not limited thereto.

[0126] Data storage patterns DSP may be respectively disposed on the landing pads LP. The data storage patterns DSP may be connected to the first and second vertical portions AP_STV1 and AP_STV2 of the channel structure AP_ST. The data storage patterns DSP may be respectively connected to the first and second channel patterns AP1 and AP2.

[0127] exist Figure 1 In the embodiment of the present invention, the data storage pattern DSP may be arranged in a matrix along the first direction D1 and the second direction D2. The data storage pattern DSP may completely or partially overlap the landing pad LP in the third direction D3. The data storage pattern DSP may contact the entire upper surface of the landing pad LP or a portion of the upper surface of the landing pad LP.

[0128] For example, the data storage pattern DSP may be a capacitor, the first channel pattern AP1 may be connected to the first capacitor, and the second channel pattern AP2 may be connected to the second capacitor.

[0129] The data storage pattern DSP may include a storage electrode 251, a plate electrode 255, and a capacitor dielectric film 253 interposed between the storage electrode 251 and the plate electrode 255. The plate electrode 255 is illustrated as a single film, but the present disclosure is not limited thereto.

[0130] For example, the storage electrode 251 may contact the landing pad LP. From a planar perspective, the storage electrode 251 may have various shapes, such as a circle, an ellipse, a rectangle, a square, a diamond, a hexagon, etc. The data storage pattern DSP may contact the entire upper surface of the landing pad LP or a portion of the upper surface of the landing pad LP. The storage electrode 251 may penetrate the cell top etch stop film 257.

[0131] The storage electrode 251 and the plate electrode 255 may include, for example, at least one of a conductive semiconductor material, a conductive metal nitride, a conductive metal silicon nitride, a metal carbonitride, a conductive metal silicide, a conductive metal oxide, and a metal. The capacitor dielectric film 253 may include at least one of a ferroelectric material, an antiferroelectric material, and a paraelectric material. For example, the capacitor dielectric film 253 may include: one of a ferroelectric material, an antiferroelectric material, and a paraelectric material; a combination of a ferroelectric material and an antiferroelectric material; a combination of a ferroelectric material and a paraelectric material; a combination of a paraelectric material and an antiferroelectric material; or a combination of a ferroelectric material, an antiferroelectric material, and a paraelectric material.

[0132] Conversely, the data storage pattern DSP may be a variable resistance pattern that can be switched between two resistance states by an electric pulse applied to the memory element. For example, the data storage pattern DSP may include a phase change material, a perovskite compound, a transition metal oxide, a magnetic material, a ferromagnetic material, or an antiferromagnetic material whose crystalline state changes with the amount of current.

[0133] Figures 7 to 10 is a diagram illustrating an example of a semiconductor memory device according to some implementations. Figure 11 and Figure 12 is a diagram showing an example of a semiconductor memory device according to some implementations. Figures 1 to 6 Describe the differences Figures 7 to 12 . Figure 12 According to some implementation methods Figure 11 An enlarged cross-sectional view of an example of a portion P.

[0134] exist Figure 7 and Figure 8In the embodiment, the upper surfaces WL_US of the first and second word lines WL1 and WL2 may include curved surfaces. The upper surfaces WL_US of the first and second word lines WL1 and WL2 may be convex.

[0135] exist Figure 8 In the embodiment, upper surfaces WL_US of the first and second word lines WL1 and WL2 may be concave.

[0136] exist Figure 9 In FIG. 4 , the gate separation pattern GSS does not contact the channel structure AP_ST.

[0137] A portion of the gate insulating film GOX may be disposed between the gate separation pattern GSS and the channel structure AP_ST. From a cross-sectional perspective, the portion of the gate insulating film GOX between the first word line WL1 and the channel structure AP_ST may be connected to the portion of the gate insulating film GOX between the second word line WL2 and the channel structure AP_ST.

[0138] exist Figure 10 In the embodiment, a portion of the gate separation pattern GSS may be recessed into the channel structure AP_ST. A thickness of the connection channel pattern AP_CP is smaller than a thickness of a horizontal portion AP_STH of the channel structure AP_ST included in the first and second channel patterns AP1 and AP2.

[0139] exist Figure 11 and Figure 12 In the embodiment, each channel structure AP_ST may further include a second metal oxide pattern 111. The second metal oxide pattern 111 may be disposed between the bit line BL and the first metal oxide pattern 110. The second metal oxide pattern 111 may extend along sidewalls and a bottom surface of the channel trench CH_T.

[0140] The second metal oxide pattern 111 may include an oxide semiconductor material. For example, the second metal oxide pattern 111 may include a metal oxide. The second metal oxide pattern 111 may include a metal oxide containing In and Sn. The second metal oxide pattern 111 may not include Ga. For example, the second metal oxide pattern 111 may include indium tin oxide (ITO).

[0141] Each of the first channel pattern AP1 , the second channel pattern AP2 , and the connection channel pattern AP_CP may include a first metal oxide pattern 110 and a second metal oxide pattern 111 .

[0142] The uppermost portion AP_UUS of the vertical portion (AP_STV1 and AP_STV2) of each channel structure AP_ST may include the uppermost portion 110_UUS of the first metal oxide pattern 110 and the uppermost portion 111_UUS of the second metal oxide pattern 111. The height from the upper surface of the bit line BL to the uppermost portion 110_UUS of the first metal oxide pattern 110 is the same as the height from the upper surface of the bit line BL to the uppermost portion 111_UUS of the second metal oxide pattern 111, but the present disclosure is not limited thereto.

[0143] On the contrary, for example, with the upper surface of the bit line BL as a reference, the uppermost portion 110_UUS of the first metal oxide pattern 110 may be lower than the uppermost portion 111_UUS of the second metal oxide pattern 111. In another example, with the upper surface of the bit line BL as a reference, the uppermost portion 110_UUS of the first metal oxide pattern 110 may be higher than the uppermost portion 111_UUS of the second metal oxide pattern 111.

[0144] Figures 13 to 16 is a diagram showing an example of a semiconductor memory device according to some implementations. Figures 1 to 6 Describe the differences Figures 13 to 16 .

[0145] Figure 13 is a layout diagram illustrating an example of a semiconductor memory device according to some implementations. Figure 14 It is along Figure 13 A cross-sectional view taken along lines AA and BB. Figure 15 It is along Figure 13 A cross-sectional view taken along lines CC and DD. Figure 16 yes Figure 14 An enlarged cross-sectional view of an example of a portion P.

[0146] exist Figures 13 to 16 In the embodiment, the first and second channel patterns AP1 and AP2 spaced apart from each other in the second direction D2 are not connected within the channel trench CH_T. Each of the first and second channel patterns AP1 and AP2 may include a first metal oxide pattern 110 .

[0147] The first channel pattern AP1 may include a horizontal portion AP1_H extending along an upper surface of the bit line BL and a vertical portion AP1_V extending along a sidewall 175SW of the protruding insulating pattern 175. The vertical portion AP1_V of the first channel pattern AP1 may protrude from the horizontal portion AP1_H in the third direction D3.

[0148] The second channel pattern AP2 may include a horizontal portion AP2_H extending along the upper surface of the bit line BL and a vertical portion AP2_V extending along the sidewall 175SW of the protruding insulating pattern 175. The vertical portion AP2_V of the second channel pattern AP2 may protrude from the horizontal portion AP2_H in the third direction D3.

[0149] The gate separation pattern GSS may contact the bit line BL. The horizontal portion AP2_H of the second channel pattern AP2 and the horizontal portion AP1_H of the first channel pattern AP1 may be spatially separated by the gate separation pattern GSS. The gate separation liner 151 may contact the bit line BL.

[0150] Figures 17 to 20 is a diagram showing an example of a semiconductor memory device according to some implementations. Figures 1 to 6 Describe the differences Figures 17 to 20 .

[0151] exist Figure 17 In the embodiment, the first and second channel patterns AP1 and AP2 may be alternately arranged in a diagonal direction with respect to the first and second directions D1 and D2. Here, the diagonal direction may be parallel to the upper surface of the substrate 100.

[0152] The channel structure AP_ST may be formed to be twisted in an oblique direction. From a plane perspective, the first channel pattern AP1, the second channel pattern AP2, and the connection channel pattern AP_CP may have a parallelogram shape or a rhombus shape.

[0153] exist Figure 18 In the embodiment, the landing pads LP and the data storage patterns DSP may be arranged in a zigzag or honeycomb pattern from a planar perspective.

[0154] exist Figure 19 In the embodiment of the present invention, the data storage patterns DSP may be staggered with respect to the landing pads LP from a planar perspective. The data storage patterns DSP may contact a portion of the landing pads LP.

[0155] exist Figure 20 In the embodiment of the present invention, the landing pads LP disposed on the first and second channel patterns AP1 and AP2 may have a semicircular or semi-elliptical shape from a planar perspective. From a planar perspective, the landing pads LP may be symmetrically arranged relative to each other.

[0156] Figure 21 is a flowchart illustrating an example of a method of manufacturing a semiconductor memory device according to some implementations. Figure 22 is a flowchart illustrating an example of a method of manufacturing a semiconductor memory device according to some implementations. Figure 23is a diagram illustrating a method for forming a Figure 21 and Figure 22 Figure 2 shows an example timing diagram of each metal oxide film deposition cycle.

[0157] exist Figure 21 In the present invention, the method of manufacturing a semiconductor memory device may include the following steps: forming a first metal oxide film (S10); forming a second metal oxide film (S20); forming another first metal oxide film (S30); and forming a third metal oxide film (S40).

[0158] The first metal oxide film, the second metal oxide film, and the third metal oxide film may include, for example, one of indium oxide, tin oxide, and gallium oxide. The first metal oxide film, the second metal oxide film, and the third metal oxide film may include different materials. For example, the first metal oxide film may include indium oxide. For example, the second metal oxide film may include tin oxide. For example, the third metal oxide film may include gallium oxide. The first metal oxide film, the second metal oxide film, and the third metal oxide film may be formed using an ALD method.

[0159] Initially, the steps of forming the first metal oxide film and the second metal oxide film (ie, steps S10 and S20) may be repeated N times. As a result, N first metal oxide films and N second metal oxide films may be alternately formed on the substrate ( Figure 2 100).

[0160] After that, a step of forming another first metal oxide film (step S30) may be performed. The additional first metal oxide film may be formed on the uppermost second metal oxide film. As a result, a total of (N+1) first metal oxide films and N second metal oxide films may be alternately stacked.

[0161] Thereafter, a step of forming a third metal oxide film (step S40) may be performed. The third metal oxide film may be formed on the first metal oxide film and the second metal oxide film that are alternately stacked.

[0162] In this way, an oxide semiconductor region ( Figure 5 By repeating the aforementioned process, a plurality of oxide semiconductor regions 110SR may be formed.

[0163] exist Figure 23 , a single deposition cycle for forming a metal oxide film is illustrated, wherein the single deposition cycle may include a metal precursor injection phase t1 , a first purge phase t2 , a metal oxidation phase t3 , and a second purge phase t4 .

[0164] In the metal precursor injection phase t1, a metal precursor may be provided in the reaction chamber. The metal precursor may contain metal atoms constituting the first metal oxide film, the second metal oxide film, or the third metal oxide film. For example, the metal precursor may include one of In, Sn, and Ga.

[0165] In the first purge phase t2, metal precursor that is not bonded to the target surface where the metal oxide film is to be deposited can be removed. Excess metal precursor can be released from the reaction chamber.

[0166] In the metal oxidation stage t3, oxygen is supplied to oxidize the metal precursor, thereby oxidizing the bonding metal on the target surface and forming a metal oxide film on the target surface. The oxygen used to oxidize the metal precursor can be provided by, for example, a plasma process.

[0167] In the second purge phase t4, any byproducts produced during the formation of the metal oxide film can be removed. Such byproducts can be released from the reaction chamber.

[0168] If the metal precursor is a Sn precursor, a single Sn deposition cycle can be completed through the aforementioned four stages.

[0169] exist Figure 23 After the deposition cycle is performed at least once, a Figure 21 For example, the step of forming the first metal oxide film (i.e., Figure 21 Step S10) may include at least one Figure 23 That is, in Figure 23 After the deposition cycle of φt is performed at least once, a first metal oxide film may be formed on the substrate 100 .

[0170] The step of forming a second metal oxide film (ie, Figure 21 Step S20) may include at least one Figure 23 Similarly, the step of forming the third metal oxide film (ie, Figure 23 Step S40) may include at least one Figure 23 sedimentation cycle.

[0171] exist Figure 21 After the method is implemented at least once, it can be obtained Figure 2 and Figure 3 Channel structure AP_ST.

[0172] exist Figure 22In the present invention, the method of manufacturing a semiconductor memory device may include the following steps: forming a first metal oxide film (S10_1); forming a second metal oxide film (S20_1); and forming a third metal oxide film (S40_1).

[0173] The step of forming the first metal oxide film (ie, step S10_1) may include at least one Figure 23 In step S10_1, by Figure 23 The deposition cycle is performed at least once, and a first metal oxide film can be formed on the substrate 100.

[0174] Thereafter, the step of forming the second metal oxide film (S20_1) can also include at least one Figure 23 In step S20_1, a second metal oxide film may be formed on the first metal oxide film by performing the deposition cycle at least once.

[0175] Thereafter, the step of forming the third metal oxide film (ie, step S40_1) may include at least one Figure 23 In step S40_1, by Figure 23 The deposition cycle is performed at least once to form a third metal oxide film on the second metal oxide film.

[0176] In passing Figure 21 Methods and Figure 23 In the ITGO film produced by the deposition cycle, an oxide semiconductor region ( Figure 5 "110SR") may include indium oxide films and tin oxide films stacked alternately.

[0177] On the contrary, through Figure 22 Methods and Figure 23 In the ITGO film produced by the deposition cycle, an oxide semiconductor region may include an indium oxide film, a tin oxide film, and a gallium oxide film stacked sequentially.

[0178] Experimental Example

[0179] Production example: Production of ITGO film

[0180] Using the ALD method, an oxide semiconductor film containing ITGO was produced. Specifically, as described above with reference to Figure 21 and Figure 23 As described, ITGO is fabricated by performing an ALD cycle for forming indium oxide, gallium oxide, and tin oxide.

[0181] Using the ALD method, examples 1, 2, 3, and 4 were produced. Specifically, example 1 was produced by forming Figure 21The illustrated example was fabricated by performing a single Sn deposition cycle during the formation of one oxide semiconductor region 110SR. Example 2 was fabricated by performing two Sn deposition cycles during the formation of one oxide semiconductor region 110SR. Example 3 was fabricated by performing three Sn deposition cycles during the formation of one oxide semiconductor region 110SR. Example 4 was fabricated by performing five Sn deposition cycles during the formation of one oxide semiconductor region 110SR.

[0182] Comparative Example: Preparation of Indium Gallium Oxide (IGO) Thin Film

[0183] An oxide semiconductor film containing IGO was produced using the ALD method. Specifically, a comparative example was produced using the ALD method. During the production of the comparative example, no Sn deposition cycle was performed.

[0184] Experimental Example 1: Composition Comparison of Metal Oxide Thin Films

[0185] The ratio of elements present in each of the metal oxide thin films according to Examples 1, 2, 3, and 4 and the comparative example was analyzed using Auger electron spectroscopy (AES), and the results are shown in the following Table 1. Table 1 shows the ratio of metal elements (excluding oxygen) present in each of the ITGO films according to Examples 1, 2, 3, and 4 and the comparative example.

[0186] [Table 1]

[0187]

[0188]

[0189] Referring to Table 1, when the Sn deposition cycle was not performed (i.e., in the case of the comparative example), the Sn content in the IGO film according to the comparative example was 0 at%. Additionally, when the Sn deposition cycle was performed once, twice, three times, and five times (i.e., in the cases of Examples 1, 2, 3, and 4), the Sn contents in the ITGO films according to Examples 1, 2, 3, and 4 were 6.18 at%, 12.8 at%, 27.12 at%, and 38.29 at%, respectively.

[0190] This indicates that during the manufacture of a metal oxide thin film using the ALD method, the content of Sn included in the metal oxide film can be precisely controlled by adjusting the number of Sn deposition cycles.

[0191] Experimental Example 2: Characteristic Evaluation of Devices Including Metal Oxide Thin Films

[0192] Transistors whose channel layers were the metal oxide thin films according to Examples 1, 2, 3, and 4 and the comparative example were manufactured, and their electrical characteristics were evaluated. The evaluation of the electrical characteristics was performed using the transistors, and the results are shown in Table 2 below.

[0193] [Table 2]

[0194]

[0195] Referring to Table 2, as the ratio of Sn deposition cycles increases, the hysteresis voltage (V hys ) did not change significantly. Additionally, compared to the other cases, when the Sn deposition cycle was performed twice, the mobility (μ FE ) features are better.

[0196] Furthermore, as the ratio of Sn deposition cycles increased, the subthreshold swing (SS) characteristics decreased and then improved. The SS characteristics of Examples 2 and 3 (in which Sn deposition cycles were performed two or three times) were improved to almost the ideal SS level of 60 mV / decade. In contrast, the SS characteristics of Example 4 (in which Sn deposition cycles were performed five times) deteriorated.

[0197] The SS characteristics are close to the ideal SS level of the Sn contents of Examples 2 and 3. Therefore, it can be inferred that when the ratio of Sn included in ITGO is close to the ratio of Sn included in Example 2 or 3, the SS characteristics can reach the ideal SS level.

[0198] For example, when the ratio of Sn among the metal elements included in each metal oxide thin film (ie, Sn / (In+Sn+Ga)) is 10 at % to 30 at %, the semiconductor device can exhibit excellent SS characteristics.

[0199] At the same time, it was confirmed whether the characteristics of ITGO films would change depending on their deposition methods. Since the electrical characteristics of Example 2 (in which Sn deposition cycles were performed twice) were excellent, Example 2 was used to evaluate the characteristics of ITGO films based on their deposition methods.

[0200] Production Example: Preparation of ITGO Membrane According to Example 2

[0201] Use the reference above Figure 21 and Figure 23 The ITGO film according to Example 2 was produced by the method described above. That is, the ALD method was used to produce the film B.

[0202] Comparative example: ITGO film production

[0203] Use the reference above Figure 22 and Figure 23 The ITGO membrane was prepared by the method described above. Figure 22 and Figure 23 The method described was to make membrane A.

[0204] In forming one oxide semiconductor region ( Figure 5 During the formation of the oxide semiconductor region 110SR in film A), the same number of Sn deposition cycles, In deposition cycles, and Ga deposition cycles are performed for film A and film B. In other words, if nine In deposition cycles are performed during the formation of one oxide semiconductor region 110SR in film A, nine In deposition cycles are also performed during the formation of one oxide semiconductor region 110SR in film B.

[0205] Film A may have a structure in which indium oxide films, tin oxide films, and gallium oxide films are alternately stacked. Film B may have a structure in which indium oxide films and gallium oxide films are alternately stacked. The indium oxide film in film B may be an indium oxide film uniformly doped with Sn.

[0206] Experimental Example 3: Composition Comparison of Metal Oxide Thin Films

[0207] Figure 24 is a graph illustrating example compositions of thin films analyzed by X-ray fluorescence spectroscopy (XRF), according to some implementations. Figure 25 is a graph illustrating example compositions of thin films analyzed by X-ray photoelectron spectroscopy (XPS), according to some implementations.

[0208] exist Figure 24 The results of XRF analysis showed that the overall composition of membrane A was almost the same as that of membrane B.

[0209] exist Figure 25 In the XPS, Al Kα X-rays (1.5 keV) as soft X-rays and Ag Lα X-rays (3.0 keV) as hard X-rays were used as sources. Figure 25 The results of measurements at an angle of 30 degrees are shown. The Sn / In intensity ratios extracted using hard X-rays were found to be similar for both Films A and B. However, the Sn / In intensity ratios extracted using soft X-rays, which are more sensitive to the surface, were found to be lower than those extracted using hard X-rays. This suggests that the Sn element may be located vertically deeper in Film B than in Film A. In other words, in Film B, Sn is uniformly doped within the indium oxide.

[0210] Through XRF and XPS, it was confirmed that the compositions of Film A and Film B deposited in different ways could be substantially the same.

[0211] Experimental Example 4: Defect Evaluation of Metal Oxide Thin Films

[0212] Film A and Film B were evaluated for defect characteristics.

[0213] The oxygen vacancy ratios (O def) and metal hydroxide (M-OH) ratio, and the results are shown in Table 3 and Figure 26 As presented.

[0214] [Table 3]

[0215] MO <![CDATA[O def ]]> M-OH Membrane A 69.9 24.0 6.1 Membrane B 76.0 17.6 6.4

[0216] Figure 26 is a graph showing an example of XPS analysis results for a metal oxide thin film according to Experimental Example 4 according to some implementations. Figure 26 And in Table 3, the oxygen deficiency ratio (O def ) is lower in film B than in film A. Additionally, the metal-oxygen ratio (MO) is higher in film B than in film A.

[0217] Spectroscopic ellipsometry (SE) analysis was performed to measure the defect ratios within Film A and Film B, and the results are shown in Tables 4 and 5. Figure 27 As presented.

[0218] [Table 4]

[0219] D1 state D2 status Membrane A 71.2 31.6 Membrane B 85.7 3.8

[0220] Figure 27 is a graph showing an example of SE analysis data for films A and B according to some implementations. The SE analysis data is divided into two sub-gap states, state D1 and state D2. State D1 may indicate carrier-related defects, and state D2 may indicate oxygen-related defects. Figure 27 , the ratio of state D1 is larger in film B than in film A. Conversely, the ratio of state D2 is smaller in film B than in film A. Therefore, it can be inferred that oxygen vacancies are reduced in film B compared to film A. In addition, film B exhibits an increased carrier concentration compared to film A.

[0221] Experimental Example 5: Evaluation of Characteristics of Devices Including Metal Oxide Thin Films

[0222] Transistors using film A and film B as channel layers were manufactured and their electrical characteristics were evaluated. Specifically, the electrical characteristics of the transistors were evaluated, and the results are shown in Table 5 below. The optical reliability of the transistors was also evaluated, and the results are shown in Table 5 below. Figures 28 to 31 As presented.

[0223] [Table 5]

[0224]

[0225] Figure 28 and Figure 29 is a graph illustrating example results of an optical reliability evaluation for a transistor according to Experimental Example 5, according to some implementations. Figure 30 is a graph illustrating example electrical characteristic evaluation results for Film A and Film B according to some implementations. Figure 31 is a graph illustrating example electrical characteristic evaluation results for a transistor according to Experimental Example 5 according to some implementations.

[0226] Referring to Table 5, the mobility of membrane B (μ FE ) is higher than the mobility of film A. In addition, the SS of film B is closer to the ideal SS level than that of film A. This suggests that the deposition method of the ITGO film does not significantly affect the hysteresis voltage (V hys ).

[0227] Figure 28 1 shows example results of a negative bias light illumination stress (NBIS) test. The NBIS test was performed by applying an electric field of -2 MV / cm to the transistors according to Experimental Example 5 while irradiating them with 1000 lux of light. Figure 28 , membrane B showed a 61% improvement over membrane A.

[0228] Figure 29 1 shows an example result of a positive bias temperature stress (PBTS) test. The PBTS test was performed by applying an electric field of +2 MV / cm to the transistor according to Experimental Example 5 while maintaining a temperature of 95°C. Figure 29 , membrane B showed a 71% improvement over membrane A.

[0229] The optical reliability can be correlated with the oxygen defect ratio (O def ) are closely related. Figure 26 and Figure 27 As shown in Tables 3 and 4, compared to Membrane A, Membrane B exhibited suppressed oxygen defects.

[0230] Figure 30 shows that film B has improved Hall mobility and carrier concentration and reduced resistance compared to film A, and Figure 31 The threshold voltage (V) of the transistor made using film B is shown compared to the transistor made using film A. th ) can be improved.

[0231] Film A and Film B may have substantially the same thin film composition. Furthermore, both Film A and Film B may be formed using an ALD method. However, Film A and Film B may differ in how indium oxide and tin oxide are deposited therein.

[0232] In film A, indium oxide is deposited continuously, followed by tin oxide. In contrast, in film B, indium oxide and tin oxide are formed alternately. In other words, in film B, tin oxide can be formed as a doped film uniformly doped within the indium oxide. By forming tin oxide as a doping film within the indium oxide, Sn can be evenly distributed within the indium oxide film. The high electron affinity of Sn within the indium oxide film can suppress the formation of oxygen vacancies within the indium oxide. Reducing such oxygen vacancies can improve the performance and reliability of semiconductor memory devices. While this disclosure contains many specific implementation details, these should not be construed as limiting the scope of what may be claimed. Certain features described in this disclosure in the context of separate implementations can also be implemented in combination within a single implementation. Conversely, various features described in the context of a single implementation can also be implemented individually in multiple implementations or in any suitable subcombination. Furthermore, although features may be described above as functioning in certain combinations, in some cases, one or more features from a combination can be removed from that combination, and the combination can involve subcombinations or variations of subcombinations.

Claims

1. A semiconductor memory device, comprising: substrate; a bit line extending along a first direction on the substrate; a first channel pattern disposed on the bit line; a second channel pattern disposed on the bit line and spaced apart from the first channel pattern in the first direction; a first word line disposed between the first channel pattern and the second channel pattern and extending in a second direction; a second word line extending in the second direction, disposed between the first channel pattern and the second channel pattern, and spaced apart from the first word line in the first direction; as well as a first capacitor and a second capacitor, the first capacitor and the second capacitor being respectively disposed on and connected to the first channel pattern and the second channel pattern, wherein each of the first channel pattern and the second channel pattern includes a first metal oxide pattern containing indium, gallium, and tin, wherein, in the composition distribution of the first metal oxide pattern, the position of the indium peak is different from the position of the gallium peak, and In the composition distribution of the first metal oxide pattern, the number of the indium peaks is different from the number of the gallium peaks.

2. The semiconductor memory device according to claim 1, wherein The number of the indium peaks is greater than the number of the gallium peaks.

3. The semiconductor memory device according to claim 2, wherein A content of indium included in the first metal oxide pattern is greater than a sum of contents of tin and gallium included in the first metal oxide pattern.

4. The semiconductor memory device according to claim 1, in, The first word line includes first and second portions alternately arranged along the second direction, and The width of the first portion of the first word line in the first direction is smaller than the width of the second portion of the first word line in the first direction.

5. The semiconductor memory device according to claim 4, in, The first channel pattern is closer to the first word line than the second word line, and The first channel pattern is disposed between the second portions of the first word line adjacent to each other in the second direction.

6. The semiconductor memory device according to claim 1, further comprising: a gate insulating film provided between the first channel pattern and the first word line, Here, a height from an upper surface of the bit line to an uppermost portion of the gate insulating film is greater than a height from the upper surface of the bit line to an uppermost portion of the first channel pattern.

7. The semiconductor memory device according to claim 1, in, Each of the first channel pattern and the second channel pattern further includes a second metal oxide pattern disposed between the first metal oxide pattern and the bit line, wherein the second metal oxide pattern comprises indium and tin, and Wherein, the second metal oxide pattern does not include gallium.

8. The semiconductor memory device according to claim 1, further comprising: a gate separation pattern disposed on the bit line and separating the first word line from the second word line, wherein the first channel pattern and the second channel pattern are connected by a connecting channel pattern, and Wherein, the gate separation pattern is arranged on the connection channel pattern.

9. The semiconductor memory device according to claim 1, further comprising: a gate separation pattern disposed on the bit line and separating the first word line from the second word line, The gate separation pattern contacts the bit line.

10. The semiconductor memory device according to claim 1, further comprising: a protruding insulating pattern disposed on the bit line; The first channel pattern includes a vertical portion extending along a sidewall of the protruding insulating pattern and a horizontal portion extending along an upper surface of the bit line.

11. A semiconductor memory device, comprising: substrate; a bit line extending along a first direction on the substrate; a protruding insulating pattern disposed on the bit line and including a channel trench extending in a second direction intersecting the first direction; a channel structure disposed on the bit line within the channel trench; a first word line disposed on the channel structure and extending in the second direction; a second word line disposed on the channel structure, extending in the second direction, and spaced apart from the first word line in the first direction; as well as a capacitor disposed on and connected to the channel structure, The channel structure includes a first metal oxide pattern having a plurality of oxide semiconductor regions. wherein the plurality of oxide semiconductor regions each include indium, gallium, and tin, wherein the plurality of oxide semiconductor regions extend along the sidewalls and bottom surface of the channel trench, and Wherein, in the composition distribution of the first metal oxide pattern, the plurality of oxide semiconductor regions each include a plurality of indium peaks.

12. The semiconductor memory device according to claim 11, in, The plurality of oxide semiconductor regions each include a gallium-rich region and an indium-rich region extending along the sidewalls and the bottom surface of the channel trench, and Wherein, the indium-rich region includes tin.

13. The semiconductor memory device according to claim 12, wherein The indium-rich region includes the plurality of indium peaks.

14. The semiconductor memory device according to claim 11, in, The channel structure further includes a second metal oxide pattern disposed between the first metal oxide pattern and the bit line, wherein the second metal oxide pattern comprises indium and tin, and Wherein, the second metal oxide pattern does not include gallium.

15. The semiconductor memory device according to claim 11, in, The first word line includes first and second portions alternately arranged along the second direction, wherein the width of the first portion of the first word line in the first direction is smaller than the width of the second portion of the first word line in the first direction, and The channel structure is provided between the second portions of the first word line that are adjacent to each other in the second direction.

16. The semiconductor memory device according to claim 11, further comprising: a gate insulating film, the gate insulating film being provided between the channel structure and the first word line, wherein the channel structure includes a horizontal portion extending along the bottom surface of the channel groove and a vertical portion protruding from the horizontal portion, and The height from the upper surface of the bit line to the uppermost portion of the gate insulating film is greater than the height from the upper surface of the bit line to the uppermost portion of the vertical portion of the channel structure.

17. A semiconductor memory device, comprising: substrate; a peripheral gate structure, the peripheral gate structure being located on the substrate; a bit line disposed on the peripheral gate structure and extending in a first direction; a channel structure disposed on the bit line and including a horizontal portion and first and second vertical portions protruding from the horizontal portion; a first word line disposed on the channel structure and extending in a second direction; a second word line disposed on the channel structure, extending in the second direction, and spaced apart from the first word line in the first direction; a gate separation pattern disposed on the horizontal portion of the channel structure and separating the first word line from the second word line; a landing pad disposed on and connected to the channel structure; and a data storage pattern, the data storage pattern being disposed on the landing pad, Wherein, the channel structure includes a first metal oxide pattern containing indium, gallium and tin, Wherein, the ratio of tin among the metal elements included in the first metal oxide pattern is 10at% to 30at%, and Here, in the composition distribution of the first metal oxide pattern, a ratio of the number of indium peaks to the number of gallium peaks is 2 or greater.

18. The semiconductor memory device according to claim 17, in, The channel structure further includes a second metal oxide pattern disposed between the first metal oxide pattern and the bit line, wherein the second metal oxide pattern comprises indium and tin, and Wherein, the second metal oxide pattern does not include gallium.

19. The semiconductor memory device according to claim 17, in, The first word line includes first and second portions alternately arranged along the second direction, wherein the width of the first portion of the first word line in the first direction is smaller than the width of the second portion of the first word line in the first direction, and The channel structure is provided between the second portions of the first word line that are adjacent to each other in the second direction.

20. The semiconductor memory device according to claim 17, further comprising: a gate insulating film, the gate insulating film being provided between the channel structure and the first word line, Here, a height from an upper surface of the bit line to an uppermost portion of the gate insulating film is greater than a height from the upper surface of the bit line to a lowermost portion of the landing pad.

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