Semiconductor memory device

Abstract

A semiconductor memory device is provided. The semiconductor memory device includes: a bit line extending in a first direction and on a substrate; an active pattern on the bit line; a word line on a first sidewall of the active pattern; and a data storage pattern on the active pattern, in which the word line includes a first line pattern including a plurality of crystals of a first conductive material, in which a direction in which a lattice of each of the plurality of crystals of the first conductive material extends is substantially the same as the second direction, and in which the first line pattern includes a plurality of first conductive material crystals. At least one of the first surface of the word line and the second surface of the word line includes at least one of the plurality of first conductive material crystals.

Description

[0001] This application claims priority from and all benefits arising from Korean Patent Application No. 10-2024-0017316 filed on February 5, 2024, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The present disclosure relates to a semiconductor memory device, and more particularly, to a semiconductor memory device including a vertical channel transistor (VCT). Background Art

[0003] There is a need to increase the integration level of semiconductor memory devices to meet the desired performance characteristics and low prices expected by consumers. In the case of semiconductor memory devices, increased integration level is particularly desirable because the integration level is a factor that determines the price of the product.

[0004] In the case of two-dimensional or planar semiconductor memory devices, their integration density is determined by the area occupied by a unit memory cell and is therefore greatly affected by the level of fine pattern formation technology. However, since expensive equipment can be used to miniaturize patterns, the integration density of two-dimensional semiconductor memory devices is increasing, but it is still limited. Therefore, semiconductor memory devices including vertical channel transistors whose channels extend in the vertical direction have been proposed. Summary of the Invention

[0005] Aspects of the present disclosure provide a semiconductor memory device having improved integration and electrical characteristics.

[0006] However, the various aspects of the present disclosure are not limited to the one described herein. The above and other aspects of the present disclosure will become more apparent to those skilled in the art by referring to the detailed description of the present disclosure given below.

[0007] According to some aspects of the present disclosure, a semiconductor memory device is provided, comprising: a bit line extending in a first direction and on a substrate; an active pattern on the bit line, wherein the active pattern includes a first sidewall and a second sidewall opposite to each other in the first direction, wherein the active pattern includes a first surface and a second surface opposite to each other in a second direction perpendicular to the first direction, and wherein the first surface of the active pattern is electrically connected to the bit line; a word line on the first sidewall of the active pattern and extending in a third direction intersecting the first direction; and a data storage pattern on the active pattern and electrically connected to the second surface of the active pattern, wherein the word line includes a first surface and a second surface opposite to each other in the second direction, wherein the word line includes a first line pattern, the first line pattern including a plurality of first conductive material crystals, wherein a direction in which a lattice of each of the plurality of first conductive material crystals extends is substantially the same as the second direction, and wherein at least one of the first surface of the word line and the second surface of the word line is defined by at least one of the plurality of first conductive material crystals.

[0008] According to some aspects of the present disclosure, a semiconductor memory device is provided, comprising: a bit line extending in a first direction and on a substrate; a first active pattern on the bit line; a second active pattern on the bit line and spaced apart from the first active pattern in the first direction; a first word line between the first active pattern and the second active pattern and extending in a second direction intersecting the first direction; a second word line between the first active pattern and the second active pattern, extending in a second direction, and spaced apart from the first word line in the first direction; a gate separation pattern on the bit line and comprising a horizontal portion and a protruding portion, wherein the horizontal portion of the gate separation pattern is between the first word line and the bit line, and between the second word line and the bit line, wherein the protrusion of the gate separation pattern is between the first word line and the second word line, and wherein the width of the horizontal portion of the gate separation pattern in the first direction is greater than the width of the protrusion of the gate separation pattern in the first direction; and a data storage pattern electrically connected to the first active pattern and the second active pattern, wherein the first word line includes a first plurality of conductive material crystals, and the second word line includes a second plurality of conductive material crystals, wherein the first plurality of conductive material crystals include first conductive material crystals, and wherein a height of the first conductive material crystals in a third direction perpendicular to the first direction and the second direction is equal to a height of the first word line in the third direction.

[0009] According to some aspects of the present disclosure, a semiconductor memory device is provided, comprising: a peripheral gate structure on a substrate; a bit line extending in a first direction and on the peripheral gate structure; a shielding conductive pattern on the peripheral gate structure and comprising: a plurality of shielding conductive line patterns extending in the first direction and adjacent to the bit line; a first word line on the bit line and the shielding conductive pattern and extending in a second direction intersecting the first direction; a second word line on the bit line and the shielding conductive pattern, extending in the second direction and spaced apart from the first word line in the first direction; a back gate electrode between the first word line and the second word line and extending in the second direction; a first active pattern on the bit line and between the first word line and the back gate electrode; a second active pattern on the bit line and between the first word line and the back gate electrode; and a data storage pattern electrically connected to the first active pattern and the second active pattern, wherein the first word line and the second word line each include a plurality of conductive material crystals, each of the plurality of conductive material crystals having a lattice extending in a direction substantially the same as a third direction, the third direction being perpendicular to the first direction and the second direction, wherein the first word line includes a first surface and a second surface opposite to each other in the third direction, wherein the second word line includes a first surface and a second surface opposite to each other in the third direction, wherein a first group of the plurality of conductive material crystals includes a first surface of the first word line and a second surface of the first word line, and wherein a second group of the plurality of conductive material crystals defines a first surface of the second word line and a second surface of the second word line. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a layout diagram for explaining a semiconductor memory device according to some embodiments.

[0011] Figure 2 It is along Figure 1 A cross-sectional view taken along lines AA and BB.

[0012] Figure 3 It is along Figure 1 Cross-sectional view taken along lines CC and DD.

[0013] Figure 4 and Figure 5 yes Figure 2 An enlarged view of a portion P of FIG.

[0014] Figure 6 is schematically shown by cutting in a first direction Figure 4 FIG. 1 is a diagram illustrating the shape of a crystal grain in a cross section taken along a word line.

[0015] Figure 7 is schematically shown by cutting in the second direction Figure 4 FIG. 1 is a diagram illustrating the shape of a crystal grain in a cross section taken along a word line.

[0016] Figure 8 、 Figure 9 、 Figure 10 and Figure 11 is a diagram for explaining a semiconductor memory device according to some embodiments.

[0017] Figure 12 and Figure 13 is a diagram for explaining a semiconductor memory device according to some embodiments.

[0018] Figure 14 and Figure 15 is a diagram for explaining a semiconductor memory device according to some embodiments.

[0019] Figure 16 、 Figure 17 、 Figure 18 and Figure 19 are diagrams for explaining semiconductor memory devices according to some embodiments.

[0020] Figure 20 、 Figure 21 、 Figure 22 、 Figure 23 、 Figure 24 、 Figure 25 、 Figure 26 、 Figure 27 、 Figure 28 、 Figure 29 、 Figure 30 、 Figure 31 、 Figure 32 、 Figure 33 、 Figure 34 、 Figure 35 、 Figure 36 、 Figure 37 、 Figure 38 、 Figure 39 、 Figure 40 、 Figure 41 、 Figure 42 、 Figure 43 、 Figure 44 、 Figure 45 、 Figure 46 、 Figure 47 、 Figure 48 、 Figure 49 、 Figure 50 、 Figure 51 、 Figure 52 and Figure 53 are diagrams for explaining a method for manufacturing a semiconductor memory device according to some embodiments. DETAILED DESCRIPTION

[0021] To clarify the present disclosure, portions not related to the description will be omitted, and identical elements or equivalents will be denoted by identical reference numerals throughout the specification. Furthermore, since the sizes and thicknesses of the components shown in the drawings are arbitrarily given for better understanding and ease of description, the present disclosure is not limited to the sizes and thicknesses shown. In the drawings, the thicknesses of layers, films, panels, regions, etc. are exaggerated for clarity. In the drawings, the thicknesses of some layers and regions are exaggerated for better understanding and ease of description.

[0022] It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it can be directly on the other element, or there can be intervening elements. In contrast, when an element is referred to as being "directly on" another element, there are no intervening elements. In addition, for ease of description, spatially relative terms (such as "below," "beneath," "below," "above," "on," etc.) may be used herein to describe the relationship between one element or feature and another as shown in the figures. It will be understood that, in addition to the orientation depicted in the figures, spatially relative terms are intended to encompass different orientations of the device in use or operation. For example, if the device in the figure is flipped, an element described as being "below" or "beneath" another element or feature will later be oriented as being "above" the other element or feature. Therefore, the term "below" can encompass both the "above" and "below" orientations. The device can be oriented differently (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein can be interpreted accordingly.

[0023] As used herein, unless the context clearly indicates otherwise, the singular is intended to include the plural as well. It will also be understood that when the terms "include" and / or "comprising" are used herein, they specify the presence of the recited features, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups thereof. The term "and / or" includes any and all combinations of one or more of the associated listed items. The term "connected" may be used herein to indicate a physical and / or electrical connection, and may indicate a direct or indirect physical and / or electrical connection.

[0024] Hereinafter, example embodiments will be explained in detail with reference to the accompanying drawings.

[0025] Figure 1 is a layout diagram for explaining a semiconductor memory device according to some embodiments. Figure 2 It is along Figure 1 A cross-sectional view taken along lines AA and BB. Figure 3 It is along Figure 1 Cross-sectional view taken along lines CC and DD. Figure 4 and Figure 5 yes Figure 2 An enlarged view of a portion P of FIG. Figure 6 is schematically shown by cutting in a first direction Figure 4 FIG. 1 is a diagram illustrating the shape of a crystal grain in a cross section taken along a word line. Figure 7 is schematically shown by cutting in the second direction Figure 4 FIG. 1 is a diagram illustrating the shape of a crystal grain in a cross section taken along a word line.

[0026] A semiconductor memory device according to an embodiment of the present disclosure may include a memory cell including a vertical channel transistor (VCT).

[0027] Reference Figures 1 to 7 , a semiconductor memory device according to some embodiments may include a bit line BL, word lines WL1 and WL2 , a back gate electrode BG, a shielding conductive pattern SL, active patterns AP1 and AP2 , and a data storage pattern DSP.

[0028] The substrate 100 may be a silicon substrate or may include other materials (eg, but not limited to, silicon germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide).

[0029] Although not shown, the substrate 100 may include a cell array region where a data storage pattern is provided, and a peripheral circuit region defined around the cell array region.

[0030] The bonding insulating film 263 may be provided on the substrate 100. The bonding insulating film 263 may be used to bond the wafers. As an example, the bonding insulating film 263 may include silicon carbonitride (SiCN). As another example, the bonding insulating film 263 may include silicon oxide (SiO2).

[0031] The shielding structures 171 , SL, and 175 may be disposed on the substrate 100 . For example, the shielding structures 171 , SL, and 175 may be disposed on the bonding insulation film 263 .

[0032] The shielding structures 171 , SL, and 175 may include a shielding conductive pattern SL and shielding insulating films 171 and 175 . For example, the shielding insulating films 171 and 175 may include a shielding insulating liner 171 and a shielding insulating capping film 175 .

[0033] The shielding conductive pattern SL may include a plurality of shielding conductive line patterns SLp. Each shielding conductive line pattern SLp may extend in the second direction D2. Each shielding conductive line pattern SLp may be adjacent to each other in the first direction D1. For example, the first direction D1 and the second direction D2 may be horizontal directions parallel to or parallel to the substrate 100.

[0034] Each shielding conductive line pattern SLp may extend from the cell array region to the peripheral circuit region. An end portion of the shielding conductive pattern SL may be disposed on the peripheral circuit region.

[0035] The shielding conductive pattern SL includes a conductive material. The shielding conductive pattern SL may include, for example, at least one of a conductive metal nitride, a conductive metal silicon nitride, a metal carbon nitride, a conductive metal silicide, a conductive metal oxide, a two-dimensional material, and a metal.

[0036] The shielding insulating cover film 175 may be disposed on the substrate 100. The shielding insulating cover film 175 may be disposed between the substrate 100 and the shielding conductive pattern SL.

[0037] The shielding insulating capping film 175 may be in contact with the shielding conductive pattern SL. In the semiconductor memory device according to some embodiments, the shielding insulating capping film 175 may be in contact with the shielding conductive line pattern SLp.

[0038] The shielding insulating capping film 175 may have a straight line shape extending along the shielding conductive line pattern SLp in the second direction D2. Unlike the illustrated example, the shielding insulating capping film 175 may have a flat plate shape. In other words, the shielding insulating capping film 175 may overlap the shielding conductive line pattern SLp and the bit line BL in the third direction D3. For example, the third direction D3 may be a vertical direction perpendicular to the substrate 100.

[0039] The shielding insulating liner 171 may be disposed on the shielding conductive pattern SL. The shielding insulating liner 171 may extend along the outline of the shielding conductive line pattern SLp.

[0040] The shielding insulating liner 171 may be disposed on the bit line BL and the substrate 100. Unlike the illustrated example, the shielding insulating liner 171 may not be disposed between the bit line BL and the bonding insulating film 263.

[0041] The shielding insulating liner 171 and the shielding insulating cover film 175 may each be made of an insulating material. When the shielding insulating liner 171 and the shielding insulating cover film 175 include the same material, the boundary between the shielding insulating liner 171 and the shielding insulating cover film 175 may not be distinguished.

[0042] Because the shielding structures 171 , SL, and 175 are disposed between the bit lines BL adjacent in the first direction D1 , coupling noise between the bit lines BL may be reduced.

[0043] The bit line BL may be provided on the substrate 100 . For example, the bit line BL may be provided on the bonding insulating film 263 .

[0044] The bit lines BL may extend long in the second direction D2. Adjacent bit lines BL may be spaced apart in the first direction D1. The bit lines BL include long sidewalls extending in the second direction D2 and short sidewalls extending in the first direction D1.

[0045] The bit line BL may be disposed adjacent to the shielding conductive pattern SL (e.g., the shielding conductive line pattern SLp). The bit line BL may be disposed adjacent to the shielding conductive line pattern SLp in the first direction D1. In other words, the shielding conductive line pattern SLp may extend in the second direction D2 along the long sidewalls of the bit line BL.

[0046] The bit line BL may be disposed between shielding conductive line patterns SLp adjacent to each other along the first direction D1. The bit line BL may be disposed on the shielding insulating pad 171. For example, the shielding insulating pad 171 may contact the bit line BL.

[0047] Although not shown, each bit line BL may extend from the cell array region to the peripheral circuit region, and an end portion of each bit line BL may be disposed on the peripheral circuit region.

[0048] The bit line BL may include an upper surface BL_US and a bottom surface BL_BS facing each other in the third direction D3. The upper surface BL_US of the bit line may face the first active pattern AP1 and the second active pattern AP2, which will be described below. In the semiconductor memory device according to some embodiments, the shielding conductive pattern SL may not be provided on the bottom surface BL_BS of the bit line.

[0049] Each bit line BL may include a semiconductor pattern 161, a metal pattern 163, and a bit line mask pattern 165 stacked in sequence. Unlike the illustrated example, as an example, the bit line BL may include one of the semiconductor pattern 161 and the metal pattern 163. As another example, the bit line BL may not include the bit line mask pattern 165.

[0050] The bit line BL may include a conductive bit line, a conductive material film within the bit line BL, and a semiconductor pattern 161 and a metal pattern 163 .

[0051] The semiconductor pattern 161 may include a conductive semiconductor material. For example, the conductive semiconductor material may be a semiconductor material doped with impurities. The semiconductor pattern 161 may include at least one of polysilicon, polycrystalline silicon germanium, polycrystalline germanium, amorphous silicon, amorphous silicon germanium, and amorphous germanium.

[0052] The metal pattern 163 may include a conductive material including a metal. For example, the metal pattern 163 may include at least one of a conductive metal nitride, a conductive metal silicon nitride, a metal carbonitride, a conductive metal silicide, a conductive metal oxide, a two-dimensional (2D) material, and a metal. In the semiconductor memory device according to some embodiments, the two-dimensional material may be a metal material and / or a semiconductor material. The 2D material may include a 2D allotrope or a 2D compound and may include, but is not limited to, at least one of graphene, molybdenum disulfide (MoS2), molybdenum diselenide (MoSe2), tungsten diselenide (WSe2), and tungsten disulfide (WS2). That is, since the 2D materials mentioned above are listed only as examples, the 2D materials that may be included in the semiconductor memory device of the present disclosure are not limited to the materials mentioned above.

[0053] The bit line mask pattern 165 may include an insulating material. The bit line mask pattern 165 may include, but is not limited to, silicon nitride or silicon oxynitride.

[0054] The first active pattern AP1 and the second active pattern AP2 may be disposed on each bit line BL. The first active pattern AP1 and the second active pattern AP2 may be alternately disposed along the second direction D2.

[0055] The first active patterns AP1 may be spaced apart from each other in the first direction D1. The first active patterns AP1 may be spaced apart at regular intervals. The second active patterns AP2 may be spaced apart from each other in the first direction D1. The second active patterns AP2 may be spaced apart at regular intervals. The first active pattern AP1 may be spaced apart from the second active pattern AP2 in the second direction D2. The first active pattern AP1 and the second active pattern AP2 may be arranged two-dimensionally along the first direction D1 and the second direction D2 that intersect each other.

[0056] For example, each of the first active pattern AP1 and the second active pattern AP2 may be formed of a single crystalline semiconductor material. As an example, each of the first active pattern AP1 and the second active pattern AP2 may be formed of single crystalline silicon.

[0057] The first active pattern AP1 and the second active pattern AP2 may each have a length in the first direction D1, a width in the second direction D2, and a height in the third direction D3. Each of the first active pattern AP1 and the second active pattern AP2 may have a substantially uniform width. That is, each of the first active pattern AP1 and the second active pattern AP2 may have substantially the same width on the first surface S1 and the second surface S2. In addition, the width of the first active pattern AP1 may be equal to the width of the second active pattern AP2.

[0058] The width of the first active pattern AP1 and the width of the second active pattern AP2 may be in a range from several nm to several tens of nm. For example, the width of the first active pattern AP1 and the width of the second active pattern AP2 may be, but is not limited to, 1 nm to 30 nm (e.g., 1 nm to 10 nm). The length of each of the first active pattern AP1 and the second active pattern AP2 may be greater than the line width of the bit line BL. In other words, the length of each of the first active pattern AP1 and the second active pattern AP2 may be greater than the width of the bit line BL in the first direction D1.

[0059] exist Figure 4 In the embodiment, each of the first active pattern AP1 and the second active pattern AP2 includes a first surface S1 and a second surface S2 facing each other in the third direction D3. For example, the first surface S1 of the first active pattern AP1 and the second active pattern AP2 may face the bit line BL. The second surface S2 of the first active pattern AP1 and the second active pattern AP2 may face the contact pattern BC.

[0060] The first surfaces S1 of the first active pattern AP1 and the second active pattern AP2 are connected to the bit line BL. For example, the first surfaces S1 of the first active pattern AP1 and the second active pattern AP2 may be connected to the semiconductor pattern 161 of the bit line BL. Unlike the illustrated example, when the semiconductor pattern 161 is omitted, the first surfaces S1 of the first active pattern AP1 and the second active pattern AP2 may be connected to the metal pattern 163. The second surfaces S2 of the first active pattern AP1 and the second active pattern AP2 may be connected to the contact pattern BC.

[0061] Each of the first and second active patterns AP1 and AP2 may include a first and second sidewalls SS1 and SS2 opposite to each other in the second direction D2. The second sidewall SS2 of the first active pattern AP1 may face the first sidewall SS1 of the second active pattern AP2.

[0062] A first sidewall SS1 of the first active pattern AP1 may be adjacent to the first word line WL1 , and a second sidewall SS2 of the second active pattern AP2 may be adjacent to the second word line WL2 .

[0063] Although not shown, as an example, each of the first active pattern AP1 and the second active pattern AP2 may include a first dopant region adjacent to the bit line BL and a second dopant region adjacent to the contact pattern BC. Each of the first active pattern AP1 and the second active pattern AP2 may include a channel region between the first dopant region and the second dopant region. The first dopant region and the second dopant region are regions doped with dopants in the first active pattern AP1 and the second active pattern AP2. Unlike the aforementioned example, each of the first active pattern AP1 and the second active pattern AP2 may not include at least one of the first dopant region and the second dopant region.

[0064] When the semiconductor memory device operates, the channel regions of the first and second active patterns AP1 and AP2 can be controlled by the first and second word lines WL1 and WL2 and the back gate electrode BG. Since the first and second active patterns AP1 and AP2 are made of a single crystalline semiconductor material, the leakage current characteristics of the semiconductor memory device can be improved.

[0065] The back gate electrodes BG may be disposed on the bit lines BL and the shielding conductive pattern SL. The back gate electrodes BG may be spaced apart from each other in the second direction D2. The back gate electrodes BG may be spaced apart at regular intervals. Each back gate electrode BG may extend in the first direction D1 across the bit lines BL.

[0066] Each back gate electrode BG may be disposed between a first active pattern AP1 and a second active pattern AP2 that are adjacent to each other along the second direction D2. That is, the first active pattern AP1 may be disposed on one side of each back gate electrode BG, and the second active pattern AP2 may be disposed on the other side of each back gate electrode BG. The height of the back gate electrode BG in the third direction D3 may be smaller than the heights of the first active pattern AP1 and the second active pattern AP2.

[0067] Each back gate electrode BG may be disposed between the second sidewall SS2 of the first active pattern AP1 and the first sidewall SS1 of the second active pattern AP2. Each back gate electrode BG may be disposed on the second sidewall SS2 of the first active pattern AP1 and the first sidewall SS1 of the second active pattern AP2.

[0068] The first active pattern AP1 may be disposed between the first word line WL1 and the back gate electrode BG. The second active pattern AP2 may be disposed between the second word line WL2 and the back gate electrode BG. A pair of the first word line WL1 and the second word line WL2 may be disposed between the back gate electrodes BG adjacent to each other along the second direction D2.

[0069] The back gate electrode BG may include a first surface BG_S1 and a second surface BG_S2 opposite to each other in the third direction D3 . The first surface BG_S1 of the back gate electrode is closer to the bit line BL than the second surface BG_S2 of the back gate electrode.

[0070] The first surface BG_S1 of the back gate electrode may face the bit line BL.

[0071] The back gate electrode BG includes a conductive material, and may include, for example, at least one of a conductive semiconductor material, a conductive metal nitride, a conductive metal silicon nitride, a metal carbonitride, a conductive metal silicide, a conductive metal oxide, a two-dimensional material, and a metal.

[0072] When the semiconductor memory device operates, a voltage is applied to the back gate electrode BG, and the threshold voltage of the vertical channel transistor can be adjusted. Since the threshold voltage of the vertical channel transistor is adjusted, the deterioration of the leakage current characteristic can be prevented.

[0073] The back gate capping pattern 111 may be disposed between the first active pattern AP1 and the second active pattern AP2 adjacent to each other along the second direction D2. The back gate capping pattern 111 may extend in the first direction D1 together with the back gate electrode BG. The back gate capping pattern 111 may be disposed on the second surface BG_S2 of the back gate electrode.

[0074] The back gate capping pattern 111 may be made of an insulating material. The back gate capping pattern 111 may include, for example but not limited to, a silicon oxide film, a silicon oxynitride film, or a silicon nitride film.

[0075] The back gate insulating pattern 113 may be disposed between the back gate electrode BG and the first active pattern AP1 and between the back gate electrode BG and the second active pattern AP2. The back gate insulating pattern 113 may be disposed between the back gate capping pattern 111 and the first active pattern AP1 and between the back gate capping pattern 111 and the second active pattern AP2.

[0076] The back gate insulating pattern 113 may be made of an insulating material, such as a silicon oxide film, a silicon oxynitride film, a high dielectric constant insulating film having a higher dielectric constant than the silicon oxide film, or a combination thereof.

[0077] The back gate capping pattern 115 may be disposed between the bit line BL and the back gate electrode BG. The back gate capping pattern 115 may be disposed between the first active pattern AP1 and the second active pattern AP2 adjacent to each other along the second direction D2. Figure 2 As shown in FIG, under the back gate capping pattern 115, the bit line BL may extend in the first direction D1 together with the back gate electrode BG. Under the back gate capping pattern 115, the bit line BL may be disposed to face the first surface BG_S1 of the back gate electrode. Figure 3 As shown in , the thickness of the back gate capping pattern 115 between the bit lines BL may be different from (eg, smaller than) the thickness of the back gate capping pattern 115 on the bit lines BL, but the present disclosure is not limited thereto.

[0078] The back gate capping pattern 115 may be made of an insulating material. The back gate capping pattern 115 may include, for example, but not limited to, at least one of a silicon oxide film, a silicon oxynitride film, and a silicon nitride film.

[0079] The first word line WL1 and the second word line WL2 may be disposed on the bit line BL and the shielding conductive pattern SL. Each of the first word line WL1 and the second word line WL2 may extend in the first direction D1. The first word line WL1 and the second word line WL2 may be alternately arranged in the second direction D2.

[0080] The first word line WL1 may be disposed on the first sidewall SS1 of the first active pattern AP1. The second word line WL2 may be disposed on the second sidewall SS2 of the second active pattern AP2. The first and second active patterns AP1 and AP2 may be disposed between the first and second word lines WL1 and WL2 adjacent to each other in the second direction D2.

[0081] The first word line WL1 and the second word line WL2 may be spaced apart from the bit line BL and the contact pattern BC in the third direction D3. The first word line WL1 and the second word line WL2 may be located between the bit line BL and the contact pattern BC.

[0082] Each of the first and second word lines WL1 and WL2 may have a width in the second direction D2 . The widths of the first and second word lines WL1 and WL2 on the bit lines BL may be different from the widths of the first and second word lines WL1 and WL2 on the shielding conductive patterns SL.

[0083] For example, each of the first word line WL1 and the second word line WL2 may include a first word line portion WLa and a second word line portion WLb. The width of the first word line portion WLa in the second direction D2 may be smaller than the width of the second word line portion WLb in the second direction D2. As an example, the first word line portion WLa may be disposed on the bit line BL. The second word line portion WLb may be disposed on the shielding conductive pattern SL. In some embodiments, each of the first word line WL1 and the second word line WL2 may include a first word line portion WLa and a second word line portion WLb spaced apart from each other in the first direction D1.

[0084] Each of the first word line WL1 and the second word line WL2 may include first word line portions WLa and second word line portions WLb alternately arranged along the first direction D1. In the first word line WL1, each first active pattern AP1 may be arranged between adjacent second word line portions WLb along the first direction D1. In the second word line WL2, each second active pattern AP2 may be arranged between adjacent second word line portions WLb along the first direction D1.

[0085] Unlike the illustrated example, the width of the first portion WLa of the word line in the second direction D2 may be equal to the width of the second portion WLb of the word line in the second direction D2.

[0086] exist Figure 4 , a width W11 of the first word line WL1 in the second direction D2 may be equal to a width W12 of the second word line WL2 in the second direction D2.

[0087] exist Figure 5 , a width W11 of the first word line WL1 in the second direction D2 may be different from a width W12 of the second word line WL2 in the second direction D2. As another example, a width W11 of the first word line WL1 in the second direction D2 may be greater than a width W12 of the second word line WL2 in the second direction D2.

[0088] The first and second word lines WL1 and WL2 may each include a first surface WL_S1 and a second surface WL_S2 facing each other in the third direction D3. The first surfaces WL_S1 and WL_S2 of the first and second word lines are closer to the bit line BL than the second surfaces WL_S2 of the first and second word lines. The first surfaces WL_S1 of the first and second word lines face the bit line BL.

[0089] The first word line WL1 will be explained as an example. As an example, the height of the first word line WL1 in the third direction D3 may be equal to the height of the back gate electrode BG in the third direction D3. As another example, the height of the first word line WL1 in the third direction D3 may be greater than the height of the back gate electrode BG in the third direction D3. As another example, the height of the first word line WL1 in the third direction D3 may be less than the height of the back gate electrode BG in the third direction D3.

[0090] Furthermore, as an example, the height of the first surface WL_S1 of the first word line may be equal to the height of the first surface BG_S1 of the back gate electrode based on the upper surface BL_US of the bit line. As another example, the first surface WL_S1 of the first word line may be higher than the first surface BG_S1 of the back gate electrode. As yet another example, the first surface WL_S1 of the first word line may be lower than the first surface BG_S1 of the back gate electrode.

[0091] In addition, as an example, the height of the second surface WL_S2 of the first word line can be equal to the height of the second surface BG_S2 of the back gate electrode based on the upper surface BL_US of the bit line. As another example, the second surface WL_S2 of the first word line can be higher than the second surface BG_S2 of the back gate electrode. As yet another example, the second surface WL_S2 of the first word line can be lower than the second surface BG_S2 of the back gate electrode.

[0092] The first surfaces WL_S1 of the first and second word lines WL1 and WL2 may be planar. Unlike the illustrated example, the first surfaces WL_S1 of the first and second word lines WL1 and WL2 may be concave. As another example, each of the first and second word lines WL1 and WL2 may have a spacer. In other words, the first surfaces WL_S1 of the first and second word lines WL1 and WL2 may be convex.

[0093] The second surfaces WL_S2 of the first word line WL1 and the second word line WL2 may be planes. Unlike the example shown, the second surfaces WL_S2 of the first word line WL1 and the second word line WL2 may have concave curved surfaces. Although the first surface BG_S1 and the second surface BG_S2 of the back gate electrode are shown as forming planes, embodiments are not limited thereto.

[0094] exist Figure 4 、 Figure 6 and Figure 7 In the embodiment, the first word line WL1 and the second word line WL2 may include a first word line pattern (or first line pattern) WL_M1 including a first conductive material. The first word line WL1 and the second word line WL2 may include a plurality of first conductive material crystals WL_MCX1. Each first conductive material crystal WL_MCX1 may be a grain of the first conductive material.

[0095] The crystal direction CX1_DR of each first conductive material crystal WL_MCX1 may be the third direction D3. In other words, the crystal direction CX1_DR of the first conductive material crystal WL_MCX1 may be a vertical direction perpendicular to the substrate 100. As used herein, "crystal direction" may refer to the direction in which a lattice comprising a plurality of atoms of a given conductive material crystal extends. Each first conductive material crystal WL_MCX1 may be oriented in the third direction D3. The first word line pattern WL_M1 includes a plurality of first conductive material crystals WL_MCX1 whose crystal directions CX1_DR are vertical.

[0096] For example, the first conductive material crystals WL_MCX1 included in the first word line pattern WL_M1 may be formed by a bottom-up growth method.

[0097] The first word line WL1 will be explained as an example. The description of the first word line WL1 can be applied to the second word line WL2.

[0098] At least one of the first surface WL_S1 of the first word line WL1 and the second surface WL_S2 of the first word line WL1 may be defined by the first word line pattern WL_M1. In other words, at least one of the first surface WL_S1 of the first word line WL1 and the second surface WL_S2 of the first word line WL1 may be defined by a plurality of first conductive material crystals WL_MCX1. That is, at least one of the first surface WL_S1 of the first word line WL1 and the second surface WL_S2 of the first word line WL1 may be formed by a collection of a plurality of first conductive material crystals WL_MCX1. In some embodiments, at least one of the first surface WL_S1 of the first word line WL1 and the second surface WL_S2 of the first word line WL1 may include at least one of the plurality of first conductive material crystals WL_MCX1.

[0099] In a semiconductor memory device according to some embodiments, a first surface WL_S1 and a second surface WL_S2 of a first word line WL1 may be defined by a first word line pattern WL_M1 and a plurality of first conductive material crystals WL_MCX1.

[0100] At least one of the plurality of first conductive material crystals WL_MCX1 may extend from the first surface WL_S1 of the first word line WL1 to the second surface WL_S2 of the first word line WL1. In other words, the height of at least one of the plurality of first conductive material crystals WL_MCX1 may be equivalent to the height H1 of the first word line WL1 in the third direction D3. In some embodiments, a first group of first conductive material crystals in the plurality of first conductive material crystals WL_MCX1 may define the first surface WL_S1 of the first word line WL1 and the second surface WL_S2 of the first word line WL1, and a second group of first conductive material crystals in the plurality of first conductive material crystals WL_MCX1 may define the first surface WL_S1 of the second word line WL2 and the second surface WL_S2 of the second word line WL2.

[0101] The plurality of first conductive material crystals WL_MCX1 may include first and second sub-conductive material crystals WL_MCX11 and WL_MCX12. Each of the first and second sub-conductive material crystals WL_MCX11 and WL_MCX12 may be a crystal grain of the first conductive material included in the first word line pattern WL_M1. The crystal directions CX1_DR of the first and second sub-conductive material crystals WL_MCX11 and WL_MCX12 may each be a third direction D3 (i.e., a vertical direction).

[0102] The first sub-conductive material crystal WL_MCX11 may extend from the first surface WL_S1 of the first word line WL1 to the second surface WL_S2 of the first word line WL1. A height GS_D11 of the first sub-conductive material crystal WL_MCX11 in the third direction D3 may be equal to a height H1 of the first word line WL1 in the third direction D3.

[0103] The height GS_D12 of the second sub-conductive material crystal WL_MCX12 in the third direction D3 is smaller than the height GS_D11 of the first sub-conductive material crystal WL_MCX11 in the third direction D3. The height GS_D12 of the second sub-conductive material crystal WL_MCX12 in the third direction D3 is smaller than the height H1 of the first word line WL1 in the third direction D3.

[0104] For example, the second sub-conductive material crystal WL_MCX12 may define a portion of the first surface WL_S1 of the first word line WL1. The second sub-conductive material crystal WL_MCX12 does not extend to the second surface WL_S2 of the first word line WL1. Unlike the example shown, the second sub-conductive material crystal WL_MCX12 may define a portion of the second surface WL_S2 of the first word line WL1.

[0105] The height GS_D11 of the first sub-conductive material crystal WL_MCX11 may be the grain size of the first sub-conductive material crystal WL_MCX11 in the third direction D3. The height GS_D12 of the second sub-conductive material crystal WL_MCX12 may be the grain size of the second sub-conductive material crystal WL_MCX12 in the third direction D3.

[0106] The first word line WL1 and the second word line WL2 may include a conductive material. For example, the first word line WL1 and the second word line WL2 may include at least one of a conductive metal nitride, a conductive metal silicon nitride, a metal carbonitride, a conductive metal oxide, and a metal. For example, the first word line pattern WL_M1 may include a selectively grown conductive material. The first word line pattern WL_M1 may include, for example, but not limited to, one of titanium nitride (TiN), titanium (Ti), tungsten (W), molybdenum (Mo), ruthenium (Ru), and cobalt (Co).

[0107] Because the first and second word lines WL1 and WL2 include a plurality of first conductive material crystals WL_MCX1 having a crystal orientation in the vertical direction D3, the grain size of the first conductive material crystals WL_MCX1 included in the first and second word lines WL1 and WL2 increases. When the grain size of the first conductive material crystals WL_MCX1 increases, the number of grain boundaries in the first and second word lines WL1 and WL2 can decrease. Electrons flowing through the first and second word lines WL1 and WL2 can scatter at the grain boundaries between the first conductive material crystals WL_MCX1. When the number of scatterings of electrons flowing through the first and second word lines WL1 and WL2 increases, the resistance of the first and second word lines WL1 and WL2 can increase.

[0108] However, since the first and second word lines WL1 and WL2 include a plurality of first conductive material crystals WL_MCX1 having a crystal orientation in the vertical direction D3, the number of scatterings of electrons flowing through the first and second word lines WL1 and WL2 can be reduced. In other words, the resistance of the first and second word lines WL1 and WL2 can be reduced. Therefore, the performance and reliability of the semiconductor memory device according to some embodiments of the present disclosure can be improved.

[0109] The gate insulating pattern GOX may be disposed between the first word line WL1 and the first active pattern AP1 and between the second word line WL2 and the second active pattern AP2. The gate insulating pattern GOX may extend in the first direction D1 together with the first word line WL1 and the second word line WL2.

[0110] The gate insulating pattern GOX may include a silicon oxide film, a silicon oxynitride film, a high dielectric constant insulating film having a higher dielectric constant than the silicon oxide film, or a combination thereof. The high dielectric constant insulating film may include, for example, but not limited to, at least one of a metal oxide, a metal oxynitride, a metal silicon oxide, and a metal silicon oxynitride.

[0111] The gate insulating pattern GOX may extend along the first sidewall SS1 of the first active pattern AP1 and may extend along the second sidewall SS2 of the second active pattern AP2. In the semiconductor memory device according to some embodiments, in a cross-sectional view, the gate insulating pattern GOX between the first active pattern AP1 and the first word line WL1 may be separated from the gate insulating pattern GOX between the second active pattern AP2 and the second word line WL2.

[0112] The gate capping pattern 143 may be disposed between the first word line WL1 and the contact pattern BC and between the second word line WL2 and the contact pattern BC. The gate capping pattern 143 may cover the second surfaces WL_S2 of the first and second word lines WL1 and WL2.

[0113] The gate separation pattern GSS may be disposed on the bit line BL. The gate separation pattern GSS may be disposed between the bit line BL and the contact pattern BC. The gate separation pattern GSS may contact an upper surface BL_US of the bit line.

[0114] The gate separation pattern GSS may be disposed between the first word line WL1 and the second word line WL2 adjacent to each other along the second direction D2. The first word line WL1 and the second word line WL2 may be separated by the gate separation pattern GSS. The gate separation pattern GSS may extend along the first direction D1 between the first word line WL1 and the second word line WL2.

[0115] The first word line WL1 may be disposed between the gate separation pattern GSS and the first active pattern AP1. The second word line WL2 may be disposed between the gate separation pattern GSS and the second active pattern AP2.

[0116] The gate separation pattern GSS may include a horizontal portion GSS_H and a protrusion GSS_P. The protrusion GSS_P of the gate separation pattern may protrude from the horizontal portion GSS_H of the gate separation pattern in the third direction D3.

[0117] The horizontal portion GSS_H of the gate separation pattern may be closer to the bit line BL than the protrusion GSS_P of the gate separation pattern. The horizontal portion GSS_H of the gate separation pattern may contact the bit line BL. The width of the horizontal portion GSS_H of the gate separation pattern in the second direction D2 is greater than the width of the protrusion GSS_P of the gate separation pattern in the second direction D2.

[0118] The protrusion GSS_P of the gate separation pattern may be disposed between sidewalls of the first and second word lines WL1 and WL2 facing each other. The horizontal portion GSS_H of the gate separation pattern may cover the first surfaces WL_S1 of the first and second word lines WL1 and WL2.

[0119] The first and second word lines WL1 and WL2 are disposed on the horizontal portion GSS_H of the gate separation pattern. The first and second word lines WL1 and WL2 may be on the horizontal portion GSS_H of the gate separation pattern. The first and second word lines WL1 and WL2 may be disposed between the horizontal portion GSS_H of the gate separation pattern and the contact pattern BC.

[0120] The gate separation pattern GSS may be made of an insulating material. Unlike the illustrated example, the gate separation pattern GSS may include a plurality of insulating films.

[0121] The contact pattern BC may penetrate the contact interlayer insulating film 231 and the contact etch stop film 212 or extend into the contact interlayer insulating film 231 and the contact etch stop film 212. The contact pattern BC may be connected to each of the first active pattern AP1 and the second active pattern AP2. The contact pattern BC may be connected to each of the second surface S2 of the first active pattern AP1 and the second surface S2 of the second active pattern AP2. In a plan view, each contact pattern BC may have various shapes (such as a circle, an ellipse, a rectangle, a square, a diamond, and a hexagon).

[0122] The contact pattern BC may include a conductive material, such as at least one of doped polysilicon, conductive metal nitride, conductive metal silicon nitride, metal carbonitride, conductive metal silicide, conductive metal oxide, a two-dimensional material, and a metal.

[0123] A contact etch stopper film 212 may be disposed on the gate capping pattern 143 and the back gate capping pattern 111. Each of the contact interlayer insulating film 231 and the contact etch stopper film 212 may be made of an insulating material.

[0124] Landing pads (LP) may be disposed on the contact patterns BC and may have various shapes (eg, circular, oval, rectangular, square, diamond, and hexagonal) in a plan view.

[0125] The pad separation insulating pattern 235 may be disposed between the bonding pads LP. In a plan view, the bonding pads LP may be arranged in a matrix along the first direction D1 and the second direction D2. The upper surface of the bonding pads LP may be substantially coplanar with the upper surface of the pad separation insulating pattern 235, but the present disclosure is not limited thereto.

[0126] The bonding pad LP includes a conductive material, and may include, for example, at least one of doped polysilicon, conductive metal nitride, conductive metal silicon nitride, metal carbonitride, conductive metal silicide, conductive metal oxide, a 2D material, and a metal.

[0127] Each data storage pattern DSP may be disposed on a bonding pad LP. The data storage pattern DSP may be electrically connected to each of the first active pattern AP1 and the second active pattern AP2. Figure 1 As shown in FIG, the data storage pattern DSP may be arranged in a matrix along the first direction D1 and the second direction D2. The data storage pattern DSP may completely or partially overlap the bonding pad LP in the third direction D3. The data storage pattern DSP may contact all or part of the upper surface of the bonding pad LP.

[0128] As an example, the data storage pattern DSP may be a capacitor. The data storage pattern DSP may include a capacitor dielectric film 253 disposed between a storage electrode 251 and a plate electrode 255. For example, the storage electrode 251 may be in contact with the bonding pad LP. In a plan view, the storage electrode 251 may have various shapes (such as circular, oval, rectangular, square, diamond, and hexagonal). The data storage pattern DSP may be in contact with all or part of the upper surface of the bonding pad LP. The storage electrode 251 may pass through or extend through the upper etch stop film 247. The upper etch stop film 247 may be made of an insulating material.

[0129] The storage electrode 251 and the plate electrode 255 may each include, for example, at least one of a conductive semiconductor material, a conductive metal nitride, a conductive metal silicon nitride, a metal carbonitride, a conductive metal silicide, a conductive metal oxide, and a metal. The capacitor dielectric film 253 may include at least one of a ferroelectric material, an antiferroelectric material, and a paraelectric material. For example, the capacitor dielectric film 253 may include one of a ferroelectric material, an antiferroelectric material, a paraelectric material, a combination of a ferroelectric material and an antiferroelectric material, a combination of a ferroelectric material and a paraelectric material, a combination of a paraelectric material and an antiferroelectric material, and a combination of a ferroelectric material, an antiferroelectric material, and a paraelectric material.

[0130] In contrast, the data storage pattern DSP may be a variable resistance pattern that can be switched between two resistance states by an electrical pulse applied to the memory element. For example, the data storage pattern DSP may include a phase change material, a perovskite compound, a transition metal oxide, a magnetic material, a ferromagnetic material, or an antiferromagnetic material.

[0131] Figures 8 to 11 is a diagram for explaining a semiconductor memory device according to some embodiments. Figures 1 to 7 The points described are different.

[0132] For reference, Figure 8 It is along Figure 1 A cross-sectional view taken along lines AA and BB. Figure 9 yes Figure 8 An enlarged view of a portion P of FIG. Figure 10 is schematically shown by cutting in a first direction Figure 9 FIG. 1 is a diagram illustrating the grain shape of a cross section taken along a word line. Figure 11 is schematically shown by cutting in the second direction Figure 9 FIG. 1 is a diagram illustrating the grain shape of a cross section taken along a word line.

[0133] Reference Figure 8 and Figure 9 In a semiconductor memory device according to some embodiments, the first word line WL1 and the second word line WL2 may include a first word line pattern WL_M1 including a first conductive material and a second word line pattern (or second line pattern) WL_M2 including a second conductive material.

[0134] The first word line WL1 and the second word line WL2 may include a plurality of first conductive material crystals WL_MCX1 and a plurality of second conductive material crystals WL_MCX2. The second word line pattern WL_M2 may include a plurality of second conductive material crystals WL_MCX2. Each second conductive material crystal WL_MCX2 may be a grain of the second conductive material. In some embodiments, the second surface WL_S2 of the first word line WL1 may include at least one of the plurality of second conductive material crystals WL_MCX2.

[0135] Each second conductive material crystal WL_MCX2 may have a random crystal direction CX2_DR. In other words, each second conductive material crystal WL_MCX2 may be oriented in a random direction.

[0136] The first word line WL1 will be explained as an example. The explanation of the first word line WL1 can be applied to the second word line WL2.

[0137] The first surface WL_S1 of the first word line WL1 may be defined by a first word line pattern WL_M1. The second surface WL_S2 of the first word line WL1 may be defined by a second word line pattern WL_M2. The second surface WL_S2 of the first word line WL1 may be defined by a plurality of second conductive material crystals WL_MCX2. The second surface WL_S2 of the first word line WL1 may be formed by a collection of the plurality of second conductive material crystals WL_MCX2.

[0138] Unlike the illustrated example, the second surface WL_S2 of the first word line WL1 may be defined by the first word line pattern WL_M1.The first surface WL_S1 of the first word line WL1 may be defined by the second word line pattern WL_M2.

[0139] The second conductive material crystals WL_MCX2 may have a random crystal direction CX2_DR, and the grain size of each second conductive material crystal WL_MCX2 may be small. The grain sizes GS_D21, GS_D22, and GS_D23 of each second conductive material crystal WL_MCX2 in the third direction D3 are smaller than the grain sizes GS_D11 and GS_D12 of each first conductive material crystal WL_MCX1 in the third direction D3.

[0140] For example, the first conductive material crystals WL_MCX1 included in the first word line pattern WL_M1 may have a first average grain size in the third direction D3 . The first average grain size may be an average of grain sizes GS_D11 and GS_D12 of the first conductive material crystals WL_MCX1 in the third direction D3 .

[0141] The second conductive material crystals WL_MCX2 included in the second word line pattern WL_M2 may have a second average grain size in the third direction D3 . The second average grain size may be an average of grain sizes GS_D21 , GS_D22 , and GS_D23 of the second conductive material crystals WL_MCX2 in the third direction D3 .

[0142] For example, the first average grain size may be equal to or greater than three times the second average grain size.

[0143] The second word line pattern WL_M2 may include, for example, at least one of a conductive semiconductor material, a conductive metal nitride, a conductive metal silicon nitride, a metal carbonitride, a conductive metal silicide, a conductive metal oxide, and a metal.

[0144] As an example, the second conductive material included in the second word line pattern WL_M2 may be identical to the first conductive material included in the first word line pattern WL_M1. That is, the second conductive material crystals WL_MCX2 may include the same conductive material as the first conductive material crystals WL_MCX1. Although the first word line pattern WL_M1 includes a material identical to that of the second word line pattern WL_M2, the boundary between the first word line pattern WL_M1 and the second word line pattern WL_M2 is distinguishable. Because the crystal direction CX1_DR of the first conductive material crystals WL_MCX1 differs from the crystal direction CX2_DR of the second conductive material crystals WL_MCX2, the boundary between the first word line pattern WL_M1 and the second word line pattern WL_M2 is distinguishable.

[0145] As another example, the second conductive material included in the second word line pattern WL_M2 may be different from the first conductive material included in the first word line pattern WL_M1 .

[0146] Figure 12 and Figure 13 is a diagram for explaining a semiconductor memory device according to some embodiments. Figures 1 to 7 The points described are different.

[0147] For reference, Figure 12 It is along Figure 1 A cross-sectional view taken along lines AA and BB, and Figure 13 It is along Figure 1 Cross-sectional view taken along lines CC and DD. Figure 12 and Figure 13 In the semiconductor memory device according to some embodiments, the shielding conductive pattern SL may include a shielding conductive plate SLh and a plurality of shielding conductive line patterns SLp.

[0148] The shielding conductive plate SLh may have a flat plate shape. The shielding conductive line pattern SLp may protrude or extend from the shielding conductive plate SLh in the third direction D3. The shielding conductive line pattern SLp is directly connected to the shielding conductive plate SLh.

[0149] The shielding insulation liner 171 may extend along outlines of the shielding conductive plate SLh and the shielding conductive line pattern SLp.

[0150] The shielding insulating cover film 175 may be disposed between the shielding conductive plate SLh and the substrate 100. The shielding insulating cover film 175 may be in contact with the shielding conductive plate SLh.

[0151] The bit line BL may be disposed on the shielding conductive pattern SL. The bit line BL may be disposed on the shielding conductive plate SLh. The shielding conductive pattern SL may be disposed on the bottom surface BL_BS of the bit line. For example, the shielding conductive plate SLh may be disposed on the bottom surface BL_BS of the bit line.

[0152] Figure 14 and Figure 15 is a diagram for explaining a semiconductor memory device according to some embodiments. Figures 1 to 13 The points described are different.

[0153] For reference, Figure 14 It is along Figure 1 A cross-sectional view taken along lines AA and BB, and Figure 15 It is along Figure 1 Cross-sectional view taken along lines CC and DD. Figure 14 and Figure 15 The semiconductor memory device according to some embodiments may further include a peripheral gate structure PG disposed between the substrate 100 and the bit line BL.

[0154] The peripheral gate structure PG may be disposed on the substrate 100. For example, the peripheral gate structure PG may be disposed on the upper surface 100US of the substrate. The peripheral gate structure PG may be disposed above the cell array region and the peripheral circuit region. In other words, a portion of the peripheral gate structure PG may be disposed in the cell array region of the substrate 100, and the remaining portion of the peripheral gate structure PG may be disposed in the peripheral circuit region of the substrate 100.

[0155] The peripheral gate structure PG may be included in a sensing transistor, a transfer transistor, a driving transistor, etc. For example, the peripheral gate structure PG included in the sensing transistor may be provided on the cell array region of the substrate 100, but the present disclosure is not limited thereto. The type of transistors in the peripheral circuit provided on the cell array region of the substrate 100 may vary depending on the design and layout of the semiconductor memory device.

[0156] The peripheral gate structure PG may include a peripheral gate insulating film 215, a peripheral lower conductive pattern 223, and a peripheral upper conductive pattern 225. The peripheral gate insulating film 215 may include a silicon oxide film, a silicon oxynitride film, a high dielectric constant insulating film having a higher dielectric constant than the silicon oxide film, or a combination thereof. The high dielectric constant insulating film may include, for example, but not limited to, at least one of a metal oxide, a metal oxynitride, a metal silicon oxide, and a metal silicon oxynitride.

[0157] The surrounding lower conductive pattern 223 and the surrounding upper conductive pattern 225 each include a conductive material. For example, the surrounding lower conductive pattern 223 and the surrounding upper conductive pattern 225 may each include at least one of a doped semiconductor material, a conductive metal nitride, a conductive metal silicon nitride, a metal carbon nitride, a conductive metal silicide, a conductive metal oxide, a two-dimensional (2D) material, and a metal. Although the surrounding gate structure PG is shown as including a plurality of conductive patterns, embodiments are not limited thereto.

[0158] Although not shown, the peripheral gate structure PG may further include a peripheral gate mask pattern disposed on the peripheral upper conductive pattern 225. The peripheral gate mask pattern is made of an insulating material.

[0159] A first peripheral lower insulating film 227 and a second peripheral lower insulating film 228 are provided on the upper surface 100US of the substrate. The first peripheral lower insulating film 227 and the second peripheral lower insulating film 228 each include an insulating material.

[0160] The peripheral contact plug 241a and the peripheral wiring line 241b may be provided inside the first peripheral lower insulating film 227 and the second peripheral lower insulating film 228. The peripheral contact plug 241a and the peripheral wiring line 241b may be connected to the peripheral lower conductive pattern 223 and the peripheral upper conductive pattern 225 of the peripheral gate structure PG. Although not shown, the peripheral contact plug 241a and the peripheral wiring line 241b may be connected to the source / drain region provided on at least one side of the peripheral gate structure PG.

[0161] Although the peripheral contact plug 241a and the peripheral wiring line 241b are shown as different films from each other, the present disclosure is not limited thereto. The boundary between the peripheral contact plug 241a and the peripheral wiring line 241b may not be distinguished. The peripheral contact plug 241a and the peripheral wiring line 241b each include a conductive material.

[0162] A first peripheral upper insulating film 261 and a second peripheral upper insulating film 262 may be provided on the peripheral contact plug 241a and the peripheral wiring line 241b. The first peripheral upper insulating film 261 and the second peripheral upper insulating film 262 each include an insulating material. Unlike the example shown, an insulating film formed of a single film may be provided on the peripheral contact plug 241a and the peripheral wiring line 241b.

[0163] The peripheral connection structures 242a and 242b may be connected to the peripheral wiring line 241b. The peripheral connection structures 242a and 242b may include a peripheral connection via 242a and a peripheral connection wiring 242b. The peripheral connection via 242a and the peripheral connection wiring 242b each include a conductive material.

[0164] Although the peripheral connection vias 242a and the peripheral connection wiring 242b are shown as different films from each other, the present disclosure is not limited thereto. Although the peripheral connection structures 242a and 242b are shown as including one peripheral connection wiring 242b provided at one metal height, this is for ease of explanation only and embodiments are not limited thereto. The peripheral connection structures 242a and 242b may include multiple peripheral connection wirings 242b provided at different metal heights from each other.

[0165] A third upper peripheral insulating film 265 may be disposed on the peripheral connection structures 242a and 242b. The third upper peripheral insulating film 265 includes an insulating material.

[0166] The shielding conductive pattern SL and the bit line BL may be disposed on the peripheral gate structure PG.The shielding conductive pattern SL and the bit line BL may be disposed on the peripheral connection structures 242a and 242b.

[0167] Unlike the illustrated example, the bonding insulating film 263 may not be provided between the shielding conductive pattern SL and the surrounding connection structures 242 a and 242 b , and between the bit line BL and the surrounding connection structures 242 a and 242 b .

[0168] Figures 16 to 19 is a diagram for explaining a semiconductor memory device according to some embodiments. Figures 1 to 15 Different points of explanation.

[0169] Reference Figure 16 In the semiconductor memory device according to some embodiments, the first active pattern AP1 and the second active pattern AP2 may be alternately arranged in a diagonal direction relative to the first direction D1 and the second direction D2. Here, the diagonal direction may be parallel to the upper surface of the substrate 100.

[0170] In a plan view, each of the first active pattern AP1 and the second active pattern AP2 may have a parallelogram or rhombus shape. Since the first active pattern AP1 and the second active pattern AP2 are arranged in a diagonal direction, coupling between the first active pattern AP1 and the second active pattern AP2 facing each other in the second direction D2 can be reduced.

[0171] Reference Figure 17 In the semiconductor memory device according to some embodiments, the bonding pads LP and the data storage patterns DSP may be arranged in a zigzag or honeycomb form in a plan view.

[0172] Reference Figure 18 , in the semiconductor memory device according to some embodiments, the data storage pattern DSP may be arranged to be offset from the bonding pad LP in a plan view.

[0173] Each of the data storage patterns DSP may be in contact with a portion of the bonding pad LP.

[0174] Reference Figure 19 In the semiconductor memory device according to some embodiments, each of the contact patterns BC disposed on the first and second active patterns AP1 and AP2 may have a semicircular shape or a semi-elliptical shape in a plan view.

[0175] In a plan view, the contact patterns BC may be disposed symmetrically to each other with the back gate electrode BG between the contact patterns BC.

[0176] Figures 20 to 53 is a diagram for explaining a method for manufacturing a semiconductor memory device according to some embodiments. Figure 14 and Figure 15 A semiconductor memory device is described.

[0177] For reference, by reversing in the first direction D1 Figure 1 The cutting line and coordinate system in Figures 20 to 49 The cutting lines and coordinate system shown in .

[0178] Reference Figures 20 to 22 , a sub-substrate structure including a sub-substrate 200 , a buried insulating layer 201 and an active layer 202 may be provided.

[0179] A buried insulating layer 201 and an active layer 202 may be provided on a submount 200. The submount 200, the buried insulating layer 201, and the active layer 202 may be a silicon-on-insulator substrate (i.e., an SOI substrate). The submount 200 may be a semiconductor substrate. The submount 200 may be, for example, a silicon substrate, a germanium substrate, and / or a silicon-germanium substrate. In the following description, the submount 200 will be described as a silicon substrate.

[0180] The buried insulating layer 201 may be a buried oxide (BOX) formed by a SIMOX (Separation by Implanted Oxygen) method or a bonding and layer transfer method. In contrast, the buried insulating layer 201 may be an insulating film formed by chemical vapor deposition. The buried insulating layer 201 may include, for example, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, and / or a low-k insulating film.

[0181] The active layer 202 may be a single crystal semiconductor film. The active layer 202 may be, for example, a single crystal silicon substrate, a germanium substrate, and / or a silicon germanium substrate. The active layer 202 may have a first surface and a second surface that are opposite to each other in the third direction D3, and the second surface of the active layer 202 may be in contact with the buried insulating layer 201.

[0182] Reference Figures 23 to 25 , a mask pattern MP1 may be formed on the active layer 202 .

[0183] The mask pattern MP1 may have a linear opening extending along the first direction D1. The mask pattern MP1 may include a first lower mask film 11 and a first upper mask film 12 sequentially stacked. The first upper mask film 12 may be made of a material having an etching selectivity relative to the first lower mask film 11. As an example, the first lower mask film 11 may include silicon oxide, and the first upper mask film 12 may include silicon nitride, but the embodiment is not limited thereto.

[0184] Subsequently, the active layer 202 may be anisotropically etched using the mask pattern MP1 as an etching mask. Thus, back gate trenches BG_T extending along the first direction D1 may be formed on the active layer 202. The back gate trenches BG_T may expose the buried insulating layer 201 and may be spaced apart at regular intervals in the second direction D2.

[0185] Unlike the illustrated example, at least a portion of the buried insulating layer 201 may be removed while forming the back gate trench BG_T.

[0186] Reference Figures 26 to 28 , a back gate insulating pattern 113 and a back gate electrode BG may be formed inside the back gate trench BG_T.

[0187] More specifically, a back gate insulating pattern 113 may be formed along the sidewalls and bottom surface of the back gate trench BG_T and the upper surface of the mask pattern MP1. A back gate conductive film may be formed on the back gate insulating pattern 113. The back gate conductive film may fill the back gate trench BG_T or be in the back gate trench BG_T. Subsequently, the back gate conductive film may be isotropically etched to form a back gate electrode BG extending in the first direction D1. The back gate electrode BG may partially fill the back gate trench BG_T or be partially in the back gate trench BG_T.

[0188] Meanwhile, according to some embodiments, a gas phase doping (GPD) process or a plasma doping (PLAD) process may be performed before forming the back gate insulating pattern 113. The active layer 202 exposed by the back gate trench BG_T may be doped with impurities through the aforementioned process.

[0189] Reference Figures 29 to 31 , a back gate capping pattern 115 may be formed on the back gate electrode BG.

[0190] The back gate capping pattern 115 may fill the remaining portion of the back gate trench BG_T or be in the remaining portion of the back gate trench BG_T. When the back gate capping pattern 115 and the back gate insulating pattern 113 are formed of the same material (e.g., silicon oxide), the back gate insulating pattern 113 on the upper surface of the mask pattern MP1 may be removed while the back gate capping pattern 115 is formed.

[0191] Meanwhile, a gas phase doping (GPD) process or a plasma doping (PLAD) process may be performed before forming the back gate capping pattern 115. Thus, the active layer 202 may be doped with impurities through the back gate trench BG_T in which the back gate electrode BG is formed.

[0192] Reference Figures 32 to 34 After forming the back gate capping pattern 115 , the first upper mask film 12 may be removed.

[0193] The back gate capping pattern 115 may have a shape protruding or extending above the upper surface of the first lower mask film 11 .

[0194] A spacer film 120 may then be formed along the upper surface of the first lower mask film 11, the sidewalls of the back gate insulating pattern 113, and the upper surface of the back gate capping pattern 115. The spacer film 120 may be formed to have a uniform thickness. The width of the active pattern of the vertical channel transistor may be determined by the deposition thickness of the spacer film 120.

[0195] The spacer film 120 may be formed of an insulating material. The spacer film 120 may include, for example, silicon oxide, silicon oxynitride, silicon nitride, silicon carbide (SiC), silicon carbonitride (SiCN), and combinations thereof.

[0196] Reference Figures 35 to 37 By performing an anisotropic etching process on the spacer film 120 , a pair of spacer patterns 121 may be formed on the sidewalls of the back gate insulating pattern 113 .

[0197] An anisotropic etching process may be performed on the active layer 202 using the spacer pattern 121 as an etching mask. Thus, a pair of pre-active patterns PAP separated from each other may be formed on both sides of each back gate insulating pattern 113. When the pre-active patterns PAP are formed, the buried insulating layer 201 may be exposed.

[0198] The pre-active pattern PAP may extend in the first direction D1 together with the back gate electrode BG. While forming the pre-active pattern PAP, a word line trench WL_T may be formed between the pre-active patterns PAP adjacent to each other in the second direction D2.

[0199] Reference Figures 38 to 40 A sacrificial film may be formed to fill the word line trench WL_T or in the word line trench WL_T. A mask pattern may be formed on the sacrificial film. The mask pattern may be in the form of a line extending in the second direction D2. As another example, the mask pattern may be in the form of a line extending in a diagonal direction relative to the first direction D1 and the second direction D2. The sacrificial film may be etched using the mask pattern as an etching mask to form a sacrificial opening within the sacrificial film.

[0200] By etching the pre-active pattern PAP exposed to the sacrificial opening, a first active pattern AP1 and a second active pattern AP2 may be formed on both sides of the back gate electrode BG. The first active pattern AP1 may be formed on the first sidewall of the back gate electrode BG so as to be spaced apart from each other in the first direction D1. The second active pattern AP2 may be formed on the second sidewall of the back gate electrode BG so as to be spaced apart from each other in the first direction D1. As the first active pattern AP1 and the second active pattern AP2 are formed, the sacrificial opening may expose a portion of the back gate insulating pattern 113.

[0201] Next, the sacrificial film, the mask pattern, the spacer pattern 121, and the first lower mask film 11 may be removed. Thus, the first active pattern AP1 and the second active pattern AP2 may be exposed. In addition, the buried insulating layer 201 may be exposed.

[0202] Reference Figures 41 to 42 , a gate insulation pattern GOX may be formed along sidewalls and bottom surfaces of the word line trench WL_T.

[0203] The gate insulating pattern GOX may be formed along sidewalls of the first active pattern AP1 , sidewalls of the second active pattern AP2 , an upper surface of the back gate capping pattern 115 , and an upper surface of the buried insulating layer 201 .

[0204] The gate insulating pattern GOX may be formed by using, but is not limited to, at least one of physical vapor deposition (PVD), thermal chemical vapor deposition (thermal CVD), low pressure chemical vapor deposition (LP-CVD), plasma enhanced chemical vapor deposition (PE-CVD), and atomic layer deposition (ALD) techniques.

[0205] Subsequently, a first pre-word line pattern P_WL1 may be formed on the gate insulating pattern GOX. The first pre-word line pattern P_WL1 may partially fill the word line trench WL_T or be in the word line trench WL_T.

[0206] More specifically, a first pre-word line film may be formed on the gate insulating pattern GOX. The first pre-word line film may fill the word line trench WL_T. A first pre-word line pattern P_WL1 may be formed inside the word line trench WL_T by etching a portion of the first pre-word line film.

[0207] Crystal directions of the conductive material crystals included in the first pre-word line pattern P_WL1 may be random directions.

[0208] Reference Figure 43 and Figure 44 , a second pre-word line pattern P_WL2 may be formed on the first pre-word line pattern P_WL1.

[0209] The second pre-word line pattern P_WL2 may fill the word line trench ( Figure 39 and Figure 40 WL_T) or in the word line trench ( Figure 39 and Figure 40 WL_T).

[0210] More specifically, the second pre-word line pattern P_WL2 may be grown over the first pre-word line pattern P_WL1 in the third direction D3. The second pre-word line pattern P_WL2 may be formed using a bottom-up growth method.

[0211] The bottom-up growth method may include, for example, a selective growth method. The selective growth method may be, for example, a method of selectively depositing a conductive material on a conductive material. The first pre-word line pattern P_WL1 may serve as a seed film for selectively growing the second pre-word line pattern P_WL2.

[0212] Since the second pre-word line pattern P_WL2 is formed through a bottom-up growth method, crystal directions of conductive material crystals included in the second pre-word line pattern P_WL2 may be the third direction D3.

[0213] Reference Figures 45 to 47 By patterning the first and second pre-word line patterns P_WL1 and P_WL2 , the first and second word lines WL1 and WL2 may be formed on the gate insulating pattern GOX.

[0214] The first word line WL1 and the second word line WL2 may be formed using, for example, an anisotropic etching process.

[0215] First and second word lines WL1 and WL2 may be formed on sidewalls of the first and second active patterns AP1 and AP2. The first pre-word line pattern P_WL1 may be patterned to form a second word line pattern WL_M2. The second pre-word line pattern P_WL2 may be patterned to form the first word line pattern WL_M1.

[0216] According to a method of patterning the first and second pre-word line patterns P_WL1 and P_WL2 , the width of the first word line WL1 in the second direction D2 may be the same as or different from the width of the second word line WL2 in the second direction D2 .

[0217] When the anisotropic etching process is performed on the first and second pre-word line patterns P_WL1 and P_WL2, the gate insulating pattern GOX may be used as an etching stopper. Unlike the illustrated example, the gate insulating pattern GOX may be overetched to expose the buried insulating layer 201. Depending on the anisotropic etching process performed on the first and second pre-word line patterns P_WL1 and P_WL2, the first and second word lines WL1 and WL2 may have various shapes.

[0218] Upper surfaces of the first and second word lines WL1 and WL2 may be located at a lower height than upper surfaces of the first and second active patterns AP1 and AP2 .

[0219] As an example, after forming the first and second word lines WL1 and WL2, a gas phase doping (GPD) process or a plasma doping (PLAD) process may be performed to dope impurities into the first and second active patterns AP1 and AP2 through the gate insulating patterns GOX exposed by the first and second word lines WL1 and WL2.

[0220] Subsequently, a gate separation pattern GSS may be formed on the first and second word lines WL1 and WL2 . For example, an upper surface of the gate separation pattern GSS may be disposed on the same plane as an upper surface of the back gate capping pattern 115 .

[0221] Reference Figure 48 and Figure 49 , a bit line BL extending in the second direction D2 may be formed on the gate separation pattern GSS and the back gate capping pattern 115 .

[0222] The bit line BL may include a bit line mask pattern 165, a metal pattern 163, and a semiconductor pattern 161. During the formation of the bit line BL, a portion of the back gate capping pattern 115 and a portion of the gate separation pattern GSS may be etched.

[0223] Subsequently, a shielding conductive pattern SL may be formed between the bit lines BL adjacent in the first direction D1 .

[0224] More specifically, a shielding insulating pad 171 may be formed along the outline of the bit line BL. The shielding insulating pad 171 may define a shielding region between the bit lines BL adjacent along the first direction D1. A shielding conductive film may be formed on the shielding insulating pad 171. The shielding conductive film may fill the shielding region defined by the shielding insulating pad 171 or be in the shielding region defined by the shielding insulating pad 171. At least a portion of the shielding conductive film may be recessed to form a shielding conductive pattern SL. As an example, when the shielding conductive film formed on the bit line BL is completely removed, the shielding conductive pattern SL may include a plurality of linear shielding conductive line patterns SLp. As another example, when a portion or all of the shielding conductive film formed on the bit line BL is not removed, the shielding conductive pattern SL may include a shielding conductive plate ( Figure 12 and Figure 13 A shielding insulating capping film 175 may be formed on the shielding conductive patterns SL.

[0225] Reference Figure 50 and Figure 51 , a peripheral gate structure PG may be formed on the substrate 100 .

[0226] The sub-substrate 200 having the back gate electrode BG, the first and second word lines WL1 and WL2, the first and second active patterns AP1 and AP2, the bit lines BL, and the shielding conductive pattern SL formed thereon may be combined with the substrate 100. The substrate 100 and the sub-substrate 200 may be bonded such that the bit lines BL and the surrounding gate structures PG face each other.

[0227] The substrate 100 and the sub-substrate 200 may be bonded using the bonding insulating film 263. Unlike the illustrated example, the substrate 100 and the sub-substrate 200 may be bonded without the bonding insulating film 263.

[0228] Unlike the example shown, the sub-substrate 200 on which the back gate electrode BG, the first word line WL1, the second word line WL2, the first active pattern AP1, the second active pattern AP2, the bit line BL and the shielding conductive pattern SL are formed can be joined to the substrate 100 on which the peripheral gate structure PG is not formed.

[0229] Reference Figure 52 and Figure 53 After the substrate 100 and the sub-substrate 200 are bonded, a back grinding process for removing the sub-substrate 200 may be performed.

[0230] The removal of the sub-substrate 200 may include exposing the buried insulating layer 201 by sequentially performing a grinding process and a wet etching process.

[0231] Next, the buried insulating layer 201 may be removed to expose the first and second active patterns AP1 and AP2 .

[0232] When the buried insulating layer 201 is removed, a portion of the gate insulating pattern GOX and a portion of the back gate insulating pattern 113 may be exposed.

[0233] Thereafter, the exposed gate insulating pattern GOX and the exposed back gate insulating pattern 113 may be removed. Thus, the back gate electrode BG, the first word line WL1, and the second word line WL2 may be exposed.

[0234] An etch-back process may then be performed to remove at least a portion of the second word line pattern WL_M2 .A gate capping pattern 143 may be formed on the recessed first and second word lines WL1 and WL2 .

[0235] When at least a portion of the second word line pattern WL_M2 is removed, a portion of the back gate electrode BG may also be removed.

[0236] Next, refer to Figure 2 、 Figure 3 、 Figure 14 and Figure 15A contact hole for exposing the first active pattern AP1 and the second active pattern AP2 may be formed inside the contact etch stop film 212 and the contact interlayer insulating film 231. A contact pattern BC may be formed inside the contact hole. The contact pattern BC may be formed on the first active pattern AP1 and the second active pattern AP2. The contact pattern BC may be connected to the first active pattern AP1 and the second active pattern AP2. A data storage pattern DSP may be formed on the contact pattern BC.

[0237] Although the embodiments of the present disclosure have been described with reference to the accompanying drawings, the present disclosure is not limited to the above embodiments and can be implemented in various different forms. A person skilled in the art of the present disclosure will understand that the present disclosure can be implemented in other specific forms without changing the technical concept or essential characteristics of the present disclosure. Therefore, it should be understood that the embodiments described above are not restrictive in all aspects but illustrative.

Claims

1. A semiconductor memory device comprising: a bit line extending in a first direction and on the substrate; an active pattern on the bit line, wherein the active pattern includes a first sidewall and a second sidewall opposite to each other in a first direction, wherein the active pattern includes a first surface and a second surface opposite to each other in a second direction perpendicular to the first direction, and wherein the first surface of the active pattern is electrically connected to the bit line; a word line on the first sidewall of the active pattern and extending in a third direction intersecting the first direction; and a data storage pattern on the active pattern and electrically connected to the second surface of the active pattern, wherein the word line includes a first surface and a second surface opposite to each other in a second direction, The word line includes a first line pattern, and the first line pattern includes a plurality of first conductive material crystals. The direction in which the lattice of each of the plurality of first conductive material crystals extends is the same as the second direction, and At least one of the first surface of the word line and the second surface of the word line includes at least one of the plurality of first conductive material crystals.

2. The semiconductor memory device according to claim 1, wherein The first surface of the word line and the second surface of the word line include the at least one of the plurality of first conductive material crystals.

3. The semiconductor memory device according to claim 2, wherein The at least one of the plurality of first conductive material crystals extends from a first surface of the wordline to a second surface of the wordline.

4. The semiconductor memory device according to claim 1, wherein The word line includes a second line pattern, the second line pattern includes a plurality of second conductive material crystals, The first surface of the word line includes the at least one of the plurality of first conductive material crystals, and The second surface of the word line includes at least one of the plurality of second conductive material crystals.

5. The semiconductor memory device according to claim 4, wherein The plurality of first conductive material crystals have a first average grain size in the second direction, The plurality of second conductive material crystals have a second average grain size in the second direction, and The first average grain size is greater than or equal to three times the second average grain size.

6. The semiconductor memory device according to claim 4, wherein The at least one of the plurality of first conductive material crystals and the at least one of the plurality of second conductive material crystals include the same conductive material.

7. The semiconductor memory device according to claim 1 , further comprising: a back gate electrode on the second sidewall of the active pattern and extending in a third direction, The active pattern is between the back gate electrode and the word line.

8. The semiconductor memory device according to claim 1, further comprising: Shielding conductive pattern, on substrate, The shielding conductive pattern includes: a shielding conductive plate; and a plurality of shielding conductive line patterns extending from the shielding conductive plate. wherein each of the plurality of shielding conductive line patterns extends in a first direction, and The bit lines are located between adjacent shielding conductive line patterns among the plurality of shielding conductive line patterns.

9. The semiconductor memory device according to claim 1, further comprising: a shielding conductive pattern adjacent to the bit line and extending in a first direction, wherein the bit line includes an upper surface and a bottom surface opposite to each other in the second direction, wherein the upper surface of the bit line faces the active pattern, and The shielding conductive pattern is not on the bottom surface of the bit line.

10. The semiconductor memory device according to claim 1, wherein The word line includes a first portion and a second portion spaced apart from each other in a third direction, and A width of the first portion of the word line in the first direction is smaller than a width of the second portion of the word line in the first direction.

11. A semiconductor memory device comprising: a bit line extending in a first direction and on the substrate; a first active pattern on the bit line; a second active pattern on the bit line and spaced apart from the first active pattern in the first direction; a first word line extending between the first active pattern and the second active pattern in a second direction intersecting the first direction; a second word line extending in the second direction between the first active pattern and the second active pattern and spaced apart from the first word line in the first direction; a gate separation pattern on the bit line and comprising a horizontal portion and a protruding portion, wherein the horizontal portion of the gate separation pattern is between the first word line and the bit line and between the second word line and the bit line, wherein the protruding portion of the gate separation pattern is between the first word line and the second word line, and wherein a width of the horizontal portion of the gate separation pattern in the first direction is greater than a width of the protruding portion of the gate separation pattern in the first direction; and a data storage pattern electrically connected to the first active pattern and the second active pattern, wherein each of the first word line and the second word line includes a first plurality of conductive material crystals and a second plurality of conductive material crystals, wherein the first plurality of conductive material crystals include first conductive material crystals, and The height of the first conductive material crystal in a third direction perpendicular to the first direction and the second direction is equal to the height of the first word line in the third direction.

12. The semiconductor memory device according to claim 11, wherein The first plurality of conductive material crystals include second conductive material crystals, and A height of the second conductive material crystals in the third direction is smaller than a height of the first conductive material crystals in the third direction.

13. The semiconductor memory device according to claim 12, wherein The direction in which the crystal lattice of each of the first conductive material crystals and the second conductive material crystals extends is the same as the third direction.

14. The semiconductor memory device according to claim 11, further comprising: The back gate electrode is on the bit line, spaced apart from the first word line and the second word line in the first direction, and extends in the second direction.

15. The semiconductor memory device according to claim 11, wherein The width of the first word line in the first direction is equal to the width of the second word line in the first direction.

16. The semiconductor memory device according to claim 11, wherein The width of the first word line in the first direction is greater than the width of the second word line in the first direction.

17. The semiconductor memory device according to claim 11, further comprising: The shielding conductive pattern is adjacent to the bit line in the second direction and includes a plurality of shielding conductive line patterns extending in the first direction.

18. A semiconductor memory device comprising: a surrounding gate structure on the substrate; a bit line extending in a first direction and over the surrounding gate structure; a shielding conductive pattern on the surrounding gate structure and comprising a plurality of shielding conductive line patterns extending in a first direction and adjacent to the bit lines; a first word line on the bit line and the shielding conductive pattern and extending in a second direction intersecting the first direction; a second word line extending in a second direction on the bit line and the shielding conductive pattern and spaced apart from the first word line in the first direction; a back gate electrode extending in a second direction between the first word line and the second word line; a first active pattern on the bit line and between the first word line and the back gate electrode; a second active pattern on the bit line and between the second word line and the back gate electrode; as well as a data storage pattern electrically connected to the first active pattern and the second active pattern, wherein each of the first word line and the second word line includes a plurality of conductive material crystals, each of the plurality of conductive material crystals having a crystal lattice extending in the same direction as a third direction, the third direction being perpendicular to the first direction and the second direction, The first word line includes a first surface and a second surface opposite to each other in the third direction, The second word line includes a first surface and a second surface opposite to each other in the third direction, wherein the first group of the plurality of conductive material crystals defines a first surface of a first word line and a second surface of the first word line, and The second group of the plurality of conductive material crystals defines a first surface of the second word line and a second surface of the second word line.

19. The semiconductor memory device according to claim 18, wherein The plurality of conductive material crystals include first conductive material crystals, and The height of the first conductive material crystals in the third direction is equal to the height of the first word line in the third direction and the height of the second word line in the third direction.

20. The semiconductor memory device according to claim 18, wherein The shielding conductive pattern also includes a shielding conductive plate, The shielding conductive line pattern extends from the shielding conductive plate in a third direction, and The bit lines are on the shielding conductive plate.

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