Power semiconductor package and manufacturing method thereof

Abstract

The invention relates to a power semiconductor package and a manufacturing method thereof. The power semiconductor package includes: a base defining a cell region and a peripheral region surrounding the cell region, and including a substrate and an epitaxial layer over the substrate; the junction layer is arranged in the peripheral region and is positioned above the epitaxial layer; the barrier layer is arranged in the unit region and is positioned above the epitaxial layer; a first electrode disposed on the junction layer; and a second electrode disposed on the barrier layer, where the epitaxial layer includes a doped channel disposed in the peripheral region and extending between the junction layer and the substrate, and a current may flow from the substrate to the first electrode through the doped channel and the junction layer.

Description

Technical Field

[0001] The present invention relates to a power semiconductor package and a manufacturing method thereof, and more particularly to a power semiconductor device packaged in an integrated circuit (IC) and a manufacturing method thereof, and more particularly to a junction barrier Schottky (JBS) rectifier in a chip scale package (CSP) and a manufacturing method thereof. Background Art

[0002] Modern power circuits require rectifiers with high power, low losses, and fast switching speeds. Schottky barrier rectifiers are often used when high switching speeds and very low forward bias voltage are required. Schottky barrier rectifiers are majority carrier devices fabricated using a metal oxide semiconductor (MOS) process, allowing only a small reverse leakage current to flow during recovery. Unfortunately, when operating at higher temperatures, Schottky barrier rectifiers suffer from undesirably high reverse leakage current.

[0003] Currently, some improvements are being adopted to improve the high-temperature operating capability of Schottky rectifiers. One such improvement method is to replace silicon with silicon carbide (SiC) as the substrate of the Schottky barrier rectifier, which gives the rectifier a high breakdown voltage, low forward voltage drop, short reverse recovery time, and high-temperature operating capability. However, SiC is brittle and easily wears out, and has poor machinability, making it difficult to process. Moreover, compared with silicon, SiC causes the rectifier to have a higher leakage current, which limits its use to low-voltage applications.

[0004] Therefore, the rectifier devices in the prior art need to be further improved to obtain more ideal high power and low loss so as to be applicable to fast switching applications. Summary of the Invention

[0005] Embodiments of the present disclosure relate to a power semiconductor package. The power semiconductor package includes: a base defining a cell region and a peripheral region surrounding the cell region, and including a substrate and an epitaxial layer located above the substrate; a junction layer disposed within the peripheral region and located above the epitaxial layer; a barrier layer disposed within the cell region and located above the epitaxial layer; a first electrode disposed on the junction layer; and a second electrode disposed on the barrier layer, wherein the epitaxial layer includes a doped channel disposed within the peripheral region and extending between the junction layer and the substrate, and current can flow from the substrate through the doped channel and the junction layer to the first electrode.

[0006] Embodiments of the present disclosure relate to a power semiconductor package. The power semiconductor package includes: a substrate defining a cell region and a peripheral region surrounding the cell region, and including a substrate and an epitaxial layer located above the substrate; a semiconductor component surrounded by the substrate and the epitaxial layer; a junction layer disposed within the peripheral region and located above the epitaxial layer; and a first electrode disposed on the junction layer, wherein the epitaxial layer includes a doped channel disposed within the peripheral region and extending between the junction layer and the semiconductor component, and current can flow from the substrate through the semiconductor component, the doped channel, and the junction layer to the first electrode.

[0007] Embodiments of the present disclosure relate to a method for manufacturing a power semiconductor package. The method includes: forming a first epitaxial sublayer above a substrate; implanting dopant ions into a portion of the first epitaxial sublayer to form a first doped sub-channel; forming a second epitaxial sublayer above the first epitaxial sublayer; implanting the dopant ions into a portion of the second epitaxial sublayer to form a second doped sub-channel above the first doped sub-channel; forming a junction layer above the second doped sub-channel; and forming a first electrode above the junction layer, wherein a doped channel including the first doped sub-channel and the second doped sub-channel is formed, and the doped channel extends between the junction layer and the substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The aspects of several embodiments of the present disclosure are best understood when the following detailed description is read in conjunction with the accompanying drawings. It should be noted that the various structures may not be drawn to scale. In fact, the dimensions of the various structures may be arbitrarily enlarged or reduced for clarity of discussion.

[0009] Figure 1 FIG2 is a cross-sectional view of a power semiconductor package according to some embodiments of the present invention;

[0010] Figure 2 FIG2 is a cross-sectional view of a power semiconductor package according to some other embodiments of the present invention;

[0011] Figure 3 FIG2 is a cross-sectional view of a power semiconductor package according to some other embodiments of the present invention;

[0012] Figures 4 to 54 Shown are one or more stages in a method of manufacturing a power semiconductor package according to certain embodiments of the present disclosure.

[0013] The same or similar components are denoted by the same reference numerals in the drawings and detailed description. Several embodiments of the present disclosure will be immediately understood from the following detailed description taken in conjunction with the accompanying drawings. DETAILED DESCRIPTION

[0014] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and configurations are described below. Of course, these are merely examples and are not intended to be restrictive. In this disclosure, references to forming a first feature above or on a second feature may include embodiments in which the first and second features are formed to be in direct contact, and may also include embodiments in which additional features may be formed between the first and second features so that the first and second features may not be in direct contact. In addition, the disclosure may repeat reference numerals and / or letters in various examples. This repetition is for simplicity and clarity and does not in itself indicate the relationship between the various embodiments and / or configurations discussed.

[0015] The following describes embodiments of the present disclosure in detail. However, it should be understood that the present disclosure provides many applicable concepts that can be embodied in a variety of specific environments. The specific embodiments discussed are merely illustrative and do not limit the scope of the present disclosure.

[0016] The present disclosure provides a power semiconductor package and a method for manufacturing the same. Compared to forming a silicon carbide epitaxial layer on a substrate, the power semiconductor package of the present disclosure forms the silicon carbide epitaxial layer by stacking silicon carbide sub-epitaxial layers one by one, and after forming each silicon carbide sub-epitaxial layer, a diffusion or ion implantation process is performed at a specific position to form a doped channel extending in the silicon carbide epitaxial layer and consisting of a plurality of sub-doped channels. This allows the power semiconductor package of the present disclosure to form doped channels without the need for cutting the silicon carbide epitaxial layer, thus avoiding the problem that silicon carbide materials are difficult to cut. In addition, the power semiconductor package of the present disclosure forms the silicon carbide epitaxial layer by stacking silicon carbide sub-epitaxial layers one by one. This method can produce a thicker silicon carbide epitaxial layer to reduce leakage current, so that the power semiconductor package of the present disclosure can be used in high-voltage applications.

[0017] Figure 1 FIG2 is a cross-sectional view of a power semiconductor package 100 according to some embodiments of the present invention. Specifically, the power semiconductor package 100 is a power semiconductor device packaged in an integrated circuit (IC). In some embodiments, the power semiconductor package 100 is a junction barrier Schottky (JBS) rectifier in a chip scale package (CSP). Figure 1As shown, power semiconductor package 100 includes a substrate 101, a contact layer 103 above substrate 101, and an electrode 104 on contact layer 103. Substrate 101 defines a cell region 100a and a peripheral region 100b adjacent to cell region 100a, as seen from a top view. In some embodiments, cell region 100a is an active region for accommodating active or passive components, while peripheral region 100b is an edge termination region for connecting to circuit terminals. In some embodiments, cell region 100a is surrounded by peripheral region 100b.

[0018] The base 101 includes a substrate 101a and an epitaxial layer 101b above the substrate 101a. In some embodiments, the substrate 101a comprises, for example, silicon, silicon carbide (SiC), germanium (Ge), silicon germanium (SiGe), gallium nitride (GaN), gallium arsenide (GaAs), gallium arsenide phosphide (GaAsP), or other semiconductor materials. The epitaxial layer 101b comprises, for example, silicon, silicon carbide (SiC), germanium (Ge), silicon germanium (SiGe), gallium nitride (GaN), gallium arsenide (GaAs), gallium arsenide phosphide (GaAsP), or other semiconductor materials. In some embodiments, both the substrate 101a and the epitaxial layer 101b comprise silicon carbide. In some embodiments, the substrate 101a is an N-type or P-type semiconductor material, and the epitaxial layer 101b is an N-type or P-type semiconductor material. In some embodiments, the substrate 101a and the epitaxial layer 101b have the same conductivity type doping, for example, both the substrate 101a and the epitaxial layer 101b are N-type. In some embodiments, substrate 101a is part of a silicon carbide wafer. In some embodiments, the doping concentration of substrate 101a is greater than the doping concentration of epitaxial layer 101b. Both substrate 101a and epitaxial layer 101b include an N-type dopant, which may be, for example, phosphorus (P) or arsenic (As). In some embodiments, the thickness of epitaxial layer 101b is greater than the thickness of substrate 101a. In some embodiments, the thickness of epitaxial layer 101b is greater than or equal to 6 μm. The greater the thickness of epitaxial layer 101b, the more preferably the power semiconductor package 100 is used in high voltage applications (e.g., 650 volts (V) to 3000 volts).

[0019] The epitaxial layer 101b includes a doped channel 101c, which is disposed within the peripheral region 100b and extends between the electrode 104 and the substrate 101a. In some embodiments, the doped channel 101c extends vertically within the epitaxial layer 101b along the thickness of the epitaxial layer 101b. The height H1 of the doped channel 101c is substantially equal to the thickness of the epitaxial layer 101b. In some embodiments, the height H1 of the doped channel 101c and the thickness of the epitaxial layer 101b are within the numerical range of approximately 2 μm and approximately 6 μm, respectively. The substrate 101a and the doped channel 101c have the same conductivity type. In some embodiments, the substrate 101a, the epitaxial layer 101b, and the doped channel 101c are all N-type.

[0020] The epitaxial layer 101b may further include a plurality of epitaxial sublayers 101b-1, 101b-2, and 101b-3 stacked on top of each other, with the doped channel 101c extending across the plurality of epitaxial sublayers 101b-1, 101b-2, and 101b-3. The number of epitaxial sublayers 101b-1, 101b-2, and 101b-3 may be one or more integers and may be adjusted as needed. In some embodiments, the epitaxial layer 101b includes a first epitaxial sublayer 101b-1, a second epitaxial sublayer 101b-2, and a third epitaxial sublayer 101b-3. The first epitaxial sublayer 101b-1 is disposed above the substrate 101a, the second epitaxial sublayer 101b-2 is disposed above the first epitaxial sublayer 101b-1, and the third epitaxial sublayer 101b-3 is disposed above the second epitaxial sublayer 101b-2. The first epitaxial sublayer 101b-1, the second epitaxial sublayer 101b-2, and the third epitaxial sublayer 101b-3 have the same conductivity type, for example, N-type. The first epitaxial sublayer 101b-1 has a thickness T1, the second epitaxial sublayer 101b-2 has a thickness T2, and the third epitaxial sublayer 101b-3 has a thickness T3. In some embodiments, thicknesses T1, T2, and T3 are substantially the same. In some embodiments, thicknesses T1, T2, and T3 are within the range of approximately 1.5 μm and approximately 2 μm, respectively.

[0021] In some embodiments, the doped channel 101c may include a first doped sub-channel 101c-1, a second doped sub-channel 101c-2, and a third doped sub-channel 101c-3. The first doped sub-channel 101c-1 extends across the first epitaxial sublayer 101b-1, the second doped sub-channel 101c-2 extends across the second epitaxial sublayer 101b-2, and the third doped sub-channel 101c-3 extends across the third epitaxial sublayer 101b-3. The first doped sub-channel 101c-1 is above the substrate 101a, the second doped sub-channel 101c-2 is above the first doped sub-channel 101c-1, and the third doped sub-channel 101c-3 is above the second doped sub-channel 101c-2. The first doped sub-channel 101c-1, the second doped sub-channel 101c-2, and the third doped sub-channel 101b-3 have the same conductivity type, for example, N-type. In some embodiments, the doping concentration of the first doped sub-channel 101c-1 is greater than the doping concentration of the second doped sub-channel 101c-2, and the doping concentration of the second doped sub-channel 101c-2 is greater than the doping concentration of the third doped sub-channel 101b-3. In some embodiments, the first doped sub-channel 101c-1, the second doped sub-channel 101c-2, and the third doped sub-channel 101c-3 have substantially the same doping concentration.

[0022] In some embodiments, the epitaxial layer 101b further includes guard rings 101d and 101f for reducing edge electric fields or surface electric fields and improving the breakdown voltage of the power semiconductor package 100. The guard rings 101d and 101f are field limiting rings. The epitaxial layer 101b further includes a first guard ring 101d, which is disposed between the cell area 100a and the peripheral area 100b and extends across at least a portion of the epitaxial layer 101b and is used to reduce the impact of the high electric field at the edge of the electrode 104. The first guard ring 101d is located adjacent to the edge of the electrode 104. The first guard ring 101d has a conductivity type opposite to that of the epitaxial layer 101b, for example, the first guard ring 101d is P-type and the epitaxial layer 101b is N-type. The first guard ring 101d includes a P-type dopant, which may be, for example, boron, aluminum, gallium, indium, or the like. In some embodiments, the height H2 of the first guard ring 101d is substantially equal to or less than the thickness of the epitaxial layer 101b. In some embodiments, the height H2 of the first guard ring 101d is within a range of about 2 μm and about 6 μm.

[0023] In some embodiments, the first guard ring 101d includes a first guard sub-ring 101d-1 and a second guard sub-ring 101d-2. The first guard sub-ring 101d-1 extends across the second epitaxial sub-layer 101b-2, and the second guard sub-ring 101d-2 extends across the third epitaxial sub-layer 101b-3. The first guard sub-ring 101d-1 is above the first epitaxial sub-layer 101b-1, and the second guard sub-ring 101d-2 is above the first guard sub-ring 101d-1. In some embodiments, the first guard ring 101d also includes a third guard sub-ring (not shown) extending across the first epitaxial sub-layer 101b-1. The first guard sub-ring 101d-1 and the second guard sub-ring 101d-2 have the same conductivity type, for example, both are P-type. In some embodiments, the doping concentration of the first guard sub-ring 101d-1 is greater than the doping concentration of the second guard sub-ring 101d-2. In some embodiments, the first guard sub-ring 101d-1 and the second guard sub-ring 101d-2 have substantially the same doping concentration.

[0024] In some embodiments, the epitaxial layer 101b further includes a second guard ring 101f. The second guard ring 101f is disposed within the peripheral region 100b and extends across at least a portion of the epitaxial layer 101b to reduce the effects of surface electric fields. In some embodiments, the second guard ring 101f extends across at least a portion of the third epitaxial sublayer 101b-3. The second guard ring 101f is disposed between the doped channel 101c and the first guard ring 101d. The second guard ring 101f surrounds the first guard ring 101d and the cell region 100a. The second guard ring 101f and the first guard ring 101d have the same conductivity type, for example, both are P-type. The second guard ring 101f has an opposite conductivity type to that of the epitaxial layer 101b, for example, the second guard ring 101f is P-type and the epitaxial layer 101b is N-type.

[0025] In some embodiments, the doping concentration of the second guard ring 101f is lower than or equal to the doping concentration of the first guard ring 101d. In some embodiments, the height of the second guard ring 101f is substantially equal to or less than the thickness T3 of the third epitaxial sublayer 101b-3. In some embodiments, the height of the second guard ring 101f is equal to or less than approximately 2 μm. In some embodiments, the second guard ring 101f is a floating field limiting ring and is not electrically connected to circuits or components within the cell region 100a.

[0026] The epitaxial layer 101b also includes a doped region 101e, which is disposed within the cell region 100a and extends across at least a portion of the epitaxial layer 101b. The doped region 101e is the active area, upon which the electrode 104 is subsequently formed. In some embodiments, the doped region 101e is surrounded by a first guard ring 101d. The doped region 101e has an opposite conductivity type to that of the epitaxial layer 101b, for example, the doped region 101e is P-type and the epitaxial layer 101b is N-type. The doped region 101e has an opposite conductivity type to that of the doped channel 101c, for example, the doped region 101e is P-type and the doped channel 101c is N-type. The doped region 101e includes a P-type dopant, which may be, for example, boron, aluminum, gallium, or indium. The deeper the doped region 101e extends along the thickness of the epitaxial layer 101b, the further it can reduce the effects of the surface electric field, thereby reducing leakage current in the power semiconductor package 100. In some embodiments, the height of the doped region 101e is substantially equal to or less than the thickness of the epitaxial layer 101b. In some embodiments, the height of the doped region 101e is within a range of about 2 μm and about 6 μm.

[0027] The doped region 101e includes a first doped sub-region 101e-1 and a second doped sub-region 101e-2. The first doped sub-region 101e-1 extends across the second epitaxial sub-layer 101b-2, and the second doped sub-region 101e-2 extends across the third epitaxial sub-layer 101b-3. The first doped sub-region 101e-1 is above the first epitaxial sub-layer 101b-1, and the second doped sub-region 101e-2 is above the first doped sub-region 101e-1. In some embodiments, the doped region 101e also includes a third doped sub-region (not shown) extending across the first epitaxial sub-layer 101b-1. The first doped sub-region 101e-1 and the second doped sub-region 101e-2 have the same conductivity type, for example, both are P-type. The first guard ring 101d, the second guard ring 101f, and the doped region 101e have the same conductivity type, for example, both are P-type. In some embodiments, the first doped sub-region 101e-1 and the second doped sub-region 101e-2 have substantially the same doping concentration. In some embodiments, the doping concentration of the first doping sub-region 101e-1 is greater than the doping concentration of the second doping sub-region 101e-2.

[0028] The power semiconductor package 100 further includes a dielectric layer 102 disposed above the substrate 101. The dielectric layer 102 is disposed above the epitaxial layer 101b and surrounds at least a portion of the contact layer 103 and at least a portion of the electrode 104. In some embodiments, the dielectric layer 102 covers the second guard ring 101f and at least a portion of the first guard ring 101d. In some embodiments, the dielectric layer 102 comprises an insulating material such as an oxide, a nitride, or an oxynitride. In some embodiments, the dielectric layer 102 comprises silicon oxide. In some embodiments, the dielectric layer 102 is a field oxide.

[0029] The contact layer 103 includes a junction layer 103a and a barrier layer 103b. The junction layer 103a is disposed within the peripheral region 100b and above the epitaxial layer 101b. In some embodiments, at least a portion of the junction layer 103a is surrounded by the dielectric layer 102, and at least a portion of the junction layer 103a is above the dielectric layer 102. The junction layer 103a contacts at least a portion of the epitaxial layer 101b. The junction layer 103a contacts at least a portion of the doped channel 101c. In some embodiments, the junction layer 103a contacts the third doped sub-channel 101c-3. The doped channel 101c extends between the junction layer 103a and the substrate 101a. In some embodiments, an ohmic contact or a non-ohmic contact is formed between the junction layer 103a and the doped channel 101c, allowing current to flow from the junction layer 103a to the doped channel 101c, or vice versa. In some embodiments, the junction layer 103a comprises a metal material, such as aluminum (Al), copper (Cu), titanium (Ti), nickel (Ni), tungsten (W), molybdenum (Mo), etc. In some embodiments, the junction layer 103a has ohmic or non-ohmic properties.

[0030] The barrier layer 103b is disposed within the cell region 100a and above the epitaxial layer 101b. In some embodiments, at least a portion of the barrier layer 103b is surrounded by the dielectric layer 102, and at least a portion of the barrier layer 103b is above the dielectric layer 102. The barrier layer 103b contacts at least a portion of the epitaxial layer 101b. The doped region 101e extends between the barrier layer 103b and the substrate 101a. The barrier layer 103b contacts at least a portion of the doped region 101e. In some embodiments, the barrier layer 103b contacts the second doped sub-region 101e-2. In some embodiments, a Schottky contact or a non-ohmic contact is formed between the barrier layer 103b and the doped region 101e, thereby allowing current to flow from the barrier layer 103b to the doped region 101e. In some embodiments, current is substantially prevented from flowing from the doped region 101e to the barrier layer 103b. In some embodiments, the barrier layer 103b comprises a metal material, such as platinum (Pt), titanium (Ti), nickel (Ni), gold (Au), or the like. In some embodiments, the barrier layer 103b is non-ohmic. In some embodiments, the barrier layer 103b is a Schottky metal. The barrier layer 103b contacts at least a portion of the first guard ring 101d. In some embodiments, the barrier layer 103b contacts the second guard sub-ring 101d-2. The first guard ring 101d extends between the barrier layer 103b and the substrate 101a.

[0031] The electrode 104 includes a first electrode 104a and a second electrode 104b. The first electrode 104a is disposed on the bonding layer 103a, and the second electrode 104b is disposed on the barrier layer 103b. In some embodiments, the first electrode 104a and the second electrode 104b are both disposed on the upper side of the power semiconductor package 100. In some embodiments, the first electrode 104a and the second electrode 104b are both disposed on the same side of the power semiconductor package 100. The first electrode 104a is disposed within the peripheral region 100b, and the second electrode 104b is disposed within the cell region 100a. In some embodiments, at least a portion of the first electrode 104a and at least a portion of the second electrode 104b are surrounded by the dielectric layer 102, and at least a portion of the first electrode 104a and at least a portion of the second electrode 104b are above the dielectric layer 102. The first electrode 104a contacts at least a portion of the bonding layer 103a. The second electrode 104b contacts at least a portion of the barrier layer 103b. In some embodiments, the first electrode 104a and the second electrode 104b each include a conductive material, such as a metal material such as copper (Cu), silver (Ag), gold (Au), or the like. In some embodiments, current can flow from the substrate 101a through the doped channel 101c and the junction layer 103a to the first electrode 104a. In some embodiments, current can flow from the second electrode 104b through the doped region 101e and the barrier layer 103b to the substrate 101a. In some embodiments, current can flow from the second electrode 104b through the barrier layer 103b, the doped region 101e, the substrate 101a, the doped channel 101c, and the junction layer 103a to the first electrode 104a. In some embodiments, the first electrode 104a is a cathode or negative electrode, and the second electrode 104b is an anode or positive electrode.

[0032] The power semiconductor package 100 further includes a passivation layer 105 disposed over the dielectric layer 102, the first electrode 104a, and the second electrode 104b. In some embodiments, the passivation layer 105 comprises an insulating material, such as a polymer, polyimide (PI), an oxide, a nitride, an oxynitride, or the like. In some embodiments, at least a portion of the first electrode 104a and at least a portion of the second electrode 104b are exposed by the passivation layer 105. The dielectric layer 102 and the passivation layer 105 isolate the junction layer 103a and the first electrode 104a from the barrier layer 103b and the second electrode 104b.

[0033] The power semiconductor package 100 also includes a plurality of conductive bumps 106, which are respectively arranged above the electrodes 104. The plurality of conductive bumps 106 are surrounded by a passivation layer 105. In some embodiments, the conductive bumps 106 include a conductive material, such as tin, lead, silver, copper, nickel, etc. In some embodiments, the conductive bumps 106 are solder balls or tin balls. The conductive bumps 106 can be electrically connected to circuits or components outside the power semiconductor package 100, so that the power semiconductor package 100 can be electrically connected to the outside. In some embodiments, the plurality of conductive bumps 106 include a first conductive bump 106a and a second conductive bump 106b. The first conductive bump 106a is arranged in the peripheral area 100b, and the second conductive bump 106b is arranged in the cell area 100a. The first conductive bump 106a is arranged above the first electrode 104a, and the second conductive bump 106b is arranged above the second electrode 106b. In some embodiments, a first conductive bump 106a is disposed on at least a portion of the first electrode 104a exposed by the passivation layer 105, and a second conductive bump 106b is disposed on at least a portion of the second electrode 104b exposed by the passivation layer 105. The first conductive bump 106a is in electrical communication with the first electrode 104a, and the second conductive bump 106b is in electrical communication with the second electrode 104b. The first conductive bump 106a is isolated from the second conductive bump 106b by the passivation layer 105. In some embodiments, the power semiconductor package 100 does not include a plurality of conductive bumps 106. For example, the plurality of conductive bumps 106 are replaced by wirebonds that contact the electrodes 104.

[0034] The epitaxial layer 101b of the power semiconductor package 100 is formed by stacking multiple sub-epitaxial layers 101b-1, 101b-2, and 101b-3, so that the power semiconductor package 100 has a thicker epitaxial layer 101b, thereby reducing the leakage current of the power semiconductor package 100 and allowing the power semiconductor package 100 to be used in high voltage applications.

[0035] Figure 2 FIG2 is a cross-sectional view of another power semiconductor package 200 according to some embodiments of the present invention. Specifically, the power semiconductor package 200 has a similar Figure 1The power semiconductor package 100 shown differs in that the power semiconductor package 200 further includes a semiconductor component 107 disposed between and extending between the doped channel 101c and the substrate 101a. The semiconductor component 107 is surrounded by the substrate 101a and the epitaxial layer 101b, and extends through a portion of the epitaxial layer 101b. The semiconductor component 107 is disposed within the peripheral region 100b, with the doped channel 101c extending between the junction layer 103a and the semiconductor component 107. Current can flow from the substrate 101a through the semiconductor component 107, the doped channel 101c, and the junction layer 103a to the first electrode 104a. In some embodiments, the semiconductor component 107 comprises a semiconductor material, such as polysilicon. The semiconductor component 107 does not involve diffusion or ion implantation processes. Compared to the power semiconductor package 100 , the power semiconductor package 200 has a semiconductor component 107 that does not involve diffusion or ion implantation processes, thereby reducing the diffusion or ion implantation processes and thereby lowering the thermal budget of the power semiconductor package 200 and improving the reliability of the power semiconductor package 200 .

[0036] In some embodiments, semiconductor component 107 is surrounded by first epitaxial sublayer 101 b - 1 and extends through first epitaxial sublayer 101 b - 1. In some embodiments, height H3 of semiconductor component 107 is substantially less than or equal to height H1 of doped channel 101 c. In some embodiments, height H3 of semiconductor component 107 is substantially less than or equal to thickness T1 of first epitaxial sublayer 101 b - 1. In some embodiments, height H3 of semiconductor component 107 is approximately 2 μm.

[0037] In some embodiments, semiconductor component 107 is surrounded by first epitaxial sublayer 101b-1 and first epitaxial sublayer 101b-2, and extends through first epitaxial sublayer 101b-1 and first epitaxial sublayer 101b-2. In some embodiments, height H3 of semiconductor component 107 is substantially greater than or equal to height H1 of doped channel 101c. In some embodiments, height H3 of semiconductor component 107 is substantially greater than thickness T1 of first epitaxial sublayer 101b-1. In some embodiments, height H3 of semiconductor component 107 is substantially greater than thickness T2 of second epitaxial sublayer 101b-2. In some embodiments, height H3 of semiconductor component 107 is greater than 2 μm.

[0038] Figure 3 FIG2 is a cross-sectional view of another power semiconductor package 300 according to some embodiments of the present invention. Specifically, the power semiconductor package 300 has a similar Figure 2The power semiconductor package 200 shown differs in that the semiconductor component 107 comprises multiple components, at least a portion of the epitaxial layer 101b is located between two adjacent components, and at least a portion of the epitaxial layer 101b extends between the doped channel 101c and the substrate 101a and is surrounded by multiple components. In some embodiments, the height H3 of the semiconductor component 107 is substantially greater than or equal to the height H1 of the doped channel 101c. In some embodiments, the height H3 of the semiconductor component 107 is substantially equal to the thickness T1 of the first epitaxial sublayer 101b-1. In some embodiments, the thickness T1 of the first epitaxial sublayer 101b-1 is substantially greater than the thickness T2 of the second epitaxial sublayer 101b-2 or the thickness T3 of the third epitaxial sublayer 101b-3. In some embodiments, the height H3 of the semiconductor component 107 is substantially greater than or equal to 5 μm. Compared to the semiconductor components 107 in the power semiconductor package 200 , each semiconductor component 107 in the power semiconductor package 300 has a larger aspect ratio. The larger aspect ratio enables better uniformity when the semiconductor material is filled between the epitaxial layers 101 b , thereby forming better and more reliable semiconductor components 107 .

[0039] Figures 4 to 44 One or more stages in a method of manufacturing a power semiconductor package 100 according to some embodiments of the present disclosure are shown. At least some of these figures have been simplified to facilitate a better understanding of aspects of the present disclosure.

[0040] Reference Figures 4 and 5 , the manufacturing method includes forming a first epitaxial sublayer 101b-1 above a substrate 101a. Epitaxial growth is performed on the substrate 101a to form the first epitaxial sublayer 101b-1. In some embodiments, the substrate 101a and the first epitaxial sublayer 101b-1 have the same conductivity type doping, for example, the substrate 101a and the first epitaxial sublayer 101b-1 are both N-type. In some embodiments, ion implantation is performed simultaneously with the epitaxial growth to implant ions with N-type electrical properties, such as phosphorus (P) or arsenic (As), to form an N-type first epitaxial sublayer 101b-1. In some embodiments, the substrate 101a and the first epitaxial sublayer 101b-1 both include silicon carbide. In some embodiments, the first epitaxial sublayer 101b-1 has a thickness T1, and the thickness T1 is in the range of about 1.5 μm and about 2 μm.

[0041] Reference Figures 6 to 10 The manufacturing method includes implanting dopant ions into a portion of the first epitaxial sublayer 101b-1 to form a first doped sub-channel 101c-1. Figure 6A first patterned shielding layer 108 is formed on the first epitaxial sub-layer 101b-1 to define the position of the first doped sub-channel 101c-1. In some embodiments, the first patterned shielding layer 108 comprises a photoresist or an oxide. The first patterned shielding layer 108 has a first opening 108a. A portion of the first epitaxial sub-layer 101b-1 exposed in the first opening 108a forms the first doped sub-channel 101c-1. Figure 7 The first doped sub-channel 101c-1 can be formed by diffusion or ion implantation on the surface of the first epitaxial sub-layer 101b-1 exposed from the first opening 108a. The substrate 101a, the first epitaxial sub-layer 101b-1 and the first doped sub-channel 101c-1 have the same conductivity type. In some embodiments, dopant ions such as phosphorus ions, arsenic ions, etc. are implanted into the surface of the first epitaxial sub-layer 101b-1 exposed from the first opening 108a to form the first doped sub-channel 101c-1. Figure 8 After the diffusion or ion implantation process, the first patterned shielding layer 108 is removed. In some embodiments, the first patterned shielding layer 108 is subjected to an etching process, such as a plasma dry etching process, to remove the first patterned shielding layer 108. Figure 9 After removing the first patterned shielding layer 108, a first protective layer 109 is formed on the first epitaxial sub-layer 101b-1 to protect the first epitaxial sub-layer 101b-1 and the first doped sub-channel 101c-1 during the annealing process. In some embodiments, the first protective layer 109 comprises carbon. After forming the first protective layer 109, an annealing process is performed on the first doped sub-channel 101c-1, such as rapid thermal annealing (RTA) or laser annealing, to activate the doped ions in the first doped sub-channel 101c-1. Figure 10 After the annealing process, the first protection layer 109 may be removed by dry thermal oxidation, plasma dry etching or other etching processes.

[0042] Reference Figure 11The manufacturing method includes forming a second epitaxial sublayer 101b-2 above the first epitaxial sublayer 101b-1. Epitaxial growth is performed above the first epitaxial sublayer 101b-1 to form the second epitaxial sublayer 101b-2. In some embodiments, the substrate 101a, the first epitaxial sublayer 101b-1, and the second epitaxial sublayer 101b-2 have the same conductivity type doping, for example, the second epitaxial sublayer 101b-2 and the first epitaxial sublayer 101b-1 are both N-type. In some embodiments, ion implantation is performed simultaneously with the epitaxial growth to implant ions with N-type electrical properties, such as phosphorus (P) or arsenic (As), to form an N-type second epitaxial sublayer 101b-2. In some embodiments, the substrate 101a, the first epitaxial sublayer 101b-1, and the second epitaxial sublayer 101b-2 all include silicon carbide. In some embodiments, the second epitaxial sub-layer 101 b - 2 has a thickness T2 , the thickness T1 is substantially the same as the thickness T2 , and the thickness T2 is within a range of about 1.5 μm and about 2 μm.

[0043] Reference Figures 12 to 14 The manufacturing method includes implanting the doping ions into a portion of the second epitaxial sub-layer 101b-2 to form a second doped sub-channel 101c-2 above the first doped sub-channel 101c-1. Figure 12 A second patterned shielding layer 110 is formed on the second epitaxial sub-layer 101b-2 to define the position of the second doped sub-channel 101c-2. In some embodiments, the second patterned shielding layer 110 comprises a photoresist or an oxide. The second patterned shielding layer 110 has a second opening 110a. A portion of the second epitaxial sub-layer 101b-2 exposed in the second opening 110a forms the second doped sub-channel 101c-2. Figure 13 The second doped sub-channel 101c-2 can be formed by a diffusion or ion implantation process on the surface of the second epitaxial sub-layer 101b-2 exposed from the second opening 110a. The second epitaxial sub-layer 101b-2 and the second doped sub-channel 101c-2 have the same conductivity type. In some embodiments, dopant ions such as phosphorus ions, arsenic ions, etc. are implanted into the surface of the second epitaxial sub-layer 101b-2 exposed from the second opening 110a to form the second doped sub-channel 101c-2. In some embodiments, the doping concentration of the first doped sub-channel 101c-1 is greater than the doping concentration of the second doped sub-channel 101c-2.

[0044] Reference Figure 14 After the diffusion or ion implantation process, the second patterned shielding layer 110 is removed. In some embodiments, the second patterned shielding layer 110 is subjected to an etching process, such as a plasma dry etching process, to remove the second patterned shielding layer 110 .

[0045] In some embodiments, reference Figure 15 After removing the second patterned shielding layer 110, a third patterned shielding layer 111 is formed on the second epitaxial sub-layer 101b-2 to define the positions of the first guard sub-ring 101d-1 and the first doped sub-region 101e-1. In some embodiments, the third patterned shielding layer 111 comprises a photoresist or an oxide. The third patterned shielding layer 111 has a third opening 111a. The first guard sub-ring 101d-1 and the first doped sub-region 101e-1 are formed in a portion of the second epitaxial sub-layer 101b-2 exposed by the third opening 111a. Figure 16 , the first guard sub-ring 101d-1 and the first doped sub-region 101e-1 can be formed by diffusion or ion implantation on the surface of the second epitaxial sub-layer 101b-2 exposed from the third opening 111a. The first guard sub-ring 101d-1 and the first doped sub-region 101e-1 have the same conductivity type, for example, both are P-type. P-type dopants can be, for example, boron, aluminum, gallium, indium, etc. In some embodiments, dopant ions such as boron ions are implanted into the surface of the second epitaxial sub-layer 101b-2 exposed from the third opening 111a to form the first guard sub-ring 101d-1 and the first doped sub-region 101e-1. Refer to Figure 17 After the diffusion or ion implantation process, the third patterned shielding layer 111 is removed. In some embodiments, the third patterned shielding layer 111 is subjected to an etching process, such as a plasma dry etching process, to remove the third patterned shielding layer 111.

[0046] Reference Figure 18 After removing the third patterned shielding layer 111, a second protective layer 112 is formed on the second epitaxial sub-layer 101b-2 to protect the second epitaxial sub-layer 101b-2, the first guard sub-ring 101d-1, the first doped sub-region 101e-1 and the second doped sub-channel 101c-2 during the annealing process. After forming the second protective layer 112, an annealing process is performed on the first guard sub-ring 101d-1, the first doped sub-region 101e-1 and the second doped sub-channel 101c-2, such as rapid thermal annealing (RTA) or laser annealing, to activate the doped ions in the first guard sub-ring 101d-1, the first doped sub-region 101e-1 and the second doped sub-channel 101c-2. Figure 19 After the annealing process, an etching process, such as a plasma dry etching process, is performed on the second protection layer 112 to remove the second protection layer 112 .

[0047] In some embodiments, reference Figure 20The manufacturing method includes forming a third epitaxial sublayer 101b-3 above the second epitaxial sublayer 101b-2. Epitaxial growth is performed above the second epitaxial sublayer 101b-2 to form the third epitaxial sublayer 101b-3. In some embodiments, the substrate 101a, the first epitaxial sublayer 101b-1, the second epitaxial sublayer 101b-2, and the third epitaxial sublayer 101b-3 have the same conductivity type doping, for example, the first epitaxial sublayer 101b-1, the second epitaxial sublayer 101b-2, and the third epitaxial sublayer 101b-3 are all N-type. In some embodiments, ion implantation is performed simultaneously with the epitaxial growth to implant ions with N-type electrical properties, such as phosphorus (P) or arsenic (As), to form an N-type third epitaxial sublayer 101b-3. In some embodiments, substrate 101a, first epitaxial sublayer 101b-1, second epitaxial sublayer 101b-2, and third epitaxial sublayer 101b-3 all comprise silicon carbide. In some embodiments, third epitaxial sublayer 101b-3 has a thickness T3, wherein thicknesses T1, T2, and T3 are substantially the same, and thickness T3 is within a range of approximately 1.5 μm and approximately 2 μm. In some embodiments, first epitaxial sublayer 101b-1, second epitaxial sublayer 101b-2, and third epitaxial sublayer 101b-3 form epitaxial layer 101b, and substrate 101a and epitaxial layer 101b form base 101.

[0048] Reference Figures 21 to 23 The manufacturing method includes implanting dopant ions into a portion of the third epitaxial sublayer 101b-3 to form a third doped sub-channel 101c-3. Figure 21 A fourth patterned shielding layer 113 is formed on the third epitaxial sub-layer 101b-3 to define the position of the third doped sub-channel 101c-3. In some embodiments, the fourth patterned shielding layer 113 comprises a photoresist or an oxide. The fourth patterned shielding layer 113 has a fourth opening 113a. The portion of the third epitaxial sub-layer 101b-3 exposed by the fourth opening 113a forms the third doped sub-channel 101c-3. Figure 22 , the third doped sub-channel 101c-3 can be formed by diffusion or ion implantation through the surface of the third epitaxial sub-layer 101b-3 exposed from the fourth opening 113a. The substrate 101a, the first epitaxial sub-layer 101b-1, the first doped sub-channel 101c-1, the second epitaxial sub-layer 101b-2, the second doped sub-channel 101c-2, the third epitaxial sub-layer 101b-3 and the third doped sub-channel 101c-3 have the same conductivity type. In some embodiments, doping ions such as phosphorus ions, arsenic ions, etc. are implanted into the surface of the third epitaxial sub-layer 101b-3 exposed from the fourth opening 113a to form the third doped sub-channel 101c-3. Figure 23After the diffusion or ion implantation process, the fourth patterned shielding layer 113 is removed. In some embodiments, the fourth patterned shielding layer 113 is subjected to an etching process, such as a plasma dry etching process, to remove the fourth patterned shielding layer 113. In some embodiments, the first doped sub-channel 101c-1, the second doped sub-channel 101c-2, and the third doped sub-channel 101c-3 form a doped channel 101c. In some embodiments, the doping concentration of the first doped sub-channel 101c-1 is greater than the doping concentration of the second doped sub-channel 101c-2, and the doping concentration of the second doped sub-channel 101c-2 is greater than the doping concentration of the third doped sub-channel 101c-3. In some embodiments, the first doped sub-channel 101c-1, the second doped sub-channel 101c-2, and the third doped sub-channel 101c-3 have substantially the same doping concentration.

[0049] In some embodiments, reference Figure 24 After removing the fourth patterned shielding layer 113, a fifth patterned shielding layer 114 is formed on the third epitaxial sub-layer 101b-3 to define the positions of the second guard sub-ring 101d-2 and the second doped sub-region 101e-2. In some embodiments, the fifth patterned shielding layer 114 comprises a photoresist or an oxide. The fifth patterned shielding layer 114 has a fifth opening 114a. The portion of the third epitaxial sub-layer 101b-3 exposed by the fifth opening 114a forms the second guard sub-ring 101d-2 and the second doped sub-region 101e-2. Figure 25 , the second guard sub-ring 101d-2 and the second doped sub-region 101e-2 can be formed by diffusion or ion implantation process on the surface of the third epitaxial sub-layer 101b-3 exposed from the fifth opening 114a. The first guard sub-ring 101d-1, the second guard sub-ring 101d-2, the first doped sub-region 101e-1 and the second doped sub-region 101e-2 have the same conductivity type, for example, all are P-type. P-type dopants can be, for example, boron, aluminum, gallium, indium, etc. In some embodiments, doping ions such as boron ions are implanted into the surface of the third epitaxial sub-layer 101b-3 exposed from the fifth opening 114a to form the second guard sub-ring 101d-2 and the second doped sub-region 101e-2. Refer to Figure 26After the diffusion or ion implantation process, the fifth patterned shielding layer 114 is removed. In some embodiments, the fifth patterned shielding layer 114 is subjected to an etching process, such as a plasma dry etching process, to remove the fifth patterned shielding layer 114. In some embodiments, the first guard sub-ring 101d-1 and the second guard sub-ring 101d-2 form a first guard ring 101d, and the first doped sub-region 101e-1 and the second doped sub-region 101e-2 form a doped region 101e. In some embodiments, the doping concentration of the first doped sub-region 101e-1 is greater than the doping concentration of the second doped sub-region 101e-2. In some embodiments, the doping concentration of the first guard sub-ring 101d-1 is greater than the doping concentration of the second guard sub-ring 101d-2.

[0050] In some embodiments, reference Figure 27 After removing the fifth patterned shielding layer 114, a sixth patterned shielding layer 115 is formed on the third epitaxial sub-layer 101b-3 to define the position of the second guard ring 101f. In some embodiments, the sixth patterned shielding layer 115 comprises a photoresist or an oxide. The sixth patterned shielding layer 115 has a sixth opening 115a. The portion of the third epitaxial sub-layer 101b-3 exposed at the sixth opening 115a forms the second guard ring 101f. Figure 28 , the second guard ring 101f can be formed by diffusion or ion implantation on the surface of the third epitaxial sub-layer 101b-3 exposed from the sixth opening 115a. The first guard sub-ring 101d-1, the second guard sub-ring 101d-2 and the second guard ring 101f have the same conductivity type, for example, all are P-type. P-type dopants can be, for example, boron, aluminum, gallium, indium, etc. In some embodiments, dopant ions such as boron ions are implanted into the surface of the third epitaxial sub-layer 101b-3 exposed from the sixth opening 115a to form the second guard ring 101f. Figure 29 After the diffusion or ion implantation process, the sixth patterned shielding layer 115 is removed. In some embodiments, the sixth patterned shielding layer 115 is subjected to an etching process, such as a plasma dry etching process, to remove the sixth patterned shielding layer 115. In some embodiments, the doping concentration of the second guard ring 101f is lower than or equal to the doping concentration of the first guard sub-ring 101d-1. In some embodiments, the height of the second guard ring 101f is substantially equal to or less than the thickness T3 of the third epitaxial sub-layer 101b-3.

[0051] Reference Figure 30After removing the sixth patterned shielding layer 115, a third protective layer 116 is formed on the third epitaxial sub-layer 101b-3 to protect the third epitaxial sub-layer 101b-3, the second protective sub-ring 101d-2, the second doped sub-region 101e-2 and the third doped sub-channel 101c-3 during the annealing process. After forming the third protective layer 112, an annealing process is performed on the second protective sub-ring 101d-2, the second doped sub-region 101e-2 and the third doped sub-channel 101c-3, such as rapid thermal annealing (RTA) or laser annealing, to activate the doped ions in the second protective sub-ring 101d-2, the second doped sub-region 101e-2 and the third doped sub-channel 101c-3. Figure 31 After the annealing process, the third protection layer 116 is subjected to an etching process, such as a plasma dry etching process, to remove the third protection layer 116 .

[0052] In some embodiments, reference Figures 32 to 34 , a dielectric layer 102 is formed on the epitaxial layer 101b. Figure 32 , dielectric material 102' covers the epitaxial layer 101b, and a seventh patterned shielding layer 117 is formed on the dielectric material 102'. In some embodiments, the dielectric material 102' is formed by thermal oxidation or other deposition methods. In some embodiments, the dielectric material 102' comprises an oxide. In some embodiments, the seventh patterned shielding layer 117 comprises a photoresist or the like. The seventh patterned shielding layer 117 has a seventh opening 117a, and a portion of the dielectric material 102' is exposed in the seventh opening 117a. Figure 33 , a portion of the exposed dielectric material 102' is removed to form a dielectric layer 102. In some embodiments, the dielectric layer 102 is a field oxide. Figure 34 After forming the dielectric layer 102, the seventh patterned shielding layer 117 is removed. In some embodiments, the seventh patterned shielding layer 117 is subjected to an etching process, such as a plasma dry etching process, to remove the seventh patterned shielding layer 117.

[0053] In some embodiments, reference Figures 35 to 39 , a contact layer 103 and an electrode 104 are formed on the epitaxial layer 101b. In some embodiments, a junction layer 103a, a barrier layer 103b, a first electrode 104a, and a second electrode 104b partially surrounded by the dielectric layer 102 are formed on the third epitaxial sublayer 101b-3. Figure 35, the contact layer material 103' covers the epitaxial layer 101b and the dielectric layer 102. In some embodiments, the contact layer material 103' is covered on the epitaxial layer 101b and the dielectric layer 102 by electroplating, chemical vapor deposition (CVD) or other deposition methods. In some embodiments, the contact layer material 103' includes a metal material, such as aluminum (Al), copper (Cu), titanium (Ti), nickel (Ni), tungsten (W), molybdenum (Mo), platinum (Pt), gold (Au), etc. Figure 36 , the electrode material 104' is covered on the contact layer material 103'. In some embodiments, the electrode material 104' is covered on the contact layer material 103' by electroplating, chemical vapor deposition (CVD) or other deposition methods. In some embodiments, the electrode material 104' includes a conductive material, such as a metal material such as copper (Cu), silver (Ag), gold (Au), etc. Figure 37 After the electrode material 104' is covered, an eighth patterned shielding layer 118 is formed on the electrode material 104'. In some embodiments, the eighth patterned shielding layer 118 comprises a photoresist. The eighth patterned shielding layer 118 has an eighth opening 118a, and a portion of the electrode material 104' is exposed in the eighth opening 118a.

[0054] Reference Figure 38 , a portion of the exposed electrode material 104' is removed, and a portion of the contact layer material 103' exposed by the remaining electrode material 104' is removed, thereby forming the contact layer 103 and the electrode 104. In some embodiments, an etching process is performed on the portion of the exposed electrode material 104' and the portion of the contact layer material 103' exposed by the remaining electrode material 104' to remove the portion of the exposed electrode material 104' and the portion of the contact layer material 103' exposed by the remaining electrode material 104'. In some embodiments, the formed contact layer 103 includes a junction layer 103a and a barrier layer 103b, and the formed electrode 104 includes a first electrode 104a and a second electrode 104b. In some embodiments, the junction layer 103a is formed within the peripheral region 100b and above the doped channel 101c, and the first electrode 104a is formed above the junction layer 103a. In some embodiments, a barrier layer 103b is formed in the cell region 100a, above the doped region 101e and the guard ring 101d, and a second electrode 104b is formed above the barrier layer 103b. In some embodiments, the doped channel 101c extends between the junction layer 103a and the substrate 101a. Figure 39 After forming the contact layer 103 and the electrode 104, the eighth patterned shielding layer 118 is removed. In some embodiments, the eighth patterned shielding layer 118 is etched, such as by a plasma dry etching process, to remove the eighth patterned shielding layer 118.

[0055] In some embodiments, reference Figures 40 to 43 , a passivation layer 105 is formed on the dielectric layer 102, the first electrode 104a and the second electrode 104b. Figure 40 , the passivation layer material 105' covers the dielectric layer 102, the first electrode 104a and the second electrode 104b. In some embodiments, the passivation layer material 105' covers the dielectric layer 102, the first electrode 104a and the second electrode 104b by deposition or other methods. In some embodiments, the passivation layer material 105' includes an insulating material, such as a polymer, polyimide (PI), oxide, nitride, oxynitride, etc. Figure 41 After the passivation layer material 105' is covered, a ninth patterned shielding layer 119 is formed on the passivation layer material 105'. In some embodiments, the ninth patterned shielding layer 119 comprises a photoresist or the like. The ninth patterned shielding layer 119 has a ninth opening 119a, and a portion of the passivation layer material 105' is exposed in the ninth opening 119a. Figure 42 , a portion of the exposed passivation layer material 105' is removed to form a passivation layer 1054. In some embodiments, an etching process is performed on a portion of the exposed passivation layer material 105' to remove a portion of the exposed passivation layer material 105'. In some embodiments, at least a portion of the first electrode 104a and at least a portion of the second electrode 104b are exposed by the passivation layer 105. The junction layer 103a and the first electrode 104a are isolated from the barrier layer 103b and the second electrode 104b by the dielectric layer 102 and the passivation layer 105. Figure 43 After forming the passivation layer 105 , the ninth patterned shielding layer 119 is removed. In some embodiments, the ninth patterned shielding layer 118 is subjected to an etching process, such as a plasma dry etching process, to remove the ninth patterned shielding layer 119 .

[0056] In some embodiments, reference Figure 44, a plurality of conductive bumps 106 are formed above the electrode 104. In some embodiments, the conductive bumps 106 include a conductive material, such as tin, lead, silver, copper, nickel, etc. In some embodiments, the conductive bumps 106 are solder balls or tin balls. In some embodiments, the plurality of conductive bumps 106 include a first conductive bump 106a and a second conductive bump 106b. The first conductive bump 106a is formed in the peripheral area 100b, and the second conductive bump 106b is formed in the cell area 100a. The first conductive bump 106a is formed above the first electrode 104a, and the second conductive bump 106b is formed above the second electrode 106b. In some embodiments, the first conductive bump 106a is formed on at least a portion of the first electrode 104a exposed by the passivation layer 105, and the second conductive bump 106b is formed on at least a portion of the second electrode 104b exposed by the passivation layer 105. The first conductive bump 106a is isolated from the second conductive bump 106b by the passivation layer 105. Reference Figure 44 , forming Figure 1 The power semiconductor package 100 is shown. In some embodiments, the power semiconductor package 100 does not include the plurality of conductive bumps 106 . For example, the plurality of conductive bumps 106 are replaced by wirebonds that contact the electrodes 104 .

[0057] Figures 4 to 5 、 Figures 45 to 48 、 Figures 12 to 43 as well as Figure 49 Shown are one or more stages in a method of manufacturing a power semiconductor package 200 according to some embodiments of the present disclosure.

[0058] Reference Figures 4 and 5 The method for manufacturing the power semiconductor package 200 includes forming a first epitaxial sublayer 101b-1 on a substrate 101a. Epitaxial growth is performed on the substrate 101a to form the first epitaxial sublayer 101b-1. Figure 45 After forming the first epitaxial sub-layer 101b-1, a first patterned shielding layer 108 is formed on the first epitaxial sub-layer 101b-1 to define the position of the subsequently formed semiconductor component 107. In some embodiments, the first patterned shielding layer 108 has a first opening 108a, and the first opening 108a exposes a portion of the first epitaxial sub-layer 101b-1. Figure 46 , a portion of the exposed first epitaxial sublayer 101b-1 is removed to form a tenth opening 120, exposing a portion of the substrate 101a. In some embodiments, an etching process is performed on the exposed portion of the first epitaxial sublayer 101b-1 to remove the exposed portion of the first epitaxial sublayer 101b-1. Figure 47After forming the tenth opening 120, the first patterned shielding layer 108 is removed. In some embodiments, the first patterned shielding layer 108 is subjected to an etching process, such as a plasma dry etching process, to remove the first patterned shielding layer 108. Figure 48 , the tenth opening 120 is filled with semiconductor material to form a semiconductor component 107. The semiconductor component 107 can be formed by sputtering, physical vapor deposition (PVD) or other deposition methods. In some embodiments, the semiconductor component 107 includes a semiconductor material, such as polysilicon. After forming the semiconductor component 107, the semiconductor component 107 is subjected to a process similar to that described in the following example. Figures 12 to 43 Refer to the steps shown. Figures 12 to 43 Following the steps shown, refer to Figure 49 , forming Figure 2 The power semiconductor package 200 shown in FIG. A semiconductor component 107 is located between a substrate 101a and a doped channel 101c. The semiconductor component 107 is surrounded by the substrate 101a and the epitaxial layer 101b, and extends through a portion of the epitaxial layer 101b. The semiconductor component 107 is disposed within the peripheral region 100b, and the doped channel 101c extends between the junction layer 103a and the semiconductor component 107.

[0059] Figures 4 to 5 、 Figures 50 to 53 、 Figures 12 to 43 as well as Figure 54 Shown are one or more stages in a method of manufacturing a power semiconductor package 300 according to some embodiments of the present disclosure.

[0060] Reference Figures 4 and 5 The method for manufacturing the power semiconductor package 300 includes forming a first epitaxial sublayer 101b-1 on a substrate 101a. Epitaxial growth is performed on the substrate 101a to form the first epitaxial sublayer 101b-1. Figure 50 After forming the first epitaxial sublayer 101b-1, a first patterned shielding layer 108 is formed on the first epitaxial sublayer 101b-1 to define the positions of the multiple components of the subsequently formed semiconductor component 107. In some embodiments, the first patterned shielding layer 108 has a plurality of first openings 108a, and the plurality of first openings 108a expose multiple portions of the first epitaxial sublayer 101b-1. Figure 51 , removing the exposed portions of the first epitaxial sublayer 101b-1 to form a plurality of tenth openings 120, exposing portions of the substrate 101a. In some embodiments, an etching process is performed on the exposed portions of the first epitaxial sublayer 101b-1 to remove the exposed portions of the first epitaxial sublayer 101b-1. Figure 52After forming the plurality of tenth openings 120, the first patterned shielding layer 108 is removed. In some embodiments, the first patterned shielding layer 108 is subjected to an etching process, such as a plasma dry etching process, to remove the first patterned shielding layer 108. Figure 53 , filling the plurality of tenth openings 120 with semiconductor material to form a plurality of components of the semiconductor component 107. The plurality of components of the semiconductor component 107 may be formed by sputtering, physical vapor deposition (PVD), or other deposition methods. In some embodiments, each component of the semiconductor component 107 includes a semiconductor material, such as polysilicon. After forming the plurality of components of the semiconductor component 107, a reference is made to Figures 12 to 43 Refer to the steps shown. Figures 12 to 43 Following the steps shown, refer to Figure 54 , forming Figure 3 The power semiconductor package 300 shown in FIG. A semiconductor component 107 is disposed between a substrate 101a and a doped channel 101c. The semiconductor component 107 is surrounded by the substrate 101a and the epitaxial layer 101b, with each semiconductor component 107 extending through a portion of the epitaxial layer 101b. Each semiconductor component 107 is disposed within the peripheral region 100b, with the doped channel 101c extending between the junction layer 103a and multiple semiconductor components 107.

[0061] According to the structure and process of the present disclosure described above, under the same purpose and concept, the steps in the above process can be adjusted or replaced in sequence to achieve the same or similar semiconductor structure.

[0062] Spatially relative terms such as "below," "beneath," "lower," "above," "upper," "left," "right," etc. may be used herein for ease of description to describe the relationship of one component or feature to another or more components or features as shown in the accompanying drawings. Spatially relative terms are intended to encompass different orientations of the device when in use or operating, in addition to the orientation depicted in the accompanying drawings. The device can be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein should be interpreted accordingly. It should be understood that when a component is referred to as being "connected to" or "coupled to" another component, it can be directly connected to or coupled to the other component, or intervening components may be present.

[0063] As used herein, the terms "approximately," "substantially," "substantially," and "about" are used to describe and explain small variations. When used in conjunction with an event or situation, the terms may refer to instances where the event or situation occurs precisely as well as instances where the event or situation is close to occurring. As used herein with respect to a given value or range, the term "approximately" generally means within ±10%, ±5%, ±1%, or ±0.5% of the given value or range. Ranges may be expressed herein as from one endpoint to another or between two endpoints. All ranges disclosed herein include endpoints unless otherwise indicated. The term "substantially coplanar" may refer to a position difference between two surfaces positioned along the same plane that is within a few microns (μm), such as within 10 μm, within 5 μm, within 1 μm, or within 0.5 μm of the position difference positioned along the same plane. When a value or characteristic is referred to as being "substantially" the same, the term may refer to a value within ±10%, ±5%, ±1%, or ±0.5% of the average value of the value.

[0064] The foregoing summarizes the features of several embodiments and detailed aspects of the present disclosure. The embodiments described in this disclosure can be readily used as a basis for designing or modifying other processes and structures to carry out the same or similar purposes and / or achieve the same or similar advantages of the embodiments described herein. Such equivalent constructions do not depart from the spirit and scope of the present disclosure, and various changes, substitutions, and modifications may be made without departing from the spirit and scope of the present disclosure.

Claims

1. A power semiconductor package, comprising: A substrate, which defines a cell area and a peripheral area surrounding the cell area, and includes a substrate and an epitaxial layer located above the substrate; a junction layer disposed in the peripheral region and above the epitaxial layer; a barrier layer disposed in the cell region and above the epitaxial layer; a first electrode disposed on the junction layer; as well as a second electrode disposed on the barrier layer, The epitaxial layer includes a doped channel, which is arranged in the peripheral region and extends between the junction layer and the substrate. Current can flow from the substrate through the doped channel and the junction layer to the first electrode.

2. The power semiconductor package according to claim 1, wherein: The height of the doped channel is substantially equal to the thickness of the epitaxial layer.

3. The power semiconductor package according to claim 2, wherein: The height of the doped channel and the thickness of the epitaxial layer are in the range of about 2 μm and about 6 μm, respectively.

4. The power semiconductor package according to claim 1, wherein: The substrate includes silicon carbide (SiC).

5. The power semiconductor package according to claim 1, wherein: The substrate and the doped channel have the same conductivity type. The power semiconductor package according to claim 1 , wherein: The epitaxial layer includes a plurality of epitaxial sublayers stacked on each other, and the doped channel extends across the plurality of epitaxial sublayers.

7. The power semiconductor package according to claim 6, wherein: Each of the plurality of epitaxial sub-layers has substantially the same thickness as one another.

8. The power semiconductor package according to claim 1, wherein: The epitaxial layer includes a doped region disposed within the cell region and extending between the barrier layer and the substrate.

9. The power semiconductor package according to claim 8, wherein: The height of the doped region is substantially smaller than the height of the doped channel.

10. The power semiconductor package according to claim 8, wherein: The conductivity type of the doped region is opposite to the conductivity type of the doped channel.

11. The power semiconductor package according to claim 1, wherein: The junction layer is ohmic or non-ohmic, and the barrier layer is non-ohmic.

12. The power semiconductor package according to claim 1, further comprising: a dielectric layer over the epitaxial layer and surrounding at least a portion of the junction layer and at least a portion of the barrier layer; a passivation layer located above the dielectric layer, the first electrode, and the second electrode; A plurality of conductive bumps are correspondingly disposed above the first electrode or the second electrode.

13. The power semiconductor package according to claim 12, wherein: The junction layer and the first electrode are isolated from the barrier layer and the second electrode by the dielectric layer and the passivation layer.

14. A power semiconductor package, comprising: A substrate, which defines a cell area and a peripheral area surrounding the cell area, and includes a substrate and an epitaxial layer located above the substrate; a semiconductor component surrounded by the substrate and the epitaxial layer; a junction layer disposed in the peripheral region and above the epitaxial layer; as well as A first electrode is provided on the junction layer, The epitaxial layer includes a doped channel disposed in the peripheral region and extending between the junction layer and the semiconductor component, and current can flow from the substrate through the semiconductor component, the doped channel and the junction layer to the first electrode.

15. The power semiconductor package according to claim 14, wherein: The semiconductor component includes polysilicon.

16. The power semiconductor package according to claim 14, wherein: The height of the epitaxial layer is substantially greater than 5 μm.

17. The power semiconductor package according to claim 14, wherein: The height of the semiconductor member is substantially smaller than the height of the doped channel.

18. The power semiconductor package according to claim 17, wherein: The height of the semiconductor component is about 2 μm.

19. The power semiconductor package according to claim 14, wherein: A portion of the epitaxial layer extends between the doped channel and the substrate and is surrounded by the semiconductor member.

20. The power semiconductor package according to claim 14, wherein The height of the semiconductor member is substantially greater than or equal to the height of the doped channel.

21. The power semiconductor package according to claim 20, wherein: The height of the semiconductor component is substantially greater than 5 μm.

22. A method for manufacturing a power semiconductor package, comprising: forming a first epitaxial sublayer over the substrate; implanting dopant ions into a portion of the first epitaxial sublayer to form a first doped sub-channel; forming a second epitaxial sublayer above the first epitaxial sublayer; implanting the dopant ions into a portion of the second epitaxial sublayer to form a second doped sub-channel above the first doped sub-channel; forming a junction layer above the second doped sub-channel; as well as forming a first electrode on the junction layer, A doped channel including the first doped sub-channel and the second doped sub-channel is formed, and the doped channel extends between the junction layer and the substrate.

23. The method according to claim 22, before forming the first epitaxial sub-layer, further comprising: forming a third epitaxial sublayer over the substrate; removing a portion of the third sub-epitaxial layer to form an opening; A semiconductor material is filled into the opening to form a semiconductor component.

24. The method according to claim 23, wherein The semiconductor component is disposed between the substrate and the doped channel.

25. The method according to claim 23, wherein The thickness of the third epitaxial sublayer is substantially greater than or equal to the thickness of the first epitaxial sublayer, or the thickness of the third epitaxial sublayer is substantially greater than or equal to the thickness of the second epitaxial sublayer. 26 . The method of claim 22 , further comprising activating the first doped sub-channel by annealing before forming the second epitaxial sub-layer and implanting the dopant ions into the portion of the second epitaxial sub-layer.

Images