FDSOI device and manufacturing method thereof
By etching the gate trench in the FDSOI device, deposition of gate material and forming the source and drain, the problem of insufficient operating current of the FDSOI device is solved, and the effect of greater current and lower leakage current is achieved.
Patent Information
- Application Number
- CN202411190620.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-28
- Publication Date
- 2025-08-05
AI Technical Summary
Since the ultra-thin top-layer silicon is used as a conductive channel, FDSOI devices cannot achieve a large operating current, limiting their application in high-performance scenarios.
By etching the SOI wafer, forming a gate trench, depositing the gate material and covering the top silicon surface, etching the non-gate region to form a gate, the gate contacts the base silicon, and ion implantation on the SOI wafer surface to form a source and drain, adding new conductive channels.
It increases the operating current of the device, and reduces the leakage current in the off-state, improving the performance and control capabilities of the device.
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Figure CN120435018A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor technology, and in particular to an FDSOI device and a method for manufacturing the same. Background Art
[0002] With the development of semiconductor technology, the size of transistors is getting smaller and smaller. In order to cope with the challenges brought by problems such as short channel effects, fully depleted silicon-on-insulator (FDSOI) devices came into being.
[0003] FDSOI devices, with their unique buried oxide layer and ultra-thin top silicon technology, achieve low leakage current, significantly reducing static power consumption. They are widely used in low-power devices that require long-term operation, such as the Internet of Things (IoT) and portable electronic devices. However, due to the ultra-thin top silicon used as the conductive channel in FDSOI devices, they cannot achieve high operating currents, which greatly limits their application in high-performance scenarios.
[0004] Therefore, how to increase the operating current of FDSOI devices becomes a problem that needs to be solved. Summary of the Invention
[0005] Based on the above problems, the present application provides an FDSOI device and a manufacturing method thereof, which can improve the operating current of the FDSOI device.
[0006] The embodiments of this application disclose the following technical solutions:
[0007] In a first aspect, an embodiment of the present application provides a method for manufacturing an FDSOI device, the method comprising:
[0008] Providing an SOI wafer; the SOI wafer includes a base silicon, a buried oxide layer and a top silicon layer stacked in sequence;
[0009] Etching the top silicon layer and buried oxide layer of the SOI wafer to form a gate trench;
[0010] Depositing a gate material to obtain a gate material layer; the gate material fills the gate trench and covers the top silicon surface;
[0011] Etching the gate material layer in the non-gate region to obtain a gate; the non-gate region is located on both sides of the gate, and the arrangement direction of the non-gate region and the gate is parallel to the extension direction of the gate trench;
[0012] Ion implantation is performed on the exposed area on the surface of the SOI wafer to form a source and a drain.
[0013] Optionally, etching the top silicon layer and the buried oxide layer of the SOI wafer to form a gate trench includes:
[0014] The top silicon layer and the buried oxide layer of the SOI wafer are etched to form a plurality of parallel gate trenches.
[0015] Optionally, etching the top silicon layer and the buried oxide layer of the SOI wafer to form a gate trench includes:
[0016] forming a hard mask on a surface of a top silicon layer in the SOI wafer;
[0017] Under the mask of the hard mask, dry-etching the top silicon layer and the buried oxide layer in the SOI wafer to form a gate trench;
[0018] The hard mask is removed.
[0019] Optionally, depositing a gate material to obtain a gate material layer includes:
[0020] Metal material is deposited by various isotropic deposition techniques to form a gate material layer that fills the gate trench and covers the surface of the top silicon layer.
[0021] Optionally, before depositing the gate material to obtain the gate material layer, the method further comprises:
[0022] Depositing a high dielectric constant material to form a dielectric layer; the dielectric layer covers the top silicon surface of the SOI wafer and the sidewalls and bottom surface of the gate trench;
[0023] The etching of the gate material layer in the non-gate region to obtain the gate comprises:
[0024] The gate material layer and the dielectric layer in the non-gate area are etched to obtain a gate.
[0025] Optionally, after etching the gate material layer in the non-gate region to obtain the gate, the method further includes:
[0026] depositing a nitride layer, wherein the thickness of the nitride layer is greater than or equal to the thickness of the gate;
[0027] The nitride layer is etched to obtain a sidewall spacer attached to the sidewall of the gate.
[0028] Optionally, the nitride layer is a silicon nitride layer.
[0029] In a second aspect, an embodiment of the present application provides an FDSOI device, the device comprising: an SOI wafer and a gate;
[0030] The surface of the SOI wafer has a gate trench; the gate trench penetrates the top silicon layer and the buried oxide layer in the SOI wafer, and the bottom of the gate trench is the base silicon in the SOI wafer;
[0031] The gate is located on the top silicon surface of the SOI wafer and fills the gate trench;
[0032] The exposed areas of the SOI wafer on both sides of the gate are the source and drain formed by ion doping.
[0033] Optionally, the device further includes: a nitride sidewall spacer covering the gate sidewall.
[0034] Optionally, the device further includes: a dielectric layer located between the gate and the SOI wafer; the dielectric layer is made of a high dielectric constant material.
[0035] Compared with the existing technology, this application has the following beneficial effects:
[0036] The embodiment of the present application provides a method for manufacturing an FDSOI device, in which, first, an SOI wafer is provided; the SOI wafer includes a base silicon, a buried oxide layer, and a top silicon stacked in sequence; then, the top silicon and buried oxide layer of the SOI wafer are etched to form a gate trench; then, a gate material is deposited to obtain a gate material layer; the gate material fills the gate trench and covers the top silicon surface; then, the gate material layer in the non-gate area is etched to obtain a gate; the non-gate area is located on both sides of the gate, and the arrangement direction of the non-gate area and the gate is parallel to the extension direction of the gate trench; finally, ion implantation is performed on the exposed area of the SOI wafer surface to form a source and a drain. Thus, the gate contacts the base silicon, and the base silicon can also serve as a conductive channel, adding a new conductive channel, thereby increasing the operating current of the device. In addition, the surface of the top silicon in the SOI wafer facing away from the base silicon and the side surface of the top silicon in the gate trench are both in contact with the gate, the contact area between the gate and the top silicon becomes larger, and the gate's control ability over the top silicon channel is enhanced, while increasing the channel current, it can also reduce the leakage current of the device in the off state. BRIEF DESCRIPTION OF THE DRAWINGS
[0037] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.
[0038] Figure 1 A flow chart of a method for manufacturing an FDSOI device provided in an embodiment of the present application;
[0039] Figure 2 A structural diagram of an FDSOI device manufacturing process provided in an embodiment of the present application;
[0040] Figure 3 A schematic diagram of the channel position in an FDSOI device provided in an embodiment of the present application;
[0041] Figure 4 A flow chart of another method for manufacturing an FDSOI device provided in an embodiment of the present application;
[0042] Figure 5 A structural diagram of an FDSOI device with a dielectric layer provided in an embodiment of the present application;
[0043] Figure 6 A structural diagram of an FDSOI device with sidewalls provided in an embodiment of the present application;
[0044] Figure 7 A structural diagram of an FDSOI device provided in an embodiment of the present application. DETAILED DESCRIPTION
[0045] The FDSOI device and the manufacturing method thereof provided in the present application can be used in the semiconductor field. The above is only an example and does not limit the application field of the FDSOI device and the manufacturing method thereof provided in the present application.
[0046] The terms "first" and "second" and the like in the specification, claims and drawings of this application are used to distinguish different objects rather than to limit a specific order.
[0047] In the embodiments of this application, words such as "as an example" or "for example" are used to indicate examples, illustrations, or explanations. Any embodiment or design described in the embodiments of this application as "as an example" or "for example" should not be interpreted as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "as an example" or "for example" is intended to present the relevant concepts in a concrete manner.
[0048] The terms used in the implementation section of this application are only used to explain the specific embodiments of this application and are not intended to limit this application.
[0049] Because fully depleted silicon-on-insulator (FDSOI) devices can effectively address short-channel effects, they can better meet current demands for low power consumption, radio frequency communications, and low costs, and have been widely used in low-power devices. However, as mentioned earlier, FDSOI devices use an ultra-thin top layer of silicon as a conductive channel. Due to the ultra-thin conductive channel, FDSOI devices cannot achieve high operating currents, which greatly limits their application in high-performance scenarios.
[0050] In view of this, an embodiment of the present application provides a method for manufacturing an FDSOI device, in which, first, an SOI wafer is provided; the SOI wafer includes a base silicon, a buried oxide layer and a top silicon stacked in sequence; then, the top silicon and the buried oxide layer of the SOI wafer are etched to form a gate trench; then, a gate material is deposited to obtain a gate material layer; the gate material fills the gate trench and covers the surface of the top silicon; then, the gate material layer in the non-gate area is etched to obtain a gate; the non-gate area is located on both sides of the gate, and the arrangement direction of the non-gate area and the gate is parallel to the extension direction of the gate trench; finally, ion implantation is performed on the exposed area on the surface of the SOI wafer to form a source and a drain.
[0051] In the resulting FDSOI device, the gate contacts the base silicon, which also serves as a conductive channel. This creates a new conductive channel, thereby increasing the device's operating current. Furthermore, the surface of the top silicon in the SOI wafer facing away from the base silicon and the side surface of the top silicon in the gate trench are both in contact with the gate. This increases the contact area between the gate and the top silicon, enhancing the gate's ability to control the top silicon channel. This increases the channel current while also reducing the device's leakage current in the off state.
[0052] In order to help those skilled in the art better understand the present invention, the following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of this application.
[0053] See also Figure 1 , which is a flow chart of a method for manufacturing an FDSOI device provided in an embodiment of the present application, the method comprising:
[0054] S101: Provide an SOI wafer.
[0055] SOI (Silicon-On-Insulator) wafers include base silicon, buried oxide (BOX) and top silicon stacked in sequence, such as Figure 2 As shown in (A), the buried oxide layer may be a silicon oxide layer. As an example, an SOI wafer may be produced by bonding a silicon substrate having a buried oxide layer to another silicon substrate.
[0056] S102: Etching the top silicon layer and buried oxide layer of the SOI wafer to form a gate trench.
[0057] Alternatively, under the masking effect of a hard mask or photoresist, the top silicon and buried oxide layers of the SOI wafer can be dry-etched using methods such as reactive ion etching or plasma etching to remove the top silicon and buried oxide layers in areas not covered by the mask, thereby forming a gate trench. During the buried oxide etching process, the etch depth must be precisely controlled to avoid over-etching and damaging the underlying silicon. After the gate trench is formed, the mask is removed.
[0058] Alternatively, as Figure 2 As shown in (B), the mask pattern can be modified to create multiple parallel rectangular gaps within a single pattern unit. Using the modified mask, the top silicon and buried oxide layers of the SOI wafer are etched to form multiple parallel gate trenches. This increases the contact area between the gate and the top silicon, enhancing the gate's control over the top silicon channel. Varying the gate voltage effectively modulates the carrier concentration in the channel, increasing the channel current while also effectively suppressing the carrier concentration even at low gate voltages, thereby reducing the device's off-state leakage current.
[0059] S103: depositing a gate material to obtain a gate material layer.
[0060] As an example, Figure 2 As shown in (C), gate material deposition can be performed by various isotropic deposition techniques such as chemical vapor deposition, atomic layer deposition, physical vapor deposition, or radio frequency sputtering physical vapor deposition, so that the gate material fills the gate trench and covers the top silicon surface to form a gate material layer.
[0061] Among them, the gate material can be any one of the metal materials such as titanium, tantalum, nickel and platinum, or an alloy material formed by multiple metals such as titanium, tantalum, nickel and platinum, or a metal nitride such as titanium nitride or tantalum nitride, or a composite material formed by stacking metals and metal nitrides.
[0062] S104: Etching the gate material layer in the non-gate area to obtain a gate.
[0063] Specifically, if Figure 2 As shown in (D), the non-gate region is located on both sides of the gate, and the arrangement direction of the non-gate region and the gate is parallel to the extension direction of the gate trench.
[0064] As an example, the gate material layer in the non-gate region may be etched by dry etching until the top silicon layer in the SOI wafer and the base silicon layer at the bottom of the gate trench are exposed.
[0065] Therefore, if Figure 3 As shown, the surface of the top silicon in the SOI wafer facing away from the base silicon and the side surface of the top silicon in the gate trench are both in contact with the gate. This increases the contact area between the gate and the top silicon, enhancing the gate's control over the top silicon, or Channel 1. This increases the channel current while also reducing the device's leakage current in the off state. Furthermore, the gate contacts the base silicon, which also serves as a conductive channel, adding a new conductive channel, Channel 2, thereby increasing the device's operating current.
[0066] S105: Ion implantation is performed on the exposed area of the SOI wafer surface to form a source and a drain.
[0067] Specifically, N-type or P-type ion implantation can be performed on the exposed area of the SOI wafer surface, that is, the non-gate area in this embodiment, to form a source electrode on one side of the gate and a drain electrode on the other side of the gate, thereby obtaining an FDSOI device. The source electrode is responsible for injecting carriers into the channel, and the drain electrode is responsible for collecting carriers from the channel.
[0068] Therefore, in an embodiment of the present application, first, an SOI wafer is provided; the SOI wafer includes a base silicon, a buried oxide layer, and a top silicon stacked in sequence; then, the top silicon and buried oxide layer of the SOI wafer are etched to form a gate trench; then, a gate material is deposited to obtain a gate material layer; the gate material fills the gate trench and covers the surface of the top silicon; then, the gate material layer in the non-gate area is etched to obtain a gate; the non-gate area is located on both sides of the gate, and the arrangement direction of the non-gate area and the gate is parallel to the extension direction of the gate trench; finally, ion implantation is performed on the exposed area of the SOI wafer surface to form a source and a drain. Thus, the gate contacts the base silicon, and the base silicon can also serve as a conductive channel, adding a new conductive channel, thereby increasing the operating current of the device in the on state. In addition, the surface of the top silicon in the SOI wafer facing away from the base silicon and the side surface of the top silicon in the gate trench are both in contact with the gate, the contact area between the gate and the top silicon becomes larger, and the gate's control ability over the top silicon channel is enhanced, while increasing the channel current, it can also reduce the leakage current of the device in the off state.
[0069] Compared with GAA (Gate-All-Around) structure devices in which the gate completely surrounds the channel material, the manufacturing method of the FDSOI device provided in this embodiment can produce an FDSOI device with strong gate control capability using a simple process flow. While increasing the operating current of the FDSOI device in the on state and reducing the leakage current of the FDSOI device in the off state, it maintains a low production cost, which is conducive to the expansion of the application scenarios of FDSOI devices.
[0070] See also Figure 4 , which is a flow chart of another method for manufacturing an FDSOI device provided in an embodiment of the present application, the method comprising:
[0071] S401: Provide an SOI wafer.
[0072] S402: forming a hard mask on the surface of the top silicon layer in the SOI wafer.
[0073] As an example, a layer of hard mask material can be deposited on the surface of the top silicon in the SOI wafer by a process method such as chemical vapor deposition to form a mask layer; wherein the hard mask material can include but is not limited to materials such as silicon nitride, silicon oxide and silicon carbide; then, a photoresist is coated on the mask layer, and the desired pattern is transferred to the photoresist by photolithography technology; wherein the desired pattern is a non-gate trench area pattern, for example, a pattern with a rectangular gap; then, the mask layer can be etched by a dry etching technology such as reactive ion etching or plasma etching to form a hard mask.
[0074] S403: Under the mask of the hard mask, dry-etch the top silicon layer and the buried oxide layer in the SOI wafer to form a plurality of parallel gate trenches.
[0075] For example, the base silicon of the SOI wafer can be used as an etch stop layer, and the top silicon and buried oxide layer of the SOI wafer can be dry-etched using methods such as reactive ion etching or plasma etching. Under the cover of a hard mask, sidewall tilt and bottom deformation in the gate trench can be reduced, forming multiple parallel gate trenches with high etching profile accuracy. This allows for multi-gate control of the top silicon, enhancing the gate's ability to control the conductive channel.
[0076] S404: removing the hard mask.
[0077] Alternatively, the hard mask can be removed by dry etching or wet etching. For example, a solution with a high selectivity for etching the hard mask can be used for wet etching to remove the hard mask. Alternatively, reactive ion etching can be used using a reactive gas with a high selectivity for etching the hard mask to remove the hard mask. Alternatively, dry etching using plasma etching can be used to remove the hard mask.
[0078] S405: depositing a high dielectric constant material to form a dielectric layer.
[0079] Specifically, if Figure 5 As shown, the dielectric layer covers the top silicon surface of the SOI wafer and the sidewalls and bottom of the gate trench. The high-K dielectric material may include, but is not limited to, one or more combinations of hafnium silicate (HfSiO), hafnium oxide (HfO2), lanthanum oxide (LaOx), zirconium oxide (ZrO2), aluminum oxide (Al2O3), and hafnium zirconium oxide (HfZrO).
[0080] Using high dielectric constant materials as the insulating dielectric layer can provide greater capacitance at the same physical thickness, reduce gate leakage current, help reduce power consumption, and improve the performance of FDSOI devices.
[0081] S406: Depositing metal material by isotropic deposition technology to form a gate material layer that fills the gate trench and covers the surface of the top silicon layer.
[0082] Specifically, selecting a metal material as the gate material can provide more accurate work function matching, which helps to improve the gate's control capability over the channel.
[0083] Optionally, a back gate covering the substrate silicon surface can be formed by depositing the gate material using various isotropic deposition techniques. Thus, the threshold voltage of the FDSOI device can be adjusted by applying a voltage to the back gate, thereby optimizing the performance of the FDSOI device under different operating conditions. For example, in low-power mode, a negative back gate voltage can be applied to reduce leakage current; in high-performance mode, a positive back gate voltage can be applied to increase current driving capability.
[0084] S407: Etching the gate material layer and the dielectric layer in the non-gate area to obtain a gate.
[0085] As an example, the gate material layer and dielectric layer in the non-gate area can be etched by dry etching technology until the top silicon of the SOI wafer and the sidewalls and bottom surfaces of the gate trench in the non-gate area are exposed, thereby obtaining a gate spanning multiple gate trenches.
[0086] Optionally, the gate material layer in the non-gate region may be etched first by dry etching technology, and then the dielectric layer in the non-gate region may be etched by isotropic wet etching technology.
[0087] S408: depositing a nitride layer.
[0088] Specifically, the nitride layer may be deposited by an isotropic deposition method, such as chemical vapor deposition, and the thickness of the deposited nitride layer is greater than or equal to the thickness of the gate. The nitride layer may be a silicon nitride layer.
[0089] Optionally, before depositing the nitride layer, photoresist can be coated on the top of the gate, and after depositing the nitride layer, the nitride layer on the top of the gate can be removed by stripping using physical or chemical methods; or after depositing the nitride layer, the nitride layer on the top of the gate can be removed by dry etching or wet etching.
[0090] S409: etching the nitride layer to obtain a sidewall spacer attached to the gate sidewall.
[0091] As an example, dry etching can be used to retain a nitride layer of a preset width on the gate sidewall as a sidewall, and remove the remaining nitride layer on the SOI wafer, such as Figure 6 .
[0092] As a result, the gate can be isolated from the source and drain by the sidewall, which helps to reduce the parasitic capacitance between the gate and the source and drain, thereby improving the performance of the FDSOI device.
[0093] S410: Ion implantation is performed on the exposed area of the SOI wafer surface to form a source and a drain.
[0094] See also Figure 7 , this figure is a structural diagram of an FDSOI device provided in an embodiment of the present application, and the device includes: an SOI wafer and a gate.
[0095] Among them, the surface of the SOI wafer has a gate trench; the gate trench penetrates the top silicon and buried oxide layer in the SOI wafer, and the bottom of the gate trench is the base silicon in the SOI wafer.
[0096] The gate is located on the top silicon surface of the SOI wafer and fills the gate trench.
[0097] The exposed areas of the SOI wafer on both sides of the gate are ion-doped to form the source and drain.
[0098] As a result, the gate contacts the base silicon, which can also serve as a conductive channel, adding a new conductive channel, thereby increasing the operating current of the device. In addition, the surface of the top silicon in the SOI wafer facing away from the base silicon and the side surface of the top silicon in the gate trench are both in contact with the gate, increasing the contact area between the gate and the top silicon. The gate's ability to control the top silicon conductive channel is enhanced, while increasing the channel current and reducing the leakage current of the device in the off state.
[0099] Optionally, the surface of the SOI wafer has a plurality of parallel gate trenches.
[0100] Optionally, the FDSOI device further has a nitride sidewall spacer covering the gate sidewall.
[0101] Optionally, the FDSOI device further comprises a dielectric layer located between the gate and the SOI wafer; the dielectric layer is made of a high dielectric constant material.
[0102] It should be noted that the various embodiments in this specification are described in a progressive manner. Similar parts between the various embodiments can be referred to in conjunction with each other. Each embodiment focuses on the differences from other embodiments. In particular, the device embodiment is described in a relatively simple manner because it is basically similar to the method embodiment. Part or all of the structures can be selected according to actual needs to achieve the purpose of the present embodiment. For relevant parts, refer to the partial description of the method embodiment. A person of ordinary skill in the art can understand and implement the present invention without inventive effort.
[0103] The above is merely one specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.
Claims
1. A method for manufacturing an FDSOI device, characterized in that: The method comprises: Providing an SOI wafer; the SOI wafer includes a base silicon, a buried oxide layer and a top silicon layer stacked in sequence; Etching the top silicon layer and buried oxide layer of the SOI wafer to form a gate trench; Depositing a gate material to obtain a gate material layer; the gate material fills the gate trench and covers the top silicon surface; Etching the gate material layer in the non-gate region to obtain a gate; the non-gate region is located on both sides of the gate, and the arrangement direction of the non-gate region and the gate is parallel to the extension direction of the gate trench; Ion implantation is performed on the exposed area on the surface of the SOI wafer to form a source and a drain.
2. The method according to claim 1, characterized in that The etching of the top silicon layer and the buried oxide layer of the SOI wafer to form a gate trench comprises: The top silicon layer and the buried oxide layer of the SOI wafer are etched to form a plurality of parallel gate trenches.
3. The method according to claim 1, characterized in that The etching of the top silicon layer and the buried oxide layer of the SOI wafer to form a gate trench comprises: forming a hard mask on a surface of a top silicon layer in the SOI wafer; Under the mask of the hard mask, dry-etching the top silicon layer and the buried oxide layer in the SOI wafer to form a gate trench; The hard mask is removed.
4. The method according to claim 1, wherein The step of depositing the gate material to obtain the gate material layer comprises: Metal material is deposited by various isotropic deposition techniques to form a gate material layer that fills the gate trench and covers the surface of the top silicon layer.
5. The method according to claim 1, wherein Before depositing the gate material to obtain the gate material layer, the method further includes: Depositing a high dielectric constant material to form a dielectric layer; the dielectric layer covers the top silicon surface of the SOI wafer and the sidewalls and bottom surface of the gate trench; The etching of the gate material layer in the non-gate region to obtain the gate comprises: The gate material layer and the dielectric layer in the non-gate area are etched to obtain a gate.
6. The method according to claim 1, characterized in that After etching the gate material layer in the non-gate region to obtain the gate, the method further includes: depositing a nitride layer, wherein the thickness of the nitride layer is greater than or equal to the thickness of the gate; The nitride layer is etched to obtain a sidewall spacer attached to the sidewall of the gate.
7. The method according to claim 6, characterized in that The nitride layer is a silicon nitride layer.
8. An FDSOI device, characterized in that: The device includes: an SOI wafer and a gate; The surface of the SOI wafer has a gate trench; the gate trench penetrates the top silicon layer and the buried oxide layer in the SOI wafer, and the bottom of the gate trench is the base silicon in the SOI wafer; The gate is located on the top silicon surface of the SOI wafer and fills the gate trench; The exposed areas of the SOI wafer on both sides of the gate are ion-doped to form a source and a drain.
9. The device according to claim 8, characterized in that The device further includes: a nitride sidewall spacer covering the gate sidewall.
10. The device according to claim 8, characterized in that The device further comprises: a dielectric layer located between the gate and the SOI wafer; the dielectric layer is made of a high dielectric constant material.