Fabrication method of laterally diffused metal oxide semiconductor field effect transistor and laterally diffused metal oxide semiconductor field effect transistor
By setting the P+ region in the source/substrate region and adjusting the contact window length, the current concentration problem of lateral diffusion metal oxide semiconductor field effect transistors is solved, the voltage and current tolerance are improved, and the manufacturing cost is reduced.
Patent Information
- Application Number
- CN202510084465.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2024-02-02
- Filing Date
- 2025-01-20
- Publication Date
- 2025-08-05
AI Technical Summary
Existing lateral diffusion metal oxide semiconductor field effect transistors are prone to burn at high voltages, and the concentration of current leads to insufficient voltage and current tolerance.
Set the P+ region at the end area of the source/substrate region, and set the lengths of the source/substrate contact window and drain contact window to the same, increasing the ratio of P+/N+, and by setting the P+ region in the source/substrate region and shortening the P+ region spacing, multiple current release paths are provided to improve the uniformity of current distribution.
The voltage and current bearing capacity of the transistor is improved, burned due to current concentration is avoided, and the manufacturing cost of the integrated circuit is reduced.
Smart Images
Figure CN120435019A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a technology of an integrated circuit manufacturing process, and particularly to a manufacturing method of a lateral diffused metal oxide semiconductor field effect transistor and a lateral diffused metal oxide semiconductor field effect transistor using this manufacturing method. Background Art
[0002] A lateral diffused metal oxide semiconductor field effect transistor (LDMOS) is a common power semiconductor device, usually used in high-frequency radio frequency (RF) and high-power amplifier applications, such as wireless communication and broadcasting. A lateral diffused metal oxide semiconductor field effect transistor is a metal oxide semiconductor field effect transistor structure with a relatively long channel region, which helps to increase the power handling capacity. A main feature of a lateral diffused metal oxide semiconductor field effect transistor is its ability to handle high-power signals. This makes it an ideal choice for amplifying high-power RF signals, such as for applications like base stations, radar systems, data communication, etc.
[0003] However, in practical applications, it is often necessary to increase the voltage withstand and current-carrying capacity according to customer requirements. Summary of the Invention
[0004] The present invention provides a manufacturing method of a lateral diffused metal oxide semiconductor field effect transistor and a lateral diffused metal oxide semiconductor field effect transistor using this manufacturing method, so as to increase the voltage tolerance and current tolerance and avoid the component from burning out during operation.
[0005] An embodiment of the present invention provides a manufacturing method of a lateral diffused metal oxide semiconductor field effect transistor. This manufacturing method of the lateral diffused metal oxide semiconductor field effect transistor includes: arranging a plurality of parallel drain regions, wherein each of the parallel drain regions includes a drain contact window; arranging a plurality of parallel source / substrate regions between the above-mentioned plurality of parallel drain regions; arranging P+ regions at the endpoints of the above-mentioned plurality of parallel source / substrate regions; arranging a plurality of source / substrate contact windows in the above-mentioned plurality of parallel source / substrate regions, wherein each of the parallel source / substrate regions includes one of the above-mentioned source / substrate contact windows.
[0006] Embodiments of the present invention provide a lateral diffused metal oxide semiconductor field effect transistor. This lateral diffused metal oxide semiconductor field effect transistor includes a plurality of parallel drain regions, a plurality of parallel source / substrate regions, a plurality of drain contact windows, a plurality of source / substrate contact windows, and a plurality of P+ regions. The plurality of parallel source / substrate regions are disposed between the plurality of parallel drain regions. Each drain contact window is disposed on the parallel drain regions. Each source / substrate contact window is disposed on the parallel source / substrate regions. The P+ regions are disposed at the ends of the plurality of parallel source / substrate regions.
[0007] A method for manufacturing a lateral diffused metal oxide semiconductor field effect transistor and the lateral diffused metal oxide semiconductor field effect transistor according to a preferred embodiment of the present invention. Among them, between the plurality of parallel drain regions, a plurality of parallel source / substrate regions are disposed, including: in each parallel source / substrate region, a P+ region is disposed at each preset distance. In a preferred embodiment, the preset distance is between 2 μm and 3 μm.
[0008] A method for manufacturing a lateral diffused metal oxide semiconductor field effect transistor and the lateral diffused metal oxide semiconductor field effect transistor according to a preferred embodiment of the present invention. The manufacturing method further includes: depositing polysilicon between the plurality of parallel source / substrate regions and the plurality of parallel drain regions to serve as the gate of the lateral diffused metal oxide semiconductor field effect transistor.
[0009] A method for manufacturing a lateral diffused metal oxide semiconductor field effect transistor and the lateral diffused metal oxide semiconductor field effect transistor according to a preferred embodiment of the present invention. Among them, in the plurality of parallel source / substrate regions, a plurality of source / substrate contact windows are disposed. Among them, each parallel source / substrate region includes one of the source / substrate contact windows, including: disposing the source / substrate contact window so that the length of the source / substrate contact window is the same as the length of the drain contact window.
[0010] In summary, embodiments of the present invention use P+ regions disposed in the terminal regions of the source / substrate regions to solve the current crowding in the terminal regions. In addition, in a preferred embodiment, the lengths of the source / substrate contact windows and the drain contact windows are set to be the same. Thereby, the geometric structure and layout of the device are improved, the current distribution is made more uniform, and the non-uniformity of the local current density is reduced. At the same time, the breakdown voltage of the component is also increased.
[0011] To further understand the technology, means and effects of the present invention, reference may be made to the following detailed description and drawings, so that the purpose, features and concepts of the present invention can be thoroughly and specifically understood. However, the following detailed description and drawings are only for reference and illustration of the implementation of the present invention, and are not used to limit the present invention. Brief Description of the Drawings
[0012] The provided drawings are used to enable those skilled in the art to further understand the present invention and are incorporated into and constitute a part of the specification of the present invention. The drawings show exemplary embodiments of the present invention and are used together with the specification of the present invention to explain the principles of the present invention.
[0013] Figure 1 It is a schematic diagram of a lateral diffused metal oxide semiconductor field effect transistor at the time of burnout according to a preferred embodiment of the present invention.
[0014] Figure 2 It is a schematic diagram of a top view structure of the source and drain of a lateral diffused metal oxide semiconductor field effect transistor according to a preferred embodiment of the present invention.
[0015] Figure 3 It is a schematic diagram of a cross-sectional structure of the source and drain of a lateral diffused metal oxide semiconductor field effect transistor according to a preferred embodiment of the present invention.
[0016] Figure 4 It is a schematic diagram of a top view structure of the improved source and drain of a lateral diffused metal oxide semiconductor field effect transistor according to a preferred embodiment of the present invention.
[0017] Figure 5 It is a flowchart of a manufacturing method of a lateral diffused metal oxide semiconductor field effect transistor according to a preferred embodiment of the present invention.
[0018] Symbol Description:
[0019] 101 Source;
[0020] 102 Drain;
[0021] 201, P+, 404, 405: P-plus region;
[0022] 202, N+: N-plus region;
[0023] 203 Drain contact window (contact);
[0024] 204 Source / substrate contact window;
[0025] PBODY: P-type substrate region;
[0026] NHDD: N-type high-voltage doped drain region;
[0027] HVPW: High-Voltage P-Type Well;
[0028] HVNW: High-Voltage N-Type Well;
[0029] P-sub: P-Type Substrate;
[0030] 301 Gate Polysilicon;
[0031] 302 Insulating Oxide Layer;
[0032] 401 Endpoint P-plus Region;
[0033] 402 Contact Window of Drain Region;
[0034] 403 Contact Window of Source / Substrate Region;
[0035] S501 to S506 Process Steps of Fabrication Method of Lateral Diffusion Metal Oxide Semiconductor Field Effect Transistor. Detailed Embodiment
[0036] Now, a detailed reference will be made to the exemplary embodiments of the present invention, which will be illustrated in the accompanying drawings. Whenever possible, the same reference numerals will be used in the drawings and the description to refer to the same or similar parts. Additionally, the practices of the exemplary embodiments are merely one of the implementation manners of the design concept of the present invention, and the following examples are not used to limit the present invention.
[0037] Since, when a laterally-diffused metal-oxide-semiconductor field effect transistor (LDMOS FET) operates, when the high voltage at the output end exceeds the rated operating voltage of the LDMOS FET, an overcurrent may burn out the LDMOS FET. In order to explore the breakdown voltage of the LDMOS FET, the applicant conducted a breakdown voltage burn-out experiment. Figure 1 It is a schematic diagram of a laterally-diffused metal-oxide-semiconductor field effect transistor at the time of burnout, shown in a preferred embodiment of the present invention. Please refer to Figure 1 , in this embodiment, the laterally-diffused metal-oxide-semiconductor field effect transistor has a multi-finger layout. Reference numeral 101 is the source, and reference numeral 102 is the drain. It can be seen that the burned part of the laterally-diffused metal-oxide-semiconductor field effect transistor is basically in the region between the endpoints of the source and the endpoints of the drain.
[0038] Figure 2The figure shows a schematic top view of the original source and drain of a lateral diffused metal oxide semiconductor field effect transistor according to a preferred embodiment of the present invention. Figure 3 The figure shows a schematic cross-sectional structure of the source and drain of a lateral diffused metal oxide semiconductor field effect transistor according to a preferred embodiment of the present invention. Please refer to Figure 2 And Figure 3 , within the source / substrate region 101, it includes an N-plus region (source part) 202, a P-plus region (substrate part) 201, a drain contact window 203, and a source / substrate contact window 204. Among them, the P+ region 201 is used as the substrate electrode of the lateral diffused metal oxide semiconductor field effect transistor. In Figure 3 a more complete structure can be seen. In the cross-sectional structure of the lateral diffused metal oxide semiconductor field effect transistor, it includes an N-plus region N+, a P-plus region P+, a P-type substrate region PBODY, an N-type high-voltage doped drain region NHDD, a high-voltage P-type well HVPW, a high-voltage N-type well HVNW, a P-type substrate P-sub, an insulating oxide layer 302, and a gate polysilicon 301.
[0039] In Figure 2 it can be seen that in the damaged intervals of the source / substrate region 101 and the drain region 102, almost all occur in the terminal blocks. The applicant believes that there is a high possibility of current crowding problems in the terminal blocks.
[0040] To solve the above current crowding problem, Figure 4 The figure shows a schematic top view of the improved source and drain of a lateral diffused metal oxide semiconductor field effect transistor according to a preferred embodiment of the present invention. Please refer to Figure 4 , in the improved top view structure of the source and drain of this lateral diffused metal oxide semiconductor field effect transistor, a P-plus region 401 is added to the end block of the source / substrate region, and the contact window 402 in the drain region is designed to be the same length as the contact window 403 in the source / substrate region. In addition, in the source / substrate region, the distance between any two P-plus regions 404 and 405 is close. For example, the original distance of 5 μm is reduced to a distance between 2 μm and 3 μm. Through the above design, since the substrate (Bulk) end is P-plus, increasing the P+ / N+ ratio allows the backflow current to have multiple paths for release. And a P-plus region 401 is also added at the end of the contact window 403 where current is likely to accumulate, which can release the external current. Also, by designing the contact window 402 in the drain region to be the same length as the contact window 403 in the source / substrate region, the current at the end is prevented from being too large.
[0041] By the above modified rules, in addition to increasing the current release path and equalizing the current, the manufacturing process can also be carried out with the original number of photomasks. Therefore, the manufacturing cost of integrated circuits can be greatly reduced. In addition, although the above embodiments adopt the following designs:
[0042] 1. A P-plus region is added to the end block of the source / substrate region;
[0043] 2. The contact window 402 of the drain region is designed to be the same length as the contact window 403 of the source / substrate region;
[0044] 3. The distance between the two P-plus regions 404 and 405 is close.
[0045] However, it is not necessary to adopt all of the above methods. By adopting any of the above designs, improvements can be obtained in terms of breakdown voltage and current withstand. The above embodiments are only proposed as preferred embodiments, and the present invention is not limited thereto.
[0046] From the above embodiments, a manufacturing method of a lateral diffusion metal oxide semiconductor field effect transistor can be summarized. Figure 5 The flowchart of the manufacturing method of the lateral diffusion metal oxide semiconductor field effect transistor according to a preferred embodiment of the present invention is shown. Please refer to Figure 5 , and the manufacturing method of this lateral diffusion metal oxide semiconductor field effect transistor includes the following steps:
[0047] Step S501: Start.
[0048] Step S502: Configure multiple parallel drain regions. As described above Figure 4 , each parallel drain region includes a drain contact window.
[0049] Step S503: Configure multiple parallel source / substrate regions. As described above Figure 4 , the parallel source / substrate regions are configured between the above multiple parallel drain regions.
[0050] Step S504: Configure P+ regions in the above multiple parallel source / substrate regions. As described above Figure 4 in the P-plus region 401 at the end point and the design that the distance between the two P-plus regions 404 and 405 is close. Thereby, the current magnitude and uniformity are increased.
[0051] Step S505: Configure multiple source / substrate contact windows in the above multiple parallel source / substrate regions. As described above Figure 4 in the design that the contact window 402 of the drain region is the same length as the contact window 403 of the source / substrate region. Thereby, the problem of current crowding at the end points is avoided.
[0052] Step S506: Deposit polysilicon between the multiple parallel source / substrate regions and the multiple parallel drain regions. Such as Figure 3 the polysilicon 301 in
[0053] Similarly, the above manufacturing method only presents preferred embodiments. Referring to the above description, those skilled in the art should know that according to different breakdown voltage requirements, the above steps or designs can be simplified or reduced. The present invention is not limited thereto.
[0054] In summary, the embodiments of the present invention adopt the setting of P+ regions in the terminal regions of the source / substrate regions to solve the current crowding in the terminal regions. Additionally, in the preferred embodiment, the lengths of the source / substrate contact windows and the drain contact windows are set to be the same. Thereby, the geometric structure and layout of the device are improved, the current distribution becomes more uniform, and the non-uniformity of the local current density is reduced. At the same time, the breakdown voltage of the component is also increased.
[0055] It should be understood that the examples and embodiments described herein are for illustrative purposes only, and various modifications or changes thereof will be suggested to those skilled in the art and will be included within the spirit and scope of this application and the scope of the appended claims.
Claims
1. A method for manufacturing a laterally diffused metal oxide semiconductor field effect transistor, characterized in that: include: Disposing a plurality of parallel drain regions, wherein each parallel drain region includes a drain contact window; Disposing a plurality of parallel source / substrate regions between the plurality of parallel drain regions; Disposing P+ regions at the end points of the plurality of parallel source / substrate regions; A plurality of source / substrate contact windows are arranged on the plurality of parallel source / substrate regions, wherein each of the parallel source / substrate regions includes one source / substrate contact window.
2. The method for manufacturing a laterally diffused metal oxide semiconductor field effect transistor according to claim 1, wherein: A plurality of parallel source / substrate regions are arranged between the plurality of parallel drain regions, including: In each parallel source / substrate region, a P+ region is disposed at a predetermined distance.
3. The method for manufacturing a laterally diffused metal oxide semiconductor field effect transistor according to claim 2, wherein: The preset distance is between 2 μm and 3 μm.
4. The method for manufacturing a laterally diffused metal oxide semiconductor field effect transistor according to claim 1, wherein: Also includes: Polysilicon is deposited between the plurality of parallel source / substrate regions and the plurality of parallel drain regions to serve as a gate of the LDMOS field effect transistor.
5. The method for manufacturing a laterally diffused metal oxide semiconductor field effect transistor according to claim 1, wherein: A plurality of source / substrate contact windows are configured in the plurality of parallel source / substrate regions, wherein each parallel source / substrate region includes one source / substrate contact window, including: The source / substrate contact window is configured so that the length of the source / substrate contact window is the same as the length of the drain contact window.
6. A laterally diffused metal oxide semiconductor field effect transistor, characterized in that include: a plurality of parallel drain regions; a plurality of parallel source / substrate regions disposed between the plurality of parallel drain regions; a plurality of drain contact windows, wherein each drain contact window is disposed in the parallel drain regions; a plurality of source / substrate contact windows, wherein each source / substrate contact window is disposed in the parallel source / substrate region; and A plurality of P+ regions are arranged at the end points of the plurality of parallel source / substrate regions.
7. The laterally diffused metal oxide semiconductor field effect transistor according to claim 6, wherein: In each parallel source / substrate region, further comprising: A plurality of P+ substrate regions, wherein in each parallel source / substrate region, a P+ region is configured at each predetermined distance as the P+ substrate region.
8. The laterally diffused metal oxide semiconductor field effect transistor according to claim 7, wherein: The preset distance is between 2 μm and 3 μm.
9. The laterally diffused metal oxide semiconductor field effect transistor according to claim 6, wherein: Also includes: A plurality of gate polysilicon layers are disposed between the plurality of parallel source / substrate regions and the plurality of parallel drain regions to serve as gates of the LDMOS field effect transistors.
10. The laterally diffused metal oxide semiconductor field effect transistor according to claim 6, wherein: The length of the source / substrate contact window is the same as the length of the drain contact window.