Semiconductor devices, power modules and electronic devices

Abstract

Embodiments of the present disclosure provide a semiconductor device, power module, and electronic device, relating to the field of semiconductor technology, for enabling a semiconductor device to conduct under reverse bias under enhanced conditions. The semiconductor device includes a substrate, a gate, a stacked structure, a first electrode, a first dielectric layer, a second dielectric layer, and a second electrode. The gate is disposed on one side of the substrate along a first direction. The stacked structure is disposed on one side of the substrate along the first direction and is at least located on one side of the gate along a second direction. The first electrode is disposed on a side of the stacked structure away from the substrate and on a side of the stacked structure away from the gate. The first dielectric layer is disposed between the substrate and the gate, and between the stacked structure and the gate. The second dielectric layer is disposed on a side of the stacked structure away from the gate and is located between the first electrode and the stacked structure. The second electrode is disposed on a side of the substrate away from the gate. The above-mentioned semiconductor device is used in a power module.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor device, a power module, and an electronic device. Background Art

[0002] Ga2O3 (gallium oxide), as a new ultra-wide bandgap (UWBG) semiconductor material, boasts an ultra-wide bandgap exceeding 4.8eV, a theoretical breakdown electric field strength of 8MV / cm, and lower on-resistance, showing broad application prospects in high-power devices. However, current enhancement-mode gallium oxide-based metal-oxide-semiconductor field-effect transistors (MOSFETs) cannot conduct under reverse bias, significantly limiting the development of gallium oxide-based power devices. Summary of the Invention

[0003] The purpose of the embodiments of the present disclosure is to provide a semiconductor device, a power module, and an electronic device, which are used to enable the semiconductor device to be turned on under reverse bias under enhancement conditions.

[0004] To achieve the above objectives, the embodiments of the present disclosure provide the following technical solutions:

[0005] In one aspect, a semiconductor device is provided, comprising a substrate, a gate, a stacked structure, a first electrode, a first dielectric layer, a second dielectric layer, and a second electrode.

[0006] In which, the gate is arranged on one side of the substrate along a first direction, and the first direction is the thickness direction of the substrate; the stacked structure is arranged on one side of the substrate in the first direction, and is at least located on one side of the gate along a second direction, and the second direction is perpendicular to the first direction; the stacked structure includes a current blocking layer and a first doping layer stacked along the first direction, and the first doping layer is farther away from the substrate than the current blocking layer; the first electrode is arranged on the side of the stacked structure away from the substrate, and on the side of the stacked structure away from the gate; the first dielectric layer is arranged between the substrate and the gate, and between the stacked structure and the gate; the second dielectric layer is arranged on the side of the stacked structure away from the gate, and is located between the first electrode and the stacked structure; the second electrode is arranged on the side of the substrate away from the gate.

[0007] In the above-described semiconductor device, the stacked structure is disposed on one side of the substrate in a first direction and at least on one side of the gate in a second direction perpendicular to the first direction; the stacked structure includes a current-blocking layer and a first doped layer stacked along the first direction, with the first doped layer being further away from the substrate than the current-blocking layer. Thus, when the gate voltage of the semiconductor device is less than the threshold voltage and the voltage of the second electrode is greater than the voltage of the first electrode, the semiconductor device is in an off state. When the gate voltage of the semiconductor device is greater than the threshold voltage of the semiconductor device and the voltage of the second electrode is greater than the voltage of the first electrode, the conductivity of the side of the current-blocking layer near the gate increases, and the semiconductor device is turned on. At this time, current flows from the second electrode through the substrate, the side of the current-blocking layer near the gate, and the first doped layer to the first electrode. Therefore, the semiconductor device provided in this embodiment is an enhancement-mode semiconductor device.

[0008] On the other hand, since the first electrode is arranged on the side of the stacked structure away from the substrate and the side of the stacked structure away from the gate; that is, the first electrode is arranged on the side of the current blocking layer away from the gate; therefore, when the gate voltage of the semiconductor device is less than the threshold voltage and the voltage of the first electrode is greater than the voltage of the second electrode, the first electrode can also be regarded as a gate. At this time, the conductivity of the side of the current blocking layer away from the gate increases, so that the semiconductor device can also be turned on. At this time, the current flows from the first electrode through the first doped layer, the side of the current blocking layer away from the gate, the substrate to the second electrode. In this way, the enhanced semiconductor device provided in this embodiment can be turned on under reverse bias when no voltage is applied to the gate, thereby improving the passive freewheeling capability of the semiconductor device, that is, the working ability of the semiconductor device in the third quadrant.

[0009] In addition, there is no PN junction when the semiconductor device is forward conducting or reverse conducting, resulting in small capacitance, fast switching speed and high current density.

[0010] In some embodiments, it further includes: a second doping layer, disposed between the current blocking layer and the substrate; the doping type of the second doping layer is the same as the doping type of the first doping layer; and the first dielectric layer is also located between the gate and the second doping layer.

[0011] In some embodiments, the doping concentration of the second doping layer is greater than the doping concentration of the current blocking layer.

[0012] In some embodiments, it also includes: a Schottky metal layer, which is arranged on the side of the second doped layer away from the gate and contacts the second doped layer; the Schottky metal layer includes a first surface and a second surface opposite to each other along the first direction, the first surface is farther away from the substrate than the second surface, the first surface contacts the first electrode, and the second surface contacts the substrate.

[0013] In some embodiments, it also includes: a Schottky metal layer, which is located on a side of the stacked structure away from the gate in a projection onto the surface of the substrate away from the stacked structure, and the Schottky metal layer is embedded in the substrate; the surface of the Schottky metal layer away from the substrate is in contact with the first electrode.

[0014] In some embodiments, the second dielectric layer is located on a side of the Schottky metal layer away from the substrate.

[0015] In some embodiments, it also includes: a third doping layer, which is arranged on the side of the current blocking layer away from the substrate; the third doping layer is arranged on the side of the first doping layer away from the gate, and is in contact with the surface of the first doping layer away from the gate; the doping type of the third doping layer is opposite to the doping type of the first doping layer; the first electrode is also arranged on the side of the third doping layer away from the substrate, and on the side of the third doping layer away from the gate.

[0016] In some embodiments, the doping concentration of the third doping layer is greater than the doping concentration of the current blocking layer.

[0017] In some embodiments, the second dielectric layer covers a surface of the third doped layer away from the gate and a surface of the current blocking layer away from the gate.

[0018] In some embodiments, the doping concentration of the first doping layer is greater than the doping concentration of the current blocking layer.

[0019] In some embodiments, the substrate includes: a first sublayer and a second sublayer stacked along the first direction, the second sublayer being closer to the gate than the first sublayer; the doping type of the first sublayer and the doping type of the second sublayer are the same as the doping type of the first doping layer, and the doping concentration of the second sublayer is less than the doping concentration of the first sublayer.

[0020] In some embodiments, the material of the first doping layer includes gallium oxide, and the doping ions include silicon ions; the material of the current blocking layer includes gallium oxide, and the doping ions include magnesium ions.

[0021] In some embodiments, the material of the third doping layer includes nickel oxide, and the doping ions include lithium ions.

[0022] In some embodiments, the stacked structure has a first opening penetrating the stacked structure along the first direction, the first dielectric layer is located at the bottom and sidewalls of the first opening, the first dielectric layer forms a first groove, and the gate is located in the first groove.

[0023] On the other hand, a power module is provided, comprising the semiconductor device provided in any of the above embodiments.

[0024] On the other hand, an electronic device is provided, comprising the power module provided in any of the above embodiments.

[0025] The above-mentioned power module and electronic equipment have the same structure and beneficial technical effects as the semiconductor devices provided in some of the above-mentioned embodiments, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] To more clearly illustrate the technical solutions of the present disclosure, the following briefly introduces the drawings required for use in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure, and those skilled in the art can also derive other drawings based on these drawings. Furthermore, the drawings described below are schematic diagrams and are not intended to limit the actual dimensions of the products, actual processes of the methods, actual timing of signals, and the like involved in the embodiments of the present disclosure.

[0027] Figure 1 A structural diagram of an electronic device provided for some embodiments of the present disclosure;

[0028] Figure 2 A structural diagram of a semiconductor device provided for some embodiments of the present disclosure;

[0029] Figure 3 A structural diagram of another semiconductor device provided for some embodiments of the present disclosure;

[0030] Figure 4 A structural diagram of another semiconductor device provided for some embodiments of the present disclosure;

[0031] Figure 5 A structural diagram of another semiconductor device provided for some embodiments of the present disclosure;

[0032] Figure 6 An output characteristic curve diagram of a semiconductor device during forward conduction provided by some embodiments of the present disclosure;

[0033] Figure 7 A transfer characteristic curve diagram of a semiconductor device in reverse conduction provided in some embodiments of the present disclosure;

[0034] Figure 8 An output characteristic curve diagram of another semiconductor device during forward conduction provided by some embodiments of the present disclosure;

[0035] Figure 9A transfer characteristic curve diagram of another semiconductor device in reverse conduction provided in some embodiments of the present disclosure;

[0036] Figure 10 A schematic flow chart of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure;

[0037] Figures 11 to 17 A schematic diagram of a process of manufacturing a display panel provided in some embodiments of the present disclosure;

[0038] Figure 18 A schematic flow chart of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure;

[0039] Figures 19 to 27 A schematic diagram of a process of manufacturing a display panel provided in some embodiments of the present disclosure. DETAILED DESCRIPTION

[0040] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the embodiments described are only some embodiments of the present disclosure, not all embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of the present disclosure.

[0041] Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as having an open, inclusive meaning, that is, "including, but not limited to." In the description of the specification, the terms "one embodiment," "some embodiments," "exemplary embodiments," "examples," or "some examples" are intended to indicate that a particular feature, structure, material, or characteristic associated with the embodiment or example is included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the particular features, structures, materials, or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0042] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0043] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. The term "connected" should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium. The term "coupled" indicates, for example, that two or more components are in direct physical or electrical contact. The term "coupled" or "communicatively coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0044] “At least one of A, B and C” has the same meaning as “at least one of A, B or C” and both include the following combinations of A, B and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B and C.

[0045] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0046] The use of "suitable for" or "configured to" herein means open and inclusive language that does not exclude that, as used herein, "parallel", "perpendicular", and "equal" include the situations described and situations similar to the situations described, and the range of the similar situations is within an acceptable deviation range, wherein the acceptable deviation range is as determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the specific quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximately parallelism, wherein the acceptable deviation range of approximately parallelism can be, for example, a deviation within 5°; "perpendicular" includes absolute perpendicularity and approximately perpendicularity, wherein the acceptable deviation range of approximately perpendicularity can also be, for example, a deviation within 5°. "Equal" includes absolute equality and approximately equality, wherein the acceptable deviation range of approximately equality can be, for example, that the difference between the two is less than or equal to 5% of either one.

[0047] It will be understood that when a layer or element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present therebetween.

[0048] Exemplary embodiments are described herein with reference to cross-sectional and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0049] like Figure 1 As shown, an embodiment of the present application provides an electronic device 1000. The electronic device 1000 may be an electronic device such as a fast charger, an uninterruptible power supply (UPS), a power motor, etc.

[0050] Continue to refer Figure 1 The electronic device 1000 includes a power module 1001 and a circuit board 1002 . The power module 1001 and the circuit board 1002 are electrically connected. The circuit board 1002 converts external power into the voltage or current required for the power module 1001 to work.

[0051] For example, the circuit board 1002 may include a printed circuit board (PCB) or the like.

[0052] For example, the circuit board 1002 may include multiple conductive layers, and the multiple conductive layers within the circuit board 1002 may be separated from each other by dielectric layers.

[0053] The power module 1001 includes semiconductor devices.

[0054] The above-mentioned semiconductor device will be described in detail below.

[0055] refer to Figure 2 The semiconductor device 100 includes a substrate 10 , a gate 20 , a stacked structure 3 , a first electrode 41 , a first dielectric layer 51 , a second dielectric layer 52 and a second electrode 42 .

[0056] In which, the gate 20 is arranged on one side of the substrate 10 along the first direction X, and the first direction X is the thickness direction of the substrate 10; the stacked structure 3 is arranged on one side of the substrate 10 in the first direction X, and is at least located on one side of the gate 20 along the second direction Y, and the second direction Y is perpendicular to the first direction X; the stacked structure 3 includes a current blocking layer 30 and a first doped layer 31 stacked along the first direction X, and the first doped layer 31 is farther away from the substrate 10 than the current blocking layer 30.

[0057] The first electrode 41 is arranged on the side of the stacked structure 3 away from the substrate 10, and on the side of the stacked structure 3 away from the gate 20; the first dielectric layer 51 is arranged between the substrate 10 and the gate 20, and between the stacked structure 3 and the gate 20; the second dielectric layer 52 is arranged on the side of the stacked structure 3 away from the gate 20, and is located between the first electrode 41 and the stacked structure 3; the second electrode 42 is arranged on the side of the substrate 10 away from the gate 20.

[0058] In the semiconductor device 100 described above, the stacked structure 3 is disposed on one side of the substrate 10 in the first direction X and at least on one side of the gate 20 in the second direction Y, which is perpendicular to the first direction X. The stacked structure 3 includes a current blocking layer 30 and a first doped layer 31 stacked along the first direction X, with the first doped layer 31 being further away from the substrate 10 than the current blocking layer 30. Thus, when the voltage of the gate 20 of the semiconductor device 100 is less than the threshold voltage and the voltage of the second electrode 42 is greater than the voltage of the first electrode 41, the semiconductor device 100 is in an off state. When the voltage of the gate 20 of the semiconductor device 100 is greater than the threshold voltage of the semiconductor device 100 and the voltage of the second electrode 42 is greater than the voltage of the first electrode 41, the conductivity of the side of the current blocking layer 30 near the gate 20 increases, and the semiconductor device 100 is turned on. At this time, current flows from the second electrode 42 through the substrate 10, the side of the current blocking layer 30 near the gate 20, the first doped layer 31, and the first electrode 41. Therefore, the semiconductor device 100 provided in this embodiment is an enhancement-mode semiconductor device.

[0059] On the other hand, since the first electrode 41 is arranged on the side of the stacked structure 3 away from the substrate 10 and the side of the stacked structure 3 away from the gate 20; that is, the first electrode 41 is arranged on the side of the current blocking layer 30 away from the gate 20; therefore, when the gate 20 voltage of the semiconductor device 100 is less than the threshold voltage and the voltage of the first electrode 41 is greater than the voltage of the second electrode 42, the first electrode 41 can also be regarded as a gate. At this time, the conductivity of the side of the current blocking layer 30 away from the gate 20 increases, so that the semiconductor device 100 can also be turned on. At this time, the current flows from the first electrode 41 through the first doped layer 31, the side of the current blocking layer 30 away from the gate 20, the substrate 10 to the second electrode 42. In this way, the enhanced semiconductor device provided in this embodiment can be turned on under reverse bias when no voltage is applied to the gate 20, thereby improving the passive freewheeling capability of the semiconductor device 100, that is, the working ability of the semiconductor device 100 in the third quadrant.

[0060] In addition, the semiconductor device 100 has no PN junction when conducting in the forward direction or the reverse direction, resulting in a small capacitance, a fast switching speed, and a high current density.

[0061] Among them, the stacked structure 3 is located on at least one side of the gate 20 along the second direction Y. The stacked structure 3 may be located on one side of the gate 20 along the second direction Y, or the stacked structure 3 may be located on the left and right sides of the gate 20 along the second direction Y, or the stacked structure 3 may surround the gate 20 along the second direction Y.

[0062] For example, reference Figure 2 The stacked structure 3 has a first opening K1 running through it along the first direction X. The first dielectric layer 51 is located at the bottom and sidewalls of the first opening K1. The first dielectric layer 51 forms a first groove G1. The gate 20 is located in the first groove G1.

[0063] In the semiconductor device 100 , the first electrode 41 is a source electrode, and the second electrode 42 is a drain electrode. In other embodiments, the second electrode 42 may be a source electrode, and the first electrode 41 may be a drain electrode.

[0064] In some embodiments, continue to refer to Figure 2 The substrate 10 includes: a first sublayer 11 and a second sublayer 12 stacked along a first direction X, the second sublayer 12 is closer to the gate 20 than the first sublayer 11; the doping type of the first sublayer 11 and the doping type of the second sublayer 12 are the same as the doping type of the first doping layer 31, and the doping concentration of the second sublayer 12 is less than the doping concentration of the first sublayer 11.

[0065] The doping type of the first sublayer 11 and the doping type of the second sublayer 12 are the same as the doping type of the first doped layer 31. Since they are isotype doping, the potential barrier of the PN junction or heterojunction can be avoided, which is conducive to the unimpeded flow of carriers.

[0066] In addition, the doping type of the first sublayer 11 and the doping type of the second sublayer 12 are the same as the doping type of the first doped layer 31. That is, the doping type of the first sublayer 11 and the doping type of the second sublayer 12 are the same. In this way, the second sublayer 12 can be directly epitaxially grown on the first sublayer 11 without switching the doping type. This not only reduces interface defects and stress, but also avoids the occurrence of electric field distortion at the heterojunction interface. The doping concentration of the second sublayer 12 is lower than the doping concentration of the first sublayer 11. Because the first sublayer 11 is doped with a high concentration (low resistance), it can serve as a mechanical support and current path. The second sublayer 12 is doped with a low concentration. In this way, the second sublayer 12 can withstand high voltages and can also form a wider depletion layer, thereby dispersing the electric field strength, avoiding breakdown, and improving the voltage resistance of the semiconductor device 100.

[0067] In some embodiments, the materials of the first sub-layer 11 and the second sub-layer 12 both include gallium oxide.

[0068] The doping ions of the first sub-layer 11 and the second sub-layer 12 both include silicon ions.

[0069] For example, the doping concentration of the first sub-layer 11 is greater than 5E18cm -3 For example, the doping concentration of the first sublayer 11 is 5E18cm -3 ~5E19cm -3 .

[0070] For example, the doping concentration of the second sub-layer 12 is 1E16 cm -3 ~5E17cm -3 For example, the doping concentration of the second sub-layer 12 is 1E16 cm -3 or 5E17cm -3 .

[0071] In some embodiments, the thickness of the first sub-layer 11 is 600 μm-700 μm, for example, 600 μm, 650 μm or 700 μm.

[0072] In some embodiments, the thickness of the second sub-layer 12 is 6 μm to 8 μm, for example, 6 μm, 7 μm or 8 μm.

[0073] In some embodiments, the material of the first doped layer 31 includes gallium oxide, and the doping ions include silicon ions. Because gallium oxide (β-Ga2O3) has a band gap of 4.8 eV, far exceeding silicon carbide (3.2 eV) and gallium nitride (3.4 eV), it has an ultra-high breakdown electric field strength and higher voltage resistance. Furthermore, gallium oxide has lower on-resistance and higher power conversion efficiency. The low on-resistance of gallium oxide can also reduce conduction losses.

[0074] Silicon ions act as shallow donor impurities in gallium oxide, providing a high concentration of free electrons. This allows first doped layer 31 to have N-type conductivity. This N-type conductivity, combined with gallium oxide's wide bandgap, allows it to withstand a high critical breakdown field of 8 MV / cm, making semiconductor device 100 suitable for high-voltage applications. Furthermore, the low diffusion coefficient of silicon ions in gallium oxide facilitates the formation of a steep doping interface and suppresses doping drift, enabling precise control of carrier distribution and improving stability under high-temperature conditions.

[0075] In some embodiments, the material of the current blocking layer 30 includes gallium oxide, and the doping ions include magnesium ions. Since magnesium ion doping can form deep-level acceptor states in the gallium oxide, it effectively compensates for intrinsic carriers, making the current blocking layer 30 exhibit high resistance characteristics, thereby suppressing leakage current and improving the withstand voltage capability of the semiconductor device 100.

[0076] The current-blocking layer 30 and the first doped layer 31 are made of the same material. Because the lattice constant and thermal expansion coefficient of the same material are identical, dislocations or cracks at the heterojunction interface between the current-blocking layer 30 and the first doped layer 31 are avoided. Furthermore, because the band structure of the same material is continuous, abrupt changes in the conduction band and valence band of the heterojunction are avoided, reducing the electron / hole transport barrier. Furthermore, the current-blocking layer 30 and the first doped layer 31 can be fabricated using a single epitaxial process, reducing the risk of contamination from switching reaction chambers and improving film uniformity.

[0077] In some embodiments, the thickness of the first doping layer 31 is 0.4 μm to 0.6 μm, for example, 0.4 μm, 0.5 μm, or 0.6 μm.

[0078] In some embodiments, the thickness of the current blocking layer 30 is 0.8 μm to 1.2 μm, for example, 0.8 μm, 1.0 μm, or 1.2 μm.

[0079] In some embodiments, the doping concentration of the first doping layer 31 is greater than the doping concentration of the current blocking layer 30. The high doping concentration of the first doping layer 31 can enhance the concentration of carriers, provide a low-resistance channel for carriers, reduce ohmic contact resistance, and thus reduce power loss in the semiconductor device 100. The low doping concentration of the current blocking layer 30 is conducive to increasing the threshold voltage of the device.

[0080] For example, the doping concentration of the first doping layer 31 is 5E18cm -3 ~5E19cm -3 , for example 5E18cm -3 、6E18cm -3 or 5E19cm -3 .

[0081] For example, the doping concentration of the current blocking layer 30 is 5E14cm -3 ~5E15cm -3 , for example 5E14cm -3 、6E14cm -3 、7E14cm -3 or 5E15cm -3 .

[0082] In some embodiments, reference Figure 3 The semiconductor device 100 further includes: a Schottky metal layer 60. In a projection onto the surface of the substrate 10 away from the stacked structure 3, the Schottky metal layer 60 is located on a side of the stacked structure 3 away from the gate 20, and the Schottky metal layer 60 is embedded in the substrate 10; the surface of the Schottky metal layer 60 away from the substrate 10 is in contact with the first electrode 41.

[0083] In this way, when the gate 20 voltage of the semiconductor device 100 is less than the threshold voltage and the voltage of the first electrode 41 is greater than the voltage of the second electrode 42, the conduction path of the semiconductor device 100 increases. At this time, the current can also pass from the first electrode 41 through the Schottky metal layer 60 and the substrate 10 to the second electrode 42. In this way, the enhanced semiconductor device provided in this embodiment has an increased conduction path under reverse bias when no voltage is applied to the gate 20, further improving the passive freewheeling capability of the semiconductor device 100.

[0084] When current flows from the first electrode 41 through the Schottky metal layer 60 and the substrate 10 to the second electrode 42 , the semiconductor device 100 conducts in the reverse direction and the current is a Schottky current, which can reduce the reverse conduction voltage, reduce the capacitance, and increase the switching speed.

[0085] Exemplarily, the material of the Schottky metal layer 60 includes nickel, platinum, and gold. In other embodiments, the material of the Schottky metal layer 60 may also be other high work function (>4 eV) metals.

[0086] Exemplarily, the thickness of the Schottky metal layer 60 is 500 nm to 550 nm; for example, 500 nm, 520 nm, or 550 nm.

[0087] In some embodiments, reference Figure 4 Semiconductor device 100 further includes a second doped layer 32 disposed between current-blocking layer 30 and substrate 10. The doping type of second doped layer 32 is the same as that of first doped layer 31. The same doping type of second doped layer 32 as that of first doped layer 31 facilitates the formation of a low-resistance path, promoting current diffusion and reducing series resistance during vertical carrier flow. Homotype doping ensures lattice matching between first doped layer 31 and second doped layer 32 and current-blocking layer 30, thereby reducing interface state density and minimizing carrier scattering.

[0088] Exemplarily, the material of the second doping layer 32 includes gallium oxide, and the doping ions include silicon ions. That is, the first doping layer 31 and the second doping layer 32, respectively located on either side of the current blocking layer 30, are made of the same material and doped with the same ions. This prevents the formation of a PN junction in the semiconductor device 100, thereby reducing capacitance, increasing switching speed, and improving the operating current of the semiconductor device 100.

[0089] Similarly, under reverse bias, the first doped layer 31 and the second doped layer 32 on both sides of the current blocking layer 30 are made of the same material and doped with the same ions. This prevents the formation of a PN junction in the semiconductor device 100, thereby reducing capacitance, increasing switching speed, and improving the operating current of the semiconductor device 100. When the semiconductor device 100 includes the second doped layer 32, the first dielectric layer 51 is also located between the gate 20 and the second doped layer 32. The first dielectric layer 51 can prevent direct carrier tunneling between the gate 20 and the second doped layer 32, thereby reducing leakage of the gate 20 and improving the reliability of the semiconductor device 100.

[0090] In some embodiments, the doping concentration of the second doping layer 32 is greater than the doping concentration of the current blocking layer 30. The high doping concentration of the second doping layer 32 is beneficial for reducing parasitic resistance and avoiding additional voltage drop on the current path.

[0091] For example, the doping concentration of the second doping layer 32 is 5E18cm -3 ~5E19cm -3 , for example 5E18cm -3 、6E18cm -3 or 5E19cm -3 .

[0092] For example, the doping concentration of the current blocking layer 30 is 5E14cm -3 ~5E15cm -3 , for example 5E14cm -3 、6E14cm -3 、7E14cm -3 or 5E15cm -3 .

[0093] In other embodiments, reference Figure 4 In the case where the semiconductor device 100 includes a second doped layer 32, the Schottky metal layer 60 is arranged on a side of the second doped layer 32 away from the gate 20 and contacts the second doped layer 32; the Schottky metal layer 60 includes a first surface m1 and a second surface m2 opposite to each other along the first direction X, the first surface m1 is farther away from the substrate 10 than the second surface m2, the first surface m1 contacts the first electrode 41, and the second surface m2 contacts the substrate 10.

[0094] Since the Schottky metal layer 60 is in contact with the second doped layer 32, the use of a second doped layer 32 with a high doping concentration helps to suppress the depletion effect caused by the Schottky metal layer 60 contacting the second doped layer 32. This can prevent the depletion region from expanding toward the gate 20, ensure that the second doped layer 32 remains in a conductive state at the sidewall away from the gate 20, and prevent the current path from being blocked.

[0095] In some embodiments, the second dielectric layer 52 is located on a side of the Schottky metal layer 60 away from the substrate 10. The second dielectric layer 52 is primarily located on a side of the first doped layer 31 and the current blocking layer 30 away from the gate 20. Thus, the second dielectric layer 52 isolates the first electrode 41 from the first doped layer 31 and the current blocking layer 30, forming a MOS (metal-oxide-semiconductor) structure, thereby preventing current leakage from the first electrode 41.

[0096] In some embodiments, the second dielectric layer 52 may also cover a portion of the Schottky metal layer 60 , and the remaining Schottky metal layer 60 is in contact with the first electrode 41 .

[0097] In some embodiments, reference Figure 5 The semiconductor device 100 further includes: a third doping layer 33, which is arranged on a side of the current blocking layer 30 away from the substrate 10; the third doping layer 33 is arranged on a side of the first doping layer 31 away from the gate 20, and is in contact with the surface of the first doping layer 31 away from the gate 20; the doping type of the third doping layer 33 is opposite to the doping type of the first doping layer 31; the first electrode 41 is also arranged on a side of the third doping layer 33 away from the substrate 10, and on a side of the third doping layer 33 away from the gate 20.

[0098] In this case, when the gate 20 voltage of the semiconductor device 100 is less than the threshold voltage and the voltage of the first electrode 41 is greater than the voltage of the second electrode 42, the first electrode 41 can be regarded as a gate. At this time, the conductivity of the current blocking layer 30 on the side away from the gate 20 increases. Since the doping type of the third doping layer 33 is opposite to the doping type of the first doping layer 31, the third doping layer 33 and the first doping layer 31 form a PN junction, so that the semiconductor device 100 can also be turned on, and the current is the PN junction current; at this time, the current flows from the first electrode 41 through the first doping layer 31, the third doping layer 33, the side of the current blocking layer 30 away from the gate 20, the substrate 10 to the second electrode 42, so that the enhanced semiconductor device provided in this embodiment can be turned on under reverse bias when no voltage is applied to the gate 20, thereby also improving the passive freewheeling capability of the semiconductor device 100.

[0099] Exemplarily, the material of the third doping layer 33 includes nickel oxide, and the doping ions include lithium ions.

[0100] Exemplarily, the thickness of the third doping layer 33 is 500 nm to 550 nm; for example, 500 nm, 520 nm or 550 nm.

[0101] In some embodiments, the doping concentration of the third doping layer 33 is greater than the doping concentration of the current blocking layer 30. Since the first electrode 41 is disposed on the side of the third doping layer 33 away from the substrate 10 and the side of the third doping layer 33 away from the gate 20, using a third doping layer 33 with a high doping concentration helps suppress the depletion effect of the third doping layer 33 caused by the first electrode 41. This prevents the depletion region from expanding toward the gate 20, ensures that the third doping layer 33 remains conductive at the sidewall away from the gate 20, and prevents the current path from being blocked.

[0102] For example, the doping concentration of the third doping layer 33 is 5E18cm -3 ~5E19cm -3 , for example 5E18cm -3 、6E18cm -3 or 5E19cm -3 .

[0103] For example, the doping concentration of the current blocking layer 30 is 5E14cm -3 ~5E15cm -3 , for example 5E14cm -3 、6E14cm -3 、7E14cm -3 or 5E15cm -3 .

[0104] Continue to refer Figure 5 When the semiconductor device 100 includes the third doped layer 33, the first electrode 41 includes a first sub-electrode 411 and a second sub-electrode 412, and the first sub-electrode 411 and the second sub-electrode 412 are connected. The first sub-electrode 411 contacts the surface of the first doped layer 31 away from the substrate 10. The second sub-electrode 412 contacts the surface of the third doped layer 33 away from the substrate 10 and covers the side of the second dielectric layer 52 away from the gate 20.

[0105] The first sub-electrode 411 is made of metal, such as nickel or gold, or a stacked structure of nickel and gold. The first sub-electrode 411 forms an ohmic contact with the first doping layer 31 .

[0106] The second sub-electrode 412 is made of a metal, such as titanium or aluminum, or a stacked structure of titanium and aluminum. The second sub-electrode 412 forms an ohmic contact with the third doping layer 33 .

[0107] Since the doping type of the third doping layer 33 is opposite to the doping type of the first doping layer 31 , different electrode materials are selected according to the doping type, which can improve the electrical performance of the semiconductor device 100 .

[0108] When the semiconductor device 100 includes the third doped layer 33, the second dielectric layer 52 covers the surface of the third doped layer 33 away from the gate 20, as well as the surface of the current blocking layer 30 away from the gate 20. In this way, the second dielectric layer 52 isolates the first electrode 41 from the third doped layer 33 and the current blocking layer 30, forming a MOS structure, thereby preventing current leakage from the first electrode 41.

[0109] Figure 6 The output characteristic curve of a semiconductor device 100 provided in some embodiments of the present disclosure during forward conduction is specifically as follows: Figure 4 The output characteristic curve of the semiconductor device 100 shown in FIG. 1 is a graph showing the output characteristic curve of the semiconductor device 100 when it is forward-conducting. DS The size of (that is, the second electrode 42 is the drain of the semiconductor device 100, the first electrode 41 is the source of the semiconductor device 100, V DS is the voltage difference between the second electrode 42 and the first electrode 41), the ordinate represents the current I DS The size of DS Refers to the magnitude of the current from the drain to the source in the semiconductor device 100, that is, the magnitude of the current from the second electrode 42 to the first electrode 41). It can be seen that the semiconductor device 100 is forward-conducting (that is, V DS >0) has good MOSFET characteristics, the current I DS The size is affected by the gate voltage V g Regulation, and the current I DS As the gate voltage V g As the threshold voltage V th About 3V.

[0110] Figure 7 A transfer characteristic curve diagram of a semiconductor device 100 in reverse conduction provided in some embodiments of the present disclosure (that is, a transfer characteristic curve diagram when the drain voltage of the semiconductor device 100 is less than the source voltage, in the case where the first electrode 41 is the source of the semiconductor device 100 and the second electrode 42 is the drain of the semiconductor device 100, V SD is the voltage difference between the first electrode 41 and the second electrode 42), specifically: Figure 4 The transfer characteristic curve of the semiconductor device 100 in reverse conduction is shown in FIG. SD The size of (that is, the second electrode 42 is the drain of the semiconductor device 100, the first electrode 41 is the source of the semiconductor device 100, V SD is the voltage difference between the first electrode 41 and the second electrode 42), the ordinate represents the current I SD The size of SDRefers to the current from the source to the drain in the semiconductor device 100, that is, the current from the first electrode 41 to the second electrode 42). At this time, it can be seen that under the condition that no voltage is applied to the gate, that is, the gate voltage V g =0V, the semiconductor device 100 realizes reverse conduction, the conduction voltage is about 2.1V, and at V SD At 10V the current density is very high.

[0111] Figure 8 The output characteristic curve of a semiconductor device 100 provided in some embodiments of the present disclosure during forward conduction is specifically as follows: Figure 5 The output characteristic curve of the semiconductor device 100 shown in FIG. 1 is a graph showing the output characteristic curve of the semiconductor device 100 when it is forward-conducting. DS The size of (that is, the second electrode 42 is the drain of the semiconductor device 100, the first electrode 41 is the source of the semiconductor device 100, V DS is the voltage difference between the second electrode 42 and the first electrode 41), the ordinate represents the current I DS The size of DS Refers to the magnitude of the current from the drain to the source in the semiconductor device 100, that is, the magnitude of the current from the second electrode 42 to the first electrode 41). It can be seen that the semiconductor device 100 is forward-conducting (that is, V DS >0) has good MOSFET characteristics, the current I DS The size is affected by the gate voltage V g Regulation, and the current I DS As the gate voltage V g As the threshold voltage V th About 4V.

[0112] Figure 9 A transfer characteristic curve diagram of a semiconductor device 100 in reverse conduction provided in some embodiments of the present disclosure (that is, a transfer characteristic curve diagram when the drain voltage of the semiconductor device 100 is less than the source voltage, in the case where the first electrode 41 is the source of the semiconductor device 100 and the second electrode 42 is the drain of the semiconductor device 100, V SD is the voltage difference between the first electrode 41 and the second electrode 42), specifically: Figure 5 The transfer characteristic curve of the semiconductor device 100 in reverse conduction is shown in FIG. SD The vertical axis represents the current I SD The size of SDRefers to the current from the source to the drain in the semiconductor device 100, that is, the current from the first electrode 41 to the second electrode 42). At this time, it can be seen that under the condition that no voltage is applied to the gate, that is, the gate voltage V g =0V, the semiconductor device 100 realizes reverse conduction, and the conduction voltage is about 1.7V. Figure 4 The semiconductor device 100 shown, Figure 5 In the semiconductor device 100 shown, the third doped layer 33 is provided on the side of the first doped layer 31 away from the gate 20, and the third doped layer 33 contacts the surface of the first doped layer 31 away from the gate 20. The doping type of the third doped layer 33 is opposite to the doping type of the first doped layer 31, and the doping type of the third doped layer 33 is P-type. This slightly reduces the forward current of the semiconductor device 100 but increases the reverse current. Since the Schottky metal layer 60 is provided on the side of the second doped layer 32 away from the gate 20, the Schottky metal layer 60 contacts the second doped layer 32, which increases the reverse current of the semiconductor device 100 and reduces the voltage of the semiconductor device 100 by 0.4V when the semiconductor device 100 is reversely conducted.

[0113] The present disclosure also provides a method for preparing a semiconductor device. Figure 10 , including the following steps:

[0114] Step S1: Combine with reference Figure 11-12 A stacked structure 3 is formed on one side of the substrate 10 along a first direction X, where the first direction X is the thickness direction of the substrate 10; the stacked structure 3 has a first opening K1 that passes through the stacked structure 3 along the first direction X, and the stacked structure 3 includes a current blocking layer 30 and a first doped layer 31 stacked along the first direction X. The first doped layer 31 is farther away from the substrate 10 than the current blocking layer 30.

[0115] Here, you can refer to Figure 11 The substrate 10 includes: a first sublayer 11 and a second sublayer 12 stacked along a first direction X, the doping type of the first sublayer 11 and the doping type of the second sublayer 12 are the same, and the doping concentration of the second sublayer 12 is less than the doping concentration of the first sublayer 11.

[0116] For example, the doping concentration of the first sub-layer 11 is greater than 5E18cm -3 For example, the doping concentration of the first sublayer 11 is 5E18cm -3 ~5E19cm -3 .

[0117] For example, the doping concentration of the second sub-layer 12 is 1E16 cm -3 ~5E17cm -3 For example, the doping concentration of the second sub-layer 12 is 1E16 cm-3 or 5E17cm -3 .

[0118] In some embodiments, the materials of the first sub-layer 11 and the second sub-layer 12 both include gallium oxide.

[0119] The doping ions of the first sub-layer 11 and the second sub-layer 12 include silicon ions.

[0120] In some embodiments, the thickness of the first sub-layer 11 is 600 μm-700 μm, for example, 600 μm, 650 μm or 700 μm.

[0121] In some embodiments, the thickness of the second sub-layer 12 is 6 μm to 8 μm, for example, 6 μm, 7 μm or 8 μm.

[0122] In some embodiments, the second sub-layer 12 is formed on one side of the first sub-layer 11 along the first direction X. The process of forming the second sub-layer 12 includes a Metal-Organic Chemical Vapor Deposition (MOCVD) process.

[0123] In the process of forming the second sublayer 12, the gallium source used includes trimethylgallium (TMGa), the oxygen source is high-purity oxygen, the doping source is silane (SiH4), the carrier gas used is argon, the growth temperature is 700°C~800°C, for example, 700°C, 750°C or 800°C, and the growth pressure is 35mbar~45mbar, for example, 35mbar, 40mbar or 45mbar.

[0124] The molar flow rate of trimethylgallium is 35 μmol / min to 40 μmol / min, for example, 35 μmol / min, 38 μmol / min or 40 μmol / min.

[0125] The molar flow rate of oxygen is 17000 μmol / min to 19000 μmol / min, for example, 17000 μmol / min, 18000 μmol / min, or 19000 μmol / min.

[0126] The molar flow rate of silane is 0.0004 μmol / min to 0.0006 μmol / min, for example, 0.0004 μmol / min, 0.0005 μmol / min, or 0.0006 μmol / min.

[0127] Wherein, step S1 includes:

[0128] Step S11: Reference Figure 11An initial stacked structure 3D is formed on one side of the substrate 10 along the first direction X. The initial stacked structure 3D includes an initial current blocking layer 300 and an initial first doping layer 310 stacked along the first direction X. The initial first doping layer 310 is farther away from the substrate 10 than the initial current blocking layer 300.

[0129] In some embodiments, the process of forming the initial current blocking layer 300 and the initial first doping layer 310 includes a metal organic chemical vapor deposition process.

[0130] In some embodiments, during the formation of the initial current blocking layer 300, the gallium source used includes trimethylgallium (TMGa), the oxygen source is high-purity oxygen, the magnesium source used includes bis(cyclopentadienyl) magnesium (Cp2Mg), the carrier gas used is argon, the growth temperature is 700°C to 800°C, for example, 700°C, 750°C or 800°C, and the growth pressure is 35 mbar to 45 mbar, for example, 35 mbar, 40 mbar or 45 mbar.

[0131] The molar flow rate of trimethylgallium is 35 μmol / min to 40 μmol / min, for example, 35 μmol / min, 38 μmol / min or 40 μmol / min.

[0132] The molar flow rate of oxygen is 17000 μmol / min to 19000 μmol / min, for example, 17000 μmol / min, 18000 μmol / min, or 19000 μmol / min.

[0133] The molar flow rate of bis(cyclopentadienyl)magnesium is 2.4 μmol / min to 2.6 μmol / min, for example, 2.4 μmol / min, 2.5 μmol / min or 2.6 μmol / min.

[0134] In some embodiments, the thickness of the initial current blocking layer 300 is 0.8 μm to 1.2 μm, for example, 0.8 μm, 1.0 μm, or 1.2 μm.

[0135] In some embodiments, during the process of forming the initial first doping layer 310, the gallium source used includes trimethylgallium (TMGa), the oxygen source is high-purity oxygen, the doping source is silane (SiH4), the carrier gas used is argon, the growth temperature is 700°C~800°C, for example, 700°C, 750°C or 800°C, and the growth pressure is 35mbar~45mbar, for example, 35mbar, 40mbar or 45mbar.

[0136] The molar flow rate of trimethylgallium is 35 μmol / min to 40 μmol / min, for example, 35 μmol / min, 38 μmol / min or 40 μmol / min.

[0137] The molar flow rate of oxygen is 17000 μmol / min to 19000 μmol / min, for example, 17000 μmol / min, 18000 μmol / min, or 19000 μmol / min.

[0138] The molar flow rate of silane is 1.0 μmol / min to 1.2 μmol / min, for example, 1.0 μmol / min, 1.1 μmol / min, or 1.2 μmol / min.

[0139] In some embodiments, the thickness of the initial first doping layer 310 is 0.4 μm to 0.6 μm, for example, 0.4 μm, 0.5 μm, or 0.6 μm.

[0140] Step S12: Combine with reference Figure 11 and Figure 12 , the initial stacked structure 3D located in the first target area Q1 is removed to form a first opening K1.

[0141] In step S12 , the initial stacked structure 3D located in the first target area Q1 is removed, and the initial stacked structure 3D located in the second target area Q2 is also removed to form a second opening K2 , which surrounds the first opening K1 .

[0142] Here, the process for removing the initial stacked structure 3D located in the first target region Q1 and the second target region Q2 includes dry etching. Specifically, inductively coupled plasma can be used. During etching, the RF power on the inductively coupled coil is set to 300 W, the bias power is set to 200 W, and the pressure in the process chamber is set to 1 Pa. The etching gases used are carbon tetrafluoride (CF4) and argon (Ar). The etching rate is 80 nm / min to 120 nm / min, for example, 80 nm / min, 100 nm / min, or 120 nm / min.

[0143] The flow rate of carbon tetrafluoride (CF4) is 28 sccm to 32 sccm, such as 28 sccm, 30 sccm or 32 sccm; the flow rate of argon (Ar) is 4 sccm to 6 sccm, such as 4 sccm, 5 sccm or 6 sccm.

[0144] The material of the mask used to remove the initial stacked structure 3D located in the first target area Q1 and the second target area Q2 includes metal, for example, nickel.

[0145] In some embodiments, continue to refer to Figure 11 , forming an initial stacked structure 3D on one side of the substrate 10 along the first direction X, further comprising step S10: before forming the initial current blocking layer 300, forming an initial second doping layer 320 on the substrate 10; the doping type of the second doping layer 320 is the same as the doping type of the first doping layer 310; referring to Figure 12 In the process of removing the initial stacked structure 3D located in the first target region Q1 , the initial second doping layer 320 located in the first target region Q1 is also removed.

[0146] The process of forming the initial second doping layer 320 includes a metal organic chemical vapor deposition process.

[0147] In some embodiments, during the process of forming the initial second doping layer 320, the gallium source used includes trimethylgallium (TMGa), the oxygen source is high-purity oxygen, the doping source is silane (SiH4), the carrier gas used is argon, the growth temperature is 700°C~800°C, for example, 700°C, 750°C or 800°C, and the growth pressure is 35mbar~45mbar, for example, 35mbar, 40mbar or 45mbar.

[0148] The molar flow rate of trimethylgallium is 35 μmol / min to 40 μmol / min, for example, 35 μmol / min, 38 μmol / min or 40 μmol / min.

[0149] The molar flow rate of oxygen is 17000 μmol / min to 19000 μmol / min, for example, 17000 μmol / min, 18000 μmol / min, or 19000 μmol / min.

[0150] The molar flow rate of silane is 1.0 μmol / min to 1.2 μmol / min, for example, 1.0 μmol / min, 1.1 μmol / min, or 1.2 μmol / min.

[0151] In some embodiments, the thickness of the initial second doping layer 320 is 0.4 μm to 0.6 μm, for example, 0.4 μm, 0.5 μm, or 0.6 μm.

[0152] Combined with reference Figure 11 and Figure 12 In the process of removing the initial stacked structure located in the second target region Q2, the initial second doping layer 320 located in the second target region Q2 is also removed.

[0153] Step S2: Reference Figure 13, forming a Schottky metal layer 60; in the projection onto the surface of the substrate 10 away from the stacked structure 3, the Schottky metal layer 60 is located on a side of the stacked structure 3 away from the first opening K1.

[0154] Here, a lift-off technique may be used to form a Schottky metal layer 60 at the bottom of the second opening K2. The process for forming the Schottky metal layer 60 includes an electron beam evaporation process, wherein the vacuum degree during evaporation is 5E-6 Torr and the evaporation rate is 1 angstrom / second to 2 angstroms / second, for example, 1 angstrom / second or 2 angstroms / second.

[0155] The material of the Schottky metal layer 60 includes metal, such as nickel, platinum, and gold.

[0156] The thickness of the Schottky metal layer 60 is 500 nm to 520 nm, for example, 500 nm, 510 nm or 520 nm.

[0157] Step S3: Combine with reference Figure 14-15 , forming a first dielectric layer 51 and a second dielectric layer 52; the first dielectric layer 51 is located at the bottom and sidewall of the first opening K1, and the first dielectric layer 51 forms a first groove G1; the second dielectric layer 52 is located on the side of the stacked structure 3 away from the first opening K1.

[0158] Here, step S3 includes:

[0159] Step S31: Reference Figure 14 An initial dielectric layer 50 is formed on the bottom and sidewalls of the first opening K1 , the sidewalls of the stacked structure 3 , and the side of the stacked structure 3 and the Schottky metal layer 60 away from the substrate 10 .

[0160] Here, the process of forming the initial dielectric layer 50 includes an atomic layer deposition (ALD) process.

[0161] In the process of forming the initial dielectric layer 50 , the sources used are tetrakis(ethylmethylamino)hafnium (TEMAHf) and H 2 O, the growth temperature is 200° C., the growth pressure is 1000 Pa, and the growth is performed for 400 cycles.

[0162] The material of the initial dielectric layer 50 includes hafnium dioxide (HfO 2 ).

[0163] The thickness of the initial dielectric layer 50 is 20 nm to 32 nm, for example, 20 nm, 28 nm, 30 nm or 32 nm.

[0164] The measured relative permittivity of the initial dielectric layer 50 at an alternating electric field frequency of 1 MHz is 25.

[0165] Step S32: Combine with reference Figure 14 and Figure 15 The initial dielectric layer 50 located on the side of the stacked structure 3 away from the substrate 10 and the initial dielectric layer 50 located on the side of the Schottky metal layer 60 away from the substrate 10 are removed. The initial dielectric layer 50 located at the bottom and sidewalls of the first opening K1 forms a first dielectric layer 51; the initial dielectric layer 50 located on the side of the stacked structure 3 away from the first opening K1 forms a second dielectric layer 52.

[0166] Here, the process for removing the initial dielectric layer 50 on the side of the stacked structure 3 away from the substrate 10 and the initial dielectric layer 50 on the side of the Schottky metal layer 60 away from the substrate 10 includes dry etching. Specifically, inductively coupled plasma can be used. During etching, the RF power on the inductively coupled coil is set to 300 W, the bias power is set to 200 W, and the pressure in the process chamber is set to 1 Pa. The etching gases used are carbon tetrafluoride (CF4) and argon (Ar). The etching rate is 80 nm / min to 120 nm / min, for example, 80 nm / min, 100 nm / min, or 120 nm / min.

[0167] The flow rate of carbon tetrafluoride (CF4) is 8 sccm to 12 sccm, such as 8 sccm, 20 sccm or 12 sccm; the flow rate of argon (Ar) is 1 sccm to 4 sccm, such as 1 sccm, 2 sccm or 4 sccm.

[0168] Step S4: Reference Figure 16 , a gate 20 is formed in the first groove G1.

[0169] Here, the gate 20 is formed in the first groove G1 through a lift-off process.

[0170] The process for forming the gate 20 includes an electron beam evaporation process, and the vacuum degree during evaporation is 5E-6 Torr.

[0171] The gate 20 is made of metal, such as nickel or aluminum. During the preparation process, the evaporation rate of nickel is 0.5 angstroms / second, and the evaporation rate of aluminum is 1 angstrom / second.

[0172] When the gate 20 is made of nickel, the thickness of the gate 20 is 80 nm to 120 nm, such as 80 nm, 100 nm or 120 nm. When the gate 20 is made of aluminum, the thickness of the gate 20 is 180 nm to 220 nm, such as 180 nm, 200 nm or 200 nm.

[0173] Step S5: Reference Figure 17 A first electrode 41 is formed on a side of the stacked structure 3 away from the substrate 10 and a side of the second dielectric layer 52 away from the gate 20 .

[0174] Here, the process of forming the first electrode 41 includes an electron beam evaporation process, and the vacuum degree during evaporation is 5E-6 Torr. After the first electrode 41 is deposited, an annealing process is required, and the annealing process time is 1 minute and the annealing process temperature is 475°C.

[0175] The material of the first electrode 41 includes metal, such as nickel or aluminum. During the preparation process, the evaporation rate of nickel is 0.5 angstroms / second, and the evaporation rate of aluminum is 1 angstrom / second.

[0176] The thickness of the first electrode 41 is 80 nm to 120 nm, for example, 80 nm, 100 nm or 120 nm.

[0177] Step S6: Continue to refer Figure 17 , a second electrode 42 is formed on a side of the substrate 10 away from the gate 20 .

[0178] Here, the process of forming the second electrode 42 includes an electron beam evaporation process, and the vacuum degree during evaporation is 5E-6 Torr. After the second electrode 42 is deposited, an annealing process is required, and the annealing process time is 1 minute and the annealing process temperature is 475°C.

[0179] The material of the second electrode 42 includes metal, such as nickel or aluminum. During the preparation process, the evaporation rate of nickel is 0.5 angstroms / second, and the evaporation rate of aluminum is 1 angstrom / second.

[0180] The thickness of the second electrode 42 is 80 nm to 120 nm, for example, 80 nm, 100 nm or 120 nm.

[0181] The present disclosure also provides a method for preparing a semiconductor device. Figure 18 , including the following steps:

[0182] Step Q1: Combine with reference Figures 19 and 20 A stacked structure 3 is formed on one side of the substrate 10 along a first direction X, where the first direction X is the thickness direction of the substrate 10. The stacked structure 3 has a first opening K1 extending through the stacked structure 3 along the first direction X. The stacked structure 3 includes a current blocking layer 30 and a first doped layer 31 stacked along the first direction X. The first doped layer 31 is further away from the substrate 10 than the current blocking layer 30.

[0183] Here, step Q1 may refer to step S1 in the previous embodiment, and will not be described in detail here.

[0184] Step Q2: Reference Figure 21-22, forming a third doping layer 33; the third doping layer 33 is arranged on the side of the first doping layer 31 away from the gate 20, and on the side of the current blocking layer 30 away from the substrate 10, and the third doping layer 33 is in contact with the surface of the first doping layer 31 away from the gate 20; the doping type of the third doping layer 33 is opposite to the doping type of the first doping layer 31.

[0185] The process of forming the third doping layer 33 includes a radio frequency magnetron sputtering process.

[0186] In some embodiments, during the formation of the third doped layer 33, the target used is a 5% Li-doped NiO ceramic, the growth temperature is room temperature (25° C.), the growth pressure is 25 mtorr, the growth time is 2 hours, and the hole concentration is 5E18 cm-3 to 6E18 cm-3, for example, 5E18 cm-3 or 6E18 cm-3. The flow rate of argon gas is 18 sccm to 22 sccm, for example, 18 sccm, 20 sccm, or 22 sccm. The flow rate of oxygen gas is 8 sccm to 12 sccm, for example, 8 sccm, 10 sccm, or 12 sccm.

[0187] In some embodiments, the thickness of the third doping layer 33 is 480 nm to 520 nm, for example, 480 nm, 500 nm, or 520 nm.

[0188] refer to Figure 21 Before forming the third doping layer 33 , the process further includes removing a portion of the first doping layer 31 .

[0189] In some embodiments, the process for removing a portion of the first doped layer 31 includes dry etching, using a mask comprising photoresist, and an etching depth of 0.5 μm. Specifically, an inductively coupled plasma (ICP) can be used. During etching, the RF power on the inductively coupled coil is set to 300 W, the bias power is set to 200 W, and the process chamber pressure is set to 1 Pa. The etching gases used are carbon tetrafluoride (CF4) and argon (Ar). The etching rate is 80 nm / min to 120 nm / min, for example, 80 nm / min, 100 nm / min, or 120 nm / min.

[0190] The flow rate of carbon tetrafluoride (CF4) is 28 sccm to 32 sccm, such as 28 sccm, 30 sccm or 32 sccm; the flow rate of argon (Ar) is 4 sccm to 6 sccm, such as 4 sccm, 5 sccm or 6 sccm.

[0191] Step Q3: Reference Figure 23 , forming a Schottky metal layer 60; in the projection onto the surface of the substrate 10 away from the stacked structure 3, the Schottky metal layer 60 is located on a side of the stacked structure 3 away from the first opening K1.

[0192] In step Q2 and step Q3, step Q2 may be performed first and then step Q3, or step Q3 may be performed first and then step Q2.

[0193] Step Q4: Combine with reference Figure 24-25 , forming a first dielectric layer 51 and a second dielectric layer 52; the first dielectric layer 51 is located at the bottom and sidewall of the first opening K1, and the first dielectric layer 51 forms a first groove G1; the second dielectric layer 52 is located on the side of the stacked structure 3 away from the first opening K1.

[0194] Here, step Q4 includes:

[0195] Step Q41: Reference Figure 24 An initial dielectric layer 50 is formed on the bottom and sidewalls of the first opening K1 , the sidewalls of the stacked structure 3 , the surface of the third doped layer 33 , and the side of the stacked structure 3 and the Schottky metal layer 60 away from the substrate 10 .

[0196] Step Q42: Combine with reference Figure 24 and Figure 25 The initial dielectric layer 50 located on the side of the stacked structure 3 away from the substrate 10, the initial dielectric layer 50 located on the side of the Schottky metal layer 60 away from the substrate 10, and a portion of the initial dielectric layer 50 located on the side of the third doped layer 33 away from the substrate 10 are removed. The initial dielectric layer 50 located at the bottom and sidewalls of the first opening K1 forms a first dielectric layer 51; the initial dielectric layer 50 located on the side of the stacked structure 3 away from the first opening K1 forms a second dielectric layer 52.

[0197] Step Q5: Reference Figure 26 , a gate 20 is formed in the first groove G1.

[0198] Step Q6: Reference Figure 26 A first electrode 41 is formed on a side of the stacked structure 3 away from the substrate 10 and a side of the second dielectric layer 52 away from the gate 20 .

[0199] Step Q6 includes:

[0200] Step Q61: Reference Figure 26 A first sub-electrode 411 is formed on a surface of the first doping layer 31 away from the substrate 10 .

[0201] Here, the process of forming the first sub-electrode 411 includes a lift-off process. When forming the first sub-electrode 411 , the vacuum degree during metal evaporation is 5E-6 Torr, and the metal evaporation rate is 1.0 angstrom / second.

[0202] The material of the first sub-electrode 411 includes metal, such as nickel or gold.

[0203] Exemplarily, when the material of the first sub-electrode 411 is nickel, the thickness of the first sub-electrode 411 is 180 nm to 220 nm, for example, 180 nm, 200 nm, or 220 nm.

[0204] Exemplarily, when the material of the first sub-electrode 411 is gold, the thickness of the first sub-electrode 411 is 45 nm to 55 nm, for example, 45 nm, 50 nm, or 55 nm.

[0205] Step Q62: Reference Figure 26 A second sub-electrode 412 is formed on a surface of the third doping layer 33 away from the substrate 10 and on a side of the second dielectric layer 52 away from the gate 20 , and the second sub-electrode 412 is connected to the first sub-electrode 411 .

[0206] Here, the process of forming the second sub-electrode 412 includes a lift-off process. When forming the second sub-electrode 412 , the vacuum degree during metal evaporation is 5E-6 Torr, and the metal evaporation rate is 1.0 angstrom / second.

[0207] The material of the second sub-electrode 412 includes metal, such as titanium or gold.

[0208] Exemplarily, when the material of the second sub-electrode 412 is titanium, the thickness of the second sub-electrode 412 is 180 nm to 220 nm, for example, 180 nm, 200 nm, or 220 nm.

[0209] Exemplarily, when the material of the second sub-electrode 412 is gold, the thickness of the second sub-electrode 412 is 18 nm to 22 nm, for example, 18 nm, 20 nm, or 22 nm.

[0210] Among them, step Q61 can be executed first and then step Q62, or step Q62 can be executed first and then step Q61, without limitation.

[0211] Step Q7: Reference Figure 27 , a second electrode 42 is formed on a side of the substrate 10 away from the gate 20 .

[0212] Here, the process for forming the second electrode 42 includes a lift-off process. The vacuum during evaporation is 5E-6 Torr, and the metal evaporation rate is 1.0 angstroms / second. After the second electrode 42 is deposited, an annealing process is required. The annealing process lasts for 1 minute and the annealing temperature is 475°C.

[0213] The material of the second electrode 42 includes metal, such as titanium or gold.

[0214] When the material of the second electrode 42 is titanium, the thickness of the second electrode 42 is 18 nm to 22 nm, for example, 18 nm, 20 nm, or 22 nm.

[0215] When the material of the second electrode 42 is gold, the thickness of the second electrode 42 is 180 nm to 220 nm, for example, 180 nm, 200 nm, or 220 nm.

[0216] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that a person skilled in the art can conceive within the technical scope disclosed in the present disclosure should be included within the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A semiconductor device, characterized in that: include: substrate; a gate, provided on one side of the substrate along a first direction, where the first direction is a thickness direction of the substrate; a stacked structure, disposed on one side of the substrate in the first direction and at least on one side of the gate in a second direction, the second direction being perpendicular to the first direction; the stacked structure comprising a current blocking layer and a first doped layer stacked along the first direction, the first doped layer being further away from the substrate than the current blocking layer; a first electrode disposed on a side of the stacked structure away from the substrate and a side of the stacked structure away from the gate along the second direction; a first dielectric layer, provided between the substrate and the gate, and between the stacked structure and the gate; a second dielectric layer, disposed on a side of the stacked structure away from the gate along the second direction, and located between the first portion of the first electrode and the stacked structure; the first portion of the first electrode being a portion of the first electrode disposed on a side of the stacked structure away from the gate along the second direction; The second electrode is arranged on a side of the substrate away from the gate.

2. The semiconductor device according to claim 1, wherein Also includes: a second doping layer, disposed between the current blocking layer and the substrate; The doping type of the second doping layer is the same as the doping type of the first doping layer; The first dielectric layer is also located between the gate and the second doped layer.

3. The semiconductor device according to claim 2, wherein The doping concentration of the second doping layer is greater than the doping concentration of the current blocking layer.

4. The semiconductor device according to claim 2, wherein Also includes: a Schottky metal layer, disposed on a side of the second doped layer away from the gate and in contact with the second doped layer; The Schottky metal layer includes a first surface and a second surface opposite to each other along the first direction. The first surface is farther away from the substrate than the second surface. The first surface contacts the first electrode, and the second surface contacts the substrate.

5. The semiconductor device according to claim 1, wherein Also includes: a Schottky metal layer, wherein in a projection onto a surface of the substrate away from the stacked structure, the Schottky metal layer is located on a side of the stacked structure away from the gate, and the Schottky metal layer is embedded in the substrate; The Schottky metal layer is away from a surface of the substrate and contacts the first electrode.

6. The semiconductor device according to claim 4 or 5, characterized in that The second dielectric layer is located on a side of the Schottky metal layer away from the substrate.

7. The semiconductor device according to claim 1, wherein Also includes: a third doping layer, provided on a side of the current blocking layer away from the substrate; The third doping layer is provided on a side of the first doping layer away from the gate, and is in contact with a surface of the first doping layer away from the gate; the doping type of the third doping layer is opposite to that of the first doping layer; The first electrode is further provided on a side of the third doping layer away from the substrate and a side of the third doping layer away from the gate.

8. The semiconductor device according to claim 7, wherein: The doping concentration of the third doping layer is greater than the doping concentration of the current blocking layer.

9. The semiconductor device according to claim 7, wherein: The second dielectric layer covers a surface of the third doped layer away from the gate, and a surface of the current blocking layer away from the gate.

10. The semiconductor device according to claim 1, wherein The doping concentration of the first doping layer is greater than the doping concentration of the current blocking layer.

11. The semiconductor device according to claim 1, wherein The substrate comprises: a first sublayer and a second sublayer stacked along the first direction, wherein the second sublayer is closer to the gate than the first sublayer; The doping type of the first sublayer and the doping type of the second sublayer are both the same as the doping type of the first doping layer, and the doping concentration of the second sublayer is less than the doping concentration of the first sublayer.

12. The semiconductor device according to any one of claims 1 to 5 and 7 to 11, wherein: The material of the first doping layer includes gallium oxide, and the doping ions include silicon ions; The material of the current blocking layer includes gallium oxide, and the doping ions include magnesium ions.

13. The semiconductor device according to any one of claims 7 to 9, wherein: The material of the third doping layer includes nickel oxide, and the doping ions include lithium ions.

14. The semiconductor device according to any one of claims 1 to 5 and 7 to 11, wherein: The stacked structure has a first opening penetrating the stacked structure along the first direction. The first dielectric layer is located at the bottom and sidewalls of the first opening. The first dielectric layer forms a first groove. The gate is located in the first groove.

15. A power module, characterized in that: include: The semiconductor device according to any one of claims 1 to 14.

16. An electronic device, characterized in that: include: The power module according to claim 15.

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