A method for preparing Micro LEDs with right-angle or nearly right-angle sidewalls

Abstract

The present application discloses a method for preparing Micro LEDs with right-angle or nearly right-angle sidewalls, comprising the following steps: S1, depositing a mask layer on the surface of an epitaxial layer; S2, using a mask plate to obtain a patterned photoresist; S3, etching the mask layer, and obtaining a patterned mask layer after degumming; S4, etching the epitaxial layer using an improved ICP process; S5, depositing a passivation layer using a rotating sample stage with dynamically adjustable angles; S6, using a mask plate to obtain a patterned photoresist; S7, etching the passivation layer, and obtaining a patterned passivation layer after degumming; S8, using a mask plate to obtain a patterned photoresist; S9, plating a metal layer, and obtaining a patterned positive and negative electrode structure after degumming and metal lifting; the present application successfully solves the problem that the sidewalls of the Micro LED mesa cannot be designed with a large angle by adopting an improved film deposition process and an ICP etching process; it can achieve a smaller pixel pitch, and the process is not affected by the thickness of the epitaxial wafer, thereby preparing a Micro LED display product with better performance.

Description

Technical Field

[0001] The present invention relates to the field of Micro LED processing technology, and in particular to a method for preparing a Micro LED with right-angle or nearly right-angle sidewalls. Background Art

[0002] Micro LED, as a new display technology with great potential, generally refers to an LED display array with a single pixel size of less than 50μm. Its basic preparation process is similar to that of traditional LED, requiring multiple patterning, etching, coating and lift-off operations on the epitaxial layer to form pixels with light-emitting function and appropriate electrical connections.

[0003] However, the current Micro LED process still has room for improvement. Micro LEDs are extremely sensitive to pixel density and strive for extremely high PPI (Pixels Per Inch). However, the inclination angle of each mesa during the process is typically 60-80°. This makes the top size of the mesa smaller than the actual pixel size, hindering further reduction in pixel pitch. The main reasons for the mesa inclination are as follows:

[0004] 1. Etching process is difficult to achieve large tilt angle etching: The current mainstream Micro LED mesa etching solution is to use inductively coupled plasma (ICP) to etch the epitaxial layer, and the commonly used etching gas is boron trichloride ( ), chlorine ( ), argon (Ar), etc. are mixed in a certain proportion. When these gases etch the sample vertically, they will also produce horizontal etching, thus forming an inclined table. If you rashly pursue large-angle etching, such as quickly increasing the etching power and gas flow, the side wall roughness will not meet the requirements.

[0005] 2. Various coating processes have poor adhesion to large-angle tables: The current mainstream Micro LED coating processes mainly include magnetron sputtering, electron beam evaporation, plasma-enhanced chemical vapor deposition (PECVD), etc. These deposition methods are top-down longitudinal deposition. Therefore, when the table angle is too large (close to a right angle), it is difficult to deposit a film layer of appropriate thickness on the side wall, which will cause short circuits, open circuits and other problems. Summary of the Invention

[0006] The purpose of the present invention is to provide a method for preparing Micro LEDs with right-angle or near-right-angle sidewalls to address current Micro LED process issues such as insufficient luminous efficiency, inability to further reduce pixel size, and excessive requirements for epitaxial thickness, ultimately achieving a high-quality Micro LED display with high pixel density.

[0007] In order to solve the above technical problems, the technical solution adopted by the present invention is:

[0008] A method for preparing a Micro LED having right-angle or nearly right-angle sidewalls, comprising the following steps:

[0009] S1, depositing a mask layer with a thickness within a preset range on the surface of the epitaxial layer;

[0010] S2, spin-coating a photoresist on the mask layer, curing, UV exposure and developing, using a mask having a periodically arranged pattern to obtain a patterned photoresist;

[0011] S3, using the patterned photoresist as a mask, etching the mask layer by a plasma etching process, and obtaining a patterned mask layer after removing the resist;

[0012] S4, using the patterned mask layer as a mask, etching the epitaxial layer using an improved ICP process, wherein the improved ICP process includes:

[0013] S4.1, first etching step: etching the epitaxial layer using an etching gas;

[0014] S4.2, Passivation Layer Deposition: Deposit the passivation layer by chemical vapor deposition using a rotating sample stage with dynamically adjustable angles;

[0015] S4.3, second etching step: Use etching gas to continue etching the epitaxial layer to obtain the Micro LED mesa at the target angle;

[0016] S5, using the rotating sample stage capable of dynamically adjusting an angle, depositing a passivation layer having a thickness within a preset range through a chemical vapor deposition process;

[0017] S6, spin-coating a photoresist on the passivation layer, and performing curing, UV exposure, and development, using a mask having a periodically arranged pattern to obtain a patterned photoresist;

[0018] S7, etching the passivation layer using the patterned photoresist as a mask, and obtaining a patterned passivation layer after removing the resist;

[0019] S8, spin-coating a photoresist on the patterned passivation layer, and performing curing, UV exposure, and development treatment using a mask having a periodically arranged pattern to obtain a patterned photoresist;

[0020] S9, uses physical vapor deposition process to plate the metal layer, and obtains the patterned positive and negative electrode structure after debonding and metal lifting.

[0021] In a preferred embodiment, in step S1, the epitaxial layer material is GaN / InGaN with a thickness of 0.8-1.2 microns; a 100-2000 nm thick GaN layer is deposited on the surface of the epitaxial layer. Mask layer.

[0022] A preferred solution is that in step S2, A photoresist with a thickness of 500-3000nm is spin-coated on the mask layer, and after curing, it is exposed to UV light. Then, a developer is used to remove the exposed photoresist. The development time is 1-3 minutes. The mask plate is a periodically arranged circle, that is, the Micro LED mesa structure to be prepared. The area inside the circle is the light-shielding part, and the photoresist outside the circular area is exposed to UV light. The through-hole aperture is 1-5 microns, and the center spacing is 3-8 microns to obtain a patterned photoresist.

[0023] A preferred solution is that in step S3, the patterned photoresist in step S2 is used as a mask and an ICP process is used to etch the Mask layer, etching gas is and Ar gas mixture, The flow rate is 15-35sccm, the etching time is 300-500s, the etching rate is 0.2-5.0nm / s, and the pattern is obtained after de-resist. Mask layer.

[0024] A preferred solution is that in step S4, the graphical The mask layer is a mask, and the epitaxial layer is etched using an improved ICP etching process, wherein the improved ICP etching process includes:

[0025] S4.1, first step of etching: etching gas is and Ar gas mixture, The flow rate is 10-50sccm, The flow rate is 10-30sccm, the etching time is 150-250s, and the etching rate of the epitaxial layer is 30-60 ;

[0026] S4.2, passivation layer deposition: using a rotating sample stage with a tilt angle of 10-60° and a rotation speed of 1-20 rpm, by PECVD deposition Passivation layer, the reaction gas is , The flow rate is 1000-1500sccm, The flow rate is 200-400 sccm, the plasma source power is 80-120 W, the deposition temperature is 200-300 ° C, the deposition time is 200-400 s, and the deposition thickness is 20-150 nm;

[0027] S4.3, second step etching: etching gas is and Ar gas mixture, The flow rate is 10-50sccm, The flow rate is 10-30sccm, the etching time is 150-250s, and the etching rate of the epitaxial layer is 30-50 The lateral etching rate of the passivation layer is 3-7 , a Micro LED table with a right-angle or near-right-angle sidewall angle range of 85-95° is obtained, and the error between the top size of the table and the pixel size is ≤5%.

[0028] A preferred solution is that in step S5, a rotating sample stage with a tiltable angle is used to deposit a 200-400 nm thick layer by PECVD. Passivation layer, sample tilt angle is 10-60°, rotation speed is 5-20rpm, reaction gas is , The flow rate is 1000-1500sccm, The flow rate is 200-400 sccm, the plasma source power is 80-120 W, and the deposition temperature is 200-300 °C.

[0029] A preferred solution is that in step S6, A photoresist with a thickness of 500-3000nm is spin-coated on the passivation layer. After curing, it is exposed to UV light, and then a developer is used to remove the exposed photoresist. The development time is 1-3 minutes. The mask is a periodically arranged circular hole, corresponding to the Micro LED passivation layer structure to be prepared. The area outside the circular hole is the light-shielding part. The photoresist inside the circular hole is exposed to UV light. The through-hole aperture is 2-6 microns, and the center spacing is 3-8 microns to obtain a patterned photoresist.

[0030] A preferred solution is to use the patterned photoresist in step S6 as a mask to etch the Passivation layer, etching gas is and Ar gas mixture, The flow rate is 15-35sccm, the etching time is 300-500s, the etching rate is 0.2-5.0nm / s, and the pattern is obtained after de-resist. Mask layer.

[0031] A preferred solution is that in step S8, A photoresist with a thickness of 500-3000nm is spin-coated on the passivation layer. After curing, it is exposed to UV light, and then a developer is used to remove the exposed photoresist. The development time is 1-3 minutes. The mask is a periodically arranged circular hole, corresponding to the Micro LED passivation layer structure to be prepared. The area outside the circular hole is the light-shielding part. The photoresist inside the circular hole is exposed to UV light. The through-hole aperture is 2-6.4 microns, and the center spacing is 3-8 microns to obtain a patterned photoresist.

[0032] A preferred solution is that in step S9, the metal layer is plated using an electron beam evaporation process, and 200-400nm thick Cr, 200-400nm thick Pt, and 100-300nm thick Au are deposited in sequence, with a deposition rate of 0.5-1.5nm / s. After debonding and metal lifting, a patterned positive and negative electrode structure is obtained.

[0033] Due to the application of the above technical solution, the beneficial effects of this application compared with the prior art are:

[0034] The present application provides a method for preparing Micro LEDs with right-angle or near-right-angle sidewalls. By adopting an improved film deposition process and ICP etching process, it successfully solves the problem that the sidewalls of Micro LED terraces cannot be designed with angles greater than 80°. Furthermore, the Micro LED process with right-angle or near-right-angle terraces can achieve a smaller pixel pitch, a larger process window for each process segment, and the process is almost unaffected by the thickness of the epitaxial wafer, ultimately enabling the production of Micro LED display products with better performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the specific embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0036] Figure 1 Schematic diagram of the typical existing Micro LED production process;

[0037] Figure 2 Schematic comparison diagram of the principles of the existing typical deposition process and the improved passivation layer deposition process of step S4.2 of the present invention;

[0038] Figure 3 Schematic diagram of the improved ICP process of step S4 of the present invention;

[0039] Figure 4 Schematic diagram comparing the chip array before optimization and the chip array after optimization of the present invention;

[0040] Figure 5 Flowchart of the method for preparing Micro LEDs with right-angle or nearly right-angle sidewalls according to the present invention. DETAILED DESCRIPTION

[0041] In order to enable those skilled in the art to better understand the present invention, the following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of this application.

[0042] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present application described here. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0043] In this application, terms such as "upper," "lower," "left," "right," "front," "back," "top," "bottom," "inner," "outer," "center," "vertical," "horizontal," "transverse," and "longitudinal" indicate positions or locations based on the positions or locations shown in the accompanying drawings. These terms are primarily intended to better describe the present invention and its embodiments and are not intended to limit the devices, elements, or components indicated to having a specific orientation, or to being constructed or operated in a specific orientation.

[0044] Furthermore, some of the above terms may be used to express other meanings besides indicating a position or location. For example, the term "on" may also be used to indicate a dependency or connection in certain circumstances. Those skilled in the art will understand the specific meanings of these terms in the present invention based on the specific circumstances.

[0045] Furthermore, the terms "installed," "disposed," "provided with," "connected," "connected," and "socketed" should be interpreted broadly. For example, they can refer to fixed connections, removable connections, or integral structures; mechanical connections or electrical connections; direct connections or indirect connections through an intermediary; or internal communication between two devices, elements, or components. Those skilled in the art will understand the specific meanings of these terms in the present invention based on specific circumstances.

[0046] It should be noted that, in the absence of conflict, the embodiments and features of the embodiments in this application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0047] Example 1

[0048] Figure 1 Schematic diagram of the typical existing Micro LED production process;

[0049] See Figure 2-5 ,exist Figure 2 (a) is a schematic diagram of the principle of the existing typical deposition process. Figure 2 (b) is a schematic diagram of the principle of the improved passivation layer deposition process in step S4.2 of the present invention;

[0050] A method for preparing a Micro LED having right-angle or nearly right-angle sidewalls, comprising the following steps:

[0051] S1, depositing a mask layer with a thickness within a preset range on the surface of the epitaxial layer;

[0052] Specifically, a 100-2000 nm thick layer is deposited on the surface of the epitaxial layer. Mask layer; the epitaxial layer material is GaN / InGaN, with a thickness of 0.8-1.2 microns;

[0053] S2, spin-coating a photoresist on the mask layer, curing, UV exposure and developing, using a mask having a periodically arranged pattern to obtain a patterned photoresist;

[0054] Specifically, in the A photoresist with a thickness of 500-3000nm is spin-coated on the mask layer. After curing, it is exposed to UV light. Then, a developer is used to remove the exposed photoresist. The development time is 1-3 minutes. The mask is a periodically arranged circle, that is, the Micro LED mesa structure to be prepared. The area inside the circle is the light-shielding part, and the photoresist outside the circle is exposed to UV light. The aperture of the through hole is 1-5 microns, and the center spacing is 3-8 microns to obtain a patterned photoresist.

[0055] S3, using the patterned photoresist as a mask, etching the mask layer by a plasma etching process, and obtaining a patterned mask layer after removing the resist;

[0056] Specifically, the patterned photoresist in step S2 is used as a mask and an ICP process is used to etch Mask layer, etching gas is and Ar gas mixture, The flow rate is 15-35sccm, the etching time is 300-500s, the etching rate is 0.2-5.0nm / s, and the pattern is obtained after de-resist. mask layer;

[0057] S4, using the patterned mask layer as a mask, the epitaxial layer is etched using an improved ICP process, as shown in the attached Figure 3 As shown, the improved ICP process includes:

[0058] S4.1, first etching step: etching the epitaxial layer using an etching gas;

[0059] S4.2, Passivation Layer Deposition: Deposit the passivation layer by chemical vapor deposition using a rotating sample stage with dynamically adjustable angles;

[0060] S4.3, second etching step: Use etching gas to continue etching the epitaxial layer to obtain the Micro LED mesa at the target angle;

[0061] Specifically, the graphical The mask layer is a mask, and the epitaxial layer is etched using an improved ICP etching process, wherein the improved ICP etching process includes:

[0062] S4.1, first step of etching: etching gas is and Ar gas mixture, The flow rate is 10-50sccm, The flow rate is 10-30sccm, the etching time is 150-250s, and the etching rate of the epitaxial layer is 20-60 ;

[0063] S4.2, passivation layer deposition: using a sample stage with a tilt angle of 10-60° and a rotation speed of 1-20 rpm, by PECVD deposition Passivation layer, the reaction gas is , The flow rate is 1000-1500sccm, The flow rate is 200-400 sccm, the plasma source power is 80-120 W, the deposition temperature is 200-300 ° C, the deposition time is 200-400 s, and the deposition thickness is 20-150 nm;

[0064] S4.3, second step etching: etching gas is and Ar gas mixture, The flow rate is 10-50sccm, The flow rate is 10-30sccm, the etching time is 150-250s, and the etching rate of the epitaxial layer is 30-50 The lateral etching rate of the passivation layer is 3-7 , obtaining a right-angle or nearly right-angle Micro LED table;

[0065] S5, using the rotating sample stage capable of dynamically adjusting an angle, depositing a passivation layer having a thickness within a preset range through a chemical vapor deposition process;

[0066] Specifically, the sample stage with a tiltable angle is used to deposit a 200-400 nm thick layer by PECVD. Passivation layer, sample tilt angle is 10-60°, rotation speed is 5-20rpm, reaction gas is , The flow rate is 1000-1500sccm, The flow rate is 200-400 sccm, the plasma source power is 80-120 W, and the deposition temperature is 200-300 ° C;

[0067] S6, spin-coating a photoresist on the passivation layer, and performing curing, UV exposure, and development, using a mask having a periodically arranged pattern to obtain a patterned photoresist;

[0068] Specifically, in the A photoresist with a thickness of 500-3000nm is spin-coated on the passivation layer. After curing, it is exposed to UV light. Then, a developer is used to remove the exposed photoresist. The development time is 1-3 minutes. The mask is a periodically arranged circular hole corresponding to the Micro LED passivation layer structure to be prepared. The area outside the circular hole is the light-shielding part. The photoresist inside the circular hole is exposed to UV light. The through-hole aperture is 2-6 microns, and the center spacing is 3-8 microns to obtain a patterned photoresist.

[0069] S7, etching the passivation layer using the patterned photoresist as a mask, and obtaining a patterned passivation layer after removing the resist;

[0070] Specifically, the patterned photoresist in S6 is used as a mask for etching Passivation layer, etching gas is and Ar gas mixture, The flow rate is 15-35sccm, the etching time is 300-500s, the etching rate is 0.2-5.0nm / s, and the pattern is obtained after de-resist. mask layer;

[0071] S8, spin-coating a photoresist on the patterned passivation layer, and performing curing, UV exposure, and development, using a mask having a periodically arranged pattern to obtain a patterned photoresist;

[0072] Specifically, in the graphical A photoresist with a thickness of 500-3000nm is spin-coated on the passivation layer. After curing, it is exposed to UV light. Then, a developer is used to remove the exposed photoresist. The development time is 1-3 minutes. The mask is a periodically arranged circular hole corresponding to the Micro LED passivation layer structure to be prepared. The area outside the circular hole is the light-shielding part. The photoresist inside the circular hole is exposed to UV light. The through-hole aperture is 2-6.4 microns, and the center spacing is 3-8 microns to obtain a patterned photoresist.

[0073] S9, using physical vapor deposition process to deposit metal layer, and after debonding and metal lift-off, a patterned positive and negative electrode structure is obtained;

[0074] Specifically, the metal layer is plated using an electron beam evaporation process, depositing 200-400nm thick Cr, 200-400nm thick Pt, and 100-300nm thick Au in sequence, with a deposition rate of 0.5-1.5nm / s. After debonding and metal lifting, a patterned positive and negative electrode structure is obtained.

[0075] Example 2

[0076] This application provides a method for preparing a Micro LED having right-angled or nearly right-angled sidewalls, comprising the following steps:

[0077] S1, deposit a 300nm thick layer on the surface of the Epi epitaxial layer Mask layer:

[0078] On the surface of the Epi epitaxial layer (made of GaN / InGaN material with a thickness of 1 micron), a 300nm thick layer was deposited using PECVD (plasma enhanced chemical vapor deposition) method. mask layer;

[0079] The reaction gas is (flow rate 1200sccm) and (flow rate 300 sccm), the plasma source power is 100 W, and the deposition temperature is 250 °C;

[0080] Micro-nano structures such as electrodes can be prepared in advance on the surface of the Epi epitaxial wafer.

[0081] S2, patterning process (spin coating, exposure, development):

[0082] In step S1, Spin-coat photoresist (1500nm thickness) on the mask layer, using positive photoresist (5214 positive photoresist is preferred);

[0083] After curing, the film was exposed to UV light, and then a developer (TMAH aqueous solution) was used to remove the exposed photoresist. The development time was 2 minutes.

[0084] The mask is a periodically arranged circle, which is the Micro LED mesa structure to be prepared. The area inside the circle is the light-shielding part, and the photoresist outside the circular area is exposed to ultraviolet light. The through-hole diameter is 2 microns, and the through-hole center spacing is 4 microns to obtain a patterned photoresist.

[0085] S3, using the patterned photoresist as a mask, etching to prepare the patterned Mask layer:

[0086] Under the photoresist mask of step S2, the ICP process is used to The mask layer is etched, and the etching gas is and Ar gas mixture, The flow rate is 25 sccm, the Ar flow rate is 0 sccm, and the etching time is 400 s.

[0087] right The etching rate of the mask layer is 1.2nm / s, and the mask layer without photoresist coverage is etched through. Mask layer, patterned underneath the photoresist layer The mask layer is then removed using an organic solvent such as acetone / isopropyl alcohol.

[0088] S4, using an improved ICP etching process to pattern The mask layer is used to prepare right-angle or nearly right-angle Micro LED tables:

[0089] The result obtained in step S3 Under the mask layer, the epitaxial layer is etched using the ICP process. The etching gas is and Ar gas mixture, The flow rate is 40 sccm, The flow rate is 20 sccm, the Ar flow rate is 0 sccm, the etching time is 200 s, and the etching rate of the epitaxial layer is 40 ;

[0090] Afterwards, improvements PECVD deposition of the passivation layer, the reaction gas is (flow rate 1200sccm) and (flow rate 300 sccm), plasma source power 100 W, deposition temperature 250 ° C, sample tilt angle 30 °, sample stage speed 10 rpm, deposition time 300 s, actual deposition thickness about 100 nm;

[0091] Under the protection of the passivation layer, the epitaxial layer is etched in the second step using the ICP process. The etching gas is and Ar gas mixture, The flow rate is 40 sccm, The flow rate is 20 sccm, the Ar flow rate is 0 sccm, the etching time is 200 s, and the etching rate of the epitaxial layer is 40 The lateral etching rate of the passivation layer is 5 .

[0092] S5, improved PECVD deposition of the passivation layer to prepare a 300nm thick Passivation layer:

[0093] Deposition using PECVD Passivation layer, the reaction gas is (flow rate 1200sccm) and (flow rate 300 sccm), plasma source power 100 W, deposition temperature 250 °C;

[0094] The sample tilt angle was 30°, the sample stage rotation speed was 10 rpm, the deposition time was 900 s, and the actual deposition thickness was 300 nm.

[0095] S6, patterning process (spin coating, exposure, development):

[0096] The result obtained in step S5 Spin-coat photoresist (1500nm thickness) on the passivation layer. Use positive photoresist (5214 positive photoresist is preferred).

[0097] After curing, the film was exposed to UV light, and then a developer (TMAH aqueous solution) was used to remove the exposed photoresist. The development time was 2 minutes.

[0098] The mask is a periodically arranged circular hole, corresponding to the Micro LED passivation layer structure to be prepared. The area outside the circular hole is the light-shielding part. The photoresist inside the circular hole is exposed to ultraviolet light. The through-hole diameter is 2.5 microns, and the through-hole center spacing is 4 microns, obtaining a patterned photoresist.

[0099] S7, using the patterned photoresist as a mask, etching to prepare the patterned Passivation layer:

[0100] In step S6, the pattern photoresist is used as a mask and an ICP process is used to The mask layer is etched, and the etching gas is and Ar gas mixture, The flow rate is 25 sccm, the Ar flow rate is 0 sccm, and the etching time is 400 s;

[0101] right The etching rate of the mask layer is 1.2nm / s, and the mask layer without photoresist coverage is etched through. Passivation layer, patterned beneath the photoresist layer The passivation layer is then removed using an organic solvent such as acetone / isopropyl alcohol.

[0102] S8, patterning process (spin coating, exposure, development):

[0103] The result obtained in step S7 Spin-coat photoresist (1500nm thickness) on the passivation layer. Use positive photoresist (5214 positive photoresist is preferred).

[0104] After curing, the film was exposed to UV light, and then a developer (TMAH aqueous solution) was used to remove the exposed photoresist. The development time was 2 minutes.

[0105] The mask is a periodically arranged circular hole, corresponding to the Micro LED passivation layer structure to be prepared. The area outside the circular hole is the light-shielding part, and the photoresist inside the circular hole is exposed to ultraviolet light. The through-hole diameter is 2.7 microns, and the through-hole center spacing is 4 microns.

[0106] S9, metallized, lift-off:

[0107] Electron beam evaporation was used to sequentially deposit 300 nm of Cr, 300 nm of Pt, and 200 nm of Au as electrode materials. Typical targets were pure Cr, Pt, and Au, with a deposition rate of 1 nm / s.

[0108] Afterwards, organic solvents such as acetone / isopropyl alcohol are used to remove the glue and lift off the metal. At this time, the metal attached to the photoresist is peeled off, leaving only the circular electrode structure.

[0109] Example 3

[0110] This application provides a method for preparing a Micro LED having right-angled or nearly right-angled sidewalls, comprising the following steps:

[0111] S1, deposit a 100nm thick layer on the surface of the Epi epitaxial layer Mask layer:

[0112] On the surface of the Epi epitaxial layer (made of GaN / InGaN material with a thickness of 0.8 microns), a 100nm thick layer was deposited using PECVD (plasma enhanced chemical vapor deposition) method. mask layer;

[0113] The reaction gas is (flow rate 1000sccm) and (flow rate 200 sccm), the power of the plasma source is 80 W, and the deposition temperature is 200 °C.

[0114] S2, patterning process (spin coating, exposure, development):

[0115] In step S1, Spin-coat photoresist (500nm thickness) on the mask layer, using positive photoresist;

[0116] After curing, the film was exposed to UV light, and then a developer (TMAH aqueous solution) was used to remove the exposed photoresist. The development time was 1 minute.

[0117] The mask is a periodically arranged circle, which is the Micro LED mesa structure to be prepared. The area inside the circle is the light-shielding part, and the photoresist outside the circular area is exposed to ultraviolet light. The through-hole diameter is 1 micron, and the through-hole center spacing is 3 microns to obtain a patterned photoresist.

[0118] S3, using the patterned photoresist as a mask, etching to prepare the patterned Mask layer:

[0119] Under the photoresist mask of step S2, the ICP process is used to The mask layer is etched, and the etching gas is and Ar gas mixture, The flow rate is 15 sccm, the Ar flow rate is 0 sccm, and the etching time is 300 s.

[0120] right The etching rate of the mask layer is 0.2nm / s, and the mask layer without photoresist coverage is etched through. Mask layer, patterned underneath the photoresist layer The mask layer is then removed using an organic solvent such as acetone / isopropyl alcohol.

[0121] S4, using an improved ICP etching process to pattern The mask layer is used to prepare right-angle or nearly right-angle Micro LED tables:

[0122] The result obtained in step S3 Under the mask layer, the epitaxial layer is etched using the ICP process. The etching gas is and Ar gas mixture, The flow rate is 10 sccm, The flow rate is 10 sccm, the Ar flow rate is 0 sccm, the etching time is 150s, and the etching rate of the epitaxial layer is 20 ;

[0123] Afterwards, improvements PECVD deposition of the passivation layer, the reaction gas is (flow rate 1000sccm) and (flow rate 200 sccm), plasma source power 80 W, deposition temperature 200 ° C, sample tilt angle 10 °, sample stage speed 1 rpm, deposition time 200 s, actual deposition thickness is about 20 nm;

[0124] Under the protection of the passivation layer, the epitaxial layer is etched in the second step using the ICP process. The etching gas is and Ar gas mixture, The flow rate is 10 sccm, The flow rate is 10 sccm, the Ar flow rate is 0 sccm, the etching time is 150s, and the etching rate of the epitaxial layer is 30 The lateral etching rate of the passivation layer is 3 .

[0125] S5, improved PECVD deposition of the passivation layer to prepare a 300nm thick Passivation layer:

[0126] Deposition using PECVD Passivation layer, the reaction gas is (flow rate 1000sccm) and (flow rate 200 sccm), plasma source power 80 W, deposition temperature 200 °C;

[0127] The sample tilt angle was 10°, the sample stage rotation speed was 5 rpm, the deposition time was 600 s, and the actual deposition thickness was 200 nm.

[0128] S6, patterning process (spin coating, exposure, development):

[0129] The result obtained in step S5 Spin-coat photoresist (500nm thickness) on the passivation layer, using positive photoresist.

[0130] After curing, the film was exposed to UV light, and then a developer (TMAH aqueous solution) was used to remove the exposed photoresist. The development time was 1 minute.

[0131] The mask is a periodically arranged circular hole, corresponding to the Micro LED passivation layer structure to be prepared. The area outside the circular hole is the light-shielding part. The photoresist inside the circular hole is exposed to ultraviolet light. The through-hole diameter is 2 microns, and the through-hole center spacing is 3 microns to obtain a patterned photoresist.

[0132] S7, using the patterned photoresist as a mask, etching to prepare the patterned Passivation layer:

[0133] In step S6, the pattern photoresist is used as a mask and an ICP process is used to The mask layer is etched, and the etching gas is and Ar gas mixture, The flow rate is 15 sccm, the Ar flow rate is 0 sccm, and the etching time is 300 s;

[0134] right The etching rate of the mask layer is 0.2nm / s, and the mask layer without photoresist coverage is etched through. Passivation layer, patterned beneath the photoresist layer The passivation layer is then removed using an organic solvent such as acetone / isopropyl alcohol.

[0135] S8, patterning process (spin coating, exposure, development):

[0136] The result obtained in step S7 Spin-coat photoresist (500nm thickness) on the passivation layer, using positive photoresist.

[0137] After curing, the film was exposed to UV light, and then a developer (TMAH aqueous solution) was used to remove the exposed photoresist. The development time was 1 minute.

[0138] The mask is a periodically arranged circular hole, corresponding to the Micro LED passivation layer structure to be prepared. The area outside the circular hole is the light-shielding part, and the photoresist inside the circular hole is exposed to ultraviolet light. The through-hole diameter is 2 microns, and the through-hole center spacing is 3 microns.

[0139] S9, metallized, lift-off:

[0140] Electron beam evaporation was used to sequentially deposit 200 nm of Cr, 200 nm of Pt, and 100 nm of Au as electrode materials. Typical targets were pure Cr, Pt, and Au, with a deposition rate of 0.5 nm / s.

[0141] Afterwards, organic solvents such as acetone / isopropyl alcohol are used to remove the glue and lift off the metal. At this time, the metal attached to the photoresist is peeled off, leaving only the circular electrode structure.

[0142] Example 4

[0143] This application provides a method for preparing a Micro LED having right-angled or nearly right-angled sidewalls, comprising the following steps:

[0144] S1, deposit a 2000nm thick layer on the surface of the Epi epitaxial layer Mask layer:

[0145] On the surface of the Epi epitaxial layer (made of GaN / InGaN material with a thickness of 1.2 microns), a 500nm thick layer was deposited using PECVD (plasma enhanced chemical vapor deposition) method. mask layer;

[0146] The reaction gas is (flow rate 1500sccm) and (flow rate 400 sccm), the power of the plasma source is 120 W, and the deposition temperature is 300 °C.

[0147] S2, patterning process (spin coating, exposure, development):

[0148] In step S1, Spin-coat photoresist (3000nm thickness) on the mask layer, using positive photoresist;

[0149] After curing, the film was exposed to UV light, and then a developer (TMAH aqueous solution) was used to remove the exposed photoresist. The development time was 3 minutes.

[0150] The mask is a periodically arranged circle, which is the Micro LED mesa structure to be prepared. The area inside the circle is the light-shielding part, and the photoresist outside the circular area is exposed to ultraviolet light. The through-hole diameter is 5 microns, and the through-hole center spacing is 8 microns to obtain a patterned photoresist.

[0151] S3, using the patterned photoresist as a mask, etching to prepare the patterned Mask layer:

[0152] Under the photoresist mask of step S2, the ICP process is used to The mask layer is etched, and the etching gas is and Ar gas mixture, The flow rate is 35 sccm, the Ar flow rate is 0 sccm, and the etching time is 500 s.

[0153] right The etching rate of the mask layer is 5.0nm / s, and the area without photoresist coverage is etched through. Mask layer, patterned underneath the photoresist layer The mask layer is then removed using an organic solvent such as acetone / isopropyl alcohol.

[0154] S4, using an improved ICP etching process to pattern The mask layer is used to prepare right-angle or nearly right-angle Micro LED tables:

[0155] The result obtained in step S3 Under the mask layer, the epitaxial layer is etched using the ICP process. The etching gas is and Ar gas mixture, The flow rate is 50 sccm, The flow rate is 30 sccm, the Ar flow rate is 0 sccm, the etching time is 250 s, and the etching rate of the epitaxial layer is 60 ;

[0156] Afterwards, improvements PECVD deposition of the passivation layer, the reaction gas is (flow rate 1500sccm) and (flow rate 400 sccm), plasma source power 120 W, deposition temperature 300 ° C, sample tilt angle 60 °, sample stage speed 20 rpm, deposition time 400 s, actual deposition thickness about 150 nm;

[0157] Under the protection of the passivation layer, the epitaxial layer is etched in the second step using the ICP process. The etching gas is and Ar gas mixture, The flow rate is 50 sccm, The flow rate is 30 sccm, the Ar flow rate is 0 sccm, the etching time is 250 s, and the etching rate of the epitaxial layer is 50 The lateral etching rate of the passivation layer is 7 .

[0158] S5, improved PECVD deposition of the passivation layer to prepare a 400nm thick Passivation layer:

[0159] Deposition using PECVD Passivation layer, the reaction gas is (flow rate 1500sccm) and (flow rate 400 sccm), plasma source power 120 W, deposition temperature 300 °C;

[0160] The sample tilt angle was 60°, the sample stage rotation speed was 20 rpm, the deposition time was 1200 s, and the actual deposition thickness was 400 nm.

[0161] S6, patterning process (spin coating, exposure, development):

[0162] The result obtained in step S5 Spin-coat photoresist (3000nm thickness) on the passivation layer, using positive photoresist.

[0163] After curing, the film was exposed to UV light, and then a developer (TMAH aqueous solution) was used to remove the exposed photoresist. The development time was 3 minutes.

[0164] The mask is a periodically arranged circular hole, corresponding to the Micro LED passivation layer structure to be prepared. The area outside the circular hole is the light-shielding part. The photoresist inside the circular hole is exposed to ultraviolet light. The through-hole diameter is 6 microns, and the through-hole center spacing is 8 microns to obtain a patterned photoresist.

[0165] S7, using the patterned photoresist as a mask, etching to prepare the patterned Passivation layer:

[0166] In step S6, the pattern photoresist is used as a mask and an ICP process is used to The mask layer is etched, and the etching gas is and Ar gas mixture, The flow rate is 35 sccm, the Ar flow rate is 0 sccm, and the etching time is 500 s;

[0167] right The etching rate of the mask layer is 5.0nm / s, and the area without photoresist coverage is etched through. Passivation layer, patterned beneath the photoresist layer The passivation layer is then removed using an organic solvent such as acetone / isopropyl alcohol.

[0168] S8, patterning process (spin coating, exposure, development):

[0169] The result obtained in step S7 Spin-coat photoresist (3000nm thickness) on the passivation layer, using positive photoresist.

[0170] After curing, the film was exposed to UV light, and then a developer (TMAH aqueous solution) was used to remove the exposed photoresist. The development time was 3 minutes.

[0171] The mask is a periodically arranged circular hole, corresponding to the Micro LED passivation layer structure to be prepared. The area outside the circular hole is the light-shielding part, and the photoresist inside the circular hole is exposed to ultraviolet light. The through-hole diameter is 6.4 microns, and the through-hole center spacing is 8 microns.

[0172] S9, metallized, lift-off:

[0173] Electron beam evaporation was used to sequentially deposit 400 nm of Cr, 400 nm of Pt, and 300 nm of Au as electrode materials. Typical targets were pure Cr, Pt, and Au, with a deposition rate of 1.5 nm / s.

[0174] Afterwards, organic solvents such as acetone / isopropyl alcohol are used to remove the glue and lift off the metal. At this time, the metal attached to the photoresist is peeled off, leaving only the circular electrode structure.

[0175] This application provides a method for preparing Micro LEDs with right-angle or nearly right-angle sidewalls. By adopting an improved film deposition process and ICP etching process, it successfully solves the problem that the sidewalls of Micro LED terraces cannot be designed with angles exceeding 80°. Furthermore, the Micro LED process with right-angle or nearly right-angle terraces can achieve smaller pixel pitches, as shown in the attached figure. Figure 4As shown, the upper part is a schematic diagram of the chip array before optimization, and the lower part is a schematic diagram of the chip array after optimization. The process window of each process segment is larger, and the process is almost unaffected by the thickness of the epitaxial wafer, which can ultimately produce Micro LED display products with better performance.

[0176] Finally, it should be noted that the above are only preferred embodiments of the present invention and are not intended to limit the present invention. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art can still modify the technical solutions described in the aforementioned embodiments or make equivalent replacements for some of the technical features therein. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A method for preparing a Micro LED having right-angle or nearly right-angle sidewalls, characterized in that: The following steps are involved: S1, depositing a mask layer with a thickness within a preset range on the surface of the epitaxial layer; S2, spin-coating a photoresist on the mask layer, curing, UV exposure and developing, using a mask having a periodically arranged pattern to obtain a patterned photoresist; S3, using the patterned photoresist as a mask, etching the mask layer by a plasma etching process, and obtaining a patterned mask layer after removing the resist; S4, using the patterned mask layer as a mask, etching the epitaxial layer using an improved ICP process, wherein the improved ICP process includes: S4.1, first etching step: etching the epitaxial layer using an etching gas; S4.2, Passivation Layer Deposition: Deposit the passivation layer by chemical vapor deposition using a rotating sample stage with dynamically adjustable angles; S4.3, second etching step: Use etching gas to continue etching the epitaxial layer to obtain the Micro LED mesa at the target angle; S5, using the rotating sample stage capable of dynamically adjusting an angle, depositing a passivation layer having a thickness within a preset range through a chemical vapor deposition process; S6, spin-coating a photoresist on the passivation layer, and performing curing, UV exposure, and development, using a mask having a periodically arranged pattern to obtain a patterned photoresist; S7, etching the passivation layer using the patterned photoresist as a mask, and obtaining a patterned passivation layer after removing the resist; S8, spin-coating a photoresist on the patterned passivation layer, and performing curing, UV exposure, and development treatment using a mask having a periodically arranged pattern to obtain a patterned photoresist; S9, uses physical vapor deposition process to plate the metal layer, and obtains the patterned positive and negative electrode structure after debonding and metal lifting.

2. The method for preparing a Micro LED having right-angle or nearly right-angle sidewalls according to claim 1, wherein: In step S1, the epitaxial layer material is GaN / InGaN with a thickness of 0.8-1.2 microns; a 100-2000 nm thick GaN layer is deposited on the surface of the epitaxial layer. Mask layer.

3. The method for preparing a Micro LED having right-angle or nearly right-angle sidewalls according to claim 2, wherein: In step S2, in the A photoresist with a thickness of 500-3000nm is spin-coated on the mask layer, and after curing, it is exposed to UV light. Then, a developer is used to remove the exposed photoresist. The development time is 1-3 minutes. The mask plate is a periodically arranged circle, that is, the Micro LED mesa structure to be prepared. The area inside the circle is the light-shielding part, and the photoresist outside the circular area is exposed to UV light. The through-hole aperture is 1-5 microns, and the center spacing is 3-8 microns to obtain a patterned photoresist.

4. The method for preparing a Micro LED having right-angle or nearly right-angle sidewalls according to claim 3, wherein: In step S3, the patterned photoresist in step S2 is used as a mask and an ICP process is used to etch the Mask layer, etching gas is and Ar gas mixture, The flow rate is 15-35sccm, the etching time is 300-500s, the etching rate is 0.2-5.0nm / s, and the pattern is obtained after de-resist. Mask layer.

5. The method for preparing a Micro LED having right-angle or nearly right-angle sidewalls according to claim 4, wherein: In step S4, the graphical The mask layer is a mask, and the epitaxial layer is etched using an improved ICP etching process, wherein the improved ICP etching process includes: S4.1, first step of etching: etching gas is and Ar gas mixture, The flow rate is 10-50sccm, The flow rate is 10-30sccm, the etching time is 150-250s, and the etching rate of the epitaxial layer is 20-60 ; S4.2, passivation layer deposition: using a rotating sample stage with a tilt angle of 10-60° and a rotation speed of 1-20 rpm, by PECVD deposition Passivation layer, the reaction gas is , The flow rate is 1000-1500sccm, The flow rate is 200-400 sccm, the plasma source power is 80-120 W, the deposition temperature is 200-300 ° C, the deposition time is 200-400 s, and the deposition thickness is 20-150 nm; S4.3, second step etching: etching gas is and Ar gas mixture, The flow rate is 10-50sccm, The flow rate is 10-30sccm, the etching time is 150-250s, and the etching rate of the epitaxial layer is 30-50 The lateral etching rate of the passivation layer is 3-7 , a Micro LED table with a right-angle or near-right-angle sidewall angle range of 85-95° is obtained, and the error between the top size of the table and the pixel size is ≤5%.

6. The method for preparing a Micro LED having right-angle or nearly right-angle sidewalls according to claim 5, wherein: In step S5, the rotating sample stage with a tiltable angle is used to deposit a 200-400 nm thick Passivation layer, sample tilt angle is 10-60°, rotation speed is 5-20rpm, reaction gas is , The flow rate is 1000-1500sccm, The flow rate is 200-400 sccm, the plasma source power is 80-120 W, and the deposition temperature is 200-300 °C.

7. The method for preparing a Micro LED having right-angle or nearly right-angle sidewalls according to claim 6, wherein: In step S6, A photoresist with a thickness of 500-3000nm is spin-coated on the passivation layer. After curing, it is exposed to UV light, and then a developer is used to remove the exposed photoresist. The development time is 1-3 minutes. The mask is a periodically arranged circular hole, corresponding to the Micro LED passivation layer structure to be prepared. The area outside the circular hole is the light-shielding part. The photoresist inside the circular hole is exposed to UV light. The through-hole aperture is 2-6 microns, and the center spacing is 3-8 microns to obtain a patterned photoresist.

8. The method for preparing a Micro LED having right-angle or nearly right-angle sidewalls according to claim 7, wherein: In step S7, the patterned photoresist in step S6 is used as a mask to etch Passivation layer, etching gas is and Ar gas mixture, The flow rate is 15-35sccm, the etching time is 300-500s, the etching rate is 0.2-5.0nm / s, and the pattern is obtained after de-resist. Mask layer.

9. The method for preparing a Micro LED having right-angle or nearly right-angle sidewalls according to claim 8, wherein: In step S8, in the graphical A photoresist with a thickness of 500-3000nm is spin-coated on the passivation layer. After curing, it is exposed to UV light, and then a developer is used to remove the exposed photoresist. The development time is 1-3 minutes. The mask is a periodically arranged circular hole, corresponding to the Micro LED passivation layer structure to be prepared. The area outside the circular hole is the light-shielding part. The photoresist inside the circular hole is exposed to UV light. The through-hole aperture is 2-6.4 microns, and the center spacing is 3-8 microns to obtain a patterned photoresist.

10. The method for preparing a Micro LED having right-angle or nearly right-angle sidewalls according to claim 9, wherein: In step S9, the metal layer is plated using an electron beam evaporation process, depositing 200-400nm thick Cr, 200-400nm thick Pt, and 100-300nm thick Au in sequence, with a deposition rate of 0.5-1.5nm / s. After debonding and metal lifting, a patterned positive and negative electrode structure is obtained.

Images