Light emitting device, display apparatus including light emitting device, photoelectric conversion apparatus, electronic apparatus, and method of manufacturing light emitting device

Abstract

The invention provides a light emitting device, a display apparatus including the light emitting device, a photoelectric conversion apparatus, an electronic apparatus, and a method of manufacturing the light emitting device. A light emitting device, first and second transistors, an insulating layer, and a third transistor are provided as a display device that reduces leakage current in a light emitting element, in which a source of the first transistor is connected to a gate electrode of the second transistor, a drain of the second transistor is connected to the light emitting element, and a drain of the third transistor is connected to a gate electrode of the third transistor. The light-emitting device includes a silicide layer in at least any one of a source electrode, a drain electrode, and a gate electrode of the third transistor. And the light emitting device includes a region in which the silicide layer is not provided between the insulating layer and at least any one of a source, a drain, and a gate electrode of the first transistor or at least any one of a source, a drain, and a gate electrode of the second transistor.

Description

Technical Field

[0001] The present disclosure relates to a light-emitting device, and for example, to a light-emitting device including a light-emitting element, a display apparatus including the light-emitting device, a photoelectric conversion apparatus, an electronic device, and a method of manufacturing the light-emitting device. Background Art

[0002] In recent years, display devices have become known that include arrays of light-emitting elements that emit light at a brightness corresponding to the current flowing through the elements. Organic electroluminescent (EL) elements are used as light-emitting elements. Display devices have greatly expanded their applications, and high definition and high functionality are required for these applications.

[0003] Japanese Patent Laid-Open No. 2020-71323 discusses a display device that includes a semiconductor compound layer (silicide layer) of a high melting point metal in the source and drain of a driving transistor in a driving circuit of an organic light emitting element.

[0004] In the transistor discussed in Japanese Patent Application Laid-Open No. 2020-71323, a silicide layer is arranged in the source and drain of the transistor. The silicide layer can reduce the impedance of the transistor. However, the provision of the silicide layer may also degrade the characteristics of the light-emitting element. Summary of the Invention

[0005] The present disclosure aims to provide a light emitting device in which degradation of characteristics of the light emitting device due to provision of a silicide layer is reduced.

[0006] The present disclosure provides a light-emitting device, comprising: a light-emitting element; a first transistor and a second transistor, the first transistor and the second transistor being arranged on a first surface of a silicon substrate; an insulating layer arranged between the light-emitting element and the first surface; and a third transistor, which is arranged in a peripheral circuit, the peripheral circuit being configured to supply an image signal to the first transistor, wherein one of the source and the drain of the first transistor is connected to the gate electrode of the second transistor, wherein one of the source and the drain of the second transistor is connected to the light-emitting element, wherein the light-emitting device includes a silicide layer in at least any one of the source, drain, and gate electrode of the third transistor, and the silicide layer is in contact with the insulating layer, and wherein the light-emitting device includes a region where no silicide layer is provided between at least any one of the source, drain, and gate electrode of the first transistor or at least any one of the source, drain, and gate electrode of the second transistor and the insulating layer.

[0007] Further features of the present disclosure will become apparent from the following description of exemplary embodiments with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1is a schematic diagram illustrating an example of a light emitting device according to the first exemplary embodiment.

[0009] Figure 2 is a circuit diagram illustrating an example of a pixel circuit of the light emitting device according to the first exemplary embodiment.

[0010] Figure 3A is a plan view illustrating an example of a circuit of the light emitting device according to the first exemplary embodiment. Figure 3B is a plan view illustrating an example of a peripheral circuit transistor of the light emitting device according to the first exemplary embodiment.

[0011] Figure 4A is a cross-sectional view illustrating an example of a light emitting device according to the first exemplary embodiment. Figure 4B is a cross-sectional view illustrating an example of a peripheral circuit transistor of the light emitting device according to the first exemplary embodiment.

[0012] Figure 5A is a cross-sectional view illustrating an example of a light emitting device according to a second exemplary embodiment. Figure 5B is a cross-sectional view illustrating a modification of the light emitting device according to the second exemplary embodiment.

[0013] 6A to 6D is a schematic diagram illustrating an example of a manufacturing process of a light emitting device according to an exemplary embodiment of the present disclosure.

[0014] Figure 7A is a cross-sectional view illustrating an example of a light emitting device according to a third exemplary embodiment. Figure 7B is a cross-sectional view illustrating an example of a light emitting device according to a fourth exemplary embodiment.

[0015] Figure 8A is a cross-sectional view illustrating an example of a light emitting device according to a fifth exemplary embodiment. Figure 8B is a cross-sectional view illustrating an example of a light emitting device according to a fifth exemplary embodiment.

[0016] Figure 9 is a schematic diagram illustrating a light emitting device according to a sixth exemplary embodiment.

[0017] Figure 10 is a circuit diagram illustrating an example of a pixel circuit according to the sixth exemplary embodiment.

[0018] Figure 11 is a plan view illustrating an example of a pixel circuit according to the sixth exemplary embodiment.

[0019] Figure 12 is a cross-sectional view illustrating an example of a light emitting device according to a sixth exemplary embodiment.

[0020] Figure 13is a schematic diagram illustrating an example of a light emitting device according to a seventh exemplary embodiment.

[0021] Figure 14 is a circuit diagram illustrating an example of a pixel circuit of a light-emitting device according to the seventh exemplary embodiment.

[0022] Figure 15 is a plan view illustrating an example of a pixel circuit according to the seventh exemplary embodiment.

[0023] Figure 16 is a cross-sectional view illustrating an example of a light emitting device according to a seventh exemplary embodiment.

[0024] Figure 17 is an example of an inverter circuit in the vertical scanning circuit according to the eighth exemplary embodiment.

[0025] Figure 18 is a plan view illustrating an example of a circuit according to the eighth exemplary embodiment.

[0026] Figure 19 is a cross-sectional view illustrating an example of a light emitting device according to an eighth exemplary embodiment.

[0027] Figure 20 is a schematic diagram illustrating an example of a display device according to an exemplary embodiment of the present disclosure.

[0028] Figure 21A is a schematic diagram illustrating an example of an imaging apparatus according to an exemplary embodiment of the present disclosure. Figure 21B is a schematic diagram illustrating an example of an electronic device according to an exemplary embodiment of the present disclosure.

[0029] Figure 22A and Figure 22B is a schematic diagram illustrating an example of a display device according to an exemplary embodiment of the present disclosure.

[0030] Figure 23A and Figure 23B is a schematic diagram illustrating an example of a wearable device according to a typical embodiment of the present disclosure. DETAILED DESCRIPTION

[0031] According to an exemplary embodiment of the present disclosure, a light-emitting device includes: a light-emitting element; a first transistor and a second transistor, the first transistor and the second transistor being disposed on a first surface of a silicon substrate; an insulating layer disposed between the light-emitting element and the first surface; and a third transistor disposed in a peripheral circuit configured to supply an image signal to the first transistor, wherein one of the source and drain of the first transistor is connected to the gate electrode of the second transistor, wherein one of the source and drain of the second transistor is connected to the light-emitting element, wherein the light-emitting device includes a silicide layer in at least one of the source, drain, and gate electrodes of the third transistor, and the silicide layer is in contact with the insulating layer, and wherein the light-emitting device includes a region without a silicide layer between at least one of the source, drain, and gate electrodes of the first transistor or at least one of the source, drain, and gate electrodes of the second transistor and the insulating layer. That is, the region without a silicide layer may be only the source, drain, or gate electrode of the first transistor. The region without a silicide layer may be a combination of the source, drain, and gate electrodes of the first transistor. The region where the silicide layer is not provided may be all of the source, drain, and gate electrodes of the first transistor. In other words, the light-emitting device includes a region where the silicide layer is not provided between at least one selected from the group consisting of the source, drain, and gate electrodes of the first transistor or the group consisting of the source, drain, and gate electrodes of the second transistor and the insulating layer.

[0032] The light emitting device includes a region where no silicide layer is provided between at least any one of the source, drain, and gate electrodes of the first transistor or the second transistor and the insulating layer, thereby reducing leakage current in the region.

[0033] According to another typical embodiment of the present disclosure, a light-emitting device includes: a light-emitting element; a first transistor and a second transistor, which are arranged on a first surface of a silicon substrate; and a third transistor, which is arranged in a peripheral circuit, which is configured to supply an image signal to the first transistor, wherein one of the source and the drain of the first transistor is connected to the gate electrode of the second transistor, wherein one of the source and the drain of the second transistor is connected to the light-emitting element, wherein the light-emitting device includes a self-aligned silicide structure in at least any one of the source, drain and gate electrode of the third transistor, and wherein the light-emitting device does not include a self-aligned silicide structure in at least any one of the source, drain and gate electrodes of the first transistor or at least any one of the source, drain and gate electrodes of the second transistor.

[0034] The light emitting device does not include a salicide structure in at least any one of the source, drain, and gate electrodes of the first transistor or the second transistor, so that leakage current in the region can be reduced.

[0035] Exemplary embodiments will be described in detail below with reference to the accompanying drawings. The following exemplary embodiments do not limit the disclosure according to the appended claims. Although multiple features are described in the exemplary embodiments, not all of the multiple features are essential to the present disclosure, and multiple features may be optionally combined. In addition, in the drawings, identical or similar components are represented by the same reference numerals, and redundant descriptions thereof are omitted.

[0036] In the following exemplary embodiments, a driving transistor connected to the anode of an organic light-emitting element is described, and all transistors are P-type transistors. However, the light-emitting device according to the present disclosure is not limited thereto. All polarities and conductivity types can be reversed. Each transistor can be either a P-type transistor or an N-type transistor. To change the transistor, the potential to be supplied and the connection can be appropriately changed according to the conductivity type and polarity of the transistor.

[0037] In the following exemplary embodiments, the peripheral circuit may be provided on the same silicon substrate as the pixel transistor, or may be provided on a second silicon substrate different from the first silicon substrate on which the pixel transistor is provided.

[0038] In this specification, a light-emitting element may be an organic light-emitting element whose light-emitting portion is a light-emitting layer having an organic compound, or may be an inorganic light-emitting element whose light-emitting portion is composed of an inorganic compound.

[0039] An organic light-emitting element includes an organic layer having a light-emitting layer between the electrodes (i.e., an anode and a cathode) of the organic light-emitting element. In addition to the light-emitting layer, the organic layer may also include one or more of a hole injection layer, a hole transport layer, an electron injection layer, and an electron transport layer. A display device including an organic light-emitting element is an example of a light-emitting device and is also referred to as an "organic light-emitting device."

[0040] In the following exemplary embodiments, examples using an organic light emitting element are described.

[0041] Figure 1 1 is a schematic diagram of an example of a light emitting device according to a first exemplary embodiment. The light emitting device 101 includes a pixel array unit 103 and a peripheral circuit unit placed on the periphery of the pixel array unit 103. The pixel array unit 103 includes a plurality of pixels 102 arranged two-dimensionally in a matrix form. Each pixel 102 includes ( Figure 2 (illustrated) organic light-emitting element 201.

[0042] The light-emitting device 101 includes a peripheral circuit unit that drives each pixel 102. For example, the peripheral circuit unit includes a vertical scanning circuit 104 and a signal output circuit 105. In the pixel array unit 103, a first scanning line 106 is arranged along the row direction for each pixel row. A signal line 107 is arranged along the column direction for each pixel column.

[0043] The first scan line 106 is connected to the output terminal of the corresponding row of the vertical scan circuit 104. The signal line 107 is connected to the output terminal of the corresponding column of the signal output circuit 105. The vertical scan circuit 104 supplies a write control signal for controlling the timing of writing the video signal to each pixel 102 of the pixel array unit 103 to the first scan line 106. The signal output circuit 105 outputs a luminance signal having a voltage corresponding to the luminance information.

[0044] Figure 2 This is an example Figure 1 1 is a circuit diagram of an example of a pixel circuit included in a light-emitting device 101 in FIG. Pixel 102 includes a light-emitting element 201, a drive transistor 202 (DRV), a write transistor 203 (SEL), and a first capacitor element 204. One of the source and drain of the drive transistor 202 is connected to the first electrode of the light-emitting element 201, and the other of the source and drain of the drive transistor 202 is connected to a first power supply terminal 205 (hereinafter referred to as "Vdd"). The second electrode of the light-emitting element 201 is connected to a second power supply terminal 206 (hereinafter referred to as "Vss").

[0045] One of the source and drain of the write transistor 203 is connected to the gate electrode of the drive transistor 202, and the other of the source and drain of the write transistor 203 is connected to the signal line 107. The gate electrode of the write transistor 203 is connected to the first scan line 106.

[0046] The first capacitor element 204 is connected between the gate and one of the source and drain (the source in this case) of the driving transistor 202, and holds the brightness signal of the pixel 102 in the pixel 102. The first capacitor element 204 may be any one of a parasitic capacitor, a gate-channel capacitor of a metal oxide semiconductor (MOS), a metal-insulator-metal (MIM) structure, and a metal-oxide-metal (MOM) structure.

[0047] In the present exemplary embodiment, the drain of the driving transistor 202 is connected to the anode of the light emitting element 201 , and the source of the driving transistor 202 is connected to the first power supply terminal 205 (Vdd).

[0048] The first capacitor element 204 is connected between the gate electrode of the driving transistor 202 and the source of the driving transistor 202, and holds the luminance signal of the pixel 102 in the pixel 102. The first capacitor element 204 according to the present exemplary embodiment is composed of an MIM structure.

[0049] Figure 3A yes Figure 2A plan view of an example of the illustrated circuit. The driving transistor 202 includes a gate electrode 301 , a source 302 , and a drain 303 .

[0050] The write transistor 203 includes a gate electrode 304, a source 305, and a drain 306. A contact wiring 307 is connected to wirings in other layers.

[0051] Figure 3B 3 is a plan view of an example of a peripheral circuit transistor. The peripheral circuit transistor 308 includes a gate electrode 309, a source electrode 310, and a drain electrode 311. The peripheral circuit supplies an image signal to the write transistor 203. The image signal is a signal for controlling the turn-on timing of the write transistor 203 or a signal indicating a luminance signal.

[0052] Figure 4A It is along Figure 3A A cross-sectional view taken along line AA' in the illustrated plan view. All transistors according to this typical embodiment are arranged on an N-type well layer 407, which is arranged on the first surface of a P-type silicon substrate 408. Specifically, a drive transistor 202 and a write transistor 203 are provided, and an insulator separation portion 409 separates these transistors. The source 302 and the drain 303 of the drive transistor 202 are formed by a P-type diffusion layer 401 and a P-type diffusion layer 402, respectively, and the source 305 and the drain 306 of the write transistor 203 are formed by a P-type diffusion layer 403 and a P-type diffusion layer 404, respectively. The insulator separation portion 409 can be any one of shallow trench isolation (STI) separation, local oxidation of silicon (LOCOS) separation, and N-type diffusion layer separation.

[0053] The silicide layer 405 can reduce contact resistance between the source or drain of the transistor and the contact wiring 307. The silicide layer 405 can be a silicide layer formed using a self-aligned silicide process.

[0054] For example, a self-aligned silicide process is performed by the following steps: (a) forming a film of a metal element on a semiconductor layer; (b) silicide the metal element; and (c) removing the metal element. First, a film of the metal element is formed on the surface of the semiconductor layer using a physical vapor deposition (PVD) method. Next, if the semiconductor layer is heated, the metal element on the semiconductor layer reacts to form a silicide. Regions other than the semiconductor layer (such as a metal layer provided on an insulating layer such as a silicon oxide layer) are not silicided and the metal layer remains.

[0055] Next, a chemical solution treatment is used to selectively remove the metal layer disposed on the insulating layer. This process leaves the silicide on the gate, source, and drain of the transistor, as it would if the insulating layer were not present. As mentioned above, since the silicide is formed in a self-aligned manner, the process is called a "self-aligned salicide process."

[0056] If a semiconductor region to be a source region or a drain region and a metal such as a contact electrode are heated while the semiconductor region and the metal are in contact with each other, the contact portion between the semiconductor region and the metal may be silicided. In this case, silicide is formed on the source region or the drain region.

[0057] However, in this case, no silicide is provided in at least a portion of the region where the source region or the drain region contacts the insulating layer. In the present specification, silicide formed during the process of forming such a contact electrode is not included in the self-aligned silicide structure or silicide layer.

[0058] Examples of metal elements constituting the silicide layer include at least one selected from the group consisting of titanium, nickel, cobalt, tungsten, molybdenum, tantalum, chromium, palladium, and platinum, or an alloy having at least one as a main component. As an example, the silicide layer provided in the source region or the drain region 211 of the transistor in the second semiconductor layer 200 is cobalt silicide, and the metal element constituting the silicide layer is cobalt.

[0059] The insulating layer 406 is an insulating layer provided between the light emitting element 201 and the first surface of the silicon substrate 408. The insulating layer 406 is also called an "interlayer insulating layer" and forms a part of the wiring layer of the light emitting device 101. Figure 4A In the illustrated example, the insulating layer 406 is the interlayer insulating layer closest to the silicon substrate 408. The contact electrode 307 contacts the source 302, drain 303, and gate electrode 301 of the drive transistor 202 and the source 305, drain 306, and gate electrode 304 of the write transistor 203 through an opening provided in the insulating layer 406.

[0060] A silicide layer 405 is provided in the source 305, drain 306, and gate electrode 304 of the write transistor 203. On the other hand, no silicide layer 405 is provided in the source 302, drain 303, and gate electrode 301 of the drive transistor 202. The provision of the silicide layer 405 in the write transistor 203 reduces the impedance between the write transistor 203 and the contact electrode 307. If only the reduction in impedance is considered, the silicide layer 405 can also be provided in the drive transistor 202. However, there is a possibility that the metal atoms constituting the silicide layer 405 may diffuse into the depletion layer of the transistor due to the heat applied during the manufacturing process. This may generate dark electrons. This may cause a leakage current to flow between the source 302 and drain 303 of the drive transistor 202. If leakage current is generated, the amount of current flowing through the light-emitting element 201 changes. As a result, the brightness of the light-emitting element may change. Therefore, in the present exemplary embodiment, the silicide layer 405 is not provided in the driving transistor 202, so that the generation of leakage current can be reduced and high-quality black can be displayed.

[0061] Figure 4B It is along Figure 3B The cross-sectional view taken along line BB' in the illustrated plan view. Figure 4B As shown, the source 310 and drain 311 of the peripheral circuit transistor 308 are formed by a P-type diffusion layer 410 and a P-type diffusion layer 411, respectively. A silicide layer 405 is provided in at least one of the source 310, drain 311, and gate electrode 309 of the peripheral circuit transistor 308. Instead of reducing leakage current, the performance of the peripheral circuit transistor 308 according to this exemplary embodiment is improved by reducing the impedance of the transistor 308.

[0062] That is, the light emitting device according to the present exemplary embodiment has a configuration including a region where the silicide layer 405 is not provided between the source 302 , drain 303 , and gate electrode 301 of the driving transistor 202 and the insulating layer 406 .

[0063] According to the configuration of this exemplary embodiment, the silicide layer 405 is not disposed in the source 302 and the drain 303 of the driver transistor 202, thereby reducing the diffusion of metal atoms in the silicide layer 405 into the depletion layer near the source 302 and the drain 303 of the driver transistor 202. This can reduce the leakage current flowing from the driver transistor 202 into the light-emitting element 201. Therefore, high-quality black can be displayed.

[0064] Although the example in which the silicide layer 405 is not disposed in any of the source 302, drain 303, and gate electrode 301 of the driver transistor 202 has been described in the present exemplary embodiment, the effect of reducing leakage current compared to the conventional configuration can also be achieved by a configuration in which the light-emitting device does not include the silicide layer 405 in at least a portion of the source 302, drain 303, and gate electrode 301 of the driver transistor 202, and includes the silicide layer 405 in any region of the source 302, drain 303, and gate electrode 301 of the driver transistor 202. That is, this effect is achieved by the light-emitting device including a region in which the light-emitting device does not include the silicide layer 405 in a portion of the source 302, a portion of the drain 303, or a portion of the gate electrode 301 of the driver transistor 202, and this effect is not limited to the description of the present exemplary embodiment.

[0065] Figure 5A is a cross-sectional view of a light-emitting device according to a second exemplary embodiment. This exemplary embodiment differs from the first exemplary embodiment in that a silicide layer 405 is provided between the source 302, drain 303, and gate electrode 301 of the drive transistor 202 and the insulating layer 406. This exemplary embodiment also differs from the first exemplary embodiment in that a silicide layer 405 is not provided between the source 305, drain 306, and gate electrode 304 of the write transistor 203 and the insulating layer 406. In the first exemplary embodiment, the configuration of the pixel circuit for reducing the generation of leakage current in the drive transistor 202 has been described. In contrast, in this exemplary embodiment, the configuration of the pixel circuit for reducing the leakage current in the write transistor 203 is described.

[0066] exist Figure 5A In FIG. 4 , a silicide layer 405 is provided in the source 302, drain 303, and gate electrode 301 of the drive transistor 202, and the silicide layer 405 and the insulating layer 406 are in contact with each other. On the other hand, a silicide layer 405 is not provided between the source 305, drain 306, and gate electrode 304 of the write transistor 203 and the insulating layer 406, and the source 305, drain 306, and gate electrode 304 of the write transistor 203 and the insulating layer 406 are in contact with each other. The peripheral circuit transistor 308 is connected to Figure 4B The peripheral circuit transistors illustrated are similar.

[0067] That is, the light-emitting device according to the present exemplary embodiment has a configuration including a region where the silicide layer 405 is not provided between the source 305 , drain 306 , and gate electrode 304 of the write transistor 203 and the insulating layer 406 .

[0068] With the above configuration, the resistance between the drive transistor 202 and the contact electrode 307 is reduced. On the other hand, the write transistor 203 has a configuration in which the write transistor 203 does not include the silicide layer 405, and leakage current between the source 305 and the drain 306 of the write transistor 203 is reduced.

[0069] The source 305 or drain 306 of the write transistor 203 is connected to one of the electrodes of the first capacitor element 204. When the leakage current in the write transistor 203 is reduced, the charge flowing out of one of the electrodes of the first capacitor element 204 can be reduced. As a result, the fluctuation of the potential of the gate electrode 301 of the drive transistor 202 connected to one of the electrodes of the first capacitor element 204 can be reduced. The potential of one of the electrodes of the first capacitor element 204 is the potential of the gate electrode 301 of the drive transistor 202 and is a potential that affects the luminance of the light-emitting element 201. Therefore, if the fluctuation of the potential of one of the electrodes of the first capacitor element 204 is reduced, the fluctuation of the luminance is reduced. The reduced fluctuation of the luminance can provide a display device with high display quality.

[0070] Figure 5B This is a modification of the light emitting device according to the present exemplary embodiment. In this modification, a configuration is adopted in which the silicide layer 405 is not provided in either the driving transistor 202 or the writing transistor 203.

[0071] That is, in a cross section perpendicular to the first surface of the silicon substrate 408, the light-emitting device includes an area where the silicide layer 405 is not set between any components among the source 302, drain 303 and gate electrode 301 of the driving transistor 202 and the source 305, drain 306 and gate electrode 304 of the writing transistor 203 and the insulating layer 406.

[0072] With this configuration, the impedance of the peripheral circuit transistor 308 is lowered, and leakage current in both the drive transistor 202 and the write transistor 203 can also be reduced.

[0073] 6A to 6D 1 and 2 are schematic diagrams illustrating an example of a manufacturing process of the light emitting device according to each of the above exemplary embodiments.

[0074] Figure 6B A configuration is illustrated in which the insulating layer 413 is formed to cover the driving transistor 202 and the writing transistor 203. A method for forming the insulating layer 413 may be a sputtering method, an atomic deposition method, or a vapor deposition method such as chemical vapor deposition (CVD).

[0075] Next, the insulating layer 413 is partially removed. Specifically, the insulating layer 413 is removed so that at least one of the drive transistor 202 and the write transistor 203 is exposed through the insulating layer 413.

[0076] Figure 6B 4 is a cross-sectional view illustrating a configuration in which the insulating layer 413 is removed to expose the write transistor 203. The write transistor 203 can be exposed using a known technique such as etching. Although the present exemplary embodiment describes a step of forming the insulating layer 413 over the entire surface and then exposing the write transistor 203, a step of selectively placing the insulating layer 413 only on the drive transistor 202 may be performed.

[0077] Figure 6C This is a cross-sectional view illustrating a configuration in which a metal layer 414 is arranged on an insulating layer 413 and a write transistor 203. The metal layer 414 is formed to cover the drive transistor 202 and the write transistor 203, and then heated to form a silicide layer 405. Since the drive transistor 202 is covered by the insulating layer 413, the silicon substrate of the drive transistor portion and the metal layer 414 are not in contact with each other. As a result, the silicide layer 405 is not formed in the drive transistor 202. This step of arranging the silicide layer 405 in portions other than the portion where the insulating layer 413 is formed is a self-aligned silicide process. The silicide layer 405 formed by the self-aligned silicide process is a self-aligned silicide structure in this specification.

[0078] Figure 6D 4 is a cross-sectional view of an example of a light-emitting device after forming a silicide layer 405. After forming the silicide layer 405, the metal layer 414 is selectively removed. Although the metal layer 414 is removed, the silicide layer 405 formed on the write transistor 203 is not removed. Then, an insulating layer 406 is formed. In this exemplary embodiment, the same material as that of the insulating layer 413 is used, and therefore, the boundary between the insulating layer 413 and the insulating layer 406 is not illustrated. After forming the insulating layer 406, an opening for forming the contact electrode 307 is formed, and connections are formed between the source 302, drain 303, and gate electrode 301 of the drive transistor 202 and the source 305, drain 306, and gate electrode 304 of the write transistor 203 and the contact electrode 307. The opening is sometimes also referred to as a through-hole. The first opening for the contact electrode 307 for contacting the write transistor 203 overlaps with the silicide layer 405 or the self-aligned silicide structure in a plan view of the silicon substrate. The second opening for the contact electrode 307 contacting the driving transistor 202 does not overlap with the silicide layer 405 or the salicide structure in a plan view of the silicon substrate. The first opening and the second opening may have opposite configurations depending on the embodiment.

[0079] Through the above process, an example of a light-emitting device according to this exemplary embodiment can be manufactured. A silicide layer is formed in the peripheral circuit transistor 308 by a salicide process. The light-emitting device according to this exemplary embodiment configured in this manner includes a salicide structure in at least one of the source 310, drain 311, and gate electrode 309 of the peripheral circuit transistor 308, and does not include a salicide structure in at least one of the source 302, drain 303, and gate electrode 301 of the driver transistor 202.

[0080] Although the configuration in which the silicide layer 405 is provided in the source 305, drain 306, and gate electrode 304 of the write transistor 203 and the silicide layer 405 is not provided in the source 302, drain 303, and gate electrode 301 of the drive transistor 202 has been described in the present exemplary embodiment, a configuration in which the silicide layer 405 is not provided in the source 305, drain 306, and gate electrode 304 of the write transistor 203 may be employed. A configuration in which the silicide layer 405 is not provided in either the drive transistor 202 or the write transistor 203 may also be employed.

[0081] Figure 7A It is along Figure 3A A cross-sectional view of the light-emitting device according to the third exemplary embodiment is shown along line AA'. The light-emitting device according to this exemplary embodiment is similar to the light-emitting device according to the first exemplary embodiment, except that the source 302 and drain 303 of the driver transistor 202 are low-concentration P-type diffusion layers. The following mainly describes configurations that differ from those in the other exemplary embodiments.

[0082] The source 302 and drain 303 of the driving transistor 202 of the light-emitting device according to this exemplary embodiment are formed by a low-concentration P-type diffusion layer 701 and a low-concentration P-type diffusion layer 702, respectively. The low-concentration P-type diffusion layers 701 and 702 have a concentration distribution having a concentration peak in the direction from the source 302 to the drain 303. The peak concentrations of the low-concentration P-type diffusion layers 701 and 702 are lower than the peak concentrations of the P-type diffusion layers 410 and 411 of the peripheral circuit transistor 308. Each peak concentration indicates the concentration at the concentration peak.

[0083] That is, the impurity concentration of the diffusion region of the source 302 of the driver transistor 202 and the impurity concentration of the diffusion region of the drain 303 of the driver transistor 202 have a concentration distribution having a peak concentration in a first direction from the source 302 to the drain 303. The impurity concentration of the diffusion region of the source 310 of the peripheral circuit transistor 308 and the impurity concentration of the diffusion region of the drain 311 of the peripheral circuit transistor 308 have a concentration distribution having a peak concentration in a second direction from the source 310 to the drain 311.

[0084] A configuration is adopted in which the peak concentration of impurities in the diffusion region of the source 302 or drain 303 of the driver transistor 202 is smaller than the peak concentration of impurities in the diffusion region of the source 310 or drain 311 of the peripheral circuit transistor 308 .

[0085] According to this configuration, the electric field strength between the source 302 and drain 303 of the driving transistor 202 and the N-type well layer 407 can be reduced, and the leakage current flowing from the well into the source 302 and drain 303 can be reduced. This can also reduce the leakage current flowing from the driving transistor 202 into the organic light-emitting element 201. Therefore, high-quality black can be displayed.

[0086] This exemplary embodiment has exemplified a configuration in which the peak concentration of impurities in the driver transistor 202 is lower than the peak concentration of impurities in the peripheral circuit transistor 308. The present disclosure is not limited thereto. A configuration in which the peak concentration of impurities in other transistors is lower than the peak concentration of impurities in the peripheral circuit transistor 308 may be employed.

[0087] Figure 7B It is along Figure 3A A cross-sectional view of a light-emitting device according to a fourth exemplary embodiment, taken along line AA', is shown. In this exemplary embodiment, the source 305 and drain 306 of the write transistor 203 are low-concentration P-type diffusion layers, and no semiconductor compound layer is provided. The following primarily describes configurations that differ from those in other exemplary embodiments.

[0088] The source 305 and drain 306 of the write transistor 203 are formed of a low-concentration P-type diffusion layer 703 and a low-concentration P-type diffusion layer 704, respectively. The low-concentration P-type diffusion layers 703 and 704 have a concentration profile having a peak concentration in the direction from the source 305 to the drain 306. The peak concentrations of the low-concentration P-type diffusion layers 703 and 704 are lower than the peak concentrations of the P-type diffusion layers 410 and 411 of the peripheral circuit transistor 308.

[0089] That is, the impurity concentration of the diffusion region of the source 305 of the write transistor 203 and the impurity concentration of the diffusion region of the drain 306 of the write transistor 203 have a concentration distribution having a concentration peak in the third direction from the source 305 to the drain 306. The impurity concentration of the diffusion region of the source 310 of the peripheral circuit transistor 308 and the impurity concentration of the diffusion region of the drain 311 of the peripheral circuit transistor 308 have a concentration distribution having a concentration peak in the second direction from the source 310 to the drain 311. The peak concentration of the impurity in the diffusion region of the source 305 or the drain 306 of the write transistor 203 is lower than the peak concentration of the impurity in the diffusion region of the source 310 or the drain 311 of the peripheral circuit transistor 308. Each peak concentration indicates the concentration at the concentration peak.

[0090] According to this configuration, the electric field strength between the source 305 and drain 306 of the write transistor 203 and the N-type well layer 407 can be reduced, and the leakage current flowing from the well into the source 305 and drain 306 can be reduced. This can also reduce the leakage current flowing into the first capacitor element 204. Therefore, the fluctuation of the brightness signal held in the first capacitor element 204 can be reduced. As a result, the organic light-emitting element 201 can emit light stably at a predetermined brightness.

[0091] Figure 8A It is along Figure 3A A cross-sectional view of the light emitting device according to the fifth exemplary embodiment is shown along line AA'. In this exemplary embodiment, the write transistor 203 and the peripheral circuit transistor 308 have a halo structure. The following mainly describes configurations different from those in other exemplary embodiments.

[0092] In the write transistor 203, high concentration N-type diffusion layers 801 and 802 as Halo implantation layers are adjacent to low concentration P-type diffusion layers 703 and 704, respectively. An N-type well layer 407 having a relatively low concentration is arranged between the high concentration N-type diffusion layer 801 and the high concentration N-type diffusion layer 802.

[0093] The drive transistor 202 according to this exemplary embodiment has a structure without a halo injection layer. Since the drive transistor 202 supplies a subthreshold current to the organic light-emitting element 201, if a halo injection layer is provided in the drive transistor 202, even if the concentration of the halo injection layer varies slightly, the subthreshold current varies significantly for each pixel 102. By not providing a halo injection layer, variations in the amount of current supplied from the drive transistor 202 to the organic light-emitting element 201 can be reduced.

[0094] Figure 8B It is along Figure 3B The cross-sectional view of the light emitting device according to the present exemplary embodiment is shown along the line BB'. Figure 8B As illustrated, in the peripheral circuit transistor 308, N-type diffusion layers 803 and 804, serving as Halo injection layers, are adjacent to P-type diffusion layers 410 and 411, respectively. An N-type well layer 407 having a relatively low concentration is disposed between the N-type diffusion layers 803 and 804. This exemplary embodiment illustrates a configuration in which the peak concentrations of the high-concentration N-type diffusion layers 801 and 802 constituting the write transistor 203 are higher than the peak concentrations of the N-type diffusion layers 803 and 804 constituting the peripheral circuit transistor 308. However, the present disclosure is not limited thereto. The concentrations of the Halo injection layers can be appropriately adjusted depending on the amount of leakage current, and the relative magnitude relationship can be reversed.

[0095] In the light-emitting device according to this exemplary embodiment, the write transistor 203 includes a halo-implanted layer in the diffusion regions of the source 305 and the drain 306. The halo-implanted layer has a polarity opposite to that of the diffusion regions. In other words, the halo-implanted layer has the same polarity as the channel formed when the transistor is turned on.

[0096] Then, the peripheral circuit transistor 308 includes a Halo implant layer in the diffusion regions of the source 310 and the drain 311 , and the Halo implant layer has a polarity opposite to that of the diffusion regions.

[0097] A configuration is adopted in which the peak concentration of the impurity concentration of the Halo injection layer of the write transistor 203 is higher than the peak concentration of the impurity concentration of the Halo injection layer of the peripheral circuit transistor 308. Although the relationship between the peak concentrations is configured as described above in the present exemplary embodiment, it is only necessary to make the peak concentration of the impurity concentration of the Halo injection layer of the write transistor 203 different from the peak concentration of the impurity concentration of the Halo injection layer of the peripheral circuit transistor 308. The peak concentration of the impurity concentration can be adjusted by adjusting the control of the leakage current.

[0098] This configuration reduces leakage current flowing from the source 305 of the write transistor 203 to the drain 306 and into the first capacitor element 204. Consequently, fluctuations in the luminance signal held in the first capacitor element 204 can be prevented. Consequently, the organic light-emitting element 201 can emit light stably at a predetermined luminance. Furthermore, leakage current flowing from the source 310 of the peripheral circuit transistor 308 to the drain 311 of the peripheral circuit transistor 308 can be reduced. Consequently, current consumption in the peripheral circuit unit can be reduced.

[0099] In the sixth exemplary embodiment, the light-emitting device includes an emission control transistor disposed between a power supply for supplying current to the light-emitting element and a driver transistor. More specifically, the light-emitting device includes an emission control transistor 1001 for controlling the current supplied from the first power supply terminal 205 (Vdd) to the driver transistor 202. The following primarily describes configurations that differ from those in the other exemplary embodiments. Following the driver transistor 202, the write transistor 203, and the peripheral circuit transistor 308, the emission control transistor is also referred to as the "fourth transistor."

[0100] Figure 9 1 is a schematic diagram illustrating an example of a light-emitting device according to the present exemplary embodiment. In the pixel array unit 103, second scan lines 901 are arranged along the row direction for each pixel row. The second scan lines 901 are connected to the output terminals of the corresponding rows of the vertical scanning circuit 104 and supply light-emission control signals to each pixel 102.

[0101] Figure 10This is an example Figure 9 1 is a circuit diagram of an example pixel circuit included in the light-emitting device 101. One of the source and drain of the light-emitting control transistor 1001 (in this case, the drain) is connected to one of the source and drain of the drive transistor 202 (in this case, the source). The other of the light-emitting control transistors 1001 (in this case, the source) is connected to the first power supply terminal 205 (Vdd). The gate of the light-emitting control transistor 1001 is connected to the second scan line 901.

[0102] The second capacitor element 1002 is connected between the drain of the light emission control transistor 1001 and the first power supply terminal 205 (Vdd). The second capacitor element 1002 may be any one of a parasitic capacitor, a gate-channel capacitor of a MOS, an MIM structure, and an MOM structure.

[0103] The emission control transistor 1001 responds to a light emission control signal applied to the gate of the emission control transistor 1001 from the vertical scanning circuit 104 via the second scan line 901 and enters a conductive state, thereby allowing current to be supplied from the first power supply terminal 205 (Vdd) to the drive transistor 202. This enables the organic light-emitting element 201 to emit light using the drive transistor 202. In other words, the emission control transistor 1001 functions as a transistor for controlling the emission and non-emission of the organic light-emitting element 201. In this way, the switching operation of the emission control transistor 1001 enables so-called duty cycle control, in which the ratio between the emission period and the non-emission period of the organic light-emitting element 201 can be controlled. This duty cycle control can reduce afterimage blur caused by the light emission from the pixel 102 over a single frame period. In particular, the image quality of moving images can be improved.

[0104] Due to manufacturing variations, the threshold value of the drive transistor 202 may differ for each pixel 102. When the same signal voltage is written to multiple pixels 102 of the same luminous color, the amount of current flowing through the drive transistor 202 differs for each pixel 102, and the amount of luminescence varies. Therefore, before writing the signal voltage, a so-called threshold correction operation is performed to maintain the threshold value between the gate 301 and the source 302 of the drive transistor 202. Through the threshold correction operation, the variation in the amount of current of the drive transistor 202 for each pixel 102 can be reduced. As a result, more uniform luminescence can be achieved.

[0105] In the threshold correction operation, after current is applied to the organic light-emitting element 201 via the light-emission control transistor 1001 and the drive transistor 202, the light-emission control transistor 1001 is turned off. Therefore, current flows to the organic light-emitting element 201, and the threshold is corrected until the voltage between the gate 301 and the source 302 of the drive transistor 202 stabilizes.

[0106] Figure 11 yes Figure 10 A plan view of an example of the illustrated circuit. The light emission control transistor 1001 includes a gate electrode 1101 , a source portion 1102 , and a drain portion 302 .

[0107] Figure 12 It is along Figure 11 A cross-sectional view taken along the line CC' in the illustrated plan view. The source portion 1102 and drain portion 302 of the emission control transistor 1001 are formed by a low-concentration P-type diffusion layer 1201 and a low-concentration P-type diffusion layer 1202, respectively. The peak concentrations of the low-concentration P-type diffusion layers 1201 and 1202 are lower than the peak concentrations of the P-type diffusion layers 410 and 411 of the peripheral circuit transistor 308. High-concentration N-type diffusion layers 1203 and 1204, serving as Halo implantation layers, are adjacent to the low-concentration P-type diffusion layers 1201 and 1202, respectively. An N-type well layer 407 having a relatively low concentration is disposed between the high-concentration N-type diffusion layer 1203 and the high-concentration N-type diffusion layer 1204. This exemplary embodiment illustrates a configuration in which the peak concentrations of the high-concentration N-type diffusion layers 1203 and 1204 constituting the emission control transistor 1001 are higher than the peak concentrations of the N-type diffusion layers 803 and 804 constituting the peripheral circuit transistor 308. However, the present disclosure is not limited thereto. The concentration of the Halo injection layer can be appropriately adjusted according to the amount of leakage current, and the relative magnitude relationship can be reversed. The concentration of the Halo injection layer of the emission control transistor 1001 can be the same as the concentration of the Halo injection layer of the write transistor 203. In this specification, "the same" includes being substantially the same in consideration of manufacturing errors.

[0108] This exemplary embodiment illustrates a configuration in which the light-emitting device includes the emission control transistor 1001 disposed between the power supply 205 that supplies current to the light-emitting element 201 and the driver transistor 202, and a halo injection layer is provided. The present disclosure is not limited thereto. Alternatively, the light-emitting device may include a region without a silicide layer between the insulating layer 406 and at least one of the source 1102, drain 302, and gate electrode 1101 of the emission control transistor 1001. Alternatively, the light-emitting device may include a region without a silicide layer provided between the insulating layer 406 and at least one of the source 1102, drain 302, and gate electrode 1101 of the emission control transistor 1001. Alternatively, the light-emitting device may include a region without a salicide structure provided in at least one of the source 1102, drain 302, and gate electrode 1101 of the emission control transistor 1001.

[0109] The following configuration can be adopted, in which the impurity concentration of the diffusion region of the source 1102 of the emission control transistor 1001 and the impurity concentration of the diffusion region of the drain 302 have a concentration distribution having a concentration peak in the fourth direction from the source 1102 to the drain 302, the impurity concentration of the diffusion region of the source 310 of the peripheral circuit transistor 308 and the impurity concentration of the diffusion region of the drain 311 of the peripheral circuit transistor 308 have a concentration distribution having a concentration peak in the second direction from the source 310 to the drain 311, and the peak concentration of the impurity in the diffusion region of the source 1102 or the drain 302 of the emission control transistor 1001 is lower than the peak concentration of the impurity in the diffusion region of the source 310 or the drain 311 of the peripheral circuit transistor 308.

[0110] According to this configuration, when the threshold is corrected, leakage current flowing from the source 1102 to the drain 302 of the light emission control transistor 1001 and into the first capacitor element 204 can be reduced. Therefore, fluctuations in the threshold voltage held in the first capacitor element 204 can be reduced.

[0111] The light-emitting device according to the seventh exemplary embodiment includes a reset transistor, which is arranged between the drain 303 and source 302 of the driving transistor 202, a terminal connected to the light-emitting element 201, and a terminal having a lower potential than the power supply 205 that supplies current to the light-emitting element 201. More specifically, a configuration is employed in which the light-emitting device includes a reset transistor 1401 that resets the light-emitting element 201 by connecting the anode of the light-emitting element 201 to a third power supply terminal 1402 (hereinafter referred to as "Vres"). Following the light-emission control transistor 1001, the reset transistor is also referred to as the "fifth transistor." The third power supply terminal 1402 can be a power supply having a lower potential than the power supply 205 that supplies current to the light-emitting element 201. According to this exemplary embodiment, the third power supply terminal 1402 only needs to have the potential used by the reset transistor 1401 to reset the light-emitting element 201, and is not limited to this exemplary embodiment. The following mainly describes configurations that differ from those in other exemplary embodiments.

[0112] Figure 13 1 is a schematic diagram illustrating an example of a light-emitting device according to the present exemplary embodiment. In the pixel array unit 103, a third scan line 1301 is arranged along the row direction for each pixel row. The third scan line 1301 is connected to the output terminal of the corresponding row of the vertical scanning circuit 104 and supplies a reset signal to each pixel 102.

[0113] Figure 14 This is an example Figure 131 is a circuit diagram of an example of a pixel circuit included in the light-emitting device 101 in FIG. One of the source and drain of the reset transistor 1401 (in this case, the source) is connected to one of the source and drain of the drive transistor 202 (in this case, the drain). The other of the reset transistors 1401 is connected to the third power supply terminal 1402 (Vres). The gate of the reset transistor 1401 is connected to the third scan line 1301. By turning on the reset transistor 1401, the anode of the organic light-emitting element 201 can be connected to the third power supply terminal 1402 (Vres), and the brightness of the organic light-emitting element 201 can be set to a black level. Therefore, a light-emitting device with a high contrast ratio can be realized. During the light-emitting period, the reset transistor 1401 is in an off state.

[0114] Figure 15 yes Figure 14 A plan view of an example of the illustrated circuit. The reset transistor 1401 includes a gate electrode 1501, a source 303, and a drain 1502. The source node of the reset transistor 1401 is the same as the drain node of the drive transistor 202, so the same reference numeral 303 is used.

[0115] Figure 16 It is along Figure 15 A cross-sectional view taken along the line DD' in the illustrated plan view. The source 303 and drain 1502 of the reset transistor 1401 are formed by a low-concentration P-type diffusion layer 1601 and a low-concentration P-type diffusion layer 1602, respectively. The peak concentrations of the low-concentration P-type diffusion layers 1601 and 1602 are lower than the peak concentrations of the P-type diffusion layers 410 and 411 of the peripheral circuit transistor 308. High-concentration N-type diffusion layers 1603 and 1604, serving as Halo implantation layers, are adjacent to the low-concentration P-type diffusion layers 1601 and 1602, respectively. An N-type well layer 407 having a relatively low concentration is arranged between the high-concentration N-type diffusion layer 1603 and the high-concentration N-type diffusion layer 1604. This exemplary embodiment illustrates a configuration in which the peak concentrations of the high-concentration N-type diffusion layers 1603 and 1604 constituting the reset transistor 1401 are higher than the peak concentrations of the N-type diffusion layers 803 and 804 constituting the peripheral circuit transistor 308. However, the present disclosure is not limited thereto. The concentration of the Halo injection layer can be appropriately adjusted according to the amount of leakage current, and the relative magnitude relationship can be reversed. The concentration of the Halo injection layer of the reset transistor 1401 can be the same as the concentration of the Halo injection layer of the write transistor 203.

[0116] The light emitting device according to this exemplary embodiment includes a reset transistor 1401 arranged between a terminal connected to the light emitting element 201 between the drain 303 and the source 302 of the driving transistor 202 and a terminal having a potential lower than that of the power supply 205 that supplies current to the light emitting element 201.

[0117] A configuration may be employed in which, as in the configurations of other exemplary embodiments, the reset transistor according to the present exemplary embodiment includes a region where a silicide layer is not provided between at least any one of the source 303, the drain 1502, and the gate electrode 1501 of the reset transistor 1401 and the insulating layer 406. A configuration may be employed in which the reset transistor does not include a salicide structure in at least any one of the source 303, the drain 1502, and the gate electrode 1501 of the reset transistor 1401.

[0118] In the reset transistor according to the present exemplary embodiment, a configuration can be adopted in which the impurity concentration of the diffusion region of the source 303 of the reset transistor 1401 and the impurity concentration of the diffusion region of the drain 1502 have a concentration distribution having a concentration peak in a fifth direction from the source 303 to the drain 1502, the impurity concentration of the diffusion region of the source 310 of the peripheral circuit transistor 308 and the impurity concentration of the diffusion region of the drain 311 of the peripheral circuit transistor 308 have a concentration distribution having a concentration peak in a second direction from the source 310 to the drain 311, and the peak concentration of the impurity in the diffusion region of the source 303 or the drain 1502 of the reset transistor 1401 is lower than the peak concentration of the impurity in the diffusion region of the source 310 or the drain 311 of the peripheral circuit transistor 308. Each peak concentration indicates the concentration at the concentration peak.

[0119] According to this configuration, leakage current flowing from the source 303 of the reset transistor 1401 to the drain 1502 of the reset transistor 1401 can be reduced. This can reduce leakage current flowing from the drive transistor 202 to the third power supply terminal 1402 (Vres) via the reset transistor 1401 during the light emission period. Therefore, the consumption current in the pixel 102 can be reduced.

[0120] The light emitting device according to the eighth exemplary embodiment has a configuration in which transistors constituting the inverter circuit 1701 in the vertical scanning circuit 104 include a Halo structure. Configurations different from those in the other exemplary embodiments are mainly described below.

[0121] Figure 17 yes Figure 13 1 is a circuit diagram of an example of an inverter circuit 1701 in a vertical scanning circuit 104 included in a light-emitting device 101 in FIG. The drain, source, and gate of a P-type transistor 1702 are connected to the drain of an N-type transistor 1703, a fourth power supply terminal 1704 (hereinafter referred to as "Vddd"), and the gate of the N-type transistor 1703, respectively.

[0122] The source of the N-type transistor 1703 is connected to a fifth power supply terminal 1705 (hereinafter referred to as “Vssd”).

[0123] The inverter circuit 1701 includes an input terminal 1706 and an output terminal 1707. The input terminal 1706 is connected to the gates of the P-type transistor 1702 and the N-type transistor 1703. The output terminal 1707 is connected to the drain of the P-type transistor 1702, the drain of the N-type transistor 1703, and also to any of the first scan line 106, the second scan line 901, and the third scan line 1301.

[0124] Figure 18 yes Figure 17 A plan view of an example of the illustrated circuit. A P-type transistor 1702 includes a gate electrode 1801 , a source 1802 , and a drain 1803 .

[0125] The N-type transistor 1703 includes a gate electrode 1804 , a source 1805 , and a drain 1806 .

[0126] Figure 19 It is along Figure 18 The source 1802 and the drain 1803 of the P-type transistor 1702 are formed by the P-type diffusion layer 1901 and the P-type diffusion layer 1902, respectively.

[0127] N-type diffusion layer 1903 and N-type diffusion layer 1904, which are Halo implantation layers, are adjacent to P-type diffusion layers 1901 and 1902, respectively. An N-type well layer 407 having a relatively low concentration is disposed between N-type diffusion layer 1903 and N-type diffusion layer 1904.

[0128] The drain 1806 and source 1805 of the N-type peripheral circuit transistor 1703 are formed by N-type diffusion layers 1905 and 1906, respectively. P-type diffusion layers 1907 and 1908, which serve as Halo implantation layers, are adjacent to the N-type diffusion layers 1905 and 1906, respectively. A P-type well layer 1809 having a relatively low concentration is arranged between the P-type diffusion layers 1907 and 1908.

[0129] This configuration reduces leakage current flowing from the fourth power supply terminal 1704 (Vddd) to the fifth power supply terminal 1705 (Vssd) via the P-type peripheral circuit transistor 1702 and the N-type peripheral circuit transistor 1703. Therefore, current consumption in the vertical scanning circuit 104 can be reduced.

[0130] [Other Typical Embodiments]

[0131] Figure 202 is a schematic diagram illustrating an example of a display device according to this exemplary embodiment. Display device 2000 may include a touch panel 2003, a display panel 2005, a frame 2006, a circuit substrate 2007, and a battery 2008 between an upper cover 2001 and a lower cover 2009. Touch panel 2003 and display panel 2005 are connected to flexible printed circuits (FPCs) 2002 and 2004, respectively. Transistors are printed on circuit substrate 2007. Unless display device 2000 is a mobile device, battery 2008 may not be provided. Even if display device 2000 is a mobile device, battery 2008 may be provided elsewhere.

[0132] The display device according to the present exemplary embodiment may include a color filter having red, green, and blue colors. In the color filter, the red, green, and blue colors may be arranged in a delta (Δ) arrangement.

[0133] The display device according to this exemplary embodiment can also be used in the display unit of a mobile terminal. In this case, the display device can have both a display function and an operation function. Examples of mobile terminals include mobile phones such as smartphones, tablet computers, and head-mounted displays.

[0134] The display device according to this exemplary embodiment can also be used in the display unit of an imaging device, which includes an optical unit having multiple lenses and an imaging element that receives light passing through the optical unit. The imaging device can include a display unit that displays information acquired by the imaging element. The display unit can be a display unit exposed to the outside of the imaging device or a display unit placed in a viewfinder. The imaging device can be a digital still camera or a digital video camera.

[0135] Figure 21A 2 is a schematic diagram illustrating an example of an imaging apparatus according to this exemplary embodiment. The imaging apparatus 2100 may include a viewfinder 2101, a rear display 2102, an operation unit 2103, and a housing 2104. The viewfinder 2101 may include a display device according to this exemplary embodiment. In this case, the display device may display not only captured images but also environmental information and imaging instructions. Environmental information may include the intensity and direction of external light, the speed of movement of a subject, and the likelihood that the subject is obscured by an obstruction.

[0136] Because the timing suitable for capturing an image is short, information needs to be displayed as quickly as possible. Therefore, it is desirable to use a display device utilizing the organic light-emitting element disclosed herein. This is because the organic light-emitting element has a fast response speed. Display devices utilizing such organic light-emitting elements are more suitable for use than these devices and liquid crystal display devices, which require fast display speeds.

[0137] The imaging device 2100 includes an optical unit (not shown). The optical unit includes a plurality of lenses and forms an image on an imaging element housed in the housing 2104. The focus can be adjusted by adjusting the relative positions of the plurality of lenses. This operation can also be performed automatically. The imaging device 2100 can also be referred to as a "photoelectric conversion device." The photoelectric conversion device can include, as an imaging method, a method for detecting a difference from a previous image when images are not captured sequentially or a method for cutting out an image from an image that is always recorded.

[0138] Figure 21B 22 is a schematic diagram illustrating an example of an electronic device according to the present exemplary embodiment. The electronic device 2200 includes a display unit 2201, an operation unit 2202, and a housing 2203. The housing 2203 may include a circuit, a printed substrate including the circuit, a battery, and a communication unit. The operation unit 2202 may be a button, or may be a response unit using a touch panel method. The operation unit 2202 may be a biometric recognition unit that recognizes a fingerprint and unlocks the device. The communication unit is a communication unit that communicates with the outside, and may be wired or wireless. The electronic device 2200 including the communication unit may also be referred to as a communication device. The electronic device 2200 may also have a camera function by including a lens and an imaging element. An image captured by the camera function is displayed on the display unit 2201.

[0139] Examples of the electronic device 2200 include a smart phone and a laptop personal computer.

[0140] Figure 22A and Figure 22B is a schematic diagram illustrating an example of the display device according to the present exemplary embodiment. Figure 22A A display device 2300 such as a television monitor or a personal computer (PC) monitor is illustrated. The display device 2300 includes a frame 2301 and a display unit 2302. The light emitting device according to the present exemplary embodiment can be used in the display unit 2302.

[0141] The display device 2300 includes a support frame 2301 and a base 2303 of a display unit 2302. The base 2303 is not limited to Figure 22A The lower side of the frame 2301 can also serve as a base.

[0142] The frame 2301 and the display unit 2302 may be curved, and a curvature radius of the curve may be greater than or equal to 5000 mm and less than or equal to 6000 mm.

[0143] Figure 22B is a schematic diagram illustrating another example of the display device according to the present exemplary embodiment. Figure 22BThe display device 2310 in the embodiment is configured to be folded and is a so-called foldable display device. The display device 2310 includes a first display unit 2311, a second display unit 2312, a housing 2313, and a folding point 2314. The first display unit 2311 and the second display unit 2312 may include a light-emitting device according to this exemplary embodiment. The first display unit 2311 and the second display unit 2312 may be a single display device without a seam. The first display unit 2311 and the second display unit 2312 may be divided at the folding point 2314. The first display unit 2311 and the second display unit 2312 may display images different from each other, or may display a single image.

[0144] Figure 23A and Figure 23B This is a schematic diagram illustrating an example of a wearable device according to this exemplary embodiment. The wearable device can be applied to a system that can be worn as a wearable device such as smart glasses, a head-mounted display (HMD), or smart contact lenses. The imaging display device used in such an application example includes an imaging device capable of photoelectrically converting visible light and a display device capable of emitting visible light.

[0145] Figure 23A Glasses 2600 (smart glasses) according to an application example are illustrated. An imaging device 2602, such as a complementary metal oxide semiconductor (CMOS) sensor or a single photon avalanche diode (SPAD), is provided on the front of a lens 2601 of the glasses 2600. A display device according to each of the above exemplary embodiments is provided on the back of the lens 2601.

[0146] Glasses 2600 also include a control device 2603. Control device 2603 serves as a power source for supplying power to an imaging device 2602 and a display device according to various exemplary embodiments. Control device 2603 controls the operation of imaging device 2602 and the display device. An optical system for collecting light from imaging device 2602 is formed in lens 2601.

[0147] Figure 23BGlasses 2610 (smart glasses) according to another application example are illustrated. Glasses 2610 include a control device 2612. A camera equivalent to the camera 2602 and a display device are mounted on the control device 2612. An optical system for projecting light emitted from the display device in the control device 2612 is formed in the lens 2611. The image is projected onto the lens 2611. The control device 2612 serves as a power supply for supplying power to the camera and display devices, and also controls the operation of the camera and display devices. The control device 2612 includes an image control unit. The image control unit sends an image control signal to the peripheral circuit of the light-emitting device. The control device 2612 may also include a line of sight detection unit for detecting the line of sight of the wearer (user). Infrared light can be used to detect the line of sight. The infrared light emitting unit emits infrared light to the eyeball of the user who is looking at the displayed image. The camera unit including a light-receiving element detects the reflected light of the emitted infrared light from the eyeball, thereby obtaining a captured image of the eyeball. The control device 2612 includes a reducing unit that reduces light from the infrared light emitting unit to the display unit in a plan view, thereby reducing degradation of image quality.

[0148] The user's line of sight to the displayed image is detected from an image of the eyeball captured by capturing infrared light. Any known technique can be applied to line of sight detection using a captured image of the eyeball. As an example, a line of sight detection method based on a Purkinje image formed by reflection of emitted light from the cornea can be used.

[0149] More specifically, gaze detection processing based on the pupil-corneal reflection method is performed. Using the pupil-corneal reflection method, a gaze vector indicating the direction (rotation angle) of the eyeball is calculated based on the pupil image and Purkinje image included in the captured image of the eyeball, thereby detecting the user's gaze.

[0150] A display device according to an exemplary embodiment of the present disclosure may include an imaging device having a light receiving element, and control a display image on the display device based on line of sight information about a user from the imaging device.

[0151] Specifically, based on the line of sight information, the display device determines a first display area at which the user is looking and a second display area other than the first display area. The first display area and the second display area may be determined by a control device of the display device, or the display device may receive the first display area and the second display area determined by an external control device. Within the display areas of the display device, the display resolution of the first display area may be controlled to be higher than the display resolution of the second display area. In other words, the resolution of the second display area may be set to be lower than the resolution of the first display area.

[0152] The first display area and the second display area of the display area can be determined based on the line of sight information. The display device can use artificial intelligence (AI) to determine the first display area and the high priority area. The AI can be a model configured to use the image of the eyeball and the direction in which the eyeball in the image is actually looking as supervision data, and estimate the angle of the line of sight and the distance to the object in the line of sight based on the image of the eyeball. The AI program can be included in the display device, or can be included in the camera device, or can be included in the external device. In the case where the AI program is included in the external device, the AI program is sent to the display device through communication.

[0153] In the case where the display device performs display control based on line of sight detection, the display device can be appropriately applied to smart glasses that also include a camera that captures the outside world. The smart glasses can display information related to the captured outside world in real time.

[0154] As described above, according to the present disclosure, a light emitting device in which leakage current in a light emitting element is reduced can be provided.

[0155] According to the present disclosure, a light-emitting device can be provided in which degradation in characteristics of the light-emitting device due to provision of a silicide layer is reduced.

[0156] While the present disclosure has been described with reference to exemplary embodiments, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. The scope of the following claims is to be accorded the broadest interpretation so as to encompass all such modifications and equivalent structures and functions.

Claims

1. A light-emitting device, comprising: Light-emitting element; A first transistor and a second transistor, wherein the first transistor and the second transistor are disposed on a first surface of a silicon substrate; an insulating layer disposed between the light emitting element and the first surface; as well as a third transistor provided in a peripheral circuit configured to supply an image signal to the first transistor, wherein one of the source and the drain of the first transistor is connected to the gate electrode of the second transistor, wherein one of the source and the drain of the second transistor is connected to the light emitting element, wherein the light emitting device includes a silicide layer in at least any one of the source, drain, and gate electrodes of the third transistor, and the silicide layer is in contact with the insulating layer; and The light emitting device includes a region where no silicide layer is provided between the insulating layer and at least any one of the source, drain and gate electrodes of the first transistor.

2. The light emitting device according to claim 1, wherein In a cross section perpendicular to the first surface, the light emitting device includes a region where no silicide layer is provided between the insulating layer and at least any one of the source, drain, and gate electrode of the second transistor.

3. The light emitting device according to claim 1 , further comprising a fourth transistor disposed between a power supply configured to supply current to the light emitting element and the second transistor, in, In a cross section perpendicular to the first surface, the light emitting device includes a region where no silicide layer is provided between the insulating layer and at least any one of the source, drain, and gate electrode of the fourth transistor.

4. The light-emitting device according to claim 3 , further comprising a fifth transistor arranged between a terminal connected to the light-emitting element between the drain and source of the second transistor and a terminal having a potential lower than a potential of a power supply configured to supply current to the light-emitting element, in, In a cross section perpendicular to the first surface, the light-emitting device includes a region where no silicide layer is provided between the insulating layer and at least any one of the source, drain, and gate electrode of the fifth transistor.

5. The light-emitting device according to claim 1, in, an impurity concentration of a diffusion region of the source of the second transistor and an impurity concentration of a diffusion region of the drain of the second transistor have a concentration distribution having a peak concentration in a first direction from the source of the second transistor to the drain of the second transistor, wherein the impurity concentration of the diffusion region of the source of the third transistor and the impurity concentration of the diffusion region of the drain of the third transistor have a concentration distribution having a peak concentration in a second direction from the source of the third transistor to the drain of the third transistor, and The peak concentration of impurities in the diffusion region of the source or drain of the second transistor is lower than the peak concentration of impurities in the diffusion region of the source or drain of the third transistor.

6. The light emitting device according to claim 1, in, The impurity concentration of the diffusion region of the source of the first transistor and the impurity concentration of the diffusion region of the drain of the first transistor have a concentration distribution having a peak concentration in a third direction from the source of the first transistor to the drain of the first transistor, wherein the impurity concentration of the diffusion region of the source of the third transistor and the impurity concentration of the diffusion region of the drain of the third transistor have a concentration distribution having a peak concentration in a second direction from the source of the third transistor to the drain of the third transistor, and The peak concentration of impurities in the diffusion region of the source or drain of the first transistor is lower than the peak concentration of impurities in the diffusion region of the source or drain of the third transistor.

7. The light emitting device according to claim 1 , further comprising a fourth transistor disposed between a power supply configured to supply current to the light emitting element and the second transistor, in, The fourth transistor includes a source electrode, a drain electrode, and a gate electrode, wherein the impurity concentration of the diffusion region of the source of the fourth transistor and the impurity concentration of the diffusion region of the drain of the fourth transistor have a concentration distribution having a peak concentration in a fourth direction from the source of the fourth transistor to the drain of the fourth transistor, wherein the impurity concentration of the diffusion region of the source of the third transistor and the impurity concentration of the diffusion region of the drain of the third transistor have a concentration distribution having a peak concentration in a second direction from the source of the third transistor to the drain of the third transistor, and The peak concentration of impurities in the diffusion region of the source or drain of the fourth transistor is lower than the peak concentration of impurities in the diffusion region of the source or drain of the third transistor.

8. The light-emitting device according to claim 7 , further comprising a fifth transistor arranged between a terminal connected to the light-emitting element between the drain and source of the second transistor and a terminal having a potential lower than a potential of a power supply configured to supply current to the light-emitting element, in, an impurity concentration of a diffusion region of the source of the fifth transistor and an impurity concentration of a diffusion region of the drain of the fifth transistor have a concentration distribution having a peak concentration in a fifth direction from the source to the drain of the fifth transistor, wherein the impurity concentration of the diffusion region of the source of the third transistor and the impurity concentration of the diffusion region of the drain of the third transistor have a concentration distribution having a peak concentration in a second direction from the source of the third transistor to the drain of the third transistor, and The peak concentration of impurities in the diffusion region of the source or drain of the fifth transistor is lower than the peak concentration of impurities in the diffusion region of the source or drain of the third transistor.

9. The light emitting device according to claim 1, wherein The first transistor includes a Halo injection layer in diffusion regions of a source of the first transistor and a drain of the first transistor, and the Halo injection layer has a polarity opposite to that of the diffusion region.

10. The light emitting device according to claim 9, in, The third transistor includes a Halo injection layer in diffusion regions of a source of the third transistor and a drain of the third transistor, and the Halo injection layer has a polarity opposite to that of the diffusion region, and The peak concentration of the impurity concentration of the Halo injection layer of the first transistor is different from the peak concentration of the impurity concentration of the Halo injection layer of the third transistor.

11. The light emitting device according to claim 1 , further comprising a fourth transistor disposed between a power source configured to supply current to the light emitting element and the second transistor, in, The fourth transistor includes a Halo implantation layer in diffusion regions of a source of the fourth transistor and a drain of the fourth transistor, wherein the Halo injection layer has a polarity opposite to that of the diffusion region, and The peak concentration of the impurity concentration of the Halo injection layer of the third transistor is different from the peak concentration of the impurity concentration of the Halo injection layer of the fourth transistor.

12. The light emitting device according to claim 11 , further comprising a fifth transistor arranged between a terminal connected to the light emitting element between the drain and source of the second transistor and a terminal having a potential lower than a potential of a power supply configured to supply current to the light emitting element, in, The fifth transistor includes a Halo injection layer in diffusion regions of a source of the fifth transistor and a drain of the fifth transistor, and the Halo injection layer has a polarity opposite to that of the diffusion region, and The peak concentration of the impurity concentration of the Halo injection layer of the third transistor is different from the peak concentration of the impurity concentration of the Halo injection layer of the fifth transistor.

13. The light emitting device according to claim 1, wherein The peripheral circuit is provided on the first surface of the silicon substrate.

14. The light emitting device according to claim 1, wherein The peripheral circuit is arranged on a second silicon substrate different from the silicon substrate.

15. A light emitting device comprising: Light-emitting element; A first transistor and a second transistor, wherein the first transistor and the second transistor are disposed on a first surface of a silicon substrate; as well as a third transistor provided in a peripheral circuit configured to supply an image signal to the first transistor, wherein one of the source and the drain of the first transistor is connected to the gate electrode of the second transistor, wherein one of the source and the drain of the second transistor is connected to the light emitting element, wherein the light emitting device includes a self-aligned silicide structure in at least any one of the source, drain and gate electrodes of the third transistor, and The light emitting device does not include a self-aligned silicide structure in at least any one of the source, drain, and gate electrodes of the first transistor.

16. The light emitting device according to claim 15, wherein: The light emitting device does not include a salicide structure in at least any one of a source, a drain, and a gate electrode of the second transistor.

17. The light emitting device according to claim 15, further comprising a fourth transistor disposed between a power source configured to supply current to the light emitting element and the second transistor, in, The light emitting device does not include a salicide structure in at least any one of the source, the drain, and the gate electrode of the fourth transistor.

18. The light emitting device according to claim 17 , further comprising a fifth transistor disposed between a terminal connected to the light emitting element between the drain and source of the second transistor and a terminal having a potential lower than a potential of a power supply configured to supply current to the light emitting element, in, The light emitting device does not include a salicide structure in at least any one of the source, drain, and gate electrodes of the fifth transistor.

19. A display device comprising: The light emitting device according to any one of claims 1 to 18; as well as an image control unit configured to send an image control signal to the peripheral circuit, The light emitting element emits light according to the image control signal.

20. A photoelectric conversion device comprising: an optical unit comprising a plurality of lenses; an imaging element configured to receive light passing through the optical unit; as well as a display unit configured to display the image captured by the imaging element, Wherein, the display unit is the display device according to claim 19.

21. An electronic device comprising: The display device according to claim 19; a housing, wherein the display device is disposed in the housing; as well as A communication unit is provided in the housing and configured to communicate with the outside.

22. A method for manufacturing a light-emitting device, the light-emitting device comprising: Light-emitting element; A first transistor and a second transistor, wherein the first transistor and the second transistor are disposed on a first surface of a silicon substrate; as well as a third transistor provided in a peripheral circuit configured to supply an image signal to the first transistor, wherein one of the source and the drain of the first transistor is connected to the gate electrode of the second transistor, and wherein one of the source and the drain of the second transistor is connected to the light emitting element, The method comprises: Setting the light emitting device; forming an opening corresponding to at least any one of the source, drain, and gate electrode of the third transistor, and providing an insulating layer in the source, drain, or gate electrode of the second transistor; and After providing the insulating layer, a metal layer is formed to cover the second transistor and the third transistor, and a silicide layer is formed in at least any one of a source, a drain, and a gate electrode of the third transistor.

23. The method for manufacturing a light emitting device according to claim 22, further comprising: After forming the silicide layer, providing an insulating layer on the silicide layer; forming a first opening in the insulating layer; as well as A contact wiring is formed in the first opening.

24. The method for manufacturing a light emitting device according to claim 23, wherein: In a plan view of the first surface, the first opening overlaps with a region where the silicide layer is formed in the third transistor.

25. The method for manufacturing a light emitting device according to claim 22, further comprising: providing an insulating layer covering the first transistor or the second transistor in a state where no silicide layer is formed on any one of the source, drain, and gate electrodes of the first transistor and any one of the source, drain, and gate electrodes of the second transistor; forming a second opening in the insulating layer; as well as A contact wiring is formed in the second opening.

26. The method for manufacturing a light emitting device according to claim 25, wherein: In a plan view of the first surface, the second opening overlaps with a region where the silicide layer is formed in the first transistor or the second transistor.

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